Semiconductor test structure

Abstract

The application provides a semiconductor test structure, which belongs to the technical field of semiconductors and comprises n+1 first connecting members, 2n test members and n second connecting members, which are sequentially connected in a loop according to the first connecting member, the test member, the second connecting member, the test member and the first connecting member; a first metal strip of a stacked structure of the test member is located on a first contact hole and electrically connected with the first contact hole; a second metal strip of the first connecting member is located on a conductive extension and a second contact hole and electrically connected with the conductive extension and the second contact hole, the conductive extension is located between two second contact holes and electrically connected with the two second contact holes, and the two second contact holes are respectively electrically connected with first metal strips of the topmost layers of two adjacent test members; and a third metal strip of the second connecting member is electrically connected with first contact holes of the bottommost layers of two adjacent test members. The application can effectively monitor the filling quality of the contact hole in the metal interconnection structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor testing structure. Background Technology

[0002] Back-end of line (BEOL) processes in semiconductor devices typically fabricate metal interconnect structures to connect devices. These interconnect structures usually consist of multiple layers, each with metal strips. The metal strips between layers are connected by vias, stacked to form a multi-layer structure. Copper interconnect structures are currently the most commonly used metal interconnect structures, and they are widely used to form the metal strips and vias in a single step using dual damascene etching combined with deposition.

[0003] However, as semiconductor dimensions continue to shrink, the difficulty of forming metal strips and contact holes in a single step using dual damascene etching combined with deposition is gradually increasing. Poor copper filling leading to voids is particularly prominent, affecting the contact resistance and electrical connection reliability of the metal interconnect structure. Especially for multilayer metal wiring, the presence of voids within the contact holes has a fatal impact on contact resistance and electrical connection reliability.

[0004] Therefore, how to monitor the copper filling quality of the contact holes formed by the double damask process is a problem that needs to be solved. Utility Model Content

[0005] In view of this, the embodiments of this application aim to provide a semiconductor testing structure to solve the problem in the prior art that the copper filling quality of contact holes formed by the double damask process cannot be monitored.

[0006] This application provides a semiconductor test structure, including n+1 first connectors, 2n test pieces, and n second connectors, where n is greater than or equal to 2. The test pieces are located between the first connectors and the second connectors and are connected in series in a cyclical pattern of the first connectors, the test pieces, the second connectors, the test pieces, and the first connectors.

[0007] The test piece includes at least one stacked structure, the stacked structure including a first metal strip and a first contact hole, the first metal strip being located on the first contact hole and electrically connected to the first contact hole;

[0008] The first connector includes a second metal strip, a conductive extension, and two twin second contact holes. The second metal strip is located on the conductive extension and the second contact holes and is electrically connected to the conductive extension and the second contact holes. The conductive extension is located between the two second contact holes and is electrically connected to the two second contact holes. The two second contact holes are respectively electrically connected to the first metal strips on the top layer of two adjacent test pieces.

[0009] The second connector includes a third metal strip that electrically connects the first contact holes at the bottom layer of two adjacent test pieces.

[0010] In some embodiments, the top surface of the conductive extension is flush with the top surface of the second contact hole, and the bottom surface of the conductive extension is located above the bottom surface of the second contact hole.

[0011] In some embodiments, the thickness of the conductive extension is 1 / 3 to 2 / 3 of the thickness of the second contact hole.

[0012] In some embodiments, the second metal strip, the conductive extension, and the two second contact holes are an integral structure.

[0013] In some embodiments, the ratio of the width of the second metal strip to the sum of the thickness of the second contact hole and the second metal strip is less than the ratio of the width of the first metal strip to the sum of the thickness of the first contact hole and the first metal strip.

[0014] In some embodiments, the ratio of the width of the first metal strip to the sum of the thickness of the first contact hole and the first metal strip is greater than or equal to 5.

[0015] In some embodiments, on the contact surface between the first metal strip and the first contact hole, the area of ​​the first metal strip is smaller than the area of ​​the first contact hole.

[0016] In some embodiments, the second metal strips of the first and last first connectors are electrically connected to a pad, respectively.

[0017] In some embodiments, the second metal strip of each of the first connectors is electrically connected to a pad.

[0018] In some embodiments, the first metal strip, the first contact hole, the second metal strip, the conductive extension, and the second contact hole are all made of copper.

[0019] This application provides a semiconductor test structure, including n+1 first connectors, 2n test pieces, and n second connectors, where n is greater than or equal to 2. The test pieces are located between the first and second connectors and are connected in series in a cyclical pattern of the first connectors, the test pieces, the second connectors, the test pieces, and the first connectors. Each test piece includes at least one stacked structure, which includes a first metal strip and a first contact hole. The first metal strip is located on the first contact hole and electrically connected to it. Each first connector includes a second metal strip, a conductive extension, and two twin second contact holes. The second metal strip is located on the conductive extension and the second contact holes and electrically connected to them. The conductive extension is located between the two second contact holes and electrically connected to them. The two second contact holes are respectively connected to the topmost first metal strip of two adjacent test pieces. Each second connector includes a third metal strip, which is electrically connected to the bottommost first contact hole of two adjacent test pieces. An unexpected benefit of this application is that it can detect the filling quality of the test piece by performing WAT testing on the semiconductor test structure, thereby obtaining the filling quality of the metal interconnect structure formed synchronously with the test piece in the device region, achieving effective monitoring of the filling quality of contact holes in the metal interconnect structure. Moreover, this application is simple and easy to implement, with extremely high detection efficiency. Furthermore, by designing the first connector as a twin hole structure and using the conductive extension to electrically connect the two twin second contact holes, not only can the first connector be better electrically connected to the first metal strip on the top layer of two adjacent test pieces, but it can also reduce the filling difficulty of the second contact holes and improve the fabrication efficiency of the first connector. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of a semiconductor test structure provided in an embodiment of this application.

[0021] Figure 2 The layout of a semiconductor test structure provided in one embodiment of this application is shown.

[0022] Figure 3 This is a schematic diagram of another semiconductor test structure provided in an embodiment of this application.

[0023] The attached figures are labeled as follows:

[0024] 100 - Test piece; 101 - Stacked structure; 111 - First metal strip; 121 - First contact hole; 201 - First connector; 211 - Second metal strip; 221 - Second contact hole; 231 - Conductive extension; 202 - Second connector; 212 - Third metal strip; 300 - Pad. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Figure 1 This is a schematic diagram of a semiconductor test structure provided in one embodiment of this application. Figure 1 As shown, the semiconductor test structure includes n+1 first connectors 201, 2n test pieces 100, and n second connectors 202, where n is greater than or equal to 2. Figure 1 The diagram shows the case where n=3. In this case, the semiconductor test structure includes 4 first connectors 201, 6 test pieces 100, and 3 second connectors 202. However, this should not be the limitation, and n can also be other values, as long as n is greater than or equal to 2.

[0027] Furthermore, the test piece 100 is located between the first connector 201 and the second connector 202, and the first connector 201, the test piece 100, and the second connector 202 are stacked sequentially from top to bottom. They are connected in series in a cyclical pattern of first connector 201, test piece 100, second connector 202, and test piece 100 and first connector 201. For example, Figure 1 The diagram shows four first connectors 201, six test pieces 100, and three second connectors 202. They need to be connected in a cyclical, serial sequence as follows: first connector 201, test piece 100, second connector 202, test piece 100, first connector 201, test piece 100, second connector 202, test piece 100, first connector 201, test piece 100, second connector 202, test piece 100, first connector 201, test piece 100, second connector 202, test piece 100, first connector 201. Figure 1 As can be seen, both ends of the structure formed by the series connection are first connectors 201, and adjacent test pieces 100 are connected by the first connector 201 or the second connector 202.

[0028] Please continue reading. Figure 1 Each test piece 100 may include at least one stacked structure 101. Figure 1 The diagram shows two stacked structures 101, each including a first metal strip 111 and a first contact hole 121. The first metal strip 111 is located on the first contact hole 121 and electrically connected to it. The first metal strip 111 and the first contact hole 121 can be made of the same material, such as copper. Furthermore, the first metal strip 111 and the first contact hole 121 can be formed using a double damask process, thus making them an integral structure.

[0029] In some embodiments, the ratio of the width L1 of the first metal strip 111 to the sum H1 of the thickness of the first contact hole 121 and the first metal strip 111 is relatively large, for example, it may be greater than or equal to 5, but should not be limited thereto.

[0030] It is understood that each test piece 100 may also include multiple stacked structures 101. When the test piece 100 includes multiple stacked structures 101, the multiple stacked structures 101 can be stacked sequentially. In two adjacent stacked structures 101, the first contact hole 121 of the previous stacked structure 101 contacts and is electrically connected to the first metal strip 111 of the next stacked structure 101.

[0031] Furthermore, all the stacked structures 101 corresponding to the test pieces 100 are located on the same layer; that is, the first metal strips 111 in all the stacked structures 101 corresponding to the test pieces 100 are located on the same layer, and the first contact holes 121 in all the stacked structures 101 corresponding to the test pieces 100 are located on the same layer. For example, Figure 1 The first metal strips 111 in the first row stacked structure 101 of all test pieces 100 are located on the same layer, and the first contact holes 121 in the first row stacked structure 101 of all test pieces 100 are located on the same layer; the first metal strips 111 in the second row stacked structure 101 of all test pieces 100 are located on the same layer, and the first contact holes 121 in the second row stacked structure 101 of all test pieces 100 are located on the same layer.

[0032] Figure 2 This is a schematic diagram of the layout of a semiconductor test structure provided in one embodiment of this application. Figure 2 As shown, in some embodiments, on the contact surface between the first metal strip 111 and the first contact hole 121, the area of ​​the first metal strip 111 is smaller than the area of ​​the first contact hole 121. In this way, even if the first metal strip 111 and / or the first contact hole 121 are offset due to process limitations during their formation, it can still be ensured that the first metal strip 111 and the first contact hole 121 can make good contact and be electrically connected, thus improving the reliability of the semiconductor test structure.

[0033] Please continue reading. Figure 1 The first connector 201 includes a second metal strip 211, a conductive extension 231, and two twin second contact holes 221. The second metal strip 211 is located on and electrically connected to the conductive extension 231 and the second contact holes 221, and directly contacts the top surface of the conductive extension 231 and the top surface of the second contact holes 221. The conductive extension 231 is located between the two second contact holes 221, and its two ends directly contact the sidewalls of the two second contact holes 221, thereby electrically connecting the two second contact holes 221. The two second contact holes 221 are electrically connected to the topmost first metal strip 111 of two adjacent test pieces 100, thus the first connector 201 can electrically connect two adjacent test pieces 100.

[0034] It should be noted that since the first and last first connectors 201 are located at the beginning and end, one of the second contact holes 221 in the first and last first connectors 201 cannot be electrically connected to the topmost first metal strip 111 of the two adjacent test pieces 100, but this does not affect the implementation of this application.

[0035] Furthermore, the second metal strip 211, the conductive extension 231, and the two second contact holes 221 can be made of the same material, such as copper. The second metal strip 211, the conductive extension 231, and the two second contact holes 221 can be formed using a double damask process (the conductive extension 231 can also be considered a shallow contact hole). In this case, the second metal strip 211, the conductive extension 231, and the two second contact holes 221 are an integral structure, simplifying the fabrication of the first connector 201. In some embodiments, the ratio of the width L2 of the second metal strip 211 to the sum H2 of the thicknesses of the second contact holes 221 and the second metal strip 211 is small, for example, it can be less than or equal to 5. In other words, the ratio of the width L2 of the second metal strip 211 to the sum of the thickness H2 of the second contact hole 221 and the second metal strip 211 can be less than the ratio of the width L1 of the first metal strip 111 to the sum of the thickness H1 of the first contact hole 121 and the first metal strip 111, making it easier to form the first connector 201.

[0036] It is understandable that since the two second contact holes 221 of the first connector 201 are twin holes, not only can the first connector 201 be electrically connected to the two adjacent test pieces 100 in a better way, but it can also reduce the difficulty of filling the second contact holes 221. At the same time, by using the conductive extension 231 to electrically connect the two twin second contact holes 221, the difficulty of filling the second contact holes 221 can be further reduced, and the manufacturing efficiency of the first connector 201 can be improved.

[0037] Please continue reading. Figure 1 The top surface of the conductive extension 231 is flush with the top surface of the second contact hole 221, while the bottom surface of the conductive extension 231 can be located above the bottom surface of the second contact hole 221. Alternatively, it can be understood that the conductive extension 231 and the second contact hole 221 are formed using different photomasks and different etching steps (for example, a through-hole to accommodate the second contact hole 221 can be formed first using one photomask, and then a through-hole to accommodate the conductive extension 231 can be formed using another photomask), resulting in inconsistent thicknesses between the conductive extension 231 and the second contact hole 221, with the thickness of the conductive extension 231 being less than that of the second contact hole 221. In this way, there is a certain distance between the conductive extension 231 and the topmost first metal strip 111, thereby avoiding the problem of short-circuiting when there are other metal strips between two adjacent first metal strips 111 on the top layer.

[0038] Understandably, the thickness of the conductive extension 231 should not be too thin, as this would make it difficult to significantly reduce the filling difficulty of the first connector 201. Conversely, the thickness of the conductive extension 231 should not be too thick, as this would cause it to be too close to the metal below, resulting in parasitic capacitance. Therefore, in some embodiments, the thickness of the conductive extension 231 can be 1 / 3 to 2 / 3 of the thickness of the second contact hole 221, preferably 1 / 2. Within this thickness range, the conductive extension 231 can greatly reduce the filling difficulty of the first connector 201 and increase its conductivity. Simultaneously, the conductive extension 231 can maintain a sufficient distance from the top-layer first metal strip 111, preventing parasitic capacitance between them.

[0039] Furthermore, all the first connectors 201 are located on the same layer, that is, the second metal strips 211 in all the first connectors 201 are located on the same layer, the second contact holes 221 in all the first connectors 201 are located on the same layer, and the conductive extensions 231 in all the first connectors 201 are also located on the same layer.

[0040] Please continue reading. Figure 1 The second connector 202 includes a third metal strip 212, which electrically connects to the bottommost first contact hole 121 of two adjacent test pieces 100. In this way, the second connector 202 can electrically connect two adjacent test pieces 100. The material of the third metal strip 212 can be the same as the material of the first metal strip 111, the first contact hole 121, the second metal strip 211, the conductive extension 231, and the second contact hole 221, for example, copper.

[0041] Furthermore, the second metal strips 211 of the first and last first connectors 201 can be electrically connected to a pad 300 respectively. By performing a WAT ​​test on the semiconductor test structure through these two pads 300, the filling quality of the device under test 100 can be detected. For example, by applying different voltages to the two pads 300, the resistance of the entire series structure can be obtained. If the resistance value is in a small range, it indicates that the filling quality of the device under test 100 is good; if the resistance value is large, it indicates that voids may have occurred in the device under test 100. Therefore, the semiconductor test structure in this application can test the filling quality of the device under test 100, thereby obtaining the filling quality of the metal interconnect structure formed synchronously with the device under test 100 within the device region. This achieves effective monitoring of the filling quality of contact holes in the metal interconnect structure. Moreover, this application is simple to implement and has extremely high detection efficiency.

[0042] Figure 3 This is a schematic diagram of another semiconductor test structure provided in an embodiment of this application. For example... Figure 3 As shown, the second metal strip 211 of each first connector 201 can be electrically connected to a pad 300. In this way, more pads 300 can provide greater redundancy for the semiconductor test structure. When the number of test pieces 100 is large, any two pads 300 can be selected for WAT testing. Furthermore, more pads 300 can also provide more test results for the semiconductor test structure, thereby facilitating the comparison between test results.

[0043] It should be noted that the semiconductor test structure can be fabricated on a substrate with a dielectric layer, and the first connector 201, the test piece 100 and the second connector 202 can all be located within the dielectric layer.

[0044] In summary, this embodiment provides a semiconductor test structure, including n+1 first connectors 201, 2n test pieces 100, and n second connectors 202, where n is greater than or equal to 2. The test pieces 100 are located between the first connectors 201 and the second connectors 202, and are connected in series sequentially according to a cyclical pattern of first connectors 201, test pieces 100, second connectors 202, test pieces 100, and first connectors 201. The test pieces 100 include at least one stacked structure 101, which includes a first metal strip 111 and a first contact hole 121. The first metal strip 111 is located on the first contact hole 121 and electrically connected to the first contact hole 121. The first connector 201 includes a second metal strip 211, a conductive extension 231, and two twin second contact holes 221. The second metal strip 211 is located on the conductive extension 231 and the second contact holes 221 and is electrically connected to the conductive extension 231 and the second contact holes 221. The conductive extension 231 is located between the two second contact holes 221 and is electrically connected to the two second contact holes 221. The two second contact holes 221 are respectively connected to the topmost first metal strip 111 of two adjacent test pieces 100. The second connector 202 includes a third metal strip 212, which is electrically connected to the bottommost first contact hole 121 of two adjacent test pieces 100. The unexpected effect of this application is that it can detect the filling quality of the test piece 100 by performing WAT testing on the semiconductor test structure, thereby obtaining the filling quality of the metal interconnect structure formed synchronously with the test piece 100 in the device area, realizing effective monitoring of the filling quality of the contact holes in the metal interconnect structure. Moreover, this application is simple and easy to implement, and has extremely high detection efficiency. Furthermore, by designing the first connector 201 as a twin hole structure and using the conductive extension 231 to electrically connect the two twin second contact holes 221, not only can the first connector 201 be better electrically connected to the first metal strip 111 of the top layer of the two adjacent test pieces 100, but it can also reduce the difficulty of filling the second contact holes 221 and improve the preparation efficiency of the first connector 201.

[0045] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0046] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0047] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0048] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A semiconductor testing structure, characterized in that, It includes n+1 first connectors, 2n test pieces, and n second connectors, where n is greater than or equal to 2. The test pieces are located between the first connectors and the second connectors and are connected in series in a cyclical pattern of the first connectors, the test pieces, the second connectors, the test pieces, and the first connectors. The test piece includes at least one stacked structure, the stacked structure including a first metal strip and a first contact hole, the first metal strip being located on the first contact hole and electrically connected to the first contact hole; The first connector includes a second metal strip, a conductive extension, and two twin second contact holes. The second metal strip is located on the conductive extension and the second contact holes and is electrically connected to the conductive extension and the second contact holes. The conductive extension is located between the two second contact holes and is electrically connected to the two second contact holes. The two second contact holes are respectively electrically connected to the first metal strips on the top layer of two adjacent test pieces. The second connector includes a third metal strip that electrically connects the first contact holes at the bottom layer of two adjacent test pieces.

2. The semiconductor test structure according to claim 1, characterized in that, The top surface of the conductive extension is flush with the top surface of the second contact hole, and the bottom surface of the conductive extension is located above the bottom surface of the second contact hole.

3. The semiconductor test structure according to claim 2, characterized in that, The thickness of the conductive extension is 1 / 3 to 2 / 3 of the thickness of the second contact hole.

4. The semiconductor test structure according to any one of claims 1 to 3, characterized in that, The second metal strip, the conductive extension, and the two second contact holes are an integral structure.

5. The semiconductor test structure according to claim 1, characterized in that, The ratio of the width of the second metal strip to the sum of the thickness of the second contact hole and the second metal strip is less than the ratio of the width of the first metal strip to the sum of the thickness of the first contact hole and the first metal strip.

6. The semiconductor test structure according to claim 1 or 5, characterized in that, The ratio of the width of the first metal strip to the sum of the thickness of the first contact hole and the first metal strip is greater than or equal to 5.

7. The semiconductor test structure according to claim 1, characterized in that, On the contact surface between the first metal strip and the first contact hole, the area of ​​the first metal strip is smaller than the area of ​​the first contact hole.

8. The semiconductor test structure according to claim 1, characterized in that, The second metal strip of the first and last first connectors is electrically connected to a solder pad, respectively.

9. The semiconductor test structure according to claim 1, characterized in that, The second metal strip of each of the first connectors is electrically connected to a pad.

10. The semiconductor test structure according to claim 1, characterized in that, The first metal strip, the first contact hole, the second metal strip, the conductive extension, and the second contact hole are all made of copper.

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