Silicon photonic package structure

Abstract

Some embodiments of the present application provide a silicon photonics packaging structure, comprising: a substrate; a photonic integrated circuit vertically disposed on the substrate; a wiring layer disposed above an upper surface and a side surface of the photonic integrated circuit, wherein the photonic integrated circuit is electrically connected to the substrate through the wiring layer at the side surface; and an optical transceiver element disposed on the upper surface of the photonic integrated circuit for transceiving optical signals. The present application can reduce the problem of excessive horizontal area of the silicon photonics packaging structure by vertically disposing the photonic integrated circuit on the substrate.

Description

Technical Field

[0001] The embodiments of this application relate to the semiconductor field, and more specifically, to silicon photonic packaging structures. Background Technology

[0002] As functional requirements continue to increase, the package size of existing SiPh (silicon photonics) is constantly increasing. The optical path is easily affected by offset, especially in large-size packages. The main reason for the need for large-size packages is that PIC (photonic integrated circuit) and EIC (electronic integrated circuit) are set on the same plane.

[0003] Specifically, in existing technologies used for SiPh applications, larger PKG (package structure) sizes are required for more functional PIC and EIC chips. For example... Figure 1 As shown in the encapsulation structure 10, PIC 12 and EIC 13 are attached to substrate 11 via adhesive layer 17, wherein sensor 18 is disposed on PIC 12. A support member 14 is disposed between PIC 12 and EIC 13 to support mirror 15. Furthermore, fiber optic array unit (FAU) 16, serving as a light source, is also attached to substrate 11 via adhesive layer 17, arranged side-by-side with PIC 12 and EIC 13. However, this encapsulation structure 10 arrangement will affect the designed optical path L, from... Figure 1 As can be seen, the light path L is reflected to the sensor 18. In some cases, the light path L is offset by the reflector 15 to become the light path L'. It can be seen that the actual path of the light path L is easily affected by the offset of the reflector 15.

[0004] In summary, in the existing package structure 10, the arrangement of PIC 12 and EIC 13 requires a larger size because PIC 12 and EIC 13 are located on the same plane, thus necessitating a larger package structure 10. Furthermore, the optical path L is easily affected; for example, a large path offset is always due to a large offset of the reflector (mirror 15). The root cause of this offset problem is that the accuracy of most current bonding technologies is limited to below ±2µm, and the impact increases with the size of the bonded devices in the package structure 10. In addition, the performance of this package structure 10 (e.g., yield, cost, manufacturing) is weaker. Utility Model Content

[0005] To address the aforementioned issues, this application reduces the problem of excessively large horizontal surface area by vertically mounting the PIC on the substrate.

[0006] Some embodiments of this application provide a silicon photonics packaging structure, including: a substrate; a photonic integrated circuit, vertically disposed on the substrate; a circuit layer disposed above the upper surface and side surface of the photonic integrated circuit, wherein the photonic integrated circuit is electrically connected to the substrate through the circuit layer at the side surface; and an optical transceiver element disposed on the upper surface of the photonic integrated circuit for receiving and transmitting light signals.

[0007] In some embodiments, the silicon photonic packaging structure further includes an electronic integrated circuit disposed on the substrate and arranged side by side with the photonic integrated circuit.

[0008] In some embodiments, the circuit layer defines a cavity.

[0009] In some embodiments, the optical transceiver element is disposed within the cavity.

[0010] In some embodiments, the silicon photonic packaging structure further includes an adhesive layer disposed between the side surface of the photonic integrated circuit and the substrate.

[0011] In some embodiments, the cavity has tapered sidewalls in a direction away from the upper surface.

[0012] In some embodiments, the height of the photonic integrated circuit is greater than the height of the electronic integrated circuit.

[0013] In some embodiments, the cavity is positioned at a height higher than that of the electronic integrated circuit.

[0014] In some embodiments, the circuit layer is disposed on the upper surface of the photonic integrated circuit facing the electronic integrated circuit.

[0015] In some embodiments, the circuit layer is disposed on the upper surface of the photonic integrated circuit opposite to the electronic integrated circuit.

[0016] In some embodiments, the electronic integrated circuit is bonded to the substrate by solder bonding.

[0017] In some embodiments, the electronic integrated circuit is bonded to the substrate by metal-to-metal bonding.

[0018] In some embodiments, the silicon photonic packaging structure further includes a molding layer that encapsulates the electronic integrated circuit and the photonic integrated circuit, wherein the molding layer has a recessed surface between the photonic integrated circuit and the electronic integrated circuit.

[0019] In some embodiments, a plurality of the photonic integrated circuits are vertically disposed on the substrate, and the optical transceiver elements disposed on the upper surface of the photonic integrated circuits are oriented in different directions.

[0020] In some embodiments, the silicon photonic packaging structure further includes a seed layer disposed on the side surface of the photonic integrated circuit.

[0021] In some embodiments, the optical transceiver element receives and transmits light signals horizontally above the electronic integrated circuit.

[0022] In some embodiments, the optical transceiver element includes a sensor and a light-emitting diode.

[0023] Some other embodiments of this application provide a silicon photonics packaging structure, including: a substrate; a photonic integrated circuit, vertically disposed on the substrate; an electronic integrated circuit, disposed side-by-side with the photonic integrated circuit on the substrate; a circuit layer disposed on the upper surface and side surface of the photonic integrated circuit; and an optical transceiver element disposed in the circuit layer on the upper surface of the photonic integrated circuit for receiving and transmitting light signals, wherein the optical transceiver element is disposed at a height higher than that of the electronic integrated circuit.

[0024] In some embodiments, the line layer defines a cavity, wherein the optical transceiver element is disposed within the cavity.

[0025] In some embodiments, the optical transceiver element receives and transmits light signals horizontally above the electronic integrated circuit.

[0026] This application vertically mounts the PIC (photonic integrated circuit) on the substrate 101, reducing the problem of excessively large horizontal area of ​​the packaging structure. Furthermore, the configuration of the silicon photonic packaging structure provided in this application eliminates the need for a reflector, allowing horizontally incident light to be directly transmitted using the space above the EIC (electronic integrated circuit), i.e., using horizontal light for direct coupling and transmission, which further effectively improves space utilization and simplifies the optical path. Attached Figure Description

[0027] The various aspects of this utility model can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0028] Figure 1 The packaging structure in the prior art is shown.

[0029] Figures 2 to 6 A silicon photonic packaging structure according to some embodiments of this application is shown.

[0030] Figures 7 to 36 as well as Figure 37A and Figure 37BThe process flow for forming silicon photonic packaging structures according to some embodiments of this application is shown. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art are within the scope of protection of this application. In addition, when using terms such as "approximately," "about," "substantial," or "basically" to describe numerical values ​​or numerical ranges, unless otherwise stated, the term is intended to cover values ​​within ±10% of the described value. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0032] This application reduces the problem of excessive horizontal area by vertically setting the PIC on the substrate. Furthermore, this configuration eliminates the need for a reflector, allowing horizontally incident light to be transmitted directly using the space above the EIC, further improving space utilization and simplifying the optical path.

[0033] See Figure 2 Some embodiments of this application provide a silicon photonics package structure 100, which includes a substrate 101; a PIC 102 vertically disposed on the substrate 101; and a circuit layer 103. Figure 2 As can be seen, the circuit layer 103 is disposed above the upper surface 102t and the side surface 102s of the PIC 102. Figure 2In the illustrated embodiment, the PIC 102 is electrically connected to the substrate 101 via a wiring layer 103 on its side surface 102s. In this application, by vertically positioning the PIC on the substrate, the problem of excessively large horizontal area is reduced. In a further embodiment, the wiring layer 103 includes a first portion 103A disposed above the upper surface 102t of the PIC 102 and a second portion 103B disposed above the side surface 102s of the PIC 102. The PIC 102 is electrically connected to the substrate 101 via the second portion 103B of the wiring layer (RDL) 103. In some embodiments, the second portion 103B of the wiring layer 103 is a terminal, or it may be a semi-through hole. In some embodiments, the silicon photonics package structure 100 further includes an optical transceiver element 104 disposed on the upper surface 102t of the PIC 102 for receiving and transmitting light signals Lg. Specifically, the optical transceiver element 104 includes a sensor (Rx) 104A for receiving light and a light-emitting diode (LED, Tx) 104B for emitting light. In some embodiments, the circuit layer 103 defines a cavity C, and the optical transceiver element 104 is disposed within the cavity C. In some embodiments, the cavity C has tapered sidewalls in a direction H away from the upper surface. That is, as... Figure 2 As shown, the cavity C has a trapezoidal shape and a smaller width (in the vertical direction perpendicular to direction H) on the side furthest from the upper surface 102t. This structure of cavity C prevents or reduces light interference because it has beveled sides that are suited to the characteristics of light, as light is attenuated when guided into the photoresist (forming beveled edges). Furthermore, the smaller opening size of cavity C (smaller width on the side furthest from the upper surface 102t) makes it less susceptible to interference from adjacent light, preventing adjacent light from being guided to the beveled metal sides within the cavity and causing mutual interference. This smaller opening size (and corresponding beveled sides) reduces such light interference.

[0034] In some embodiments, the first portion 103A of the circuit layer 103 includes a dielectric layer 103L and metal lines and vias 103M disposed in the dielectric layer 103L. In some embodiments, the dielectric layer 103L includes polyimide, imide, etc., and the metal lines and vias 103M include a metal such as copper. In some embodiments, the silicon photonics package structure 100 further includes a seed layer 112 disposed on a side surface 102s of the PIC 102, and a second portion 103B of the circuit layer 103 is disposed on the seed layer 112. In some embodiments, the first portion 103A of the circuit layer 103 is connected to a pad 102P on the upper surface 102t of the PIC 102. In some embodiments, the second portion 103B of the circuit layer 103 extends through a corner portion of the PIC 102.

[0035] Further as Figure 2 As shown, the silicon photonic packaging structure 100 also includes an EIC 105 disposed on a substrate 101, and the EIC 105 is disposed side by side with the PIC 102. In this application, the height of the PIC 102 is greater than the height of the EIC 105 because the PIC 102 is vertically disposed on the substrate, and the cavity C defined in the circuit layer 103 above the upper surface 102t of the PIC 102 is also disposed at a height higher than the EIC 105, so that the optical transceiver element 104 in the cavity C receives and transmits light signals Lg at a height higher than the EIC 105, that is, the light signal Lg is exposed to the environment and can be incident horizontally. Figure 2 As shown, the optical transceiver element 104 horizontally receives and transmits the optical signal Lg above the EIC 105. Figure 2 In the illustrated embodiment, the circuit layer 103 (the first portion 103A) is disposed on the upper surface 102t of the PIC 102 facing the EIC 105. In some embodiments, Figure 2 The silicon photonics packaging structure 100 shown is designed to minimize the volume of the corresponding packaging structure.

[0036] also, Figure 2 The illustrated silicon photonics package structure 100 further includes an adhesive layer 106 disposed between the side surface 102s of the PIC 102 and the substrate 101. In some embodiments, the adhesive layer 106 is a metal layer such as copper and is disposed on a corresponding seed layer 106s. In some embodiments, the EIC 105 is bonded to the substrate 101 by solder bonding, specifically, the EIC 105 is bonded to the substrate 101 by solder bumps (microbumps) 107 to pads 105P on the EIC 105 and pads 101P on the substrate 101. In some embodiments, pads 105P and pads 101P are disposed on corresponding seed layers. Figure 2 As can be seen, corresponding solder bumps 107 are also provided around the adhesive layer 106.

[0037] Furthermore, the silicon photonics packaging structure 100 also includes a molding layer 108 for encapsulating the PIC 102 and EIC 105. In some embodiments, the molding layer 108 may include molding compound, underfill, etc. Figure 2As can be seen, the molding layer 108 has a recessed surface between the PIC 102 and the EIC 105. Furthermore, the silicon photonic package structure 100 also includes a heat sink 109 disposed on the back side of the EIC 105 for heat dissipation. Additionally, the PIC 102 is encapsulated by a molding compound (CPD) 110 for better protection. In some embodiments, the molding compound 110 is made of materials such as molding compounds, underfills, etc. In some embodiments, the silicon photonic package structure 100 also includes a connector 111 disposed on the side of the substrate 101 opposite to the PIC 102 and EIC 105. In some embodiments, the connector 111 may be an external connector and may be a solder ball. Further, the connector 111 may be formed on a corresponding pad 111P.

[0038] In the above embodiments, the molding compound 110, molding layer 108, and dielectric layer 103L in the silicon photonics packaging structure 100 can be made of non-metallic materials, including but not limited to materials such as PI (polyimide), epoxy resin, ABF (Ajinomoto reinforced film), PP (polypropylene) and / or acrylic acid, and can also be organic photosensitive and / or non-photosensitive liquids and / or dry film materials. In some embodiments, the heat sink 109, the metal lines and vias 103M in the first portion 103A of the circuit layer 103, the second portion 103B of the circuit layer 103, the pads 105P, 101P, 102P, and 111P, and the seed layers (such as seed layers 106s and 112) can be made of metallic materials such as copper, gold, silver, aluminum, palladium, platinum, and nickel alloys, and the solder bumps 107 and connectors 111 can be made of solder, ACP (anisotropic conductive adhesive) / ACF (anisotropic conductive film).

[0039] Next, see Figure 3 , Figure 3 It shows Figure 2 The dimensions of the various components of the silicon photonics packaging structure 100 shown are important for ease of understanding. Figure 3 Only some components of the silicon photonics package structure 100 are marked. Furthermore, in Figure 3 The diagram shows the horizontal direction S containing direction H and the vertical direction D perpendicular to both direction H and the horizontal direction S. See also... Figure 3The width / length of EIC 105 in the horizontal direction S ranges from tens of μm to tens of mm, and the thickness (ECT) of EIC 105 in the vertical direction D ranges from 10 μm to 500 μm. The width / length of PIC 102 in the vertical direction D ranges from tens of μm to several mm, and the thickness (PCT) of PIC 102 in the horizontal direction S ranges from 10 μm to 100 μm. The thickness (HST) of heat sink 109 in the vertical direction D ranges from 5 μm to 50 μm, and the opening size (COS) of the cavity C ranges from 5 μm to 100 μm. Furthermore, the distance / gap (DEC) in the vertical direction D from the edge of EIC 105 to the cavity C is between 5 μm and 100 μm; the distance (CTP) in the horizontal direction S from the surface of the circuit layer 103 on the upper surface 102t of PIC 102 to the edge of EIC 105 is between 5 μm and 20 μm; the gap (GSP) in the vertical direction D between the surface of substrate 101 and the edge of PIC 102 (the bottom surface of the second portion 103B of circuit layer 103) is between 5 μm and 20 μm; the gap (GSE) in the vertical direction D between the surface of substrate 101 and the surface of EIC 105 is between 5 μm and 20 μm; the thickness (TPC) of PIC 102 having molding compound (CPD) 110 in the horizontal direction S is between 20 μm and 200 μm; and the PIC The second part 103B (edge ​​connector) of the circuit layer 103 on the side surface of 102 has a dimension (PES) in the vertical direction D between 5 μm and 500 μm.

[0040] Next, see Figure 4 , Figure 4 A silicon photonics packaging structure 200 according to some embodiments is shown, which is related to... Figure 2 The silicon photonics packaging structure shown is similar to 100, except that... Figure 4 In the silicon photonics package structure 200 shown, the upper surface 102t of PIC 102 is disposed away from EIC 105, the circuit layer 103 (first part 103A) is disposed on the upper surface 102t of PIC 102 away from EIC 105, and the cavity C is also disposed away from EIC 105, and the cavity C has tapered sidewalls in the direction H away from the upper surface.

[0041] See Figure 5 , Figure 5 A silicon photonics packaging structure 300 according to some embodiments is shown, which is related to... Figure 2The silicon photonic packaging structure 100 shown is similar, except that multiple PICs 102 are vertically arranged on the substrate 101, and the optical transceiver elements 104 arranged on the upper surface 102t of the PICs 102 face different directions. Therefore, Figure 2 The silicon photonics packaging structure 100 shown is a single-edge design, while Figure 5 The silicon photonics package structure 300 shown is a multi-edge design to make the design more flexible and to simultaneously transmit and receive optical signals from different light sources.

[0042] See Figure 6 , Figure 6 A silicon photonics packaging structure 400 according to some embodiments is shown, which is related to... Figure 2 The silicon photonics packaging structure shown is similar to 100, except that... Figure 2 The EIC 105 shown is bonded to the substrate 101 via solder bumps 107, while for Figure 6 The silicon photonics package structure 400 shown has an EIC 105 that is directly bonded to the substrate 101 via metal-to-metal bonding of pads 101P and 105P, and no solder bumps 107 are formed under the PIC 102.

[0043] In summary, the silicon photonic packaging structure 100-400 of this application provides excellent performance in terms of efficiency and miniaturization for SiPh packaging structure applications using the following two methods: one is to directly pass light (optical signal Lg) through the space above EIC 105 to generate a shorter optical path; the other is that the silicon photonic packaging structure 100 involves the absence of a reflector. In this application, PIC 102 is a full-length design, and the cavity C is formed by a line layer (RDL) 103 fabricated on PIC 102.

[0044] Secondly, the molding compound 110 encapsulating the PIC 102 provides sufficient area to cover the PIC 102 for fabricating the terminals (semi-vias) (second portion 103B of the circuit layer 103), the RDL (first portion 103A of the circuit layer 103), and the cavity C design. Direct light includes the transmission of optical signals between Rx (sensor 104A, incident on the cavity) and Tx (LED 104B, emitted from the cavity).

[0045] Furthermore, the EIC 105 has a heat sink 109 on its back side, which directs heat upwards to the environment, thereby enhancing and advantageously improving the heat dissipation of the silicon photonic package structure 100. The molding layer 108 protects the solder bumps (microbumps) 107 and the second portion 103B (terminal) of the circuit layer 103, etc. In addition, the silicon photonic package structure 100 also supports the full-length PIC 102 for direct optical transmission.

[0046] Finally, the overall WL (wafer-level) (or PNL (panel-level)) manufacturing integrates EIC 105, PIC 102 and substrate 101, achieving a low-cost solution.

[0047] Return to reference Figure 2 Other embodiments of this application provide a silicon photonics package structure 100, which includes: a substrate 101; a PIC 102 vertically disposed on the substrate 101; an EIC 105 disposed side-by-side with the PIC 102 on the substrate 101; a circuit layer 103 disposed on the upper surface 102t and side surfaces 102s of the PIC 102; and an optical transceiver element 104 disposed in the circuit layer 103 on the upper surface 102t of the PIC 102 for receiving and transmitting light signals, wherein the optical transceiver element 104 is disposed at a height above the EIC 105. In some embodiments, the circuit layer 103 defines a cavity C, and the optical transceiver element 104 is disposed within the cavity C.

[0048] The following reference Figures 7 to 36 Let me introduce Figure 2 The process for forming the silicon photonic packaging structure 100 shown.

[0049] See Figure 7 A carrier 1001 is prepared or provided, wherein a release layer 1002 is formed on the carrier 1001. The carrier 1001 may be a glass carrier substrate, a ceramic carrier substrate, etc. The release layer 1002 may be formed of a polymer-based material, which may be removed together with the carrier 1001 from the above structure formed in a subsequent step. In some embodiments, the release layer 1002 is a heat-release material based on epoxy resin, such as a photothermal conversion (LTHC) release coating, which loses its adhesiveness upon heating. In other embodiments, the release layer 1002 may be a UV adhesive, which loses its adhesiveness upon exposure to UV light.

[0050] See Figure 8 This illustrates the assembly manufacturing of the PIC 102. (As shown) Figure 8 As shown, multiple PICs 102 are bonded to a carrier 1001. Pads 102P and optical transceiver elements 104 are formed on the upper surface 102t of each PIC 102. The optical transceiver element 104 includes a sensor (Rx) 104A for receiving light and a light-emitting diode (Tx) 104B for emitting light. See also... Figure 9 A molding compound 110 is formed on PIC 102, such as by a molding process. After forming the molding compound 110, an opening 101o is formed in the molding compound 110 by a laser drilling process P1, resulting in a structure as shown in the image. Figure 10 As shown. See also Figure 10After the opening 101o is formed, a seed layer 112 is formed on the surface of the molding compound 110 and in the opening 101o by a process such as physical vapor deposition (PVD), for example using copper.

[0051] See Figures 11 to 12 A photoresist (PR) 1003 is formed above the seed layer 112, such as through a coating process. A photolithography process P2, involving exposure and development, is performed on the photoresist 1003, thereby forming [the desired structure / structure]. Figure 12 The opening shown exposes an opening 101o formed in the molding compound 110, thereby forming a new opening 101o'. Continuing to refer to... Figure 12 A conductive material, such as copper, is plated into the opening 101o' through a plating process to form a through hole 103B'.

[0052] See Figure 13 The photoresist 1003 is removed by a process such as stripping, and the portion of the seed layer 112 not covered by the via 103B' is etched to obtain the desired result. Figure 13 The structure shown. See also... Figure 14 Remove carrier 1001, such as by debonding carrier 1001. Next, see... Figures 15 to 16 For example, photoresist 1004 is formed on the upper surface 102t of PIC 102 by a coating process, and then a photolithography process P4 of exposure and development is performed on the photoresist 1004, thereby forming the photoresist 1004 into a... Figure 16 The trapezoidal shape shown, which is narrower at the top and wider at the bottom, corresponds to the shape of the cavity C that will be formed later.

[0053] See Figures 17 to 18 A dielectric layer 103L is formed on the upper surface 102t of PIC 102 using a PI (polyimide) coating process. A photolithography process P5, involving exposure and development, is then performed on the dielectric layer 103L to create openings, such as... Figure 18 As shown. See also Figure 18 A seed layer 103s is formed on the dielectric layer 103L, such as through a PVD process. See also Figures 19 to 20 Photoresist 1005 is formed on the seed layer 103s using processes such as lamination. A photolithography process P5, involving exposure and development, is then performed on the photoresist 1005 to form openings. (Continue to see...) Figure 20 Metal lines and vias 103M are deposited in the openings of the photoresist 1005 using a plating process, employing a metal such as copper. See also Figure 21 Remove the photoresist 1005 and etch the portion of the seed layer 103s not covered by the metal lines and vias 103M.

[0054] Then repeat Figures 17 to 21The steps are used to form a multilayer RDL, thereby forming the first portion 103A of the line layer 103 of the desired thickness. Figure 22 The formation of the last metal line and via 103M in the first portion 103A of the circuit layer 103 is shown. It should be noted that the height of the trapezoidal photoresist 1004 is greater than the height of the first portion 103A of the circuit layer 103.

[0055] See Figures 23 to 24 The photoresist 1004 is removed using a commonly used etching process P6, such as oxygen plasma etching, thereby forming a layer in the first portion 103A of the circuit layer 103. Figure 24 Cavity C is shown. From Figure 24 As can be seen from the image, cavity C exposes the optical transceiver element 104.

[0056] Next, see Figures 25 to 26 Cutting is performed using a cutting process 1006, such as using a blade. Figure 24 The structure shown forms a single PIC 102 package with a first portion 103A and a second portion 103B of a circuit layer 103 respectively formed on its respective surface. Figure 26 As shown, a single PIC 102 package is picked up and manufactured.

[0057] See Figure 27 A substrate 101 is provided or prepared, on which seed layers 106s and pads 111P are formed respectively on opposite surfaces. In some embodiments, the substrate 101 can be any suitable substrate, such as a silicon substrate.

[0058] See Figure 28 and Figure 29 Photoresist 1007 is formed on the seed layer 106s using processes such as lamination. A photolithography process P7, involving exposure and development, is then performed on the photoresist 1007 to form openings. (Continue to see...) Figure 29 A metal such as copper is used in a plating process to sequentially plate copper pads 101P and solder bumps 107 into the openings of the photoresist 1007, as well as a copper adhesive layer 106 and solder bumps 107 for attaching the PIC 102. See also Figure 30 Remove the photoresist 1007 and etch the portion of the seed layer 106s that is not covered by the pads 101P, the adhesive layer 106, and the solder bumps 107.

[0059] See Figure 31 This illustrates the bonding fabrication of EIC 105. (As shown) Figure 31As shown, the EIC 105, on which the heat sink 109 is formed, is bonded to the substrate 101 by bonding the pads 105P on the EIC 105 to the solder bumps 107. See also Figure 32 It shows Figure 26 The diagram shows the assembly fabrication of a single PIC 102 package, including the PIC 102. (As shown) Figure 32 As shown, the second portion 103B and the side portion 103A of the circuit layer 103 on the side surface 102s of the PIC 102 are bonded to the adhesive layer 106 and solder bump 107 on the substrate 101 to bond the PIC 102. Then, as... Figure 33 As shown, the solder bumps 107 are reflowed by performing a solder reflow process P8, such as heating, thereby bonding the EIC 105 and PIC 102 to the substrate 101.

[0060] Next, see Figure 34 The molding seal layer 108 of the molding seals EIC 105 and PIC 102 is formed using a manufacturing process such as capillary underfill (CUF) protection, such as by using an underfill or molding compound, and in some embodiments, by using a molding process. After forming the molding seal layer 108, see [link to documentation]. Figure 35 ,Will Figure 34 The resulting structure is flipped, and a connector 111, such as a solder ball, is formed on the pad 111P using a ball placement process for external connection. Finally, as Figure 36 As shown, Figure 35 The resulting structure is flipped and then cut using a sawing process P9. Figure 35 The resulting structure is sawn to obtain Figure 2 The silicon photonics packaging structure 100 shown is illustrated.

[0061] Figure 37A and Figure 37B A top view of the carrier 1001 is shown, from Figure 37A and Figure 37B It can be seen that carriers 1001 of different shapes can be used, such as the carrier 1001 used can be as follows: Figure 37A The square shape shown can also be Figure 37B The circular shape shown.

[0062] In the aforementioned manufacturing process, after dicing (e.g., dicing PIC 102 first), PIC 102 is picked up from the SiPh functional wafer and embedded in a PNL (or WL) molding compound (CPD) 110. The multilayer RDL of the first portion 103A of the circuit layer 103 and the through-holes (semi-through-holes) of the second portion 103B are fabricated from the surface of the PNL molding compound (CPD) 110 using photolithography and plating processes. Figures 25 to 26 As shown, a PIC 102 package with a circuit layer 103 is formed by cutting a PNL molding compound (CPD) 110. In each PIC 102 package, a cavity C is fabricated in the RDL (redistribution) structure of the first portion 103A of the circuit layer 103 to provide space for the transmission of optical signals between Rx (sensor 104A) and Tx (LED 104B). At one edge of the PIC 102 (side surface 102s), a terminal (semi-through hole) (the second portion 103B of the circuit layer 103) is formed by cutting through-holes for interconnection. The aforementioned through-holes for interconnection are fabricated within the structure of the PNL molding compound (CPD) 110.

[0063] Next, EIC 105 is formed after the electrical functional chip is cut (not shown). Then, it (EIC 105) is bonded to the substrate 101 (PNL or WL) by the connection between solder bumps 107 and pads 101P and 105P (or metal to metal), and a thermal pad is attached to the back of EIC 105 as a heat sink 109.

[0064] Finally, the PIC 102 package is soldered onto the substrate 101 via solder terminals (second portion 103B of circuit layer 103), the edges of the top RDL lines (first portion 103A of circuit layer 103), and solder bumps 107 on the substrate 101. A molding layer 108 is formed using underfill CUF to protect all connectors and secure the EIC 105 and the full-length PIC 102. After placing connectors 111, such as solder balls, on the bottom side of the substrate 101 (the side opposite the EIC 105 and PIC 102) and performing sawing, the silicon photonic package structure 100 is formed.

[0065] In the above-mentioned forming process, in addition to the methods mentioned, the heat sink 109, the first part 103A of the circuit layer 103 on the PIC 102, the terminal (semi-through hole) (the second part 103B of the circuit layer), the pad 105P, the pad 101P, the seed layer 112, the connector 111 and the solder bump 107 can all be manufactured using different manufacturing processes such as PVD, electroplating, chemical plating, printing, and metal potting.

[0066] In summary, this application vertically positions the PIC 102 on the substrate 101, reducing the problem of excessively large horizontal area of ​​the packaging structure. Furthermore, by adopting the above-mentioned silicon photonic packaging structure 100-400 configuration, a reflector is not required. Horizontal incident light (optical signal Lg) can be directly transmitted using the space above the EIC 105 (optical transceiver element 104 includes Rx 104A and Tx 104B). That is, horizontal light is directly coupled and transmitted, further effectively improving space utilization and simplifying the optical path.

[0067] The features of several embodiments have been summarized above to enable those skilled in the art to better understand aspects of the present invention. Those skilled in the art should understand that they can readily use the present invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present invention.

Claims

1. A silicon photonics packaging structure, comprising: substrate; Photonic integrated circuits are vertically disposed on the substrate; A circuit layer is disposed above the upper surface and side surface of the photonic integrated circuit, wherein the photonic integrated circuit is electrically connected to the substrate through the circuit layer at the side surface; as well as An optical transceiver element is disposed on the upper surface of the photonic integrated circuit for receiving and transmitting optical signals.

2. The silicon photonic packaging structure according to claim 1 further includes: An electronic integrated circuit is disposed on the substrate and arranged side by side with the photonic integrated circuit.

3. The silicon photonic packaging structure according to claim 2, wherein, The circuit layer defines the cavity.

4. The silicon photonic packaging structure according to claim 3, wherein, The optical transceiver element is disposed within the cavity.

5. The silicon photonic packaging structure according to claim 3, wherein, The cavity has tapered sidewalls in the direction away from the upper surface.

6. The silicon photonic packaging structure according to claim 2, wherein, The height of the photonic integrated circuit is greater than the height of the electronic integrated circuit.

7. The silicon photonic packaging structure according to claim 3, wherein, The cavity is positioned at a height higher than that of the electronic integrated circuit.

8. The silicon photonic packaging structure according to claim 2, wherein, The circuit layer is disposed on the upper surface of the photonic integrated circuit facing the electronic integrated circuit.

9. The silicon photonic packaging structure according to claim 2, wherein, The optical transceiver element receives and transmits light signals horizontally above the electronic integrated circuit.

10. A silicon photonics packaging structure, comprising: substrate; A photonic integrated circuit is vertically disposed on the substrate; An electronic integrated circuit is disposed side-by-side with the photonic integrated circuit on the substrate; A circuit layer is disposed on the upper surface and side surface of the photonic integrated circuit; as well as An optical transceiver element is disposed in a circuit layer on the upper surface of the photonic integrated circuit for receiving and transmitting optical signals. The optical transceiver element is positioned at a height higher than that of the electronic integrated circuit.

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