Semiconductor device

Abstract

A semiconductor device includes a substrate having a semiconductor fin, a first transistor above the substrate, and a second transistor vertically above the first transistor. The first transistor includes a first gate structure above the semiconductor fin, where in a cross-sectional view, the semiconductor fin includes a channel portion in contact with a bottom surface of the first gate structure, and source / drain portions on opposite sidewalls of the first gate structure. The second transistor includes a semiconductor channel layer above the semiconductor fin, a second gate structure above the semiconductor channel layer, and source / drain epitaxial structures on opposite ends of the semiconductor channel layer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] The integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have resulted in several generations of ICs. Each generation features smaller and more complex circuits than the previous one. However, these advancements increase the complexity of handling and manufacturing ICs. In the evolution of ICs, functional density (i.e., the number of interconnects per wafer area) generally increases, while geometry (i.e., the smallest component (or wiring) that can be produced using manufacturing processes) decreases. This scaling down generally provides benefits by increasing production efficiency and reducing associated costs. However, as feature sizes continue to shrink, manufacturing processes continue to become more difficult. Therefore, forming reliable semiconductor devices in increasingly smaller dimensions remains a challenge.

[0003] As the semiconductor industry progresses towards higher technology nodes, pursuing greater device density, higher performance, and lower costs, the challenges in both manufacturing and design have led to stacked device structure configurations, such as complementary field-effect transistors (C-FETs), where n-type multi-gate transistors and p-type multi-gate transistors are stacked vertically, one on top of the other. While existing C-FET structures are generally sufficient, they are not satisfactory in all configurations. Utility Model Content

[0004] A semiconductor device includes: a substrate having a semiconductor fin; a first transistor above the substrate and including a first gate structure above the semiconductor fin, wherein in a cross-sectional view, the semiconductor fin includes a channel portion contacting a bottom surface of the first gate structure; and source / drain portions on a plurality of opposing sidewalls of the first gate structure; and a second transistor perpendicularly above the first transistor and including: a semiconductor channel layer above the semiconductor fin; a second gate structure above the semiconductor channel layer; and a source / drain epitaxial structure on a plurality of opposing ends of the semiconductor channel layer.

[0005] A semiconductor device includes: a substrate having a semiconductor fin; a first transistor above the substrate and including a first gate structure having a portion embedded in the semiconductor fin; a source / drain intersecting with a portion of the semiconductor fin; and a second transistor perpendicularly above the first transistor and including: a semiconductor channel layer above the semiconductor fin; a second gate structure above the semiconductor channel layer; and a source / drain epitaxial structure at a plurality of opposite ends of the semiconductor channel layer.

[0006] A semiconductor device includes: a substrate having a semiconductor fin; a first transistor above the substrate and including a first gate structure above the semiconductor fin, wherein in a cross-sectional view, the semiconductor fin includes a channel portion contacting a bottom surface of the first gate structure; and a source / drain portion on a plurality of opposing sidewalls of the first gate structure; and a second transistor perpendicularly above the first transistor and including: a semiconductor channel layer above the semiconductor fin; a second gate structure above the semiconductor channel layer; and a source / drain epitaxial structure on a plurality of opposing ends of the semiconductor channel layer, wherein the first gate structure is in contact with the second gate structure. Attached Figure Description

[0007] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figures 1A to 16E The figures illustrate methods for forming semiconductor devices at various stages according to some embodiments of the present disclosure;

[0009] Figure 17 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0010] Figure 18 The figure shows a circuit diagram of a static random access memory (SRAM) cell according to some embodiments of the present disclosure;

[0011] Figure 19 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0012] Figure 20 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;

[0013] Figure 21 and Figure 22 These are simulation results of a semiconductor device based on some embodiments of this disclosure.

[0014] [Symbol Explanation]

[0015] 10: Memory Unit

[0016] 100:Substrate

[0017] 100CH: Channel Section

[0018] 100F: Semiconductor fin

[0019] 100SD: Source / Drain Section

[0020] 102: Semiconductor layer

[0021] 102A~102B: Semiconductor layer

[0022] 104A~104B: Semiconductor layer

[0023] 105: Isolation Structure

[0024] 110F: Isolation Structure

[0025] 115: Gate spacer

[0026] 116: Internal spacers

[0027] 120: Dummy gate structure

[0028] 122: Dummy gate dielectric

[0029] 124: Dummy gate electrode

[0030] 130: Isolation layer

[0031] 135: Source / Drain

[0032] 140: Isolation layer

[0033] 150A~150C: Source / Drain epitaxial structure

[0034] 155: Source / Drain Contact

[0035] 155A~155B: Source / Drain Contacts

[0036] 160: ILD layer

[0037] 170: Metal gate structure

[0038] 170A~170B: Metal gate structure

[0039] 172: Gate dielectric layer

[0040] 174: Work Function Metal Layer

[0041] 176: Gate fill metal

[0042] 180: Source / Drain via

[0043] 180A~180C: Source / Drain vias

[0044] 270: Metal gate structure

[0045] 270A~270B: Metal gate structure

[0046] 272: Gate dielectric layer

[0047] 274: Work function metal layer

[0048] 276: Gate fill metal

[0049] FN: Fin structure

[0050] GT1: Gate Trench

[0051] H1: Height

[0052] Inverter-1: Inverter (Inverter-1)

[0053] Inverter-2: Inverter (Inverter-2)

[0054] L1: Gate length

[0055] n1~n2: Nodes

[0056] O1: Opening

[0057] R1: Groove

[0058] ST: Semiconductor Stacking Detailed Implementation

[0059] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0060] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly. As used herein, “approximately,” “about,” “approximately,” or “substantially” generally means within 20%, 10%, or 5% of a given value or range. The values ​​given herein are approximate, meaning that unless explicitly stated otherwise, the terms “approximately,” “about,” “approximately,” or “substantially” can be inferred. However, those skilled in the art will recognize that the values ​​or ranges referenced throughout the description are merely examples and may decrease or vary as the scale of integrated circuits shrinks.

[0061] Gate all-around (GAA) transistor structures can be patterned using any suitable method. For example, the structure can be patterned using one or more optical lithography processes, including dual-patterning or multi-patterning processes. Generally, dual-patterning or multi-patterning processes combine optical lithography with self-alignment processes, thereby allowing the production of patterns with, for example, smaller pitches than that achievable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0062] Figures 1A to 16E The illustrations depict various stages of a method for forming a semiconductor device according to some embodiments of this disclosure. Although Figures 1A to 16E The description is a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are applicable to other structures. In other embodiments, some of the actions illustrated and / or described may be omitted, in whole or in part.

[0063] refer to Figure 1A and Figure 1B ,in Figure 1A This is a top view of a semiconductor device. Figure 1B It is along Figure 1AA cross-sectional view along line C1-C1 is shown, illustrating substrate 100. Generally, substrate 100 may comprise a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer, which is the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor generally comprise crystalline semiconductor materials such as germanium (Ge) or silicon (Si). Other suitable semiconductor materials may include silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, and the like), or alloys thereof (e.g., Ga...). x Al 1-x As, Ga x Al 1-x N、In x Ga 1-x As, and the like), or combinations thereof. In some embodiments, the substrate 100 is undoped.

[0064] A semiconductor layer 104A is formed over a substrate 100. In some embodiments, the semiconductor layer 104A may be a doped semiconductor layer. For example, the semiconductor layer 104A may include a p-type dopant or an n-type dopant. In some embodiments, exemplary p-type dopant may include boron (B), gallium (Ga), indium (In), aluminum (Al), or the like. In some embodiments, exemplary n-type dopant may include phosphorus (P), arsenic (As), or antimony (Sb), or the like. The semiconductor layer 104A may be formed over the substrate 100 using a suitable deposition process, such as selective epitaxial growth (SEG), such that the semiconductor layer 104A can be selectively grown on a semiconductor material, such as the substrate 100. In some embodiments, an implantation process may be performed during or after the formation of the semiconductor layer 104A to dope the semiconductor layer 104A.

[0065] For p-type devices, substrate 100 may be a germanium (Ge) layer, and semiconductor layer 104A may be a semiconductor material with p-type dopant, such as a boron-doped germanium (Ge:B) layer. On the other hand, for n-type devices, substrate 100 may be a silicon layer, and semiconductor layer 104A may be a semiconductor material with n-type dopant, such as a phosphorus-doped silicon (Si:P) layer. Semiconductor layer 104A can be used as a solid-phase dopant source for subsequent solid-phase diffusion processes. In some embodiments, semiconductor layer 104A and substrate 100 may comprise the same material.

[0066] refer to Figure 2A and Figure 2B ,in Figure 2A This is a top view of a semiconductor device. Figure 2B It is along Figure 2AA cross-sectional view along line C1-C1. After forming the semiconductor layer 104A, a thermal annealing process is performed. The annealing process allows solid-phase diffusion (driving) of the dopant in a solid-phase dopant source (e.g., semiconductor layer 104A), such that the dopant in semiconductor layer 104A is driven into substrate 100. For example, when semiconductor layer 104A includes a p-type dopant, the p-type dopant can be driven from semiconductor layer 104A into substrate 100. Similarly, when semiconductor layer 104A includes an n-type dopant, the n-type dopant can be driven from semiconductor layer 104A into substrate 100. In some embodiments, the doped regions in substrate 100 may include a gradient concentration due to the thermal annealing process. For example, the dopant may include a maximum concentration at the top surface of substrate 100, and the dopant concentration may decrease downward toward the bottom surface of substrate 100.

[0067] refer to Figure 3A and Figure 3B ,in Figure 3A This is a top view of a semiconductor device. Figure 3B It is along Figure 3A A cross-sectional view of line C1-C1. In Figure 2A and Figure 2B After the thermal annealing process is completed, semiconductor layers 102 and 104B are alternately deposited over semiconductor layer 104A to form a semiconductor stack (ST). In some embodiments, the semiconductor stack (ST) may include semiconductor layers 102, 104A, and 104B. In some embodiments, semiconductor layers 102 and 104B may be deposited using suitable deposition processes, such as selective epitaxial growth (SEG), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable processes(s). Semiconductor layer 102 may be used as a channel layer of a semiconductor device, and may also be referred to as a semiconductor channel layer. Semiconductor layers 104A and 104B may be removed during a replacement gate (RPG) process, therefore semiconductor layers 104A and 104B may also be referred to as sacrificial layers, with semiconductor layer 104A being the bottom sacrificial layer.

[0068] In some embodiments, the semiconductor layer 102 may include a channel material, such as silicon (Si), germanium (Ge), tin (Sn), or silicon-germanium (Si). 1-x Ge x germanium-tin (Ge) 1-y Sn y ), silicon-germanium-tin (Si)1-x-y Ge x Sn y III-V materials, or other suitable channel materials. In some embodiments, semiconductor layer 102 may include a material different from semiconductor layers 104A and 104B, thereby providing sufficient etch selectivity for semiconductor layers 104A and 104B.

[0069] In some embodiments, semiconductor layer 104B may comprise the same or similar material as semiconductor layer 104A. As described above, semiconductor layer 104A may be doped with p-type or n-type dopants for solid-phase diffusion, while semiconductor layer 104B may not contain the p-type or n-type dopants found in semiconductor layer 104A. For example, in some embodiments, semiconductor layer 104A may be a germanium layer doped with boron (B), and semiconductor layer 104B may be a germanium layer that is substantially free of boron (B).

[0070] refer to Figures 4A to 4C Among them, respectively, Figure 4A This is a top view of a semiconductor device. Figure 4B For along Figure 4A The cross-sectional view of line C1-C1, and Figure 4C For along Figure 4A A cross-sectional view along line C2-C2. The substrate 100 and the semiconductor stack ST are patterned to form a fin structure FN. In some embodiments, a mask (not shown) is formed over the semiconductor stack ST, wherein the mask defines the location and outline of the fin structure FN. An etching process is performed to remove portions of the semiconductor stack ST and the substrate 100 exposed via the mask, leaving the remaining portions of the semiconductor stack ST and the substrate 100 as the fin structure FN. Once the fin structure FN is formed, the mask is removed. In some embodiments, after the patterning process, the substrate 100 may include semiconductor fins 100F. The fin structure FN may include the remaining portions of the semiconductor stack ST and the semiconductor fins 100F.

[0071] An isolation structure 105 is formed above the substrate 100 and laterally surrounds the lower portion of the semiconductor fin 100F. In some embodiments, the isolation structure 105 may contact the sidewall of the semiconductor fin 100F. The isolation structure 105 may be a shallow trench isolation (STI) structure, a suitable isolation structure, a combination of the above structures, or the like. In some embodiments, the isolation structure 105 may be made of an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a combination thereof.

[0072] refer to Figures 5A to 5C ,in Figure 5A This is a top view of a semiconductor device. Figure 5B For along Figure 5AThe cross-sectional view of line C1-C1, and Figure 5C For along Figure 5A A cross-sectional view of line C2-C2 is shown. A dummy gate structure 120 is formed above the substrate 100 and intersects with the fin structure FN. In some embodiments, the dummy gate structure 120 includes a dummy gate dielectric 122 and a dummy gate electrode 124 above the dummy gate dielectric 122. The dummy gate dielectric 122 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The dummy gate electrode 124 may be a conductive or non-conductive material and may be selected from the group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polySiGe), metal nitrides, metal silicides, metal oxides, and metals. In some embodiments, the dummy gate electrode 124 may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering deposition, or other techniques for depositing the selected material. In some embodiments, the dummy gate dielectric 122 may be formed by thermal oxidation.

[0073] refer to Figures 6A to 6C ,in Figure 6A This is a top view of a semiconductor device. Figure 6B For along Figure 6A The cross-sectional view of line C1-C1, and Figure 6C For along Figure 6A The cross-sectional view along line C3-C3. Gate spacers 115 are formed on opposite sidewalls of the dummy gate structure 120. In some embodiments, gate spacers 115 may be formed of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. In some embodiments, gate spacers 115 may be formed, for example, by depositing a spacer layer over substrate 100, followed by performing an anisotropic etching process to remove the horizontal portion of the spacer layer, leaving the vertical portion of the spacer on the sidewalls of the dummy gate structure 120. In some embodiments, the spacer layer may be deposited using CVD, ALD, or similar techniques.

[0074] An etching process is performed using a dummy gate electrode 124 and a gate spacer 115 as an etching mask to remove the dummy gate dielectric 122 and a portion of the fin structure FN, thereby forming a source / drain opening O1 in the fin structure FN. In some embodiments, the etching process is stopped once the top surface of the semiconductor fin 100F is exposed. In some embodiments, the etching process may be wet etching, dry etching, or a combination thereof.

[0075] refer to Figure 7A and Figure 7B ,in Figure 7AThis is a top view of a semiconductor device, and Figure 7B For along Figure 7A A cross-sectional view along line C1-C1. After forming the source / drain opening O1, internal spacers 116 are formed at the opposite ends of semiconductor layers 104A and 104B. Internal spacers 116 can be formed, for example, by performing an etching process to laterally etch semiconductor layers 104A and 104B to form sidewall grooves, depositing a dielectric material over the substrate 100 to blanket and fill the sidewall grooves, followed by anisotropic etching to remove portions of the dielectric material outside the sidewall grooves, thereby leaving the remaining portion of the dielectric material in the sidewall grooves as internal spacers 116. Internal spacers 116 can be deposited using conformal deposition processes such as CVD, ALD, or similar methods. The internal spacer layer can include materials such as SiN, SiOCN, SiCN, and SIOC, although any suitable material can also be used, such as low-k materials having a k value less than about 3.5.

[0076] refer to Figures 8A to 8C Among them, respectively, Figure 8A This is a top view of a semiconductor device. Figure 8B For along Figure 8A The cross-sectional view of line C1-C1, and Figure 8C For along Figure 8A The diagram shows a cross-sectional view along line C3-C3. An isolation layer 130 is formed over the substrate 100 and fills one of the source / drain openings O1, thereby covering a portion of the top surface of the semiconductor fin 100F. In some embodiments, the isolation layer 130 may comprise an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or the like. The isolation layer 130 can be formed, for example, by depositing a dielectric material over the substrate 100 and then patterning the dielectric material.

[0077] After the isolation layer 130 is formed, a source / drain 135 is formed above the substrate 100, and intersects with at least a portion of the semiconductor fin 100F via the other of the source / drain openings O1. Figure 8C As shown in the cross-sectional view, the source / drain 135 may contact a portion of the top surface and opposite sidewalls of the semiconductor fin 100F, and may also contact the top surface of the isolation structure 105. In some embodiments, the source / drain 135 may include suitable conductive materials such as platinum (Pt), titanium (Ti), titanium nitride (TiN), aluminum (Al), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO), tantalum (Ta), tantalum nitride (TaN), nickel (Ni), cobalt (Co), copper (Cu), silver (Ag), gold (Au), alloys thereof, compositions thereof, and the like.

[0078] refer to Figures 9A to 9CAmong them, respectively, Figure 9A This is a top view of a semiconductor device. Figure 9B For along Figure 9A The cross-sectional view of line C1-C1, and Figure 9C For along Figure 9A The cross-sectional view along line C3-C3. An isolation layer 140 is formed over the substrate 100 and covers the source / drain 135. In some embodiments, the isolation layer 140 may be made of a low-k dielectric material, such as SiOCN, SiOC, and / or other suitable dielectric materials. The isolation layer 140 may be formed, for example, by depositing a dielectric material blanket over the substrate 100 and then patterning the dielectric material.

[0079] refer to Figures 10A to 10D Among them, respectively, Figure 10A This is a top view of a semiconductor device. Figure 10B For along Figure 10A A cross-sectional view of line C1-C1. Figure 10C For along Figure 10A The cross-sectional view of line C3-C3, and Figure 10D For along Figure 10A A cross-sectional view along line C4-C4. Once the isolation layer 140 is formed, the isolation layer 130 can be removed using a suitable etching process. Next, source / drain epitaxial structures 150A and 150B are formed in the source / drain openings O1 and at their respective ends in the semiconductor layer 102. In some embodiments, the source / drain epitaxial structures 150A and 150B may comprise semiconductor materials such as silicon germanium (SiGe) or other suitable semiconductor materials. For example, the source / drain epitaxial structures 150A and 150B may be Si... 0.1 Ge 0.9 In some embodiments, the source / drain epitaxial structures 150A and 150B can be formed by a selective epitaxial growth (SEG) process. The SEG process selectively grows semiconductor material on exposed semiconductor surfaces, such as the exposed surface of semiconductor layer 102.

[0080] In some embodiments, the source / drain epitaxial structures 150A and 150B may be doped with p-type or n-type dopants. In some embodiments, the dopants of the source / drain epitaxial structures 150A and 150B may include a conductivity type opposite to that of the dopants in the semiconductor layer 104A and the dopants driven into the semiconductor fin 100F. For example, if the semiconductor layer 104A and the semiconductor fin 100F include p-type dopants, then the source / drain epitaxial structures 150A and 150B may include n-type dopants; and vice versa.

[0081] In some embodiments, the source / drain epitaxial structures 150A and 150B may include different profiles. Due to the presence of the source / drain 135 and the isolation layer 140, the source / drain epitaxial structure 150A can be separated from the semiconductor fin 100F via the isolation layer 140 and the source / drain 135, and can be formed to contact the top surface of the isolation layer 140. On the other hand, the source / drain epitaxial structure 150B can contact the semiconductor fin 100F. As a result, the bottom surface of the source / drain epitaxial structure 150B is lower than the bottom surface of the source / drain epitaxial structure 150A.

[0082] refer to Figures 11A to 11D Among them, respectively, Figure 11A This is a top view of a semiconductor device. Figure 11B For along Figure 11A A cross-sectional view of line C1-C1. Figure 11C For along Figure 11A The cross-sectional view of line C3-C3, and Figure 11D For along Figure 11A A cross-sectional view of line C4-C4. Source / drain contacts 155A and 155B are formed above substrate 100 and respectively cover source / drain epitaxial structures 150A and 150B. In some embodiments, source / drain contacts 155A and 155B may include suitable conductive materials such as platinum (Pt), titanium (Ti), titanium nitride (TiN), aluminum (Al), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO), tantalum (Ta), tantalum nitride (TaN), nickel (Ni), cobalt (Co), copper (Cu), silver (Ag), gold (Au), alloys thereof, compositions thereof, and the like. Source / drain contacts 155A and 155B may be formed, for example, by depositing a conductive material above substrate 100 and then patterning the conductive material.

[0083] In some embodiments, the source / drain contact 155A contacts the top surface of the isolation layer 140 and can be vertically separated from the source / drain 135 via the isolation layer 140. Conversely, the source / drain contact 155B can contact the opposite sidewall of the semiconductor fin 100F and the top surface of the isolation structure 105. In some embodiments, the bottom surface of the source / drain contact 155B is lower than the bottom surface of the source / drain contact 155A.

[0084] refer to Figures 12A to 12D Among them, respectively, Figure 12A This is a top view of a semiconductor device. Figure 12B For along Figure 12A A cross-sectional view of line C1-C1. Figure 12C For along Figure 12A The cross-sectional view of line C3-C3, and Figure 12D For along Figure 12AA cross-sectional view of line C4-C4. An interlayer dielectric (ILD) layer 160 is formed over the substrate 100 and covers the source / drain contacts 155A and 155B. In some embodiments, the ILD layer 160 may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), silicon phosphosilicate glass (PSG), borosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorosilicone glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bisbenzocyclobutene (BCB), or polyimide. A planarization process may be performed to remove excess material from the ILD layer 160 until the dummy gate structure 120 is exposed.

[0085] refer to Figures 13A to 13C Among them, respectively, Figure 13A This is a top view of a semiconductor device. Figure 13B For along Figure 13A The cross-sectional view of line C1-C1, and Figure 12C For along Figure 12A A cross-sectional view of line C2-C2. The dummy gate structure 120 is removed to form a gate trench GT1 between the gate spacers 115. (See diagram below.) Figure 13C As shown, once the dummy gate structure 120 is removed, a portion of the fin structure FN can be exposed via the gate trench GT1. In some embodiments, after the dummy gate structure 120 is removed, at least a portion of the dummy gate dielectric 122 can remain below the gate spacer 115 (see...). Figure 13B ).

[0086] refer to Figures 14A to 14C Among them, respectively, Figure 14A This is a top view of a semiconductor device. Figure 14B For along Figure 14A The cross-sectional view of line C1-C1, and Figure 14C For along Figure 14A A cross-sectional view along line C2-C2 is shown. An etching process is performed to remove semiconductor layers 104A and 104B via gate trench GT1, such that semiconductor layer 102 is suspended above substrate 100. In some embodiments, because the semiconductor fins 100F of substrate 100 may comprise a material similar to semiconductor layers 104A and 104B, the etching process for semiconductor fins 100F and semiconductor layers 104A and 104B may comprise an etching rate higher than that for semiconductor layer 102. As a result, a portion of semiconductor fins 100F may also be removed, thereby forming a recess R1 in semiconductor fins 100F. Figure 14BAs shown, in some embodiments, due to the lateral etching of the semiconductor fin 100F, the width of the groove R1 can be wider than the width of the gate trench GT1. Therefore, the groove can expose the bottom surface of the bottommost internal spacer 116.

[0087] refer to Figures 15A to 15C Among them, respectively, Figure 15A This is a top view of a semiconductor device. Figure 15B For along Figure 15A The cross-sectional view of line C1-C1, and Figure 15C For along Figure 15A The diagram shows a cross-sectional view along line C2-C2. Gate dielectric layer 172 is formed on the exposed surface of semiconductor fin 100F, and gate dielectric layer 272 is formed on the exposed surface of semiconductor layer 102. Next, work function metal layers 174 and 274 are formed on gate dielectric layers 172 and 272, respectively. In some embodiments, gate dielectric layers 172 and 272 may be formed using the same deposition process and may include the same materials, and work function metal layers 174 and 274 may be formed using the same deposition process and may include the same materials.

[0088] After forming the gate dielectric layers 172 and 272 and the work function metal layers 174 and 274, gate fill metal material is formed in the recess R1 and the gate trench GT1. The portion of the gate fill metal material above the work function metal layer 174 can be referred to as gate fill metal 176, and the portion of the gate fill metal material above the work function metal layer 274 can be referred to as gate fill metal 276. That is, gate fill metal 176 and 276 can be different portions of the gate fill metal material.

[0089] The gate dielectric layer 172, the work function metal layer 174, and the gate fill metal 176 can be collectively referred to as the metal gate structure 170. The gate dielectric layer 272, the work function metal layer 274, and the gate fill metal 276 can be collectively referred to as the metal gate structure 270. In some embodiments, the metal gate structure 170 is embedded in the semiconductor fin 100F and may include a width wider than the metal gate structure 270. Therefore, the metal gate structure 170 can contact the bottom surface of the bottommost internal spacer 116.

[0090] In some embodiments, gate dielectric layers 172 and 272 may each include an interface layer and a high-k dielectric layer above the interface layer. Examples of the interface layer may include oxides, such as aluminum oxide (Al2O3), silicon oxide (SiO2), or the like. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof.

[0091] Work function metal layers 174 and 274 can be n-type or p-type work function layers. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layers may include multiple layers. Gate fill metals 176 and 276 may include tungsten (W), aluminum (Al), copper (Cu), or another suitable conductive material(s).

[0092] refer to Figures 16A to 16E Among them, respectively, Figure 16A This is a top view of a semiconductor device. Figure 16B For along Figure 16A A cross-sectional view of line C1-C1. Figure 16C For along Figure 16A The cross-sectional view of line C2-C2. Figure 16D For along Figure 16D The cross-sectional view of line C3-C3, and Figure 16E For along Figure 16E The cross-sectional view is shown along line C4-C4. Source / drain vias 180A, 180B, and 180C are formed in ILD layer 160. More specifically, source / drain via 180A is formed to contact source / drain contact 155A, source / drain via 180B is formed to contact source / drain contact 155B, and source / drain via 180C is formed to contact source / drain 135. The source / drain vias 180A, 180B, and 180C may comprise suitable conductive materials such as platinum (Pt), titanium (Ti), titanium nitride (TiN), aluminum (Al), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO), tantalum (Ta), tantalum nitride (TaN), nickel (Ni), cobalt (Co), copper (Cu), silver (Ag), gold (Au), alloys thereof, compositions thereof, and the like. The source / drain vias 180A, 180B, and 180C may be formed, for example, by patterning the ILD layer 160 to form openings that expose source / source contacts 155A and 155B and the source / drain 135, respectively; filling the openings with a conductive material; then performing planarization to remove excess conductive material until the ILD layer 160 is exposed.

[0093] Figures 16A to 16EThe structure is an example of a complementary FET (CFET), which may include a first transistor and a second transistor vertically stacked on top of the first transistor. More specifically, the semiconductor fin 100F and the metal gate structure 170 may jointly serve as the first transistor. On the other hand, the semiconductor layer 102, the metal gate structure 270, and the source / drain epitaxial structures 150A and 150B may jointly serve as the second transistor. In some embodiments, the first transistor and the second transistor may include opposite conductivity types. For example, the first transistor may be a p-type transistor and the second transistor may be an n-type transistor, or vice versa.

[0094] Regarding the first transistor, it may include a finned configuration, and therefore may also be referred to as a FinFET device. More specifically, in Figure 16C In the cross-sectional view, the metal gate structure 170 may intersect with the semiconductor fin 100F. That is, the metal gate structure 170 may contact three sides of the semiconductor fin 100F. Regarding the second transistor, the second transistor may include a gate all-around (GAA) configuration, therefore the first transistor may also be referred to as a GAA device. More specifically, in Figure 16C In the cross-sectional view, the metal gate structure 270 can surround each of the semiconductor layers 102. That is, the metal gate structure 270 can contact the four sides of each of the semiconductor layers 102.

[0095] like Figure 16B As shown in the cross-sectional view, the semiconductor fin 100F includes a channel portion 100CH that contacts the bottom surface of the metal gate structure 170. The semiconductor fin 100F further includes a source / drain portion 100SD on the opposite side of the channel portion 100CH and in contact with the opposite sidewall of the metal gate structure 170. Therefore, the semiconductor fin 100F may include a saddle-shaped cross-sectional profile.

[0096] As mentioned above, in such Figures 14A to 14C During the removal process described herein, a recess R1 is formed in the semiconductor fin 100F. This results in the metal gate structure 170 being embedded in the semiconductor fin 100F, causing the top surface of the channel portion 100CH to be lower than the top surface of the source / drain portion 100SD. Furthermore, in... Figure 2A and Figure 2B During the solid-state diffusion process described herein, the semiconductor fin 100F may include a gradient dopant concentration, wherein the dopant concentration in the semiconductor fin 100F may decrease downwards from the top surface of the semiconductor fin 100F. Therefore, the dopant concentration in the channel portion 100CH will be lower than the dopant concentration in the source / drain portion 100SD. In some embodiments, the top surface of the channel portion 100CH may include approximately 1 x 10⁻⁶ ppm.10 cm -3 To approximately 1 x 10 18 cm -3 Dopant concentration within a range. In some embodiments, each of the source / drain portions 100SD may include the maximum dopant concentration at the top surface of the semiconductor fin 100F, and within approximately 1 x 10⁻⁶. 18 cm -3 To approximately 1x10 22 cm -3 Within the range. In some embodiments, the maximum dopant concentration at the top surface of the source / drain portion 100SD may be at least 10 times the maximum dopant concentration at the top surface of the channel portion 100CH. Furthermore, the source / drain portion 100SD may also include a gradient dopant concentration, wherein the dopant concentration in the source / drain portion 100SD may decrease downwards from the top surface of the semiconductor fin 100F. More specifically, the dopant concentration at the surface of the source / drain portion 100SD in contact with the metal gate structure 170 may decrease downwards.

[0097] A channel portion 100CH with a lower dopant concentration can improve the device performance of the first transistor. In the absence of formation Figure 14A and Figure 14B In some embodiments of the recess R1, the resulting channel portion 100CH of the semiconductor fin 100F may be at the same level as the source / drain portion 100SD and will include substantially the same dopant concentration. Therefore, during operation of the first transistor, current leakage may occur from one source / drain portion 100SD through the channel portion 100CH to another source / drain portion 100SD, also known as a "breakdown effect." In the embodiments disclosed herein, current leakage can be suppressed at the lower location of the channel portion 100CH with a lower dopant concentration, thereby improving device performance.

[0098] exist Figure 16B In the semiconductor fin 100F, a portion of the metal gate structure 170 may include a height H1. In some embodiments, the height H1 is in the range of about 25 nm to about 35 nm, such as 30 nm. If the height H1 is too small, the dopant concentration of the channel portion 100CH may be too high, which may fail to suppress current leakage. If the height H1 is too large, the dopant concentration of the channel portion 100CH may be too low, and the device performance may be unsatisfactory. The metal gate structure 270 may include a gate length L1. In some embodiments, the gate length L1 is in the range of about 1 nm to about 200 nm, such as 12 nm.

[0099] exist Figure 16CIn this embodiment, the semiconductor fin 100F (or the channel portion 100H of the semiconductor fin 100F) may include a thickness TH1 and a width W1. In some embodiments, the thickness TH1 is in the range of about 1 nm to about 200 nm. The width W1 is in the range of about 1 nm to about 200 nm, such as 25 nm. Each of the semiconductor layers 102 may include a thickness TH2 and a width W2. In some embodiments, the thickness TH2 is in the range of about 1 nm to about 200 nm, such as 5 nm. The width W2 is in the range of about 1 nm to about 200 nm, such as 25 nm. In other embodiments, the semiconductor layers 102 may include different thicknesses TH2. In some embodiments, the vertical distance between adjacent semiconductor layers 102 may be different. In some embodiments, the vertical distance between adjacent semiconductor layers 102 is in the range of about 3 nm to about 200 nm. In some embodiments, the number of semiconductor layers 102 may be in the range of about 2 to 20. In some embodiments, the cross-sectional profile of the semiconductor layer 102 may be rectangular, square, rhomboid, etc., with or without rounded corners.

[0100] Figure 17 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Figure 17 Similar to Figure 16B Therefore, similar components are marked the same, and for the sake of simplicity, the relevant details will not be repeated. Figure 17 and Figure 16B The difference is that the metal gate structure 170 embedded in the semiconductor fin 100F may include substantially the same width as the metal gate structure 270. That is, the metal gate structure 170 may not interface with the bottom surface of the bottommost internal spacer 116.

[0101] Figure 18The illustration shows a circuit diagram of a static random access memory (SRAM) cell according to some embodiments of the present disclosure. A memory cell 10 is provided. The memory cell 10 may include a pair of cross-coupled inverter-1 and inverter-2, and two channel gate transistors PG-1 and PG-2. Inverter-1 and inverter-2 are cross-coupled between nodes n1 and n2 and form a latch circuit. In some embodiments, one of nodes n1 and n2 serves as the output terminal of the latch circuit, while the other node serves as the input terminal of the latch circuit. Channel gate transistor PG-1 is coupled between bit line BL and node n2, and channel gate transistor PG-2 is coupled between bit line BLB and node n1, wherein the complementary bit line BLB is complementary to bit line BL. The gates of channel gate transistors PG-1 and PG-2 are coupled to the same word line WL. Furthermore, in some embodiments, channel gate transistors PG-1 and PG-2 are NMOS transistors. In some embodiments, memory cell 10 may include two isolation transistors, wherein the sources of the isolation transistors are floating, and the gate and drain of one of the isolation transistors are coupled to one of nodes n1 and n2. In some embodiments, the isolation transistor may be a PMOS transistor.

[0102] Inverter-1 includes a pull-up transistor PU-1 and a pull-down transistor PD-1. Pull-up transistor PU-1 can be a PMOS transistor, and pull-down transistor PD-1 can be an NMOS transistor. The drains of both pull-up transistor PU-1 and pull-down transistor PD-1 are coupled to node n2, which connects to the gate transistor PG1. The gates of both pull-up transistor PU-1 and pull-down transistor PD-1 are coupled to node n1, which connects to the gate transistor PG-2. Furthermore, the source of pull-up transistor PU-1 is coupled to the power supply VDD, and the source of pull-down transistor PD-1 is coupled to ground VSS.

[0103] Similarly, Inverter-2 includes a pull-up transistor PU-2 and a pull-down transistor PD-2. Pull-up transistor PU-2 can be a PMOS transistor, and pull-down transistor PD-2 can be an NMOS transistor. The drains of both pull-up transistor PU-2 and pull-down transistor PD-2 are coupled to node n1 of the connecting gate transistor PG-2. The gates of both pull-up transistor PU-2 and pull-down transistor PD-2 are coupled to node n1 of the connecting gate transistor PG-1. Furthermore, the source of pull-up transistor PU-2 is coupled to the power supply VDD, and the source of pull-down transistor PD-2 is coupled to ground VSS.

[0104] In some embodiments where memory cell 10 includes two isolation transistors, the drain and gate of one isolation transistor are both coupled to node n2, and the drain and gate of the other isolation transistor are both coupled to node n1. The source of the isolation transistor is depicted as floating. In some embodiments, the source of the isolation transistor may be coupled to an individual transistor in an adjacent memory cell.

[0105] Figure 19 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. More specifically, Figure 19 yes Figure 18 An example structure of the memory cell 10 described herein is shown. A substrate 100 having semiconductor fins 100F is shown. The memory cell 10 includes a pull-down transistor PD, a pull-up transistor PU, a channel gate transistor PG, and a dummy transistor DU above the substrate 100. Here, the pull-down transistor PD, the pull-up transistor PU, and the channel gate transistor PG can be respectively as follows: Figure 18 The pull-down transistor PD-1, pull-up transistor PU-1, and gate transistor PG-1 are shown. Alternatively, the pull-down transistor PD, pull-up transistor PU, and gate transistor PG can be respectively as follows: Figure 18 The pull-down transistor PD-2, pull-up transistor PU-2, and channel gate transistor PG-2 are shown. Although they exist... Figure 19 In the structure, the dummy transistor DU is not used as part of the memory cell 10.

[0106] In some embodiments, the pull-down transistor PD and the channel gate transistor PG may include the components described above. Figures 1A to 16E The second transistor discussed has a similar configuration. For example, the pull-down transistor PD may include a semiconductor layer 102A, a metal gate structure 270A surrounding each element in the semiconductor layer 102A, and source / drain epitaxial structures 150A and 150B at opposite ends of the semiconductor layer 102A. Similarly, the channel gate transistor PG may include a semiconductor layer 102B, a metal gate structure 270B surrounding each element in the semiconductor layer 102B, and source / drain epitaxial structures 150B and 150C at opposite ends of the semiconductor layer 102B. In some embodiments, the pull-down transistor PD and the channel gate transistor PG may share a common source / drain epitaxial structure 150B.

[0107] In some embodiments, the pull-up transistor PU and the dummy transistor DU may include the components described above. Figures 1A to 16EThe first transistor discussed has a similar configuration. For example, the pull-up transistor PU may include a semiconductor fin 100F and a metal gate structure 170A intersecting the semiconductor fin 100F, wherein the semiconductor fin 100F includes a channel portion 100CH under the metal gate structure 170A and a source / drain portion 100SD along the sidewall of the metal gate structure 170A. Similarly, the dummy transistor DU may include a semiconductor fin 100F and a metal gate structure 170B intersecting the semiconductor fin 100F, wherein the semiconductor fin 100F includes a channel portion 100CH under the metal gate structure 170B and a source / drain portion 100SD along the sidewall of the metal gate structure 170B.

[0108] The memory cell 10 further includes a source / drain 135 that contacts the source / drain portion 100SD of the semiconductor fin 100F. The memory cell 10 further includes source / drain contacts 155 that respectively contact the source / drain epitaxial structures 150A, 150B, and 150C. The memory cell 10 further includes source / drain vias 180 that contact the individual source / drain contacts 155.

[0109] In some embodiments, the source / drain 135, electrically connected to the source / drain portion 100SD of the pull-up transistor PU, can be electrically connected to the power supply VDD. The source / drain epitaxial structure 150A of the pull-down transistor PD can be electrically connected to the power supply VSS via individual source / drain contacts 155 and source / drain vias 180. The source / drain epitaxial structure 150C of the channel gate transistor PG can be electrically connected to the bit line BL via individual source / drain contacts 155 and source / drain vias 180. The metal gate structure 270B of the channel gate transistor PG can be electrically connected to the word line WL.

[0110] The embodiments disclosed herein provide a 6T (six-transistor) SRAM device with a CFET configuration. The CFET configuration allows the 6T SRAM device to have a 4T (four-transistor) footprint, achieving two pFETs in a 6T SRAM without increasing the area. This configuration can facilitate a reduction in device area and promote device shrinkage.

[0111] Figure 20 This is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure. Figure 20 Similar to Figure 16B Therefore, similar components will be marked the same, and for the sake of simplicity, the relevant details will not be repeated. Figure 20 and Figure 16BThe difference lies in the presence of an additional source / drain 135 and an additional isolation layer 140 between the source / drain epitaxial structure 150B and the semiconductor fin 100F. The additional source / drain 135 and the additional isolation layer 140 can be formed together with the source / drain 135 and the isolation layer 140, such as... Figures 8A to 9C As shown. Therefore, the source / drain epitaxial structure 150B can be separated from the semiconductor fin 100F. In these embodiments, the source / drain epitaxial structure 150B may include... Figure 16D The cross-sectional view shows a similar configuration to the source / drain epitaxial structure 150A.

[0112] Figure 21 and Figure 22 These are simulation results of a semiconductor device based on some embodiments of this disclosure. Figure 21 The IV curves of different p-type FinFET devices are shown, simulating both a FinFET device with a saddle-shaped semiconductor fin and a FinFET device with a planar top surface semiconductor fin. Simulation results show that the FinFET device with the saddle-shaped semiconductor fin exhibits stable IV performance. However, when the gate-to-source (V1) voltage drop occurs... GS Current leakage may occur in FinFET devices with planar top surface semiconductor fins when the voltage is from about 0.0V to about -0.1V. Figure 22 The display shows the IV curves for a p-type FinFET device and an n-type GAA device, where the p-type FinFET device includes a saddle-shaped semiconductor fin. It can be seen that the p-type FinFET device involves lower current than the n-type GAA device. Since the n-type device of an SRAM device is stronger than the p-type device, this will also benefit the SRAM device.

[0113] Based on the foregoing embodiments, it can be seen that the present disclosure has advantages in manufacturing integrated circuits. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor is any particular advantage required for all embodiments. Embodiments of the present disclosure provide a method for forming a memory cell with a CFET configuration, wherein the CFET device may include a bottom fin transistor and a top GAA transistor above the bottom fin transistor. The CFET configuration can facilitate device shrinkage of the memory cell. The bottom fin transistor includes a gate structure intersecting with semiconductor fins, wherein the semiconductor fins may include a saddle-shaped cross-sectional profile. This results in the channel portion of the semiconductor fin being located at a lower position with a lower dopant concentration than the source / drain portion of the semiconductor fin, which helps suppress current leakage, thereby improving device performance.

[0114] In some embodiments disclosed herein, the semiconductor device includes a substrate having semiconductor fins, a first transistor above the substrate, and a second transistor perpendicularly above the first transistor. The first transistor includes a first gate structure above the semiconductor fins, wherein, in a cross-sectional view, the semiconductor fins include a channel portion contacting the bottom surface of the first gate structure and source / drain portions on opposite sidewalls of the first gate structure. The second transistor includes a semiconductor channel layer above the semiconductor fins, a second gate structure above the semiconductor channel layer, and source / drain epitaxial structures at opposite ends of the semiconductor channel layer.

[0115] In some embodiments, in a cross-sectional view, the first gate structure is wider than the second gate structure.

[0116] In some embodiments, the semiconductor device further includes an internal spacer between the semiconductor channel layer and the semiconductor fin, wherein the first gate structure interfaces with the bottom surface of the internal spacer.

[0117] In some embodiments, each of the source / drain portions of the semiconductor fin has a dopant concentration that decreases downward from the top surface of the semiconductor fin.

[0118] In some embodiments, the semiconductor device further includes a source / drain that is in contact with one of the source / drain portions of the semiconductor fin.

[0119] In some embodiments, the semiconductor device further includes an isolation layer perpendicularly between the source / drain and one of the source / drain epitaxial structures of the second transistor.

[0120] In some embodiments, the first transistor and the second transistor have opposite conductivity types.

[0121] In some embodiments, the first gate structure is in contact with the second gate structure.

[0122] In some embodiments disclosed herein, the semiconductor device includes a substrate having semiconductor fins, a first transistor above the substrate, a source / drain, and a second transistor perpendicularly above the first transistor. The first transistor includes a first gate structure having a portion embedded in the semiconductor fins. The source / drain intersects with a portion of the semiconductor fins. The second transistor includes a semiconductor channel layer above the semiconductor fins, a second gate structure above the semiconductor channel layer, and source / drain epitaxial structures at opposite ends of the semiconductor channel.

[0123] In some embodiments, the source / drain portions of the semiconductor fins in contact with the sidewalls of the first gate structure have a gradient dopant concentration.

[0124] In some embodiments, the semiconductor fin includes a source / drain portion of the semiconductor fin that contacts the sidewall of the first gate structure and a channel portion that contacts the bottom surface of the first gate structure, wherein the maximum dopant concentration of the drain / source portion of the semiconductor fin is greater than the maximum dopant concentration of the channel portion of the semiconductor fin.

[0125] In some embodiments, the first gate structure is wider than the second gate structure.

[0126] In some embodiments, the semiconductor device further includes an isolation layer above the source / drain.

[0127] In some embodiments, one of the source / drain epitaxial structures is in contact with the semiconductor fin, and the other of the source / drain epitaxial structure is spaced apart from the semiconductor fin.

[0128] In some embodiments, the dopants in the semiconductor fins have the opposite conductivity type to the dopants in the source / drain epitaxial structure.

[0129] In some embodiments disclosed herein, a method includes forming an alternating stack of sacrificial layers and semiconductor layers over a semiconductor fin; forming a source / drain epitaxial structure at opposite ends of the semiconductor layers; performing an etching process to remove the sacrificial layers and a portion of the semiconductor fin, such that the semiconductor layers are suspended over the semiconductor fin and a groove is formed in the semiconductor fin; and forming a gate material surrounding the semiconductor layers and in the groove of the semiconductor fin.

[0130] In some embodiments, forming a stack of sacrificial layers and semiconductor layers includes forming the bottommost of the sacrificial layers over a semiconductor fin, wherein the bottommost of the sacrificial layers is doped; performing an annealing process to drive the dopant of the bottommost of the sacrificial layers into the semiconductor fin, such that the semiconductor fin has a gradient dopant concentration; and after the annealing process is completed, forming a semiconductor layer and other sacrificial layers over the bottommost of the sacrificial layers.

[0131] In some embodiments, the other sacrificial layers are undoped.

[0132] In some embodiments, the method further includes forming a metal layer that intersects with a portion of the semiconductor fins before forming the source / drain epitaxial structure.

[0133] In some embodiments, the method further includes forming an isolation layer covering a metal layer, wherein the metal layer is spaced apart from one of the source / drain epitaxial structures via the isolation layer.

[0134] In some embodiments disclosed herein, a semiconductor device includes: a substrate having a semiconductor fin; a first transistor above the substrate and including a first gate structure above the semiconductor fin, wherein in a cross-sectional view, the semiconductor fin includes a channel portion contacting a bottom surface of the first gate structure; and a source / drain portion on a plurality of opposing sidewalls of the first gate structure; and a second transistor perpendicularly above the first transistor and including: a semiconductor channel layer above the semiconductor fin; a second gate structure above the semiconductor channel layer; and a source / drain epitaxial structure on a plurality of opposing ends of the semiconductor channel layer, wherein the first gate structure contacts the second gate structure.

[0135] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, It includes: A substrate having a semiconductor fin; A first transistor is located above the substrate and includes a first gate structure above the semiconductor fin, wherein, in a cross-sectional view, the semiconductor fin includes a channel portion that contacts a bottom surface of the first gate structure; and source / drain portions located on a plurality of opposing sidewalls of the first gate structure; and A second transistor, which is perpendicular to the first transistor, and includes: A semiconductor channel layer is disposed on the semiconductor fin; A second gate structure is disposed above the semiconductor channel layer; and Source / drain epitaxial structures are located at multiple opposite ends of the semiconductor channel layer.

2. The semiconductor device as claimed in claim 1, characterized in that, In the cross-sectional view, the first gate structure is wider than the second gate structure.

3. The semiconductor device as claimed in claim 1, characterized in that, It further includes an internal spacer between the semiconductor channel layer and the semiconductor fin, wherein the first gate structure interfaces with a bottom surface of the internal spacer.

4. The semiconductor device as claimed in claim 1, characterized in that, It further includes a source / drain that is in contact with one of the source / drain portions of the semiconductor fin.

5. The semiconductor device as claimed in claim 4, characterized in that, It further includes an isolation layer perpendicularly between the source / drain and one of the source / drain epitaxial structures of the second transistor.

6. A semiconductor device, characterized in that, It includes: A substrate having a semiconductor fin; A first transistor is located above the substrate and includes a first gate structure having a portion embedded in the semiconductor fin; A source / drain electrode that intersects with a portion of the semiconductor fin; and A second transistor, which is perpendicular to the first transistor, and includes: A semiconductor channel layer is disposed on the semiconductor fin; A second gate structure is disposed above the semiconductor channel layer; and Source / drain epitaxial structures are located at multiple opposite ends of the semiconductor channel layer.

7. The semiconductor device as claimed in claim 6, characterized in that, The first gate structure is wider than the second gate structure.

8. The semiconductor device as claimed in claim 6, characterized in that, It is further contained in an isolation layer above the source / drain.

9. The semiconductor device as claimed in claim 6, characterized in that, One of the source / drain epitaxial structures is in contact with the semiconductor fin, and the other of the source / drain epitaxial structures is spaced apart from the semiconductor fin.

10. A semiconductor device, characterized in that, It includes: A substrate having a semiconductor fin; A first transistor is located above the substrate and includes a first gate structure above the semiconductor fin, wherein, in a cross-sectional view, the semiconductor fin includes a channel portion that contacts a bottom surface of the first gate structure; and source / drain portions located on a plurality of opposing sidewalls of the first gate structure; and A second transistor, which is perpendicular to the first transistor, and includes: A semiconductor channel layer is disposed on the semiconductor fin; A second gate structure is disposed above the semiconductor channel layer; and Source / drain epitaxial structures are located at multiple opposite ends of the semiconductor channel layer, wherein the first gate structure is in contact with the second gate structure.

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