SiCr-based resistance chip and layout structure thereof

Abstract

The utility model relates to electronic circuit technical field discloses a kind of resistance chip and layout structure based on SiCr, including silicon base wafer, oxidation isolation layer, metal connecting line, PAD, metal resistance, it is characterized by: a layer of oxidation isolation layer is grown on the silicon base wafer, for electric isolation and prevent electric leakage, the metal connecting line is laid on oxidation isolation layer, for connecting resistance metal and PAD inside resistance chip, the chip of metal resistance adopts SiCr thin-film resistance. In the utility model, by adopting SiCr thin-film resistance material, with very low resistance temperature coefficient, resistance stability is high, the layout design of optimization, the precision and reliability of resistance chip are improved, through the design of one public PAD and multiple separate PAD resistance pin, the output of different resistance value can be realized, the flexibility and applicability of resistance chip are enhanced.

Description

Technical Field

[0001] This utility model relates to the field of electronic circuit technology, and in particular to a SiCr-based resistor chip and its layout structure. Background Technology

[0002] Resistor chips are important electronic devices in the field of semiconductor technology, and developing a high-precision resistor chip with good temperature stability is of great significance. Therefore, it is necessary to develop a SiCr-based resistor chip and its layout structure.

[0003] A SiCr-based resistor chip and its layout structure are disclosed. This resistor chip, made of SiCr material, features high precision and resistance that is not easily affected by temperature changes, making it suitable for various precision electronic devices. However, existing resistor chips generally suffer from low precision and resistance values ​​that are easily affected by temperature changes during manufacturing. Especially in precision electronic devices, this instability can lead to performance degradation or even system failure. Utility Model Content

[0004] To overcome the above shortcomings, this utility model provides a SiCr-based resistor chip and its layout structure, aiming to improve the problems of low precision and resistance value being easily affected by temperature changes during the manufacturing process in existing resistor chips.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a SiCr-based resistor chip and its layout structure, comprising a silicon-based wafer, an oxide isolation layer, metal interconnects, a PAD, and a metal resistor. An oxide isolation layer is grown on the silicon-based wafer for electrical isolation and to prevent leakage. The metal interconnects are laid on the oxide isolation layer to connect the resistive metal inside the resistor chip and the PAD. The metal resistor chip is a SiCr thin-film resistor, which is deposited between corresponding metal lines and formed into a resistor pattern through photolithography. The SiCr thin-film resistor is drawn using a raised pattern and is equipped with a laser trimming structure.

[0006] The above technical solution uses a silicon-based wafer as the physical carrier of the entire chip, providing a stable substrate for the subsequent growth and fabrication of functional layers. The combination of an oxide isolation layer, metal interconnects, PADs, and metal resistors ensures that the chip can complete the entire process from electrical signal input to resistance characteristic output. By using SiCr thin film resistor material, which has good electrical properties and whose resistivity and other characteristics can meet the resistance requirements of the resistor chip, the influence of temperature changes on the resistance value can be significantly reduced.

[0007] As a further description of the above technical solution: The PAD includes a common PAD and multiple individual PADs, with different portions of the SiCr thin film resistor connected between the common PAD and each individual PAD.

[0008] Through the above technical solution: PAD serves as a pad for connecting the resistor chip to external circuits. The common PAD can provide a unified electrical reference node for all SiCr thin film resistor paths, ensuring that the working reference of each resistor unit is consistent. Multiple individual PADs are connected to different parts of the resistor to form multiple independent resistor paths, allowing the chip to output different resistance values ​​simultaneously or selectively. This greatly improves the chip's integration and functional flexibility, thereby meeting the differentiated needs of external circuits for resistors of various specifications.

[0009] As a further description of the above technical solution: The metal connecting wire is divided into parts A, B, C, D, and E.

[0010] The above technical solution divides the metal connecting wires into five areas in the layout design, avoiding cross-interference between different paths and facilitating precision control of each section of the line during the manufacturing process.

[0011] As a further description of the above technical solution: PADs are placed in the five areas A, B, C, D, and E of the metal connecting wire.

[0012] The above technical solution involves placing PADs in the corresponding areas of each segmented connection line, which shortens the conductive distance between the PADs and the connection lines, reduces parasitic resistance and signal loss during current transmission, and ensures efficient current transmission.

[0013] As a further description of the above technical solution: The PAD in region A of the metal connecting line serves as the common terminal.

[0014] With the above technical solution, the external circuit can be connected to multiple resistor paths through only one common terminal, which simplifies the external wiring logic, avoids resistance performance deviation caused by reference differences, and improves the stability of the resistor chip output.

[0015] As a further description of the above technical solution: The PADs in regions B, C, D, and E of the metal connecting lines serve as independent connection terminals.

[0016] Through the above technical solution, the external circuit can selectively connect to the corresponding resistor unit by connecting to the independent PADs in areas B, C, D, and E, thereby flexibly calling different resistor functions within the chip. The external circuit can accurately call the required resistor unit by selecting different independent terminals, achieving flexible selection of specific resistance values ​​and improving the chip's operational reliability.

[0017] As a further description of the above technical solution: The PAD in region A of the metal connection line is used to connect different resistors to the pins with other PADs via wire bonding, for outputs of different resistance values.

[0018] Through the above technical solution, the independent PAD and the common PAD form an electrical path through a metal connecting wire, which allows the external circuit to flexibly select the connected resistor unit, thereby outputting a variety of different resistance values ​​to meet diverse circuit connection needs and improve the flexibility of chip use.

[0019] As a further description of the above technical solution: The metal connecting wire is used to connect the metal resistor to the PAD.

[0020] The above technical solution: the segmented design of the metal connection line makes the connection responsibilities of each part clear, which not only ensures the orderly connection between metal resistors, but also realizes the effective connection between resistor and PAD, so that the current can be smoothly transmitted between the inside and outside of the chip, allowing the current to flow according to the design path and ensuring that the resistor functions normally.

[0021] This utility model has the following beneficial effects: 1. In this utility model, by using SiCr thin film resistor material, which has an extremely low temperature coefficient of resistance and high resistance stability, the optimized layout design improves the accuracy and reliability of the resistor chip. Through the design of a common PAD and multiple individual PAD resistor pins, different resistance values ​​can be output, enhancing the flexibility and applicability of the resistor chip.

[0022] 2. In this utility model, SiCr is deposited between corresponding metal lines and the required resistor pattern is formed by photolithography. The raised SiCr pattern in this design is used to add laser adjustment, which can ensure that the resistor is more accurate. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the overall layout of a SiCr-based resistor chip and its layout structure proposed in this utility model. Figure 2 This is a schematic diagram of the metal interconnection layers in the layout structure of a SiCr-based resistor chip and its proposed layout. Figure 3 This is a schematic diagram of a SiCr-based resistor chip and its layout structure, including the PAD and metal interconnects. Figure 4 This invention presents a schematic diagram of a SiCr-based resistor chip and its layout structure, including metal interconnects and SiCr resistors. Figure 5 This is a schematic diagram of a SiCr-based resistor chip and its layout structure proposed in this utility model. Figure 6 This is a schematic diagram of the PAD layering of a SiCr-based resistor chip and its layout structure proposed in this utility model. Figure 7 This is a schematic diagram of the SiCr resistor and metal interconnect region layering of a SiCr-based resistor chip and its layout structure proposed in this utility model. Figure 8 This is a schematic diagram of the Pad and metal interconnect regions of a SiCr-based resistor chip and its layout structure proposed in this utility model. Detailed Implementation

[0024] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0025] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 and Figure 7 The present invention provides an embodiment of a SiCr-based resistor chip and its layout structure, comprising a silicon-based wafer, an oxide isolation layer, metal interconnects, a PAD, and a metal resistor. An oxide isolation layer is grown on the silicon-based wafer for electrical isolation and to prevent leakage. The metal interconnects are laid on the oxide isolation layer to connect the resistive metal inside the resistor chip and the PAD. The metal resistor chip is a SiCr thin film resistor, which is deposited between corresponding metal lines and formed into a resistor pattern by photolithography. The SiCr thin film resistor is drawn using a raised pattern and is provided with a laser trimming structure. Specifically, the extremely high resistivity of the oxide isolation layer isolates the silicon-based wafer from the conductive structures such as the metal interconnects and metal resistors above it, preventing leakage or short circuits caused by direct contact between different electrical components. Simultaneously, this isolation layer reduces the parasitic capacitance and interference of the silicon substrate to the circuitry above, ensuring the stable electrical performance of the resistor chip and providing a reliable foundation for the precise operation of subsequent functional layers. The metal interconnects, acting as conductive bridges within the chip, have their placement and connection function directly determining the circuit's conductivity. By placing the metal interconnects on the oxide isolation layer, the insulating properties of the isolation layer are utilized to prevent interference with the silicon-based wafer, while a reasonable wiring design enables efficient connection between the resistor metal and the PAD. This connection method ensures that current flows smoothly from the PAD into the resistor metal, then returns to the PAD through the interconnects after resistance, forming a complete current path, thereby enabling signal interaction between the resistor chip and external circuits. By using SiCr thin-film resistors as the core material for the metal resistor, utilizing… Due to its stable resistivity and low temperature coefficient, SiCr ensures the accuracy and reliability of resistance values. By depositing SiCr material between metal lines, the resistor is directly placed in the current path, ensuring that the current must flow through the resistive film to produce the expected resistive effect. Specific resistor patterns are formed through photolithography, allowing precise control of dimensional parameters such as length and width. Based on the resistance calculation formula, the resistance value can be precisely adjusted to meet the customized requirements of different circuits. The raised pattern on SiCr, combined with laser trimming, ensures even greater precision. The raised pattern design increases the effective thickness or surface area of ​​the SiCr thin-film resistor, optimizing its power handling capacity and stability within the same dimensions. It also provides more physical space for laser trimming, which is key to improving resistor accuracy. By using laser to locally cut or trim the raised portion, the actual resistance value can be finely adjusted, compensating for resistance deviations caused by manufacturing errors, achieving higher standards of resistance accuracy, and thus meeting the stringent requirements of high-precision circuits for resistance parameters.

[0026] Reference Figure 1 , Figure 3 and Figure 6 The PAD consists of a common PAD and multiple individual PADs. Different parts of the SiCr thin film resistor are connected between the common PAD and each individual PAD. The metal connection line is divided into parts A, B, C, D, and E. PADs are placed in the five regions A, B, C, D, and E of the metal connection line. Specifically, by using a common PAD as a shared node, multiple resistor paths can share a common connection point, simplifying the connection complexity of external circuits. Multiple individual PADs correspond to different resistor paths, forming independent resistor units in conjunction with different parts of the SiCr thin film resistor. This allows the chip to output various resistance values ​​or achieve different circuit functions through a combination of a single common terminal and multiple independent terminals, thereby greatly improving the chip's integration and flexibility. By having each connection line correspond to a specific PAD area, the internal circuit layout of the chip is orderly and controllable. Placing PADs in each area ensures close connection between the PADs and their corresponding connection lines, reducing parasitic resistance and signal loss in the current transmission path and improving circuit transmission efficiency. This partitioned design also facilitates process control during manufacturing and subsequent testing and debugging, reducing the risk of short circuits or connection failures caused by messy wiring.

[0027] Reference Figure 1 , Figure 6 and Figure 8 The PAD in area A of the metal connection line serves as the common terminal; the PADs in areas B, C, D, and E of the metal connection lines serve as independent connection terminals; the PAD in area A of the metal connection line is used to connect different resistors to the pins with other PADs via wire bonding for outputs of different resistance values; the metal connection line is used to connect the metal resistor to the PAD. Specifically, by clarifying the common terminal attributes of PADs in region A and the independent connection terminal attributes of PADs in regions B, C, D, and E, the functional division of each PAD is further refined. The common terminal of PADs in region A provides a unified reference node for all resistor paths, ensuring a consistent baseline for the electrical parameters of each independent resistor unit. The independent connection terminals correspond to different resistor paths, allowing external circuits to precisely call the required resistor function by selecting different independent terminals. This functional division makes the chip's circuit logic clearly identifiable, facilitating circuit design and connection according to actual needs. Wire bonding technology connects the common PAD to other independent PADs. Connecting to the chip pins enables physical connection between the chip's internal resistors and external circuits. The common PAD serves as a shared connection point, and by combining with different independent PADs, the external circuit can flexibly select the connected resistor unit, thereby outputting a variety of different resistance values. This design meets the diverse resistance value requirements of various circuit scenarios, enhancing the chip's versatility and adaptability. The metal connecting wire, as a conductive medium, acts as a bridge for current transmission, constructing a low-resistance path between the metal resistor and the PAD. Furthermore, the high conductivity of the metal material ensures minimal current loss during transmission, allowing the chip's internal resistance effect to be accurately reflected in the external circuit.

[0028] Working principle: First, a silicon-based wafer is used as the base carrier for the entire resistor chip. Then, an oxide isolation layer is grown on the silicon wafer, and SiCr material is deposited on this isolation layer. Next, the required resistor pattern is created through photolithography. An insulating environment is first constructed using the oxide isolation layer to prevent leakage. Then, metal interconnects are laid on the oxide isolation layer as conductive paths. Region A (PAD) of the metal interconnects is the common terminal, while regions B, C, D, and E are independent terminals, forming multiple independent paths. The metal interconnects connect the PAD and the metal resistor. Through wire bonding, the PAD is connected to external pins, allowing the chip to be integrated into an external circuit system. (SiCr thin film...) Resistors are deposited between corresponding metal lines, forming specific resistor patterns through photolithography. The use of raised drawing and laser adjustment structures enhances resistor stability while allowing for fine-tuning of resistance values, ensuring accuracy. This enables specific resistive effects when current flows through the metal resistor. A common PAD and multiple individual PADs are connected to different parts of the metal resistor via metal interconnects, forming diverse current paths. When external current flows through the pins, it can flow through the common PAD, then through different individual PADs, through the corresponding SiCr thin-film resistor sections, and finally out of the PADs back to the external circuit, achieving different resistance values ​​for the output.

[0029] Finally, it should be noted that the above are merely preferred embodiments of the present utility model and are not intended to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A SiCr-based resistor chip and its layout structure, comprising a silicon-based wafer, an oxide isolation layer, metal interconnects, a PAD, and a metal resistor, characterized in that: An oxide isolation layer is grown on the silicon-based wafer for electrical isolation and to prevent leakage. The metal interconnects are laid on the oxide isolation layer to connect the resistive metal and PAD inside the resistor chip. The metal resistor chip is a SiCr thin film resistor. The SiCr thin film resistor is deposited between the corresponding metal lines and the resistor pattern is formed by photolithography. The SiCr thin film resistor is drawn using a raised method and has a laser trimming structure.

2. The SiCr-based resistor chip and its layout structure according to claim 1, characterized in that: The PAD includes a common PAD and multiple individual PADs, with different portions of the SiCr thin film resistor connected between the common PAD and each individual PAD.

3. The SiCr-based resistor chip and its layout structure according to claim 1, characterized in that: The metal connecting wire is divided into parts A, B, C, D, and E.

4. The SiCr-based resistor chip and its layout structure according to claim 1, characterized in that: PADs are placed in the five areas A, B, C, D, and E of the metal connecting wire.

5. A SiCr-based resistor chip and its layout structure according to claim 1, characterized in that: The PAD in region A of the metal connecting line serves as the common terminal.

6. A SiCr-based resistor chip and its layout structure according to claim 1, characterized in that: The PADs in regions B, C, D, and E of the metal connecting lines serve as independent connection terminals.

7. A SiCr-based resistor chip and its layout structure according to claim 1, characterized in that: The PAD in region A of the metal connection line is used to connect different resistors to the pins with other PADs via wire bonding, for outputs of different resistance values.

8. A SiCr-based resistor chip and its layout structure according to claim 1, characterized in that: The metal connecting wire is used to connect the metal resistor to the PAD.

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