Optoelectronic sensor

Abstract

The application discloses an optoelectronic sensor and relates to the technical field of optoelectronic detection. The optoelectronic sensor comprises a substrate and a P-well region formed on the substrate. The P-well region is provided with a plurality of optoelectronic regions arranged in an array. Two adjacent optoelectronic regions are field effect tube regions. The optoelectronic regions and the field effect tube regions are electrically isolated. The optoelectronic regions are provided with photodiodes. The field effect tube regions are provided with amplifying tubes. The amplifying tube comprises a first drain, a first gate, a source, a second gate and a second drain arranged in sequence along the direction of two photodiode connecting lines. The photodiode is used for converting received incident light into a photoelectric current. The amplifying tube is used for amplifying the photoelectric current received on both sides. The optoelectronic sensor can improve the migration efficiency of photo-generated carriers to the source, thereby improving the utilization rate of light.

Description

Technical Field

[0001] This application relates to the field of photoelectric detection technology, and more specifically, to a photoelectric sensor. Background Technology

[0002] With the continuous development of photoelectric sensing technology, photoelectric sensors have been widely used in fields such as image sensing, optical communication, biological detection, and environmental monitoring. Among them, the photoelectric sensing structure that integrates a photodiode (PD) and a metal-oxide-semiconductor field-effect transistor (MOSFET) has attracted widespread attention due to its dual functions of photoelectric conversion and signal amplification.

[0003] In existing technologies, photoelectric sensing functions are typically achieved by placing photodiodes and MOSFETs in parallel or sharing a portion of their area. This type of structure utilizes the photodiode to absorb incident photons and generate photogenerated carriers, which are then read and amplified by external circuitry or subsequent amplifier circuitry. However, due to the unreasonable layout of the photodiode and MOSFET in traditional structures, the photogenerated carriers have a long migration path to the source, resulting in low migration efficiency. Especially under weak light conditions, a large number of photogenerated carriers recombine during transport, significantly reducing the device's quantum efficiency and responsivity. Utility Model Content

[0004] The purpose of this application is to provide a photoelectric sensor that can improve the efficiency of photogenerated carrier migration to the source, thereby improving the utilization rate of light.

[0005] The embodiments of this application are implemented as follows: A first aspect of this application provides a photoelectric sensor, comprising: a substrate and a P-well region formed on the substrate; the P-well region is provided with a plurality of photoelectric regions arranged in an array, and a field-effect transistor region is located between two adjacent photoelectric regions, and the photoelectric regions and the field-effect transistor regions are electrically isolated; a photodiode is provided in each photoelectric region, and an amplifying transistor is provided in the field-effect transistor region, the amplifying transistor including a first drain, a first gate, a source, a second gate, and a second drain sequentially arranged along the connection direction of the two photodiodes; the photodiode is used to convert the received incident light into photocurrent, and the amplifying transistor is used to amplify the received photocurrents from both sides.

[0006] As one possible implementation, the photoelectric area is square, and the photoelectric areas in adjacent rows are aligned or staggered.

[0007] As one possible implementation, the photoelectric region is a regular hexagon, and the photoelectric regions in two adjacent rows are staggered to fill the gap between two photoelectric regions in adjacent rows.

[0008] As one possible implementation, the first drain, the first gate, the source, the second gate, and the second drain all extend along the extension direction of the edge of the photoelectric region.

[0009] As one possible implementation, the lengths of the first drain, the first gate, the source, the second gate, and the second drain are all the same as the side length of the photoelectric region.

[0010] As one possible implementation, the photoelectric region includes a doped cathode disposed on the upper surface of the P-well region.

[0011] As one possible implementation, an intrinsic layer is also provided on the lower surface of the doped cathode.

[0012] As one possible implementation, the field-effect transistor region includes: a source / drain layer disposed on the upper surface of the P-well region, and a gate oxide layer and a gate layer disposed sequentially on the source / drain layer; a first drain, a source, and a second drain are disposed sequentially at intervals on the source / drain layer, and a first gate and a second gate are disposed at intervals on the gate layer, wherein the projection of the first gate on the source / drain layer is located between the first drain and the source, and the projection of the second gate on the source / drain layer is located between the second drain and the source.

[0013] As one possible implementation, the first gate and the second gate are polysilicon gates.

[0014] As one possible implementation, a shallow trench isolation structure is provided between the photoelectric region and the field-effect transistor region.

[0015] The beneficial effects of the embodiments of this application include: The photoelectric sensor provided in this application includes: a substrate and a P-well region formed on the substrate; the P-well region is provided with a plurality of photoelectric regions arranged in an array, and a field-effect transistor region is located between two adjacent photoelectric regions, and the photoelectric regions and the field-effect transistor regions are electrically isolated; photodiodes are provided in the photoelectric regions, and the photodiodes in the two adjacent photoelectric regions absorb photons to generate electron-hole pairs. Under the action of the built-in electric field in the photodiode, the photogenerated carriers are separated and move to the two electrodes of their respective connected photodiodes to form photocurrents. An amplifying transistor is provided in the field-effect transistor region, and the amplifying transistor includes a first drain, a first gate, a source, a second gate, and a second drain arranged sequentially along the connection direction of the two photodiodes. The amplifying transistor is used to amplify the photocurrents received from both sides. Since the first drain and the second drain of the amplifying transistor are adjacent to the left and right photodiodes, respectively, the photocurrent from the left photodiode can be directly injected into the first drain, and the photocurrent from the right photodiode is injected into the second drain. The first gate and the second gate of the amplifying transistor can be biased by applying a bias voltage independently or simultaneously to control the conduction state. When the gate voltage forms the channel, the photocurrent injected from the first drain and the second drain flows to the common source, achieving current convergence and amplification output. That is, the amplifying transistor can receive the photocurrent from the photodiodes on both sides. Similarly, the photocurrent generated by the photodiodes also flows to the amplifying transistors on both sides. Therefore, in the photoelectric sensor provided in this application embodiment, the photodiodes can transfer photogenerated carriers to the sources of the amplifying transistors on both sides, while the sources can also absorb photogenerated carriers from the photodiodes on both sides, thereby increasing the efficiency of photogenerated carrier migration to the source and thus improving the utilization rate of incident light. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is one of the structural schematic diagrams of a photoelectric sensor provided in the embodiments of this application; Figure 2 for Figure 1 Enlarged view of point A in the middle; Figure 3 This is a second schematic diagram of the structure of a photoelectric sensor provided in an embodiment of this application; Figure 4 This is the third schematic diagram of the structure of a photoelectric sensor provided in the embodiments of this application; Figure 5This is the fourth schematic diagram of a photoelectric sensor provided in the embodiments of this application.

[0018] Icons: 100-Photoelectric sensor; 110-Substrate; 120-P-well region; 130-Photodiode; 131-Doped cathode; 132-Intrinsic layer; 140-Amplifier; 141-First drain; 142-First gate; 143-Source; 144-Second gate; 145-Second drain; 150-Shallow trench isolation structure. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of this application, not all embodiments. Similar reference numerals and letters in the following drawings indicate similar items. Once an item is defined in one drawing, it does not need to be further defined in other drawings.

[0020] The terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use. They are used only for the convenience of describing this application and should not be construed as limiting this application. The terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0021] Unless otherwise expressly specified and limited, the terms "set up," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to connections within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0022] Please refer to the reference. Figures 1 to 4 This application provides a photoelectric sensor 100, which may include a substrate 110 and a P-well region 120 formed on the substrate 110. The P-well region 120 is provided with a plurality of photoelectric regions arranged in an array. A field-effect transistor region is located between two adjacent photoelectric regions, and the photoelectric regions and the field-effect transistor regions are electrically isolated. A photodiode 130 is provided in the photoelectric region, and an amplifier 140 is provided in the field-effect transistor region. The amplifier 140 includes a first drain 141, a first gate 142, a source 143, a second gate 144, and a second drain 145 arranged sequentially along the line connecting two photodiodes 130. The photodiode 130 receives incident light and converts the light intensity into photocurrent. The amplifier 140 is used to receive the photocurrent on both sides and amplify the photocurrent.

[0023] The photoelectric sensor 100 of this application embodiment integrates multiple photodiodes 130 and an amplifier tube 140. The multiple photodiodes 130 are arranged in an array for photosensitive purposes, specifically, they are responsible for receiving incident light and converting it into photocurrent. An amplifier tube 140 is disposed in the region between two adjacent photoelectric regions for signal processing. The amplifier tube 140 adopts a special double-sided symmetrical structure. Specifically, along the line connecting two adjacent photodiodes 130, a first drain 141, a first gate 142, a source 143, a second gate 144, and a second drain 145 are arranged sequentially. This structure essentially constitutes a composite MOSFET with a shared source 143 and two independent gate control channels, wherein the two drains are respectively close to the left and right photodiodes 130.

[0024] When the photoelectric sensor 100 provided in this embodiment is in operation, external light shines on the photoelectric sensor 100 as incident light. The photodiodes 130 in the two adjacent photoelectric regions on the left and right absorb photons, generating electron-hole pairs (i.e., photogenerated carriers). Under the action of the built-in electric field within the photodiodes 130, the photogenerated carriers are separated and move towards the two poles of their respective connected photodiodes 130, forming a photocurrent. Since the first drain 141 and the second drain 145 of the amplifier tube 140 are adjacent to the left and right photodiodes 130, respectively, the photocurrent from the left photodiode 130 can be directly injected into the first drain 141, and the photocurrent from the right drain is injected into the second drain 145. The first gate 142 and the second gate 144 of the amplifier tube 140 can be independently or simultaneously biased with voltage to control the conduction state. When the gate voltage forms the channel, the photocurrent injected from the first drain 141 and the second drain 145 flows to the common source 143, achieving current convergence and amplification output. That is, the amplifying tube 140 can receive the photocurrent from the photodiodes 130 on both sides. Similarly, the photocurrent generated by the photodiodes 130 also flows to the amplifying tubes 140 on both sides. Therefore, in the photoelectric sensor 100 provided in this application embodiment, the photodiodes 130 can transfer photogenerated carriers to the sources 143 of the amplifying tubes 140 on both sides, and the sources 143 can also absorb photogenerated carriers from the photodiodes 130 on both sides, thereby increasing the migration efficiency of photogenerated carriers to the source 143 and thus improving the utilization rate of incident light.

[0025] In addition, the photoelectric sensor 100 of this application significantly shortens the migration distance of photogenerated carriers from the photoelectric region to the amplification device by placing the amplifying tube 140 between two photodiodes 130, thereby improving the carrier collection efficiency and transmission speed. In particular, it effectively suppresses carrier recombination under weak light conditions, thereby improving the quantum efficiency and responsivity of the device, and achieving high integration and high sensitivity photoelectric sensing performance.

[0026] Optional, such as Figure 1 As shown, the photoelectric area is square, and the photoelectric areas in adjacent rows are either aligned or staggered.

[0027] In this application, the photoelectric region is set as a square, so that the projection shape of each photosensitive unit, i.e., each photodiode 130, on the surface of the substrate 110 is square. This geometry has the advantage of isotropy, which is conducive to uniform light reception and facilitates regular arrangement in the array; in addition, the square design can achieve a large photosensitive area within a limited area, especially when aligned, it is easy to achieve a high fill rate, reduce the area loss of non-photosensitive areas, and thus improve the utilization rate of incident light by the device.

[0028] Specifically, alignment refers to the photoelectric areas of two adjacent rows being perfectly aligned horizontally, meaning that the photoelectric areas of each column are arranged in a straight line vertically, forming a regular rectangular grid array. Misalignment refers to the photoelectric areas of two adjacent rows being offset horizontally, so that the photoelectric areas of the upper row are located directly above the middle of two adjacent photoelectric areas in the lower row, forming a staggered arrangement similar to brickwork or a triangular pattern.

[0029] As an feasible approach, such as Figure 3 As shown, the photoelectric region is a regular hexagon, and the photoelectric regions in two adjacent rows are staggered to fill the gap between two photoelectric regions in adjacent rows.

[0030] Specifically, the upper and lower rows of regular hexagonal photoelectric regions are not aligned, but offset from each other in the horizontal direction, so that a hexagon in the upper row is embedded in the recessed position between two adjacent hexagons in the lower row, forming a honeycomb-like or densely packed structure. This arrangement makes full use of the geometric close packing principle, so that multiple regular hexagons are seamlessly and tightly arranged with almost no gaps, thereby improving the utilization rate of the substrate 110 area and allowing more area to absorb light.

[0031] In the above embodiments, the staggered nested arrangement can effectively eliminate the gaps between rows and significantly reduce the dead zone caused by the non-photosensitive area, thereby improving the optical fill factor and enhancing the low light response capability.

[0032] Taking a regular hexagon with side length 2a as an example, when the photoelectric region is a regular hexagon, the area of ​​photodiode 130 is... When the photoelectric region is an inscribed circle, the area of ​​photodiode 130 is... The hexagon increases the light-receiving area by 10% compared to the circle.

[0033] Optional, such as Figure 1 and Figure 3 As shown, the first drain 141, the first gate 142, the source 143, the second gate 144, and the second drain 145 all extend along the extension direction of the edge of the photoelectric region.

[0034] The first drain 141, the first gate 142, the source 143, the second gate 144, and the second drain 145 all extend along the extension direction of the edge of the photoelectric region. That is, the amplifying tube 140 extends along the direction of the edge of the photoelectric region, so that it is consistent with the overall layout direction of the pixel array. This is beneficial for regular arrangement in a limited space, avoiding structural disorder or space waste, and improving the pixel density and device integration per unit area.

[0035] Extending the transistor along the edge means that its first drain 141 and second drain 145 can be close enough to face the two photodiodes 130 on the left and right, forming a larger contact or adjacent area, reducing the carrier injection barrier and resistance, and improving signal transmission efficiency.

[0036] In addition, since the transistor structure spans the boundary between the two photoelectric regions and extends along the boundary, photogenerated carriers only need to move laterally a short distance to enter the drain region, which significantly reduces the transmission path length, suppresses recombination loss, and especially improves the weak light response performance.

[0037] As an feasible approach, such as Figure 1 and Figure 3 As shown, the lengths of the first drain 141, the first gate 142, the source 143, the second gate 144, and the second drain 145 are all the same as the side length of the photoelectric region.

[0038] The lengths of the first drain 141, the first gate 142, the source 143, the second gate 144, and the second drain 145 are all the same as the side length of the photoelectric region. That is, the amplifying tube 140 is spatially aligned with the side length of a photodiode 130. In this way, the left and right drains can be fully connected with the adjacent photoelectric regions in the length direction, avoiding misalignment or floating areas. This ensures that the charge carriers generated by the photodiode 130 can be effectively collected and read out over the entire width range, improving signal integrity.

[0039] Optionally, the photoelectric region includes a doped cathode 131 disposed on the upper surface of the P-well region 120.

[0040] Specifically, an N-type doped region is formed on the upper surface of the P-well region 120 through processes such as ion implantation. This N-type region serves as the cathode of the photodiode 130 and together with the P-well region 120 below, forms a PN junction, namely the so-called NP photodiode 130. This N-type doped cathode 131 is located in the shallow layer of the device, directly located or near the light receiving surface, so as to efficiently absorb incident light.

[0041] When incident light shines on the photodiode 130, photons enter the depletion region or P-well region 120 below the doped cathode 131. If the photon energy is greater than the semiconductor bandgap, it excites valence band electrons to jump to the conduction band, generating electron-hole pairs. Under the action of the built-in electric field of the PN junction, photogenerated electrons are swept toward the N+ cathode, and holes are swept toward the P-well region 120. Electrons accumulate at the N+ cathode, forming a measurable photocurrent or voltage signal.

[0042] As an feasible approach, such as Figure 5 As shown, an intrinsic layer 132 is also provided on the lower surface of the doped cathode 131.

[0043] An intrinsic layer 132 is formed on the lower surface of the doped cathode 131. The doped cathode 131, intrinsic layer 132, and P-well region 120 form a PIN diode, which significantly expands the width of the depletion region inside the device. This allows most of the photogenerated carriers to be generated in the strong electric field region of intrinsic layer 132 and quickly collected by the drift mechanism, avoiding the delay and recombination loss caused by slow diffusion in the neutral region. This reduces the tailing effect and noise caused by diffusion current and improves the dynamic response speed.

[0044] Optional, such as Figure 4 and Figure 5 As shown, the field-effect transistor region includes a source / drain layer disposed on the upper surface of the P-well region 120, and a gate oxide layer and a gate layer disposed sequentially on the source / drain layer. A first drain 141, a source 143, and a second drain 145 are disposed sequentially and spaced apart on the source / drain layer. A first gate 142 and a second gate 144 are disposed spaced apart on the gate layer. The projection of the first gate 142 on the source / drain layer is located between the first drain 141 and the source 143, and the projection of the second gate 144 on the source / drain layer is located between the second drain 145 and the source 143.

[0045] As one possible implementation, the first gate 142 and the second gate 144 are polysilicon gates.

[0046] The first gate 142 and the second gate 144 are located on the gate oxide layer and are used to control the channel between the first drain 141 and the source 143 and the second drain 145 and the source 143, respectively.

[0047] Polycrystalline silicon can withstand high-temperature processes and is not easily deformed during subsequent high-temperature processes such as annealing. In addition, the low interface state density between polycrystalline silicon and the gate oxide layer of silicon dioxide results in a stable interface, which helps to form high-quality contacts.

[0048] Optionally, a shallow trench isolation structure 150 is provided between the photoelectric region and the field-effect transistor region.

[0049] The shallow trench isolation structure 150 can block unintended electrical connections between the photoelectric region and the amplifier tube 140, preventing photocurrent from flowing directly into the source 143 or gate without passing through the control channel, thus avoiding signal distortion or readout errors.

[0050] The above description is merely an optional embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0051] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this application will not describe the various possible combinations separately.

Claims

1. A photoelectric sensor, characterized in that, include: Substrate and P-well region formed on said substrate; The P-well region is provided with multiple photoelectric regions arranged in an array, and a field-effect transistor region is located between two adjacent photoelectric regions, and the photoelectric regions and the field-effect transistor regions are electrically isolated from each other. The photoelectric region is provided with a photodiode, and the field-effect transistor region is provided with an amplifying transistor. The amplifying transistor includes a first drain, a first gate, a source, a second gate, and a second drain arranged sequentially along the line connecting the two photodiodes. The photodiode is used to convert the received incident light into photocurrent, and the amplifier tube is used to amplify the received photocurrent from both sides.

2. The photoelectric sensor according to claim 1, characterized in that, The photoelectric area is square, and the photoelectric areas in adjacent rows are aligned or staggered.

3. The photoelectric sensor according to claim 1, characterized in that, The photoelectric region is a regular hexagon, and the photoelectric regions in two adjacent rows are staggered to fill the gap between two photoelectric regions in an adjacent row.

4. The photoelectric sensor according to claim 2 or 3, characterized in that, The first drain, the first gate, the source, the second gate, and the second drain all extend along the extension direction of the edge of the photoelectric region.

5. The photoelectric sensor according to claim 4, characterized in that, The lengths of the first drain, the first gate, the source, the second gate, and the second drain are all the same as the side length of the photoelectric region.

6. The photoelectric sensor according to claim 1, characterized in that, The photoelectric region includes a doped cathode disposed on the upper surface of the P-well region.

7. The photoelectric sensor according to claim 6, characterized in that, The lower surface of the doped cathode is also provided with an intrinsic layer.

8. The photoelectric sensor according to claim 1, characterized in that, The field-effect transistor region includes: a source / drain layer disposed on the upper surface of the P-well region, and a gate oxide layer and a gate layer disposed sequentially on the source / drain layer; The first drain, the source, and the second drain are sequentially and spaced apart on the source-drain layer. The first gate and the second gate are spaced apart on the gate layer. The projection of the first gate on the source-drain layer is located between the first drain and the source. The projection of the second gate on the source-drain layer is located between the second drain and the source.

9. The photoelectric sensor according to claim 8, characterized in that, The first gate and the second gate are polysilicon gates.

10. The photoelectric sensor according to claim 1, characterized in that, A shallow trench isolation structure is provided between the photoelectric region and the field-effect transistor region.

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