A spad chip and a laser radar device
By slotting SPAD dies in the substrate and using a flip-chip soldering and molding compound sealing structure, the problems of poor heat dissipation and increased package thickness in traditional iBGA packaging are solved, achieving a thinner and lower-cost packaging effect.
Patent Information
- Application Number
- CN202522517156.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-11-03
- Estimated Expiration
- 2035-11-26
AI Technical Summary
Traditional iBGA packaging solutions result in poor chip heat dissipation performance and increased package thickness, making packaging more difficult.
The packaging structure using SPAD chips involves placing SPAD dies in slots in the substrate, and then sealing them with flip-chip soldering and a plastic encapsulation, combined with solder ball connections, to form a thin and lightweight package.
This enables thinner and lighter chip packaging, improves heat dissipation performance, and reduces packaging costs.
Smart Images
Figure CN224936021U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit packaging, and more particularly to a SPAD chip and a lidar device. Background Technology
[0002] Traditional flip-chip ball grid array (iBGA) packaging solutions place the active side of the chip (i.e. the side with transistor circuitry) downwards, and use solder bumps on it to place the chip on top of the packaging substrate, thereby connecting it to the packaging substrate.
[0003] However, because the chip is encased in the package, it is difficult to dissipate heat during operation, resulting in poor heat dissipation performance of iBGA packaged chips. Furthermore, since the chip is located on top of the package substrate, it increases the overall thickness of the packaged chip, making packaging more difficult. Utility Model Content
[0004] This application provides a SPAD chip to address the issues of reducing the overall chip packaging thickness and complexity.
[0005] The first aspect of this application provides a SPAD chip, including:
[0006] A substrate; wherein the substrate has a slot in the middle for transmitting light to the SPAD chip, and the lower surface of the substrate has substrate pads for soldering the SPAD chip.
[0007] An optical cover plate is fixedly disposed on the substrate and covers the slot;
[0008] SPAD die; wherein the SPAD die is bonded to the substrate pads by flip-chip bonding and faces the side of the optical cover, so that the photosensitive area of the SPAD chip is directly opposite the slot;
[0009] Multiple bumps are formed between the substrate pads and the corresponding lead-out pads on the SPAD die, so as to electrically connect and mechanically fix the SPAD die to the substrate;
[0010] A molding compound is used to fill the gap between the SPAD die and the substrate, covering all bumps;
[0011] Multiple solder balls are mounted on the substrate pads on the side of the substrate facing the SPAD die.
[0012] Optionally, it also includes a sealing reinforcement body;
[0013] The sealing and reinforcing body covers a portion of the SPAD die and a portion of the lower surface of the substrate, and extends to the root of the covered solder balls to form an integral package structure.
[0014] Optionally, the material of the sealing reinforcement is a sealant or a molding compound.
[0015] Optionally, the plurality of bumps includes at least one gold bump, and a redistribution layer is provided in the substrate;
[0016] The lead-out pads of the SPAD die are electrically connected to the solder balls via the gold bumps, the substrate pads on the substrate, and the redistribution layer.
[0017] Optionally, solder ball pads; wherein the solder ball pads are formed on the redistribution layer and are used to connect the redistribution layer and the solder balls.
[0018] Optionally, the height of the gold bump is 10 micrometers to 50 micrometers.
[0019] Optionally, the optical cover plate is made of one of optical glass, narrowband filter or superlens;
[0020] The thickness of the optical cover plate is between 200 micrometers and 2000 micrometers.
[0021] Optionally, the substrate is either a single-sided panel or a double-sided panel.
[0022] Optionally, the substrate has multiple SPAD die packaging structures arranged in an array, with cleaving channels between each packaging structure.
[0023] The second aspect of this application provides a lidar device, including: the SPAD chip and laser emitting device described in the first aspect.
[0024] As can be seen from the above technical solutions, the embodiments of this application have the following advantages: With the SPAD chip disclosed in this application, since the die thickness is smaller than that of the solder ball, placing the SPAD die under the substrate does not increase the package thickness, thereby reducing the overall package structure thickness. Secondly, since the SPAD die is not completely enclosed and its back side is exposed, the heat generated during SPAD die operation can be directly dissipated, which is far superior to the iBGA solution that completely encloses the die within the package. Attached Figure Description
[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.
[0026] Figure 1 This is a partial schematic diagram of an iBGA package in the prior art;
[0027] Figure 2 This is an overall schematic diagram of a SPAD chip disclosed in an embodiment of this application;
[0028] Figure 3 This is a partial schematic diagram of a SPAD chip disclosed in an embodiment of this application. Detailed Implementation
[0029] To facilitate understanding of this application, a more complete description of the application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the application. However, the application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of this application thorough and complete. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0030] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0031] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0033] Combination Figure 1 , Figure 1 This is a partial schematic diagram of an iBGA package in the prior art. Figure 1 As shown, in existing technologies, the chip is directly soldered to the upper surface of the PCB substrate in a top-mount configuration using gold wire (Au wire). Simultaneously, encapsulated epoxy resin is used to wrap the gold wire, achieving electrical connection between the chip and the PCB substrate. The glass cover is bonded to the chip using epoxy resin (an adhesive). Furthermore, solder balls are soldered to the lower surface of the PCB substrate. Therefore, the existing iBGA packaging scheme tends to result in a large package thickness, and because the back of the chip is the PCB board, heat dissipation is poor. Secondly, in top-mount configuration, the chip is placed in the middle, requiring connecting wires, which are relatively long, leading to low electrical conductivity. Moreover, the gold wire, being a precious metal, also increases packaging costs.
[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0035] Please see Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of an overall SPAD chip disclosed in an embodiment of this application. Figure 3 This is a partial schematic diagram of a SPAD chip disclosed in an embodiment of this application. (In conjunction with...) Figure 1 and Figure 2 As shown, in the technical solution of this application, a slot is cut in the middle of the PCB substrate, and the chip is placed directly below the slot. Furthermore, the PCB substrate can be selected as a single-sided or double-sided board according to actual needs, and the relevant circuits can be placed below the PCB substrate.
[0036] Please continue reading. Figure 2 and Figure 3 The SPAD chip disclosed in this application comprises a substrate 201, an optical cover plate 202, a SPAD die 203, multiple bumps 204, a molding compound 205, and multiple solder balls 206. In some specific embodiments,
[0037] A substrate 201 is provided; wherein, a slot for light transmission to the SPAD die 203 is provided in the middle of the substrate 201, and a substrate 201 pad for soldering the SPAD die 203 is provided on the lower surface of the substrate 201. In some embodiments, the substrate 201 is a PCB substrate 201. For example, in this embodiment, a PCB cover plate with a low coefficient of thermal expansion (CTE) can be used. For ease of understanding, this will not be described in detail below.
[0038] An optical cover plate 202 is fixedly disposed on a substrate 201 and covers the slot. In some embodiments, the optical cover plate 202 is a glass cover plate.
[0039] SPAD die 203; wherein, the SPAD die 203 is bonded to the substrate 201 pad by flip-chip bonding and faces the side of the optical cover plate 202, so that the photosensitive area of the SPAD die 203 is directly opposite the slot.
[0040] Multiple bumps 204 are formed between the pads on the substrate 201 and the corresponding lead-out pads on the SPAD die 203 to electrically connect and mechanically fix the SPAD die 203 to the substrate 201. In some embodiments, the bumps 204 are gold Au bumps 204 on the SPAD die 203.
[0041] The molding compound 205 fills the gap between the SPAD die 203 and the substrate 201, covering all the bumps 204. In some embodiments, the molding compound 205 may be an epoxy resin, or other similar curing agents, adhesives, etc., and the specific material of the molding compound 205 is not limited here.
[0042] Multiple solder balls 206 are mounted on the substrate 201 pads on the side of the substrate 201 facing the SPAD die 203. In some embodiments, one or more metal routing layers (RDL, Redistribution Layer) are fabricated on the substrate 201 pads. Its main function is to rearrange the originally closely spaced I / O solder joints inside the die 203 to a more spacious and easily connectable area on the surface of the die 203. The solder balls 206 are soldered to the surface of the RDL, thus forming metal pads (solder ball 206 pads) for soldering the BGA solder balls 206.
[0043] In some embodiments, the packaging structure of the SPAD die 203 further includes a sealing reinforcement 207. Specifically, the sealing reinforcement 207 covers a portion of the SPAD die 203 and the lower surface of a portion of the substrate 201, and extends to the root of a portion of the solder balls 206, forming an integral packaging structure. In some embodiments, the sealing reinforcement 207 is made of a sealant or molding compound, such as encapsulated epoxy resin or epoxy encapsulating adhesive.
[0044] In some embodiments, the plurality of bumps 204 include at least one gold bump 204 (Au Bump), and a redistribution layer is provided in the PCB substrate 201. Thus, the lead-out pads of the SPAD die 203 are electrically connected to the solder balls 206 through the gold bump 204, the substrate 201 pads on the substrate 201, and the redistribution layer.
[0045] In some embodiments, a plurality of solder balls 206 are soldered onto solder ball 206 pads. The solder ball 206 pads are formed on the redistribution layer and are used to connect the redistribution layer and the solder balls 206.
[0046] In some embodiments, the height of the gold bump 204 is 10 micrometers to 50 micrometers. The optical cover plate 202 is made of optical glass, a narrow-band filter, or a superlens. The thickness of the optical cover plate 202 is 200 micrometers to 2000 micrometers. The PCB substrate 201 is either a single-sided board or a double-sided board.
[0047] In some embodiments, a plurality of SPAD die 203 packaging structures are arranged in an array on the PCB substrate 201, and a cutting channel is provided between each packaging structure.
[0048] In some embodiments, the glass cover can be bonded to the PCB substrate 201 using glass attach epoxy 208. The glass attach epoxy 208 can be epoxy resin or other similar curing agents, adhesives, etc., and the specific material of the glass attach epoxy is not limited here.
[0049] In the embodiments of this application, in conjunction with the above description, it can be seen that the following operations are required to implement the packaging structure of the SPAD die 203 in this application.
[0050] Step 1: Use a low CTE PCB substrate 201. Specifically, a slot is made in the middle of the PCB substrate 201 to prepare for light transmission to the SPAD die 203. At the same time, pads are led out at the relative positions of each pad on the SPAD die 203 to prepare for flip-chip soldering of the die 203.
[0051] Step 2: Cover with glass. Place the glass (i.e., the optical cover plate 202 mentioned above) onto the PCB substrate 201 to provide light transmission and protection for the photosensitive surface of the SPAD die 203. This glass can be any optical component, such as high-transmittance glass, narrow-band filters, or superlenses, with a thickness selectable from 200 to 2000 μm to meet any optical requirements of the sensor.
[0052] Step 3, Au Bump. Create Au bumps 204 (i.e., the gold bumps 204 mentioned above) on the PAD of the SPAD die 203. The height of the bumps 204 is between 10 and 50 μm.
[0053] Step 4: Flip-chip bonding. The bare die 203 with Au bumps 204 is flip-chip bonded to the pads of the substrate 201. The Au bumps 204 and the pads of the substrate 201 are bonded by flip-chip thermoforming of the bare die 203, thus completing the I / O lead-out.
[0054] Step 5: Applying adhesive. Apply sealant (i.e., the molding compound 205 mentioned above) around the flipped SPAD die 203 and into the gap between the SPAD die 203 and the PCB substrate 201 by applying adhesive, sealing all Au bumps 204 to the PCB substrate 201 and providing bonding strength for the overall structure.
[0055] Step 6: Ball Placement. Ball placement is performed on the RDL solder ball 206 pads to complete the fabrication of the solder balls 206 in surface mount technology (SMT). At this point, all I / Os on the wafer are connected and conductive to the individual solder balls 206 via the RDL process.
[0056] Step 7: Sealing. The solder ball 206 and the SPAD die 203 are reinforced with sealant or molding compound (i.e., the sealing reinforcement 207 mentioned above) to form a reinforced seal.
[0057] Step 8: Cutting. Cut the PCB substrate 201 to form a package structure of a single ICSPAD die 203.
[0058] This leads to the formation of a complete SPAD chip.
[0059] Furthermore, in this embodiment of the application, this packaging scheme replaces the traditional iBGA packaging scheme, see... Figure 1 Specifically, eliminating long leads and directly soldering the chip onto the underside of the PCB via flip-chip bonding results in superior electrical performance. Furthermore, sealing the chip by applying adhesive around its perimeter and adding a glass cover to the front of the PCB creates a sealed cavity for the sensor area, achieving a thinner and lighter package. The glass cover provides strong reinforcement during packaging and can also meet the stringent spectral requirements of different chips, achieving a transmittance of over 99% to satisfy detection conditions.
[0060] The SPAD chip in this embodiment can achieve the following technical effects.
[0061] Small package thickness: The main innovation of this package is the flip-chip design, which makes the Z-axis dimension of this package smaller than that of the iBGA package (0.5mm). Because the chip thickness is smaller than that of the solder ball, placing it under the PCB board will not increase the overall thickness, thus reducing the thickness on the board.
[0062] Excellent heat dissipation: This packaging method uses direct exposed silicon backing, allowing the heat generated by the IC chip during operation to be dissipated directly through the silicon backing. This heat dissipation effect is far superior to iBGA packaging (where the chip is encased within the package). In this application, only sealant is used to encapsulate the chip; in existing technologies, the back of the chip is a PCB board.
[0063] High electrical performance: Flip-chip technology has a shorter signal path, which can reduce signal transmission delay and improve electrical performance.
[0064] Low cost: Replacing traditional gold wires with Au Bumps reduces the use of precious metals, further lowering costs; fewer glass substrate packaging methods and steps also effectively reduce packaging costs.
[0065] A second aspect of this application also provides a lidar device, including a SPAD chip and a laser emitting device.
Claims
1. A SPAD chip, characterized in that, include: A substrate; wherein the substrate has a slot in the middle for transmitting light through the SPAD die, and the lower surface of the substrate has substrate pads for soldering the SPAD die. An optical cover plate is fixedly disposed on the substrate and covers the slot; SPAD die; wherein the SPAD die is bonded to the substrate pad by flip-chip bonding and faces the side of the optical cover plate, so that the photosensitive area of the SPAD die is directly opposite the slot; Multiple bumps are formed between the substrate pads and the corresponding lead-out pads on the SPAD die, so as to electrically connect and mechanically fix the SPAD die to the substrate; A molding compound is used to fill the gap between the SPAD die and the substrate, covering all the bumps; Multiple solder balls are mounted on the substrate pads on the side of the substrate facing the SPAD die.
2. The SPAD chip according to claim 1, characterized in that, It also includes sealing reinforcement; The sealing and reinforcing body covers a portion of the SPAD die and a portion of the lower surface of the substrate, and extends to the root of the covered solder balls to form an integral package structure.
3. The SPAD chip according to claim 2, characterized in that, The material of the sealing reinforcement is sealant or molding compound.
4. The SPAD chip according to claim 1, characterized in that, The plurality of bumps includes at least one gold bump, and a redistribution layer is provided in the substrate. The lead-out pads of the SPAD die are electrically connected to the solder balls via the gold bumps, the substrate pads on the substrate, and the redistribution layer.
5. The SPAD chip according to claim 4, characterized in that, Solder ball pads; wherein the solder ball pads are formed on the redistribution layer and are used to connect the redistribution layer and the solder balls.
6. The SPAD chip according to claim 4, characterized in that, The height of the gold bumps is 10 micrometers to 50 micrometers.
7. The SPAD chip according to claim 1, characterized in that, The optical cover is made of one of the following materials: optical glass, narrow-band filter, or superlens. The thickness of the optical cover plate is between 200 micrometers and 2000 micrometers.
8. The SPAD chip according to claim 1, characterized in that, The substrate is either a single-sided panel or a double-sided panel.
9. The SPAD chip according to claim 1, characterized in that, Multiple SPAD chips are arranged in an array on the substrate, and cleaving channels are provided between each package structure.
10. A lidar device, characterized in that, include: The SPAD chip and laser emitting device as described in any one of claims 1-9.