Method for forming an opening in a metallization structure of a semiconductor device using a self-limiting deposition process

Abstract

Methods involving: Forming an opening (208) in a metallization structure of a semiconductor device (200), wherein the opening has a substantially horizontal first surface (208B) and a substantially vertical second surface (208S); Providing an inhibitor material (221) over the first surface (208B) by performing a directional deposition process, wherein the substantially horizontal first surface is a surface that is oriented substantially perpendicular with respect to a deposition direction of the directional deposition process; and After the provision of the inhibitor material, at least one first layer of a coating material (210) is deposited by a self-limiting deposition process (211), wherein the inhibitor material produces a reduced deposition rate on the first surface compared to a deposition rate on the second surface of the opening.

Description

Field of the present invention

[0001] The present invention relates generally to the field of integrated circuit fabrication and, more particularly, to the fabrication of an interconnect structure requiring a barrier layer formed between a metal and a dielectric, wherein the barrier layer is formed at least partially by self-limiting deposition techniques, such as ALD (atomic layer deposition). Description of the state of the art

[0002] In a complex circuit, a large number of circuit elements, such as transistors, capacitors, resistors, and the like, are manufactured in or on a suitable substrate, typically in a planar configuration. Due to the large number of circuit elements and the required complex circuit design of integrated circuits, the electrical connections of the individual circuit elements generally cannot be made in the same plane as the circuit elements. Instead, one or more additional "wiring layers," also referred to as metallization layers, are required.These metallization layers generally contain metal lines that provide the electrical connection within the level and also contain a plurality of interlevel connections, also called vias, where the metal lines and vias are collectively referred to as the interconnect structure.

[0003] Due to the constant reduction in the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, i.e., the packing density, is also increasing, requiring an even greater number of electrical connections to achieve the desired circuit function. Therefore, the number of stacked metallization layers increases as the number of circuit elements per chip area increases. Since the fabrication of multiple metallization layers presents major challenges with regard to the mechanical, thermal, and electrical reliability of the many stacked metallization layers required, for example, in modern microprocessors, semiconductor device manufacturers are increasingly using a metal that enables higher current densities and thus offers the possibility of reducing the dimensions of the interconnect structures.For example, copper is a metal generally considered a suitable candidate due to its superior properties in terms of resistance to electromigration and its significantly lower electrical resistance compared to other metals, such as aluminum, which has been used efficiently over the past decades. Despite these advantages, copper presents several disadvantages with regard to the processing and handling of copper in a semiconductor fabrication facility. For example, copper cannot be efficiently deposited onto a substrate in large quantities using well-established deposition techniques, such as chemical vapor deposition (CVD), nor can it be effectively patterned using typically used anisotropic etching procedures due to the formation of essentially no volatile etch byproducts.Therefore, the so-called damascene technique is preferred for the production of metallization layers with copper. A dielectric layer is first deposited and then patterned to create trenches and contact holes, which are subsequently filled with copper. A major disadvantage of copper is its ability to diffuse into low-k dielectric materials, such as silicon and silicon dioxide, which are well-established and proven dielectric materials in the manufacture of integrated circuits.

[0004] It is therefore necessary to use a so-called barrier material in conjunction with a copper-based metallization to essentially suppress the out-diffusion of copper into the surrounding dielectric material, as copper can otherwise migrate to sensitive semiconductor regions, significantly altering their properties. On the other hand, the barrier material should suppress the diffusion of reactive components into the metal region. However, the barrier material provided between the copper and the dielectric material should, in addition to the required barrier properties, exhibit good adhesion to the dielectric material and the copper and should also have the lowest possible electrical resistance so as not to undesirably impair the electrical properties of the interconnect structure.However, it is becoming apparent that a single material cannot easily meet the requirements imposed on a desired barrier material. Therefore, a mixture of materials is often used to provide the desired barrier properties. For example, a bilayer of tantalum and tantalum nitride is often used as a barrier material in conjunction with a copper damascene metallization layer.Tantalum, which effectively suppresses the diffusion of copper atoms into neighboring material, even when applied as an extremely thin layer, exhibits poor adhesion to a variety of dielectric materials, such as silicon dioxide-based dielectrics. Consequently, a copper interconnect structure with a tantalum barrier layer often exhibits lower mechanical stability, particularly during chemical-mechanical polishing of the metal layer, which may be required to remove excess copper and level the surface for the application of another metallization layer. However, the low mechanical stability during CMP can lead to serious reliability issues related to reduced thermal and electrical conductivity of the interconnect structure.On the other hand, tantalum nitride exhibits excellent adhesion properties to silicon dioxide-based dielectrics, but has very poor adhesion to copper. Consequently, modern integrated circuits with copper-based metallization typically use a tantalum nitride / tantalum bilayer. The requirement for low resistance of the interconnect structure, combined with the continuous reduction in the dimensions of circuit elements and thus also of metal lines and vias, requires a reduction in the thickness of the barrier layer while still achieving the required barrier effects. Tantalum nitride has been recognized to offer excellent barrier properties even when deposited at a thickness of only a few nanometers or less.Therefore, sophisticated deposition processes have been developed to form thin tantalum nitride layers with a high degree of conformality even in high aspect ratio openings, such as the vias of modern metallization structures. These deposition processes exhibit essentially self-limiting deposition behavior, allowing the deposition of extremely thin layers with reliable coverage even in critical areas, such as the sidewall regions of vias and the like. Thus, self-limiting processes, also referred to as ALD (atomic layer deposition), are used to fabricate barrier layers for copper-based interconnect structures. Although these processes offer a promising approach for further device size reduction, there is still room for improvement, as described in detail below with reference to the . Fig. 1a to 1c.

[0005] In Fig. 1a, a metallization structure 100 comprises a substrate 101, for example a semiconductor substrate with a plurality of individual circuit elements (not shown), such as transistors, resistors, capacitors, and the like. The substrate 101 is intended to represent any type of suitable substrate, with or without additional circuit elements, and in particular represents substrates for modern integrated circuits and circuit elements formed therein with critical feature sizes well below 1 µm. A first dielectric layer 102 is formed on the substrate 101 and includes a metal region 104 including a metal line 103, such as a copper line, and a first barrier layer 106 composed of tantalum and a second barrier layer 105 composed of tantalum nitride.The dielectric layer 102, which may include an etch stop layer 102a, represents a first metallization layer in conjunction with the metal interconnect structure 104. A second dielectric layer 107, comprised of silicon dioxide or a silicon dioxide-based dielectric material or another suitable dielectric material, is formed over the first dielectric layer 102 and has formed therein a trench 109 and a via connected to the metal line 103. A preform 110a of the first barrier layer 110 is formed on exposed surface areas, such as the inner surfaces of the via 108 and the trench 109.

[0006] A typical process flow for producing the metallization structure 100 as shown in Fig. 1a may comprise the following steps, wherein for the sake of simplicity, only the formation of the second metallization layer, i.e., the second dielectric layer 107 and the metal interconnect structure formed therein, will be described in detail, since the processes for forming the metal interconnect structure 104 in the first dielectric layer 102 may include substantially the same process steps. Thus, after planarizing the dielectric layer 102 comprising the metal interconnect structure 104, the etch stop layer 102a may be deposited, followed by the deposition of the dielectric layer 107 by well-known deposition techniques, such as plasma-enhanced CVD. Subsequently, the dielectric layer 107 may be patterned by well-known photolithography and anisotropic etching techniques, wherein an intermediate etch stop layer (not shown) may optionally be used to pattern the trench 109.It should also be noted that different approaches can be used to form the trench 109 and the via 108, such as the so-called "via first, trench last" approach or a "trench first, via last" approach, where in the former approach, the via 108 is filled with metal before the trench 109 is formed. In the present example, a so-called dual Damascene technique is described, in which the trench 109 and the via hole 108 are filled with metal simultaneously.After the formation of the contact via 108 and the trench 109, the preform 110a of the first barrier layer 110 is deposited by a self-limiting deposition process 111, in which, in a first step, suitable gases are supplied, for example, obtained from organometallic compounds, such as pentakis(dimethylamino)Ta (PDMAT). In other cases, the layer 110a is formed based on tantalum chloride if the presence of chlorine does not negatively affect the reliability of the resulting interconnect structure. In general, the deposition of the thin barrier layer 110, typically with a thickness in the range of 1 to 15 nm or less, can be reliably accomplished on the entire inner surfaces of the trench 109 and the contact via 108 based on the ALD process 111, wherein, in particular, the contact via 108 has a high aspect ratio.It is therefore generally desirable to achieve reliable coverage of the sidewalls of trench 109 and contact via 108 with a minimal thickness of layer 110 such that only a minimal amount of volume is "consumed" by layer 110. Increasing the thickness of barrier layer 110 would otherwise undesirably impair the electrical conductivity of the interconnect structures to be formed in contact via 108 and trench 109, particularly when the feature sizes in the metallization level are set to 0.2 µm and less.

[0007] Fig. 1b schematically shows the metallization structure 100 during a second step of the ALD process 111, wherein a second gas environment is generated to form the tantalum nitride layer 110. For example, activated nitrogen may be introduced to initiate the desired surface reaction based on the preform 110a, wherein the reaction and thus the final layer thickness are determined by the preform 110a. Thus, a continuous coverage of the inner surfaces of the trench 109 and the contact via 108 is achieved to thereby create a reliable diffusion barrier, in particular at critical positions, such as the sidewalls of the contact via 108 and the trench 109. However, tantalum nitride has a moderately high electrical resistance, which may lead to an undesirably high overall resistance of the contact via 108 after providing the tantalum material and filling the structure with a copper-based material.Therefore, before forming a second tantalum-based barrier layer, layer 110 is removed from the underside of the via 108b. This is done using a sputter etching process, typically with a high degree of directional stability.

[0008] Fig. 1c schematically shows the metallization structure 100 during a corresponding sputter-etch process 112 for opening the bottom side 108b of the via. During the process 112, corresponding material is also removed at other substantially horizontal areas, for example, in the trench 109, which may also affect the extremely sensitive low-k dielectric material 107. During the aggressive back-sputtering process 112 on the via bottom side 108b, copper is also released into the etching environment, which may then redeposit at undesired positions, possibly resulting in lower performance and possibly reduced reliability of the finally obtained interconnect structure in conjunction with the damaged low-k dielectric.

[0009] After the sputter etching process 112, tantalum is deposited, for example by sputter deposition, to obtain the desired barrier and adhesion properties, as previously explained.

[0010] Fig. Figure 1d schematically shows the metallization structure 100 with a second barrier layer 113 composed of tantalum, wherein the layer 113 may extend into the metal line 103 due to the preceding sputter etching process 112. The trench 109 may have damaged areas that may lead to corresponding line irregularities.

[0011] US 2006 / 0 027 925 A1 shows a method for producing a multilayer barrier structure in a contact hole, wherein conventional deposition methods are used to deposit an amorphous layer on the contact hole bottom, and the amorphous layer is removed again from the contact hole bottom by ion beam processing.

[0012] WO 2006 / 097 426 A1 shows a method for producing a multilayer barrier structure comprising two barrier layers in a contact hole, wherein the first barrier layer has a different growth rate than the second barrier layer for a subsequently formed layer.

[0013] US 2006 / 0 019 485 A1 describes a multilayer wiring of a semiconductor device, wherein a protective film is deposited within a trench to be filled.

[0014] US 2006 / 0 251 800 A1 describes a via filling with a barrier layer over a silicide layer. A process such as PVD, CVD, or ALD is used to fill the structure.

[0015] US 2005 / 0 054 196 A1 describes a contact hole filling, wherein a conformal monolayer is first deposited in the contact hole.

[0016] US 2003 / 0 087 490 A1 describes a method for producing an interconnection structure in a semiconductor device, in which a Ti film is first deposited by ion metal plasma sputtering in order to improve the crystallinity of the subsequently deposited copper.

[0017] US 2006 / 0 178 002 A1 describes a method for producing a dual damascene wiring using a cover layer at the bottom of the contact hole to protect the underlying connecting line.

[0018] Consequently, although the ALD process for the tantalum nitride layer provides high reliability in covering critical sidewalls of the via and trench, the subsequent aggressive removal of the high-resistance tantalum nitride material can cause damage in other sensitive device areas, reducing the performance and reliability of the interconnect structure, especially when considering extremely reduced-size semiconductor devices.

[0019] In view of the problems identified previously, there is a need for improved barrier technology that avoids or at least reduces the impact of one or more of the problems identified above. Overview of the invention

[0020] According to the invention, a method having the features of claim 1 is provided.

[0021] In general, the present invention relates to a technique for fabricating material layers using a self-limiting deposition process, such as ALD (atomic layer deposition), to advantageously exploit the high degree of conformality achieved for the resulting material layer, even when provided at very low layer thicknesses and based on challenging surface topography, as is typically encountered during the fabrication of modern semiconductor devices. On the other hand, the highly conformal deposition rate can be deliberately modified locally to achieve a certain degree of selectivity for the deposition process, enabling the selective deposition of extremely thin yet continuous layer regions on specific device surfaces while maintaining a correspondingly reduced layer thickness in other regions.The concept of a selective self-limiting deposition process can be advantageously applied to the fabrication of critical material layers, such as conductive barrier layers for conductive metallization structures for other advanced coating materials, which require highly selective deposition between different exposed surface areas. Therefore, in one illustrative aspect of the present invention, the selective self-limiting deposition process according to claim 1 is applied to form conductive barrier layers, providing selectivity with respect to substantially horizontal and substantially vertical surface areas, thereby significantly reducing, for example, the contact resistance between extremely reduced-size vias and metal lines in corresponding metallization structures. Short description of the drawings

[0022] Further advantages, objects and embodiments of the present invention are defined in the appended claims and will become more apparent from the following detailed description when studied with reference to the accompanying drawings in which: Fig. 1a to 1d schematically show cross-sectional views of a conventional semiconductor device during the fabrication of a metallization structure based on a self-limiting deposition process for forming a tantalum nitride barrier layer, wherein an aggressive sputter etching process is required to remove the tantalum nitride material from unwanted areas according to a conventional technique; Fig. 2a to 2c schematically show cross-sectional views of a semiconductor device having a device structure on whose exposed surfaces a material layer is to be selectively formed based on a self-limiting deposition process with a preceding step of applying an inhibitor material according to illustrative embodiments; Fig. 2d to 2f schematically show cross-sectional views of a component structural element selectively receiving a material layer based on a self-limiting process using a selectively applied catalyst material according to alternative methods; Fig. 2g to 2i schematically show cross-sectional views of a component structural element during different steps of a self-limiting deposition process, wherein intermediately exposed surfaces are modified to achieve a different layer thickness according to further alternative methods; and Fig. 3a to 3d schematically show cross-sectional views of a device structural element of a metallization structure during various manufacturing stages for producing a barrier layer based on a self-limiting deposition process, wherein the deposition rate is different for substantially vertical and horizontal surface areas. Detailed description

[0023] Although the present invention has been described with reference to the embodiments illustrated in the following detailed description and the drawings, it should be understood that the following detailed description and the drawings are not intended to limit the present invention to the specific illustrative embodiments disclosed, but the described illustrative embodiments merely exemplify the various aspects of the present invention, the scope of which is defined by the appended claims.

[0024] As previously discussed, during the manufacturing sequence for modern semiconductor devices, sophisticated coating materials must often be created on exposed surface areas, exploiting the inherently advantageous properties of the self-limited deposition processes to achieve highly conformal deposition even for state-of-the-art device structures and extremely reduced critical dimensions. For example, device structural elements are frequently encountered during the complex manufacturing process flow in which substantially vertical and horizontal surface areas are required, at least within certain regions of a corresponding device structural element.For example, semiconductor lines, such as gate electrodes, and the like have substantially vertical sidewall regions and a substantially horizontal surface region, which may require different types of coating materials depending on the process strategy. It should be noted in this regard that any positional specifications regarding the orientation or position of certain components are to be understood as relative specifications with respect to a plane defined by a corresponding surface region. For example, the terms "vertical," "horizontal," "lateral," and the like generally refer to the respective substrate material in and above which the respective device features are formed, wherein the respective substrate material is typically provided in a disk shape at least during most of the manufacturing processes contemplated in this application.On the other hand, terms such as "above," "below," and the like may occasionally refer to a certain reference surface area that does not correspond to the substrate surface. For example, according to the teachings herein, a material layer may be formed "on" or "over" a surface area, regardless of whether the surface area is oriented substantially vertically with respect to the substrate material. Particularly in deposition processes, the corresponding deposition surface is considered a reference plane to precisely indicate the position at which a specific material is actually deposited.

[0025] Another important area for the application of a selective self-limiting deposition process is the fabrication of modern metallization structures, as previously discussed with reference to the Fig. 1a to 1d, since in this case, selective deposition or at least a significantly different layer thickness on various surfaces of corresponding contact hole openings and / or trenches can be extremely advantageous with regard to the overall performance and reliability of the resulting interconnect structure. However, it should be noted that although the present invention is particularly advantageous in connection with metallization structures, the invention can also be applied to any situation in which very thin layer regions are to be provided by a self-limiting deposition process, in which a high degree of conformality is to be suitably adapted for limited surface areas according to the specific process and device requirements.Therefore, unless otherwise stated in the description or the appended claims, the present invention should not be considered limited to the fabrication of metallization structures.

[0026] With reference to the accompanying drawings, various illustrative methods are now described in more detail.

[0027] Fig. 2a schematically shows a cross-sectional view of a semiconductor device 200 formed on and above a corresponding substrate 201, which may represent any suitable carrier material for fabricating corresponding semiconductor features. For example, the substrate 201 represents a bulk semiconductor substrate, an SOI (silicon-on-insulator) substrate, and the like. In some illustrative embodiments, the substrate 201 represents a silicon-based material, i.e., the substrate 201 has formed thereon a corresponding semiconductor layer with a significant proportion of silicon, since the largest proportion of complex integrated circuits, such as CPUs, high-capacity memory chips, and the like, are currently and in the near future manufactured on the basis of silicon.The semiconductor device 200 includes a material layer 207, which may represent any suitable material, such as a dielectric material, a low-k dielectric material, a semiconductor material, and the like. In one illustrative embodiment, the material layer 207 represents a dielectric material, as described in more detail with reference to FIGS. Fig. 3a to 3d. In this manufacturing phase, the semiconductor device 200 comprises a device structure element 208, which in the illustrated embodiment is provided as an opening with at least a first exposed surface 208b and a second exposed surface 208s. For example, the device structure element 208 may comprise a trench with a width, ie, Fig. 2, the horizontal extent, according to the device requirements, wherein in demanding applications, a corresponding trench width may be in the range of 200 nm and significantly less, or 100 nm and less. In one illustrative embodiment, the first exposed surface 208b represents a substantially horizontal surface, while the second exposed surface 208s represents a substantially vertical surface according to the previously defined definition. In yet other illustrative embodiments, the device feature 208 represents any type of opening, such as a via opening with substantially similar dimensions in each lateral direction.Furthermore, in this manufacturing phase, the semiconductor device 200 may include a surface modification layer 221 configured to modify the deposition rate with respect to a specific self-limiting deposition process, as described below. In the illustrated embodiments, the surface modification layer 221 is provided on substantially horizontal surface areas, such as the first surface 208b, wherein, in one illustrative embodiment, the material 221 generates a reduced deposition rate during a self-limiting process. In this case, a corresponding deposition on or above the first surface 208b is intended to be less efficient due to process- and device-specific requirements.In other illustrative embodiments, the surface modification layer 221 may be a deposition-enhancing material if a lower deposition rate on the second surface 208s is desired. It should be noted that the surface modification layer 221 may be constructed from any suitable material that provides the required surface modification properties and has the required compatibility with subsequent process conditions.

[0028] According to the invention, the surface modification layer 221 is a deposition-preventing material when a significantly reduced degree of deposition is required, at least over the first surface 208b. In this case, any suitable materials can be used for the layer 221 that lead to reduced adhesion of a corresponding preform during a corresponding self-limiting deposition process, as described in more detail below. For example, silicon carbide, possibly in combination with hydrogen, can reduce the degree of adhesion during a self-limiting process for depositing tantalum nitride according to an ALD process, as previously described with reference to the Fig. 1a to 1d. Other suitable materials include corresponding polymer types that significantly modify the local deposition conditions during the self-limiting process. In other illustrative embodiments, the layer 221, if it represents a deposition-hindering material, may comprise corresponding metal-containing materials, as long as the required process compatibility and the deposition-hindering properties are ensured. It should be noted that a thickness of the surface modification layer 221 may be relatively small, since the subsequent self-limiting deposition process essentially depends on the surface properties and therefore even extremely small amounts of "disturbing" particles are sufficient to significantly modify the deposition dynamics at the deposition surface.Thus, a suitable thickness can be in the range of a few nanometers and significantly less, about 1 nm and less.

[0029] The Fig. The semiconductor device 200 shown in Figure 2a may be formed based on the following processes. After providing the substrate 201 and forming the material layer 207, suitable patterning processes, which may include, for example, advanced lithography techniques, anisotropic etching processes, and the like, may be performed according to the device requirements. For example, the device structure element 208, if provided in the form of an opening, may be formed based on appropriately designed masking schemes in conjunction with advanced anisotropic etching techniques, thereby creating the surfaces 208s, 208b as shown.Next, a process 220 for providing the modification layer 221 is performed. In one illustrative embodiment, the process 220 comprises a highly anisotropic deposition process to provide the desired degree of selectivity for covering the first surface 208b while leaving the surface 208s substantially uncovered. For example, corresponding deposition methods with a high degree of directionality may be performed based on ionized physical vapor deposition processes and the like. Corresponding process recipes are well-established for a variety of materials and may be employed in the present invention. Furthermore, certain plasma-enhanced CVD (chemical vapor deposition) processes also have a high degree of nonconformity and may also be advantageously employed in connection with the present invention.According to the invention, a variety of dielectric materials that can be efficiently used as deposition hindering materials can be deposited with a high degree of non-conformal behavior, wherein the degree of conformity can be adjusted by performing a subsequent isotropic and highly selective etching process during which the surface 208s is substantially exposed, while still leaving a certain amount of material on the first surface 208b.

[0030] In other cases, suitable materials, such as polymer materials, can be incorporated into the corresponding surface area during an appropriately designed plasma treatment so that they serve as efficient inhibitor material during the subsequent self-limiting process.

[0031] Fig. 2b schematically illustrates the semiconductor device 200 during a first step of a self-limiting deposition process 211. In the illustrated embodiment, the layer 221 may efficiently reduce the corresponding deposition rate for a preform 210a on the surface 208b, while achieving a reliable and continuous coverage of the surface 208s.

[0032] Fig. 2c schematically shows the semiconductor device 200 during a second step of the self-limiting deposition process 211, wherein the preform 210a is efficiently converted into the desired material layer 210, representing a suitable coating material, a conductive barrier layer, and the like. During the second step of the process 211, the material 221 may also reduce interaction with the gas environment of the second step of the process 211, thereby achieving a high degree of integrity for material disposed beneath the opening 208. Thus, the material 210 may locally provide the desired properties with regard to layer thickness, coverage, and the like, i.e., the surface 208s is reliably covered by the material of the layer 210, while simultaneously achieving a high degree of selectivity with respect to the bottom surface 208b.Thus, the advantages of the highly conformal deposition behavior of the process 211 can be exploited in conjunction with a reliable coverage of critical surface areas, such as the sidewall surface 208s, while still substantially avoiding or at least significantly reducing deposition on and above the surface 208b.

[0033] Fig. 2d schematically illustrates the semiconductor device 200 according to another method. Here, the device structure element 208 also represents an opening, which requires a reliable coverage of the sidewall region 208s, wherein a significantly smaller amount of material is formed on and above the surface 208b. In the manufacturing stage shown, the semiconductor device 200 further comprises a modification layer 221a formed on exposed surfaces of the device 200. In some illustrative methods, the modification layer 221 is formed with a small layer thickness in order to minimize the effects of a corresponding anisotropic patterning process 222 with regard to the material integrity, for example, at the surface 208b.For example, in some illustrative methods, the modification layer 221a is formed based on a deposition process that provides a high degree of conformality, such as a self-limiting process, a chemical vapor deposition process, and the like, where the degree of coverage is critical because continuous coverage is not required for catalytic action in the subsequent process 211. In one illustrative method, the modification layer 221a represents a portion of the material to be formed on the sidewall 208s, but with a significantly smaller layer thickness. Thus, in this case, the modification layer 221a may be formed based on the self-limiting deposition process 211, as will also be described in more detail later.Thus, in some cases, a layer thickness of 1 nm or significantly less may be suitable for layer 221a, thereby appropriately improving the corresponding deposition conditions in the subsequent deposition process. After the deposition of layer 221a, the patterning process 222 may be performed, for example, in the form of a highly anisotropic etching process, to selectively remove material of layer 221a from horizontally oriented surface areas, such as surface 208b. It should be noted that corresponding highly anisotropic etching conditions may be established based on well-established methods, for example, by generating a corresponding plasma environment and / or adding suitable polymer materials that significantly reduce the lateral etch rate compared to the vertical etch rate.Due to the moderately small layer thickness of the layer 221a, a corresponding etch damage possibly caused by the process 222 may not significantly influence the properties of the surface 208b, which is substantially completely exposed during the patterning process 222.

[0034] Fig. 2e schematically shows the semiconductor device 200 after removing unwanted portions of the layer 221a and during a first step of the self-limiting process 211, whereby the preform 210a is deposited with high selectivity due to the presence of the deposition-enhancing material on the sidewall surface region 208s. It should be noted that the self-limiting process 211 is typically performed in a plurality of individual cycles, each comprising the first and second steps, in order to obtain the ultimately required layer thickness of the respective coating material. Thus, in a first step of the self-saturating process 211, a significantly increased thickness is obtained at the surface 208s, which can then be efficiently converted into the desired material composition in a subsequent step.Thus, as long as exposed areas of surface 208b are not sufficiently covered by preform 210a to initiate a self-catalyzing effect, a subsequent step of process 211 may also result in a reduced layer thickness at surface 208b, even though the initial effect of modification layer 211a is no longer effective. Thus, in some illustrative methods, the corresponding process 211 is designed to achieve a significant layer thickness within a moderately small number of process cycles, thereby utilizing the significantly improved deposition rate on material 221a compared to surface 208b.

[0035] Fig. 2f schematically shows the semiconductor device 200 during the second step, ie one of the second steps when several process cycles are considered to convert the preform 210a into the desired material composition in order to obtain the required coating material 210.

[0036] In these processes, a high degree of selectivity of the deposition process 211 based on the layer 221a is also achieved, with the availability of suitable catalyst materials ensuring a high degree of process flexibility.

[0037] With reference to the Fig. 2g to 2i, further illustrative processes are now described in which the corresponding selectivity is created within the different cycles or steps of the self-limiting deposition process.

[0038] Fig. 2g schematically illustrates the semiconductor device 200 of a specified cycle, for example, during a first cycle leading to the deposition of a very thin layer of the preform 210a. This means that a gas environment has been established to form the layer 210a in a self-limiting manner, wherein, in some illustrative embodiments, the resulting thickness of the layer 210a is set to approximately 1 nm and significantly less, thereby ensuring high efficiency in a subsequent patterning process 222. The process 222 represents a highly anisotropic treatment to preferentially remove material from the surface 208b while substantially maintaining the initially generated layer thickness at the surface 208s.For this purpose, suitable anisotropic etch recipes may be employed, wherein in some illustrative embodiments, the process 222 is performed as an in-situ process with respect to the first and second steps of the self-limiting process 211. For example, a suitable plasma environment may be established, thereby creating a high degree of directionality, wherein, due to the reduced layer thickness in the preform 210a, extremely short exposure times are sufficient to produce a corresponding anisotropic material removal.

[0039] Fig. 2h schematically shows the semiconductor device 200 during the first cycle, but during the second step of the process 211, to convert the preform 210a into the final desired material composition of the coating material 210. Due to the preceding anisotropic treatment 222, a high degree of selectivity between the surfaces 208s and 208b is achieved during the first cycle of the process 211.

[0040] Fig. 2i schematically illustrates the semiconductor device 200 during a second cycle of the process 211, i.e., after forming another preform 210a, which may also be treated based on the process 222, as previously described, to thereby provide the desired selectivity in the subsequent second step of the second cycle. Thus, each cycle or multiple cycles of the self-limiting process 211 may obtain a specified selectivity with respect to the surfaces 210s, 210b due to the treatment 222, thereby progressively building up the desired layer thickness at the surface 208s, while maintaining a significantly smaller thickness or substantially exposed area at 208b.It should be noted that the corresponding process 222 for generating the desired degree of selectivity does not necessarily have to be performed after each cycle, but can be performed at specific points in the corresponding process flow to thereby obtain the desired degree of thickness difference of the surfaces 208b, 208s. Since the anisotropic modification process 222 applies to a very thin layer of the preform 210a, the corresponding process conditions can be selected to exert a moderately low influence on the surface 208b. In this case, even repeated application of the anisotropic process 222 results in very little etch damage, thereby maintaining a high degree of integrity of the surface 208b.In other illustrative embodiments, the corresponding anisotropic treatment 222 is performed based on a certain layer thickness on the bottom surface 208b, which is not completely removed, in order to further reduce impacts on the surface 208b.

[0041] Consequently, the methods described so far offer a high degree of selectivity during the self-limiting deposition process, which inherently exhibits high conformality, thereby providing a suitable technique for producing reliable coating materials with a high degree of selectivity between exposed surfaces of the device features. It should also be noted that the device feature 208, shown in the form of an opening, may in other cases be represented by a corresponding feature protruding from the layer 207, for example, to provide a suitable coating material on the corresponding sidewall regions thereof.As previously discussed, the fabrication of extremely thin conductive barrier materials can be an important aspect for further reducing the size of modern semiconductor devices, as metals with good diffusivity, such as copper, can be reliably incorporated into the metallization layer, even in high-aspect-ratio features such as trenches and vias of modern metallization structures. Thus, providing a selective yet highly conformal deposition technique can represent an efficient process technology for future device generators.

[0042] With reference to the Fig. 3a to 3d, further illustrative methods are now described in which the selective self-limiting deposition process is used to form corresponding barrier layers, such as tantalum nitride / tantalum-based layers, wherein the deposition of a corresponding barrier material on the underside of a contact via is efficiently suppressed in order to achieve improved performance of the corresponding interconnect structure compared to conventional structures, as previously described with reference to the Fig. 1a to 1d.

[0043] In Fig. 3a, a semiconductor device 300 comprises a substrate 301 having a dielectric layer 302 formed thereon with a metal region 303. For example, the layer 302 in connection with the metal region 303 represents a metallization layer of the device 300, similar to what has been described with reference to Fig. 1a for the device 100. A dielectric layer 307, which may include an etch stop layer 307a, is formed over the layer 302 and the metal region 303. In modern applications, the dielectric layer 307 may include a low-k dielectric material, which may be understood as a material having a relative permittivity of 3.0 or significantly less. The layer 307 may have a suitable opening formed therein, and for the sake of simplicity, in this illustrative embodiment, a corresponding trench 309 may be formed in conjunction with a contact via 308 connected to the metal region 303. It should be noted that the embodiment shown is merely illustrative in nature and that any other suitable configuration is contemplated, as required for modern metallization structures. While the Fig. In the manufacturing stage shown in Figure 3a, a surface modification layer 321 in the form of a deposition-hindering material may be provided, as previously explained. As shown, the material of layer 321 may be selectively applied to horizontal surface regions of the device 300. Thus, the material of layer 321 may also be present on the surface 308b, while the material of layer 321 may be substantially absent from the sidewall surface 308s or at least provided there with a significantly lower concentration compared to the bottom surface 308b. As previously explained, layer 321 may be formed by an anisotropic treatment, such as a deposition process with a high degree of directionality, a combined deposition and patterning process, and the like.In some illustrative embodiments, the material 321 is deposited using a highly non-conformal deposition technique based on moderately adjusted parameters with regard to ion bombardment, thereby keeping surface degradation of the surface 308b to a low level, while similarly sensitive device regions in the material 307 also remain in a state of high integrity. Next, the device 300 may be subjected to a self-limiting deposition process, as previously described with reference to process 211 or 111, wherein in one illustrative embodiment, the respective process is configured to deposit a conductive barrier material suitable for copper-based metallization structures.Thus, in one illustrative embodiment, the corresponding self-limiting deposition process is performed such that tantalum nitride is deposited, for example, based on corresponding deposition recipes as previously described with reference to the device 100. During the deposition process, the layer 321 provides a high degree of selectivity with respect to the resulting deposition rate, thereby significantly reducing or completely avoiding deposition above the surface 308b.

[0044] Fig. Figure 3b schematically shows the device 300 with a selectively formed material layer 310, which may represent an efficient barrier layer when considering copper-based metallization structures. Thus, critical sidewall regions of the trench 309 and the sidewall of the contact hole opening 308, denoted as 308s, may be reliably covered, while the amount of barrier material above the bottom surface 308b may be efficiently reduced, thereby providing improved overall conductivity performance, as previously explained.

[0045] Fig. 3c schematically shows the semiconductor device 300 in a more advanced manufacturing stage, wherein a second barrier layer 313 is formed over the first layer 310 and over horizontal surface regions, such as the surface 308b. The second barrier layer 313, in conjunction with the layer 310, provides the desired barrier properties, i.e., a high degree of diffusion blocking combined with good adhesion properties. In one illustrative embodiment, the barrier layer 313 is composed of tantalum, which exhibits moderately high adhesion to copper and also efficiently suppresses copper diffusion into the adjacent dielectric materials.The barrier layer 313 may be formed based on well-established processes, such as CVD, sputter deposition, and the like, wherein reliable coverage of the critical sidewall regions is less important due to the reliable coverage by the first barrier layer 310. During the deposition of the second barrier layer 313, an appropriate pre-cleaning process may be performed to efficiently remove residues of the layer 321 and / or other contaminants, which may be accomplished, for example, based on a non-aggressive sputtering process performed during an initial phase of the deposition process for forming the layer 313.Compared to the conventional strategy described above, undesired damage to sensitive device areas, such as the dielectric material 307, when provided as a low-k dielectric material, is substantially avoided or at least significantly reduced, since the corresponding inhibitor material of layer 321 has a significantly reduced thickness and can also be selected to exhibit a high degree of volatility during the corresponding sputter etching process. Thus, the corresponding process parameters for removing contaminants from the material 321 can be selected such that the exposed surface 308b and / or other sensitive device areas are not undesirably affected.In yet other illustrative embodiments, residues of layer 321 are removed by a suitably designed cleaning process, such as a wet-chemical process with a high degree of selectivity with respect to the material of layer 307, thereby further reducing undesirable influence on sensitive component areas. In this case, a corresponding aggressive sputter etching process can be omitted entirely, thereby achieving further improved performance and reliability.

[0046] Thereafter, further processing may be continued, for example, by depositing a seed layer, which may represent a suitable material, such as copper, copper / aluminum, and the like, which provides the desired process conditions during a subsequent electrochemical deposition process of a metal, such as copper, copper alloys, silver, and the like.

[0047] Fig. 3d schematically illustrates the semiconductor device 300 according to further methods, wherein the opening 308, which may represent a trench, a via, and the like, may have a suitable catalyst material 321a on its sidewalls such that the deposition on the substantially vertical surfaces 308s is promoted, while the corresponding material deposition above the surface 308b is significantly reduced. The corresponding catalyst layer 321a may be formed on the basis of any suitable process technique, as may also be described, for example, with reference to the Fig. 2d to 2f. Thus, in this case, too, a high degree of selectivity can be achieved during the deposition of the material in a self-limited deposition process.

[0048] Thus, the present invention provides a technique for combining the advantages of a self-limiting deposition process—i.e., a highly controllable layer thickness even at very critical device regions, such as the sidewalls of via openings—with the selectivity of a highly non-conformal deposition process. Consequently, by combining these two concepts, coating material can be reliably formed on corresponding device features with high selectivity, without unnecessarily increasing process complexity.The high degree of selectivity of the inherently highly conformal self-limiting deposition process can be achieved based on a corresponding selective surface modification of the corresponding device structure element by providing an inhibitor material to influence the deposition behavior during the subsequent self-limiting process in a corresponding manner. The high selectivity offered by the self-limiting process according to the present invention is advantageously used in some illustrative embodiments to form suitable barrier layers in modern metallization structures, wherein the deposition of the corresponding barrier material at corresponding surface areas, such as the lower surface of a via, is suppressed or at least significantly reduced.

Claims

[1] Procedure with: Forming an opening (208) in a metallization structure of a semiconductor device (200), the opening having a substantially horizontal first surface (208B) and a substantially vertical second surface (208S); Providing an inhibitor material (221) over the first surface (208B) by performing a directional deposition process, wherein the substantially horizontal first surface is a surface oriented substantially perpendicularly with respect to a deposition direction of the directional deposition process; and after providing the inhibitor material, depositing at least a first material layer of a coating material (210) by a self-limiting deposition process (211), wherein the inhibitor material produces a reduced deposition rate on the first surface compared to a deposition rate on the second surface of the opening. [2] The method of claim 1, further comprising depositing a second material layer of the coating material over the first and second surfaces. [3] The method of claim 1, wherein the first material layer has a thickness of about 5 nm or less over the second surface. [4] The method of claim 1, wherein the opening represents a via opening of a metallization structure of the semiconductor device. [5] The method of claim 2, wherein the second material layer is formed by a physical vapor deposition technique. [6] The method of claim 5, wherein the first and / or second material layer comprises tantalum. [7] The method of claim 6, wherein the first material layer comprises tantalum nitride. [8] The method of claim 7, wherein the second material layer comprises tantalum.

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