Heat-treated semiconductor wafer made of single-crystal silicon

Abstract

Uncoated semiconductor wafer made of single-crystalline silicon having a front side and a denuded zone extending from the front side into the interior of the semiconductor wafer, with a nitrogen concentration of not less than 1×10 13 atoms / cm 3 and not more than 8×10 14 atoms / cm 3 and with a nanotopography of the front side of the semiconductor wafer of not more than 4.48 nm, based on a circular measuring window with a diameter of 4 mm, and of not more than 10.01 nm, based on a circular measuring window with a diameter of 20 mm.

Description

[0001] The claimed invention relates to a heat-treated semiconductor wafer made of monocrystalline silicon. Heat treatment is typically carried out in a vertical furnace ("wafer boat"). In such a furnace, a large number of semiconductor wafers are heated simultaneously to high temperatures over an extended period of time. They are stacked one above the other and spaced apart from each other on support rings. Such a support ring ("susceptor ring") is usually made of silicon carbide and serves to support the semiconductor wafer lying on it during heat treatment.

[0002] The goal of heat treatment is to create a denuded zone extending from the surface into the interior of the semiconductor wafer for electronically active structures. This denuded zone is free of defects that could disrupt the function of electronic components. Such defects include, in particular, accumulations of precipitated oxygen, known as bulk micro defects (BMD), and defects formed by clusters of vacancies, also known as crystal-originated particles (COP). Heat treatment dissolves BMD-forming nuclei and COP defects, and reduces the oxygen concentration in the zone below the threshold required for BMD formation.

[0003] The larger the COP defects, the longer it takes to dissolve them through heat treatment of the semiconductor wafer. It is therefore advisable to take measures during the pulling of the single crystal from a crucible that will produce the semiconductor wafers to create COP defects with comparatively small dimensions. Two measures are usually considered for this, which can also be combined. Firstly, rapid cooling of the single crystal prevents vacancies from remaining mobile long enough to aggregate into comparatively large COP defects. Secondly, doping the single crystal with nitrogen causes vacancies to become supersaturated later during the cooling of the single crystal, thus reducing the time available for the vacancy clusters to form.

[0004] At the temperatures prevailing during heat treatment, ranging from 1050 °C to 1300 °C, the crystal lattice of single-crystal silicon is particularly sensitive to disturbances. Temperature gradients, relative movements between the wafer and the support ring due to different thermal expansion coefficients of silicon and silicon carbide, and the weight of the wafer pressing on the support ring can trigger slippage in the crystal lattice or cause scratches.

[0005] Typically, measurements of laser scattered light or measurements of the depolarization of laser light are used to detect stresses and slippages. The measurement method based on the latter is known by the acronym SIRD, which stands for "Scanning Infrared Depolarization." US 2004 / 0 021 097 A1 describes a measurement method using SIRD that can be used to detect defects on semiconductor wafers caused by the support ring.

[0006] DE 10 2005 013 831 A1 discloses that both the temperature during heat treatment and the nitrogen concentration in the semiconductor wafer have a significant influence on the upper yield stress (UYS). The UYS is a parameter for the resistance of the semiconductor material to the formation of slip. Accordingly, the resistance decreases significantly in the temperature range from 1000 °C to 1350 °C, as does a reduction in the nitrogen concentration. To obtain heat-treated semiconductor wafers made of single-crystal silicon that do not exhibit slip in a SIRD measurement, the cited document recommends using the upper yield stress measured at a temperature of 1200 °C as a criterion for carrying out the heat treatment in a specific manner.Accordingly, comparatively high heating rates in the temperature range above 900 °C or comparatively high cooling rates in the temperature range up to 900 °C and the use of a closed ring as a support ring during heat treatment are only suitable for relatively resistant semiconductor wafers.

[0007] JP 2003 - 59 851 A describes a support ring comprising an inner and an outer surface, a horizontal surface for depositing the semiconductor wafer, and a rounded or beveled edge between the inner surface and the horizontal deposit surface. The distance Ry between the highest elevation ("peak") and the deepest recess ("valley") within a measuring section measuring the roughness of the edge is no greater than 5 µm.

[0008] EP 1 772 901 A2 describes a two-part support ring whose surface roughness, expressed as the average roughness depth Rz, should not exceed 15 µm. A silicon semiconductor wafer heated on such a support ring at a temperature of 1200 °C for a period of 600 minutes showed no slip detectable by laser scattering or depolarization of laser light following the heat treatment.

[0009] DE 11 2006 000 816 T5 describes a production process for silicon single crystals for reducing shallow surface defects (SSDs) that form on the surface of a wafer undergoing heat treatment.

[0010] DE 10 2006 053 942 A1 describes a method for regenerating a donor semiconductor wafer with a damaged side surface remaining after a layer produced using ion implantation is separated from the donor semiconductor wafer. The method comprises a first polishing of the donor semiconductor wafer, with which the damaged side surface and a side surface opposite this side surface are simultaneously polished, and a second polishing of the donor semiconductor wafer, with which the damaged and polished side surface is polished alone.

[0011] DE 10 2008 053 610 A1 describes a process that results in a silicon wafer with a polished front and back surface, wherein the silicon wafer has a diameter of 300 mm or larger and has a nanotopology of the front surface - expressed as THA-2 (SEMI Standard M43), of 1 to 10 nm.

[0012] However, the inventors of the present invention have discovered that semiconductor wafers made of single-crystal silicon are subjected to stresses during heat treatment when using known support rings, which can affect the nanotopography of the front side of the semiconductor wafer.

[0013] The object of the present invention is therefore to provide an improved heat-treated semiconductor wafer made of single-crystal silicon.

[0014] The task is solved by an uncoated semiconductor wafer made of single-crystalline silicon with a front side and a denuded zone extending from the front side into the interior of the semiconductor wafer, with a nitrogen concentration of not less than 1×10 13 atoms / cm 3 and not more than 8×10 14 atoms / cm 3and a nanotopography of not more than 4.48 nm, based on a circular measuring window with a diameter of 4 mm, and of not more than 10.01 nm, based on a circular measuring window with a diameter of 20 mm.

[0015] A silicon semiconductor wafer placed on a support ring bends due to its own weight because the support ring lacks support in the center area.

[0016] It is unfavorable to use a support ring with a horizontal surface for depositing a semiconductor wafer, even if the inner edge between the horizontal deposit surface and the inner surface is rounded. The deflection of the semiconductor wafer leads to a stress field, particularly in the area of the inner edge of the support ring, which regularly causes slippage. Heat treatment of the semiconductor wafer simultaneously also partially smooths out the unevenness caused by slippage. Such slippage is therefore often undetectable. However, it does lead to a deterioration of the nanotopography of the semiconductor wafer and possibly to defocusing problems when exposing the front side of the semiconductor wafer during the manufacture of electronic components. Nanotopography describes flatness deviations in a measurement range with a spatial wavelength of 0.2 to 20 mm.A suitable measurement technique for determining nanotopography is optical interferometry. Measurement devices based on this technique are commercially available. The nanotopography of the front side of the semiconductor wafer is measured to characterize its flatness and to estimate the effect of heat treatment on flatness. The front side of the semiconductor wafer is the side intended for the integration of electronic structures.

[0017] Fig. Figure 1 shows a sectional view of a prior art support ring. This support ring is characterized by a horizontal surface 1 for depositing a semiconductor wafer.

[0018] Fig. 2 shows a support ring which is a closed ring and is characterized by a concavely curved surface 4 for depositing the semiconductor wafer. The concavely curved deposit surface 4 extends from the outer surface 2 to the inner surface 3 and therefore has no horizontal portion. It has a cross-section which slopes concavely from the outer to the inner surface. The radius of curvature of the deposit surface 4 is not less than 6000 mm and not more than 9000 mm if the deposit surface is designed for depositing a semiconductor wafer with a diameter of 300 mm, or not less than 9000 mm and not more than 14000 mm if the deposit surface is designed for depositing a semiconductor wafer with a diameter of 450 mm, and preferably corresponds to the radius of the deflection of the semiconductor wafer.As a result, the stress field acting on the semiconductor wafer during heat treatment in the area of the inner edge between the support surface and the inner surface of the support ring is significantly lower than when using a support ring with a fully or partially horizontal support surface. Using a support ring designed in this way results in a lower density of stress-induced defects, which is also reflected in an improved nanotopography of the front side of the heat-treated semiconductor wafer.

[0019] The outer diameter of the support ring is preferably equal to the diameter of the semiconductor wafer deposited on the curved surface for heat treatment or no more than 2 mm larger. The inner diameter of the support ring is preferably no less than 60 mm and no more than 100 mm smaller than the outer diameter.

[0020] The support ring is preferably made of silicon carbide or is coated with silicon carbide.

[0021] It is also advantageous if the curved surface for depositing the semiconductor wafer meets certain roughness and flatness criteria.

[0022] The average roughness depth Rz should preferably be no less than 3 µm and no more than 5 µm, and the largest individual roughness depth Rmax should preferably not exceed 5 µm. The average roughness depth Rz corresponds to the arithmetic mean of the individual roughness depths (the difference between the highest elevation and the deepest notch based on an individual measuring section). The individual roughness depths are determined using a profile that maps the roughness over a total measuring section divided into five individual measuring sections. A roughness characterized by an average roughness depth Rz of less than 3 µm is less favorable because it promotes slippage of the semiconductor wafer on the support ring. A roughness characterized by an average roughness depth Rz of more than 5 µm carries the risk that local material peaks will impair the nanotopography of the heat-treated semiconductor wafers.

[0023] In addition, the material fraction Rmr(t) of the curved deposition surface at a cutting depth t of 2 µm should not be less than 85%. This parameter is defined in DIN EN ISO 4287 1997 and describes the percentage share (bearing share) of the material-containing sections of the total measuring section at the specified cutting depth. The latter is calculated from the highest elevation of the profile. An Rmr(2 µm) of less than 85%, and in particular less than 50%, is not favorable because the low material fraction is an indicator of the presence of local material peaks and has a correspondingly adverse effect on the nanotopography of the heat-treated semiconductor wafers. At an Rmr(2 µm) of at least 85%, material elevations are wider and more rounded than tapered.

[0024] Finally, the support ring should be shaped as ideally as possible. To ensure that the nanotopography of the front side of heat-treated semiconductor wafers reliably remains within the desired range, the deposition surface should preferably deviate by no more than 30 µm from a geometrically ideally shaped surface whose radius of curvature lies within the specified range. The surface shape according to DIN ISO 1101 2004 should therefore preferably be no more than 0.03 mm. Accordingly, the deposition surface must be located between two enveloping surfaces, the distance between which is determined by spheres with a diameter of 30 µm, with the center of the spheres located on the geometrically ideal surface.

[0025] If the above criteria are met, heat-treated semiconductor wafers made of single-crystal silicon exhibit the comparatively best nanotopography of the front side.

[0026] A method for heat treating a semiconductor wafer made of single-crystal silicon comprises placing the semiconductor wafer on a support ring having an outer and an inner circumferential surface and a curved surface extending from the outer to the inner circumferential surface for depositing the semiconductor wafer, and heating the semiconductor wafer deposited on the support ring to a temperature of not less than 1050 °C and not more than 1300 °C for a period of not less than 30 minutes and not more than 180 minutes.

[0027] If the lower temperature limit is not reached or the heat treatment period is shorter than 30 minutes, no denuded zone will be formed, or one will not extend deep enough into the interior of the semiconductor wafer. If the upper temperature limit is exceeded or the heat treatment period is longer than 180 minutes, the process becomes uneconomical.

[0028] The process is also characterized by the fact that criteria such as the upper yield strength of the semiconductor wafer material or the heating rate in the temperature range above 900 °C or the cooling rate in the temperature range up to 900 °C do not need to be considered. This allows semiconductor wafers to be heat-treated with a comparatively low nitrogen concentration without the formation of slip.

[0029] It is nevertheless preferable to set the heating rate in the temperature range above 900 °C and the cooling rate in the temperature range up to 900 °C to values in the range of 1 °C / min to 10 °C / min.

[0030] The heat treatment is preferably carried out in an atmosphere that does not chemically react with silicon under the prevailing conditions or in a reducing atmosphere.

[0031] Examples include heat treatment in argon or in a mixture of argon and hydrogen.

[0032] The invention relates to an uncoated semiconductor wafer made of single-crystalline silicon having a front side and a denuded zone extending from the front side into the interior of the semiconductor wafer, with a nitrogen concentration of not less than 1×10 13 atoms / cm 3 and not more than 8×10 14 atoms / cm 3 and a nanotopography of not more than 4.48 nm, based on a circular measuring window with a diameter of 4 mm and not more than 10.01 nm, based on a circular measuring window with a diameter of 20 mm.

[0033] The nanotopography is measured according to the SEMI standard M78-1000 of October 2010.

[0034] If the nitrogen concentration is lower than the lower limit, the stabilization of the semiconductor wafer due to the presence of nitrogen is too weak. If the nitrogen concentration exceeds the upper limit, unwanted nitrogen-induced defects occur more frequently.

[0035] A suitable method for producing the semiconductor wafer is the method described above for heat-treating a semiconductor wafer made of single-crystal silicon.

[0036] The “denuded zone” is a zone extending from the front side of the semiconductor wafer to a length of preferably not less than 8 µm into the interior of the semiconductor wafer, in which no COP defects and BMD can be detected.

[0037] The semiconductor wafer preferably has an oxygen concentration of not less than 4×10 17 atoms / cm 3 and not more than 7.5×10 17atoms / cm 3 (new ASTM) and a specific resistance of 1 ohm-cm to 80 ohm-cm. The BMD density outside the denuded zone is preferably 5×10 8 up to 2×10 10 cm -3 .

[0038] The diameter of the semiconductor wafer is preferably 300 mm or 450 mm.

[0039] The single crystal that produces the semiconductor wafer is pulled from a melt contained in a crucible using the Czochralski method at a pulling rate that produces an excess of vacancies relative to silicon interstitial atoms. The single crystal is cooled in the temperature range of 1150 °C to 1000 °C, preferably at a high cooling rate, to limit the size of any COP defects that form. Example:

[0040] Single-crystal silicon semiconductor wafers with a diameter of 300 mm were subjected to heat treatment in an ASM A412 vertical furnace. During the heat treatment, the wafers were heated to a temperature of 1200°C for a period of 120 minutes.

[0041] The semiconductor wafers were cut from single crystals that had been pulled from a nitrogen-doped silicon melt contained in a crucible using the Czochralski method at an average pulling speed of 0.86 mm / min in the wafer-producing section of the single crystals. The cooling rate in the temperature range from 1150 to 1000 °C was 2.5 K / min in the center and 3.2 K / min at the edge of each single crystal.

[0042] During the heat treatment, the semiconductor wafers were placed on silicon carbide support rings, which were arranged as in Fig. 2. The outer diameter of the support rings was 1 mm larger than the diameter of the semiconductor wafers.

[0043] The roughness profile of the support surface was measured using a profiler.

[0044] The average roughness depth Rz of the support rings used ranged from 3 µm to 5 µm, and the largest measured individual roughness depth Rmax was no more than 5 µm. Furthermore, the material fraction Rmr(t) of the curved support surface at a cutting depth t of 2 µm was never below 85% for any of the support rings.

[0045] After a period of 1000 process runs, not a single failure was observed due to exceeding the upper limit of the allowable nanotopography of the front side of the semiconductor wafer.

[0046] The nanotopography measurement was carried out according to the SEMI standard M78-1000 of October 2010, with a fixed quality area (FQA) of 297 mm, the key options NT-CC, the threshold area x = 0.25 % and the cut-off wavelength λ c = 20 mm. The evaluation was carried out according to the "Deviation Metric."

[0047] Under otherwise similar conditions, semiconductor wafers were also heat-treated, which were placed on a support ring, which was arranged as shown in Fig. 1 was formed. A significant number of failures were observed in these semiconductor wafers after both SIRD and nanotopography measurements.

[0048] Fig. 3 and Fig. 4 show typical SIRD images of a failed semiconductor wafer and a semiconductor wafer according to the invention. The images were taken using a SIRD A300P measuring device from PVA TePla. Fig. 3, local SIRD stresses are marked as the cause of the wafer failure. The position of the markings indicates that the stresses were caused by the interaction between the wafer and the inner edge of the support ring.

[0049] Fig. 5 and Fig. Figure 6 shows typical nanotopography measurements of the front side of a failed semiconductor wafer and a semiconductor wafer according to the invention. The images were taken using a WaferSight2 measuring device from KLA Tencor. Fig. In Figure 5, an excess of the local nanotopography is highlighted as the reason for the semiconductor wafer failure. Its location near the inner edge of the support ring used indicates that the shape of the support ring is responsible for the excess.

[0050] The Fig. The semiconductor wafer shown in Figure 5 had a nanotopography of 8.68 nm, based on a measurement window with a diameter of 4 mm, and of 55.56 nm, based on a measurement window with a diameter of 20 mm. Fig. For the semiconductor wafer according to the invention shown in Figure 6, the corresponding measured values were 4.48 nm and 10.01 nm, respectively.

Claims

[1] Uncoated semiconductor wafer made of single-crystalline silicon having a front side and a denuded zone extending from the front side into the interior of the semiconductor wafer, with a nitrogen concentration of not less than 1×10 13 atoms / cm 3 and not more than 8×10 14 atoms / cm 3 and with a nanotopography of the front side of the semiconductor wafer of not more than 4.48 nm, based on a circular measuring window with a diameter of 4 mm, and of not more than 10.01 nm, based on a circular measuring window with a diameter of 20 mm.

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