Semiconductor device

Abstract

A method for manufacturing a semiconductor device comprising the steps: Forms of a recessed section (26) on a circumferential section of a semiconductor substrate (20), wherein a surface of the recessed section (26) is deeper than a main surface of the semiconductor substrate (20), and After forming the recessed section (26), forming a channel stopper (28) along an inner wall of the recessed section (26) by diffusing disturbances.

Description

[0001] The invention relates to the field of semiconductor devices and in particular a semiconductor device, e.g. for switching a high current, etc.

[0002] JP 2005-183 891 A discloses a semiconductor device in which guard rings and a channel stopper are formed in the semiconductor substrate. The guard rings and the channel stopper are used to increase the breakdown voltage of the semiconductor device. Documents US 2002 / 0100935 A1, DE 10 2006 011 567 A1, and US 2002 / 0179974 A1 also describe a similar arrangement of a semiconductor device with guard rings and a channel stopper.

[0003] However, the magnitude and stability of the breakdown voltage cannot be significantly increased in the disclosed configuration of the semiconductor device.

[0004] The invention is intended to solve the problems mentioned above. The invention therefore aims to create a semiconductor device with an increased magnitude and stability of a breakdown voltage.

[0005] This problem is solved according to the invention by the features of the independent claims. The dependent claims contain preferred embodiments of the invention.

[0006] Further features and advantages of the invention will become apparent from the description of embodiments of the invention with reference to the figures. The figures show: Fig. 1 a top view of a semiconductor device in accordance with a first embodiment of the invention; Fig. 2 a cross-sectional view along the dashed line 2-2 from Fig. 1; Fig. 3 a cross-sectional view of a partially completed semiconductor device before the anode and guard rings have been formed in it; Fig. 4 a cross-sectional view of the in Fig. 3 partially completed semiconductor device shown, after the anode and the guard rings have been formed; Fig. 5 a cross-sectional view of the partially completed semiconductor device before the recessed section has been formed in it; Fig. 6 a cross-sectional view of the in Fig. 5 partially completed semiconductor device shown, after the recessed section has been formed in it; Fig. 7 a cross-sectional view of the in Fig. 6 partially completed semiconductor device shown, after the channel stopper has been formed; Fig. 8 a cross-sectional view of a semiconductor device in accordance with a second embodiment of the invention; Fig. 9 a cross-sectional view of a partially completed semiconductor device after trenches have been formed in it; Fig. 10 a cross-sectional view of the in Fig. 9 partially completed semiconductor device shown, after the anode, the guard rings and the trench-internal guard rings have been formed in it; Fig. 11 a cross-sectional view of the in Fig. 10 partially completed semiconductor device shown, after the channel stopper has been formed; Fig. 12 a cross-sectional view of a semiconductor device in accordance with a third embodiment of the invention; Fig. 13 a cross-sectional view of a partially completed semiconductor device after an anode and trench-internal guard rings have been formed; Fig. 14 a cross-sectional view of the in Fig. 13 partially completed semiconductor device shown, after the trench has been filled with the insulating layer and covered; Fig. 15 a cross-sectional view of the in Fig. 14 partially completed semiconductor device shown, after the trenches have been filled with the conductive layers and covered; Fig. 16 a cross-sectional view of the in Fig. 15 partially completed semiconductor device shown, after the channel stopper has been formed; and Fig. 17 a cross-sectional view of the in Fig. 16 partially completed semiconductor device shown, after an insulating layer has been formed on it. First embodiment Fig. Figure 1 is a top view of a semiconductor device 10 in accordance with a first embodiment of the invention. In the central section of the semiconductor device 10 of the first embodiment, a conductive layer 12 is formed. Furthermore, an insulating layer 14 is formed, which surrounds the conductive layer 12. Fig. 2 is a cross-sectional view along the dashed line 2-2 from Fig. 1. The semiconductor device 10 contains an N-type semiconductor substrate 20 (hereinafter referred to as the first conductivity type). An anode 22 of the P-type (hereinafter referred to as the second conductivity type) is formed in the semiconductor substrate 20. This anode 22 acts as the anode of a diode. Guard rings 24 are formed outside the anode 22. The guard rings 24 are formed in the main surface of the semiconductor substrate 20 and surround the diode. The guard rings 24 are formed from a diffused layer of the second conductivity type.

[0007] A recessed section 26 is formed in the semiconductor substrate 20, surrounding the guard rings 24. The surface of the recessed section 26 is deeper than the main surface of the semiconductor substrate 20. A channel stopper 28 is formed along the inner walls of the recessed section 26. The channel stopper 28 is formed from a diffused layer of the first conductivity type.

[0008] The semiconductor device 10 comprises a device region 40 in which the diode is formed, a guard ring region 42 in which the guard rings 24 are formed, and a channel stopper region 44 in which the channel stopper 28 is formed. An insulating layer 30 is formed such that it extends continuously over the stopper 28 and through the guard ring region 42 and a section of the semiconductor region 40. The conductive layer 12 is formed on the diode 22. Furthermore, a section of the conductive layer 12 lies on a section of the insulating layer 30. The insulating layer 14 is formed on the insulating layer 30. Furthermore, a section of the insulating layer 14 lies on a section of the insulating layer 12. It is noted that the dashed line in Fig. 2 indicates how the depletion layer runs within the semiconductor substrate 20.

[0009] The following description is directed to a method for manufacturing a semiconductor device in accordance with the first embodiment. First, a pattern is formed to create an anode and guard rings. Fig. Figure 3 is a cross-sectional view of a partially completed semiconductor device before the anode and guard rings are formed (i.e., after the pattern has been formed on it). As shown, an insulating layer 50 is more precisely formed such that it has openings where the anode and guard rings are to be formed.

[0010] The anode and the protective rings are then formed. Fig. 4 is a cross-sectional view of the in Fig. Figure 3 shows a partially completed semiconductor device after the anode and guard rings have been formed. Specifically, in this step, defects of the second conductivity type are first implanted into the semiconductor substrate 20 using an ion implantation technique with the insulating layer 50 acting as a mask. The defects are then thermally diffused to form the anode 22 and the guard rings 24. The insulating layer 50 is then removed before proceeding to the next step.

[0011] A more in-depth section will be developed below. Fig. Figure 5 is a cross-sectional view of the partially completed semiconductor device before the recessed section is formed within it (i.e., a cross-sectional view of the [partially completed] semiconductor device). Fig. Figure 4 shows a partially completed semiconductor device after the insulating layer 50 has been removed and an insulating layer 52 has been formed on it. More precisely, in this step, the insulating layer 52 is first formed on the semiconductor substrate 20 to create the recessed section. The insulating layer 52 is a patterned insulating layer with an opening through which the circumferential section of the semiconductor substrate 20 is exposed.

[0012] Subsequently, the circumferential section of the semiconductor substrate 20 is etched using the insulating layer 52 as a mask, thereby forming the recessed section 26. Fig. 6 is a cross-sectional view of the in Fig. 5 partially completed semiconductor device shown, after the recessed section has been formed in it.

[0013] A channel stopper will be trained in the following. Fig. 7 is a cross-sectional view of the in Fig. Figure 6 shows a partially completed semiconductor device after the channel stopper has been formed. Specifically, in this step, defects of the first conductivity type are first implanted into the recessed section 26 using an ion implantation technique with the insulating layer 52 acting as a mask. As a result of this defect implantation, the defect density of the recessed section 26 becomes higher than that of the semiconductor substrate 20. The implanted defects are then thermally diffused to form the channel stopper 28, which runs along the inner walls of the recessed section 26. The insulating layer 52 is then removed before proceeding to the next step. In the next step, the insulating layer 30, the conductive layer 12, and the insulating layer 14 are formed in the aforementioned order, thus completing the fabrication of the device shown in Figure 6. Fig. The semiconductor device shown in 1 is complete.

[0014] It is noted that applying a reverse voltage to the diode leads to the formation of a depletion layer in the semiconductor substrate, causing the electric field to concentrate in this layer. This can lead to a loss of quality in the semiconductor device. To prevent this loss of quality, the magnitude and stability of the semiconductor device's breakdown voltage must be increased. (It is noted that breakdown voltage stability refers to its resistance to change, such as over time.) To increase the magnitude and stability of the breakdown voltage, the defects forming the guard rings or channel stopper must be allowed to diffuse to a considerable depth in the thickness direction of the substrate into the semiconductor substrate.However, in the case of conventional semiconductor devices, the diffusion of defects deep into the substrate along its thickness requires that the diffusion process be carried out for an extended period at elevated temperatures, leading to reduced productivity. Furthermore, prolonged defect diffusion also results in the defects diffusing extensively laterally, making it more difficult to reduce the size of the semiconductor device.

[0015] In contrast, in the semiconductor device 10 of the first embodiment, the recessed section 16 is formed, the surface of which is deeper than the main surface of the semiconductor substrate 20, and the channel stopper 28 is formed therein along the inner walls of the recessed section 26. As a result of this configuration, the channel stopper 28 can extend deep into the semiconductor substrate 20, thereby increasing the magnitude and stability of the breakdown voltage of the semiconductor device. Since the defects do not need to be allowed to diffuse for extended periods, their lateral diffusion is also minimized, so that the size of the semiconductor device can be reduced. In particular, the sizes of the guard ring region 42 and the channel stopper region 44, which were described above based on Fig. The amounts described in section 2 will be reduced.

[0016] To achieve the advantages described above in connection with the present embodiment, the surface of the recessed section 26 only needs to be deeper than the main surface of the semiconductor substrate 20. Thus, the recessed section 26 does not necessarily need to have the shape described above, but can, for example, be a groove.

[0017] Although a diode is formed in the device area 40 of the semiconductor device 10 in the first embodiment, it should be noted that a semiconductor element such as an IGBT or a power MOSFET can be formed in the device area 40. Furthermore, in the semiconductor device 10 of the first embodiment, the conductivity type (if any) of each component can be reversed. That is to say, in this case, in the above description, the term "first conductivity type" refers to the P-type and the term "second conductivity type" refers to the N-type.

[0018] To prevent damage to the semiconductor substrate during ion implantation, a thin insulating layer can be formed on the surface of the semiconductor substrate prior to ion implantation. Furthermore, the diffused layers can be formed using a technique other than ion implantation.

[0019] Typically, the semiconductor substrate 20 is made of silicon. However, the semiconductor substrate 20 can be made of a wide-bandgap semiconductor whose bandgap is wider than that of silicon. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, and diamond. Second embodiment

[0020] Fig. Figure 8 is a cross-sectional view of a semiconductor device in accordance with a second embodiment of the invention. Fig. 8 corresponds to the one described above Fig. 2. The following description of the semiconductor device of the second embodiment is mainly limited to differences from the semiconductor device 10 described above.

[0021] The semiconductor device of the second embodiment includes trenches 60. The trenches 60 are formed in the main surface of the semiconductor substrate 20 and surround the semiconductor element (i.e., the diode). The trenches 60 are filled with the insulating layer 30. Furthermore, an internal guard ring 62 is formed along the inner walls of each trench 60. These internal guard rings 62 are formed from a diffused layer of the second conductivity type. The internal guard rings 62 extend from the main surface of the semiconductor substrate 20 to a greater depth than the anode 22. The other components are the same as those described in connection with the semiconductor device of the first embodiment.

[0022] The following description is directed to a method for manufacturing a semiconductor device in accordance with the second embodiment. Fig. Figure 9 is a cross-sectional view of a partially completed semiconductor device after trenches have been formed in it. Specifically, in this trench formation step, a patterned insulating layer 70 is first formed such that it has openings through which the semiconductor substrate 20 is exposed. The exposed sections of the semiconductor substrate 20 at these openings are then etched to form the trenches 60. The insulating layer 70 is then removed before proceeding to the next step.

[0023] Subsequently, an anode, protective rings and trench-internal protective rings are formed. Fig. 10 is a cross-sectional view of the in Fig. Figure 9 shows a partially completed semiconductor device after the anode, guard rings, and trench-internal guard rings have been formed. Specifically, in this step, defects of the second conductivity type are first implanted into the semiconductor substrate 20 using an ion implantation technique with a patterned insulating layer 72 as a mask. The defects are then thermally diffused to form the anode 22, the guard rings 24, and the trench-internal guard rings 62. The trench-internal guard rings 62 are formed along the inner walls of the trenches 60. The insulating layer 72 is then removed before proceeding to the next step.

[0024] A channel stopper will be trained in the following. Fig. 11 is a cross-sectional view of the in Fig. Figure 10 shows a partially completed semiconductor device after the channel stopper has been formed. Specifically, in this step, a patterned insulating layer 74 with an opening is first formed. Then, the section of the semiconductor substrate 20 exposed at the opening of the insulating layer 74 is etched to form the recessed section 26. Subsequently, the channel stopper 28 is formed along the inner walls of the recessed section 26 in the manner described in connection with the first embodiment. The insulating layer 74 is then removed before proceeding to the next step.

[0025] In the next step, the insulating layer 30 is formed to fill the trenches. Furthermore, the conductive layer 12 and subsequently the insulating layer 14 are formed, thus completing the construction of the Fig. The semiconductor device shown in section 8 is complete.

[0026] Since the trench-internal guard rings 62 in the semiconductor device 10 of the second embodiment extend from the main surface of the semiconductor substrate 20 to a greater depth than the anode 22, the depletion layer formed in the semiconductor substrate 20 has a considerable depth. As a result, compared to the semiconductor device described above in connection with the first embodiment, the magnitude and stability of the breakdown voltage of the semiconductor device 10 of the second embodiment can be increased, while the size of the guard ring region is reduced.

[0027] Furthermore, in the semiconductor device 10 of the second embodiment, two types of guard rings with different depths (i.e., the guard rings 24 and the trench-internal guard rings 62) are formed. Thus, the extent or distribution of the depletion layer when a blocking voltage is applied to the anode 22 can be modified or optimized by adjusting the depth of the trenches 60 and the positions of the trench-internal guard rings 62 and the guard rings 64. As a result, the magnitude and stability of the breakdown voltage of the semiconductor device can be increased compared to the semiconductor device of the first embodiment.

[0028] Although the semiconductor device of the second embodiment includes both the guard rings 24 and the trench-internal guard rings 62, the guard rings 24 can, of course, be omitted in other embodiments. Furthermore, the semiconductor device of the second embodiment allows at least the same modifications as the semiconductor device of the first embodiment. Third embodiment

[0029] Fig. Figure 12 is a cross-sectional view of a semiconductor device in accordance with a third embodiment of the invention. Fig. 12 corresponds to the one described above Fig. 8. The following description of the semiconductor device of the third embodiment is mainly limited to the differences from the semiconductor device of the second embodiment.

[0030] The semiconductor device of the third embodiment includes trenches 80. The trenches 80 are formed in the main surface of the semiconductor substrate 20 and surround the semiconductor element (i.e., the diode). Each trench 80 is filled with a conductive layer 82a of the second conductivity type. An internal guard ring 84 is formed along the inner walls of each trench 80. These internal guard rings 84 are formed from a diffused layer of the second conductivity type. A conductive potential stabilization layer 92, connected to the conductive layers 82a, is arranged above them. Thus, the conductive potential stabilization layer 92, connected to the conductive layers 82a, extends upwards from the semiconductor substrate 20 and serves to equalize the potentials of the internal guard rings 84.

[0031] Furthermore, the semiconductor device includes a trench 60 filled and covered with an insulating layer 86. Thus, the semiconductor device of the third embodiment includes the trenches 80 filled with the conductive layer 82a and the trench 60 filled with the insulating layer 86. A non-grounded field plate 82b of the second conductivity type is formed on the insulating layer 86. The non-grounded field plate 82b is formed above the main surface of the semiconductor substrate 20 and surrounds the semiconductor element (i.e., the diode). It is noted that the channel stopper 28 is formed in the main surface of the semiconductor substrate 20.

[0032] The following description is directed to a method for manufacturing a semiconductor device in accordance with the third embodiment. Fig. Figure 13 is a cross-sectional view of a partially completed semiconductor device after the formation of an anode and trench-internal guard rings. Specifically, in this step, a patterned insulating layer 100 with openings is first formed, followed by the formation of the trench 60 and the trenches 80. Subsequently, using an ion implantation technique and the insulating layer 100 as a mask, defects of the second conductivity type are implanted into the semiconductor substrate 20. The defects are then thermally diffused to form the anode 22, the trench-internal guard rings 84, and a trench-internal guard ring 62. The insulating layer 100 is then removed before proceeding to the next step.

[0033] The trench 60 is then filled with an insulating layer and covered. Fig. 14 is a cross-sectional view of the in Fig. Figure 13 shows a partially completed semiconductor device after the trench 60 has been filled and covered with the insulating layer. More precisely, in this step, the trench 60 is filled and covered with an insulating layer 102. The insulating layer 102 partially covers the main surface of the semiconductor substrate 20; more precisely, it fills and covers the trench 60, but it has openings through which the trenches 80 are exposed.

[0034] The trenches are then filled with conductive layers and covered. Fig. 15 is a cross-sectional view of the in Fig. Figure 14 shows a partially completed semiconductor device after the trenches 80 have been filled and covered with the conductive layers. Specifically, in this step, each trench 80 is filled and covered with a conductive layer 82a of the second conductivity type. These conductive layers 82a are formed such that they extend down to the insulating layer 102. Simultaneously with the insulating layers 82a, the ungrounded field plate 82b is formed on the insulating layer 102. The conductive layers 82a and the ungrounded field plate 82b are formed concurrently during the same process.

[0035] A channel stopper will be trained in the following. Fig. 16 is a cross-sectional view of the in Fig. Figure 15 shows a partially completed semiconductor device after the channel stopper has been formed. Specifically, in this step, the circumferential section of the insulating layer 102 above is first etched away to form an insulating layer 104 with an opening. Subsequently, defects of the first conductivity type are implanted into the surface of the semiconductor substrate 20, which is exposed at the opening of the insulating layer 104, by means of ion implantation, and these defects are then allowed to diffuse thermally, thereby forming the channel stopper 28.

[0036] A further insulating layer is then formed. Fig. 17 is a cross-sectional view of the in Fig. Figure 16 shows a partially completed semiconductor device after this insulating layer has been formed on it. More precisely, in this step, a portion of the insulating layer 104 on the anode 22 is first etched away to form the insulating layer 86. Subsequently, an insulating layer 90 is formed such that it covers the ungrounded field plate 82b and has openings through which sections of the conductive layers 82a are exposed.

[0037] The conductive potential stabilization layer 92 is then formed in such a way that it is connected to the sections of the conductive layers 82a that are exposed at the openings of the insulating layer 90. Subsequently, the conductive layer 12 and the insulating layer 14 are formed in this sequence, thus completing the production of the Fig. The semiconductor device shown in section 12 is complete.

[0038] The design of the third embodiment of the semiconductor device described above allows for an increase in the magnitude and stability of the breakdown voltage of the device compared to prior art designs. Furthermore, since the trenches 80 are filled and covered with the conductive layers 82a, the mechanical stresses to which the semiconductor substrate 20 is subjected can be reduced, leading to improved leakage characteristics of the semiconductor device. Additionally, the design of the semiconductor device offers the advantage that the potentials of the trench-internal protective rings can be equalized, as the conductive equipotential bonding layer 92 is arranged above the semiconductor substrate 20 and connected to the conductive layers 82a. Finally, the ungrounded field plate 82b serves to increase the breakdown voltage stability of the semiconductor device.

[0039] The semiconductor device of the third embodiment allows at least similar modifications to the semiconductor device of the first embodiment.

[0040] In accordance with the invention, a channel stopper or protective rings can be formed deep within the substrate of a semiconductor device, thereby increasing the magnitude and stability of the breakdown voltage of the semiconductor device.

Claims

[1] A method of manufacturing a semiconductor device comprising the steps of: forming a recessed portion (26) on a peripheral portion of a semiconductor substrate (20), wherein a surface of the recessed portion (26) is deeper than a main surface of the semiconductor substrate (20), and After forming the recessed portion (26), forming a channel stopper (28) along an inner wall of the recessed portion (26) by diffusing impurities. [2] Method according to claim 1, characterized by Forming a trench (60) in the main surface of the semiconductor substrate (20), and forming an intra-trench guard ring (26) along an inner wall of the trench (60) by diffusing impurities. [3] Method according to claim 1 or 2, characterized by that the semiconductor substrate (20) is formed from a semiconductor with a wide band gap. [4] Method according to claim 3, characterized bythat the wide band gap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.

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