Semiconductor arrangement

Abstract

Semiconductor arrangement comprising: a circuit carrier (5) comprising a first metallization layer (41), a second metallization layer (82), an inner metallization layer (81) arranged between the first metallization layer (41) and the second metallization layer (82), a first insulating layer (83) arranged between the inner metallization layer (81) and the second metallization layer (82), and a second insulating layer (43) arranged between the first metallization layer (41) and the inner metallization layer (81); a bond wire (6); at least N half-bridge circuits (I, II, III), where N ≥ 1, and where each of the half-bridge circuits (I, II, III) comprises the following: - a first circuit node (31), a second circuit node (32) and a third circuit node (33); - a controllable first semiconductor switch (1) having a first main contact (11) which is electrically connected to the first circuit node (31), a second main contact (12) which is electrically connected to the third circuit node (33); and a gate contact (13) for controlling an electric current between the first main contact (11) and the second main contact (12); - a controllable second semiconductor switch (2) having a first main contact (21) which is electrically connected to the second circuit node (32), a second main contact (22) which is electrically connected to the third circuit node (33), and a gate contact (23) for controlling an electric current between the first main contact (21) and the second main contact (22); wherein the first semiconductor switch (1) and the second semiconductor switch (2) of each of the half-bridge circuits (I, II, III) is arranged on the side of the first metallization layer (41) facing away from the second insulating layer (43); and the bond wire (6) is bonded directly to the inner metallization layer (81) at a first bonding point (61), so that a material of the bond wire (6) at the first bonding point (61) is in physical contact with a material of the inner metallization layer (81).

Description

TECHNICAL AREA

[0001] The invention relates to semiconductor arrangements. BACKGROUND

[0002] Publication JP 2003-086747A discloses an insulated printed circuit board which has a structure in which one or more layers of a heat diffusion plate, in which a ceramic plate is arranged, are arranged between a printed circuit board and a radiation plate, wherein the heat diffusion plate is made into a current flow path of the semiconductor power element and, if required, a water channel for cooling is formed in the heat diffusion plate.

[0003] German patent application DE 10 2008 036 112 A1 discloses a power semiconductor module with a multilayer substrate comprising several metal layers and several ceramic layers, wherein a ceramic layer is arranged between two metal layers; one or more semiconductor chips arranged on the multilayer substrate; an electrical circuit comprising at least one power semiconductor chip; a housing cover comprising a side wall, wherein the side wall has a lower surface facing the multilayer substrate;and an elastic filler, wherein the multilayer substrate forms a base plate of the power semiconductor module, so that the power semiconductor module with the multilayer substrate can be pressed directly against a heat sink, the multiple metal layers comprising at least a first metal layer, a second metal layer and a third metal layer, the multiple ceramic layers comprising at least a first ceramic layer and a second ceramic layer, and the elastic filler being arranged at least partially between the lower surface of the side wall and the upper surface of the second ceramic layer.

[0004] In many semiconductor arrangements, two semiconductor switches are connected in series to form a semiconductor bridge. One, two, three, or more such half-bridges can be used, for example, to power motors, rectifiers, inverters, etc.

[0005] In a half-bridge, at least two controllable power semiconductor switches are connected in series. Between each controllable power semiconductor switch, the series connection has a switching node. During operation, the series connection is connected to a supply voltage between a positive and a negative supply potential. The power semiconductor switch connected to the negative supply potential is often called the "low-side switch." Conversely, the power semiconductor switch connected to the positive supply potential is often called the "high-side switch." During operation, the voltage at the switching node alternates between two potentials that are essentially identical to the positive and negative supply potentials, respectively.

[0006] In many conventional semiconductor arrays, metallized ceramic substrates are used to establish at least some of the array's electrical connections. The power semiconductor switches are located on the top side of the substrates. The underside can be thermally and / or electrically coupled to a heat sink. Together with the insulating ceramic, the metallizations of the ceramic substrate form a capacitance with respect to the ground potential applied to the heat sink. Depending on the amplitude and frequency of the alternating voltage at the circuit node, displacement currents occur that continuously charge and discharge this capacitance. Due to displacement currents in unavoidable inductances within the array, voltage drops across such inductances can lead to unwanted electromagnetic interference (EMI).

[0007] To reduce inductance, ceramic substrates can be designed as multilayer substrates with vias that connect different metal layers of the substrate. These vias enable the creation of short electrical connections with reduced impedance. However, ceramic multilayer substrates with vias are very expensive.

[0008] Therefore, there is a need for a semiconductor arrangement that exhibits low inductance even when no ceramic substrate with vias is used. OVERVIEW

[0009] According to one aspect, a semiconductor arrangement comprises a circuit carrier, a bond wire, and at least N half-bridge circuits. N is an integer with a value of at least 1. The circuit carrier comprises a first metallization layer, a second metallization layer, an inner metallization layer arranged between the first and second metallization layers, a first insulating layer arranged between the inner and second metallization layers, and a second insulating layer arranged between the first and inner metallization layers. Each of the half-bridge circuits comprises a first circuit node, a second circuit node, a third circuit node, a controllable first semiconductor switch, and a controllable second semiconductor switch.The controllable first semiconductor switch has a first main contact electrically connected to the first circuit node, a second main contact electrically connected to the third circuit node, and a gate contact for controlling an electrical current between the first and second main contacts. Similarly, the second semiconductor switch has a first main contact electrically connected to the second circuit node, a second main contact electrically connected to the third circuit node, and a gate contact for controlling an electrical current between the first and second main contacts. The first and second semiconductor switches of each of the half-bridge circuits are located on the side of the first metallization layer facing away from the second insulating layer.The bond wire is bonded directly to the inner metallization layer at a first bonding point. BRIEF DESCRIPTION OF THE FIGURES

[0010] The invention is explained in more detail below with reference to the accompanying figures. The components shown in the figures are not necessarily to scale; rather, emphasis has been placed on illustrating the principles of the invention. Furthermore, identical reference numerals in the figures denote identical or corresponding elements. Fig. 1A is a circuit diagram of a half-bridge formed from a series connection of two MOSFETs. Fig. 1B is a circuit diagram of a half-bridge formed from a series connection of two IGBTs. Fig. Figure 2 is a circuit diagram of a 2-phase bridge, consisting of two in Fig. The half-bridges shown in 1A are formed. Fig. Figure 3 is a circuit diagram of a 3-phase bridge, consisting of three in Fig. The half-bridges shown in 1A are formed. Fig. Figure 4 shows a vertical sectional view through a semiconductor arrangement, which shows a number of half-bridges according to a first embodiment. Fig. Figure 5 shows a vertical sectional view through a semiconductor arrangement, which shows a number of half-bridges according to a second embodiment. Fig. Figure 6 shows a vertical sectional view through a semiconductor arrangement, which shows a number of half-bridges according to a third embodiment. Fig. Figure 7 shows a vertical sectional view through a semiconductor arrangement, which shows a number of half-bridges according to a fourth embodiment. DETAILED DESCRIPTION

[0011] Fig. Figure 1A shows a circuit diagram of a half-bridge I with a controllable first semiconductor switch 1 (“low-side switch”, LS, implemented in a first semiconductor chip) connected in series with a controllable second semiconductor switch 2 (“high-side switch”, HS, implemented in a second semiconductor chip). The half-bridge circuit has a first circuit node 31, a second circuit node 32, and a third circuit node 33.

[0012] The controllable first semiconductor switch 1 has a first main contact 11, which is electrically connected to the first circuit node 31, a second main contact 12, which is electrically connected to the third circuit node 33, and a gate contact 13 for controlling an electrical current between the first main contact 11 and the second main contact 12. The controllable second semiconductor switch 2 has a first main contact 21, which is electrically connected to the second circuit node 32, a second main contact 22, which is electrically connected to the third circuit node 33, and a gate contact 23 for controlling an electrical current between the first main contact 21 and the second main contact 22.

[0013] In the simplest case, the gate contact 13 of the first semiconductor switch 1 can be used to switch an electric current between the first main contact 11 and the second main contact 12 ON or OFF. However, the gate contact can also be used to set an electric current between the first main contact 11 and the second main contact 12 to any value between essentially 0 A (amperes) when the first semiconductor switch 1 is OFF, and a maximum current that occurs when the first semiconductor switch 1 is ON. The phrase "essentially 0 A" is intended to express "0 A except for unavoidable residual currents".

[0014] Accordingly, in the simplest case, the gate contact 23 of the second semiconductor switch 2 can be used to switch an electric current between the first main contact 21 and the second main contact 22 ON or OFF. However, the gate contact 23 can also be used to set an electric current between the first main contact 21 and the second main contact 22 to any value between essentially 0 A when the second semiconductor switch 2 is OFF and a maximum current that occurs when the second semiconductor switch 2 is ON.

[0015] In many applications, the half-bridge is supplied with electrical energy, for example via an intermediate circuit voltage. For this purpose, the first circuit node 31 can be connected to a negative supply potential (DC-) and the second circuit node 32 to a positive supply potential (DC+). The arrangement has a first terminal 71 and a second terminal 72 for connecting the positive and negative supply potentials DC+ and DC-, respectively. It should be noted that in some embodiments, the first terminal 71 serves to connect a positive supply potential DC+ and the second terminal 72 to connect a negative supply potential DC-, while in other embodiments, the first terminal 71 serves to connect a negative supply potential DC- and the second terminal 72 to connect a positive supply potential DC+.

[0016] During operation, the first and second semiconductor switches 1, 2 are alternately switched ON and OFF. This means that in the first switching state, the second semiconductor switch 2 is OFF when the first semiconductor switch 1 is ON. Similarly, in the second switching state, the first semiconductor switch 1 is ON when the second semiconductor switch 2 is OFF. When switching from the first switching state to the second switching state, or vice versa, there is an intermediate state in which both the first and second semiconductor switches 1, 2 are briefly OFF to prevent a short circuit between DC+ and DC-, or to disconnect a load connected to a third circuit node 33.

[0017] Accordingly, during normal switching operation of the half-bridge I, the third circuit node 33 is alternately connected either to the positive or to the negative supply potential DC+ or DC-.

[0018] In the case of the half bridge I according to Fig. In 1A, the first and second semiconductor switches 1, 2 are implemented as MOSFETs. Instead of or in addition to MOSFETs, any other type of controllable semiconductor switch, such as IGBTs, JFETs, thyristors, etc., can be used for the first and / or second semiconductor switch 1, 2. The first and second semiconductor switches 1, 2 can be of the same type, i.e., two MOSFETs in series, two IGBTs in series, two JFETs in series, etc. Alternatively, different types of controllable semiconductor switches 1 and 2 can also be connected in series.

[0019] Furthermore, the first and second semiconductor switches 1, 2, if they are field-effect transistors, can be n-channel or p-channel types. However, it is also possible to use an n-channel type as the first semiconductor switch 1 and a p-channel type as the second semiconductor switch 2, or, conversely, a p-channel type as the first semiconductor switch 1 and an n-channel type as the second semiconductor switch 2.

[0020] As another example of a half-bridge, Fig. 1B a half-bridge I, which has two IGBTs 1,2 connected in series.

[0021] Fig. Figure 2 is a circuit diagram of a 2-phase bridge formed from two half-bridges I and II connected to common terminals 71 and 72. Accordingly, Figure 2 shows... Fig. Figure 3 shows a circuit diagram of a 3-phase bridge formed from half-bridges I, II and III connected to common terminals 71, 72. In any arrangement with at least one half-bridge I, II, III, the common terminals 71, 72 serve to connect all half-bridges I, II, III together to the supply potentials DC+ and DC-.

[0022] Each of the half-bridges I and II according to Fig. 2 and each of the half-bridges I, II and III according to Fig. 3 can the structure of the in Fig. 1A shows the half-bridge I. Alternatively, a 2-phase bridge or a 3-phase bridge could also be realized by using two or three half-bridges according to Fig. 1B instead of the half-bridge according to Fig. 1A can be used. Furthermore, half-bridges can be formed from any series connection of any other controllable semiconductor switches, as described above with reference to the Fig. 1A and Fig. 1B were explained.

[0023] In the circuit arrangements according to the Fig. 1A and Fig. 1B is N = 1. In the circuit arrangement according to Fig. 2 is N = 2, and in the circuit arrangement according to Fig. 3 is N = 3. However, N can also be greater than or equal to 4. In general, N is an integer with N ≥ 1, N ≥ 2, or N ≥ 3.

[0024] Provided the circuit arrangement has at least two half-bridges I, II, III (N ≥ 2), the first circuit nodes 31 of all half-bridges I, II, III of the circuit arrangement can be electrically connected to each other, and the second circuit nodes 32 of all half-bridges I, II, III of the circuit arrangement can be electrically conductively connected to each other. This makes it possible to connect all half-bridges I, II, III of the circuit arrangement to common supply potentials DC+ and DC-. In the same way, a circuit arrangement with four or more such half-bridges can be easily achieved by adding one or more additional half-bridges. Each of the additional half-bridges can have one of the half-bridge structures described above and be connected to the common first and second supply terminals 71 and 72.

[0025] Fig. Figure 4 is a vertical sectional view through a semiconductor arrangement showing at least two half-bridges I, II, III according to a first embodiment. The circuit of the arrangement comprises a circuit carrier 5, which has a first metallization layer 41, a second metallization layer 82, an inner metallization layer 81 arranged between the first metallization layer 41 and the second metallization layer 82, a first insulating layer 83 arranged between the inner metallization layer 81 and the second metallization layer 82, and a second insulating layer 43 arranged between the first metallization layer 41 and the inner metallization layer 81.

[0026] The circuit carrier 5 comprises a number of sub-carriers 9 arranged on a common base carrier 8. The common base carrier 8 includes the inner metallization layer 81, the second metallization layer 82, and the first insulating layer 83. The inner metallization layer 81 and the second metallization layer 82 are electrically insulated from each other. The inner metallization layer 81 can be a closed, non-perforated metal layer. To improve heat dissipation from the first and second semiconductor switches 1, 2, a heat sink can be attached to the side of the second metallization layer 82 facing away from the inner metallization layer 81.

[0027] The first insulating layer 83 is a closed, continuous dielectric layer that has no electrically conductive vias. The sub-carriers 9 are arranged on the side of the inner metallization layer 81 facing away from the second metallization layer 82. Each sub-carrier has a first metallization 91, a dielectric 93, and an optional second metallization 92. Each of the first metallizations 91 can have a conductor structure with conductor tracks. The first metallizations 91 of all sub-carriers 9 together form the first metallization layer 41. Correspondingly, the dielectrics 93 of all sub-carriers 9 together form the second insulating layer 43.

[0028] According to one embodiment, each of the half-bridge circuits I, II, III can be arranged on a different sub-carrier 9. In particular, both the first and the second semiconductor switches 1, 2 of each half-bridge circuit I, II, III can be arranged on a common sub-carrier 9 of the respective half-bridge circuit I, II, III. For this purpose, the first and second semiconductor switches 1, 2, which can be semiconductor chips, can be soldered, sintered, or electrically bonded to the first metallization 91 of the respective sub-carrier 9 using a bonding layer 15, for example, a solder layer, a sintered layer containing a noble metal such as silver, or an adhesive layer. Since each of the semiconductor chips has a first or second semiconductor switch with a first main contact, a second main contact, and a gate contact, each of the semiconductor chips requires (at least) three contacts.

[0029] An arrangement comprising a base substrate 8 and one or more individual subcarriers 9 can be manufactured by equipping each of the subcarriers 9 with the respective first and second semiconductor chips 1, 2 and, optionally, with the respective second connecting tab 72. Equally optionally, the first and second semiconductor chips 1, 2 can be electrically connected to one another using electrically conductive connecting elements such as bond wires, ribbons, metal strips, etc. All connecting elements designated with the reference numeral "7" can optionally be mounted on the respective subcarrier 9 before this subcarrier 9 is mounted on the base substrate 8. After the subcarriers 9 have been pre-equipped with at least some of the aforementioned elements, they can be mounted on the base substrate 8.For this purpose, the second metallization 92 of the respective sub-carrier 9 can be connected to the inner metallization layer 81, for example by soldering, sintering, or bonding. As a result of such a joining process, respective connecting layers 45 link the sub-carriers 9 to the inner metallization layer 81. However, the connecting layers 45 between the sub-carriers 9 and the inner metallization layer 81 are optional. Instead, the second metallizations 92 of the sub-carriers can also be directly connected to the inner metallization layer 81, for example by a direct copper-to-copper bonding process (DCB).

[0030] Alternatively, the sub-carriers 9 can be connected to the common base carrier 8 using bonding layers 45 as explained above, or by means of a direct copper-to-copper bonding process without additional bonding layers 45, and then fitted with the respective elements.

[0031] It is pointed out that in Fig. 4 and likewise in the following figures, the electrical connections of the gate contacts are not shown. However, in each embodiment, a gate contact of a semiconductor switch 1, 2 can be arranged either on the side facing the circuit carrier 5 or on the side of the semiconductor chip in which the respective semiconductor switch 1, 2 is integrated.An arrangement comprising a first semiconductor chip containing a first semiconductor switch 1 and a second semiconductor chip containing a second semiconductor switch 2, in which the first and second semiconductor switches 1 and 2 form a half-bridge circuit I, II, III, the first and second semiconductor switches 1, 2 can be arranged on the circuit carrier 5 such that the gate contacts 13 and 23 of both the first and second semiconductor switches 1, 2 are arranged on the sides of the respective first and second semiconductor chips facing the circuit carrier 5, or alternatively such that the gate contacts 13 and 23 of both the first and second semiconductor switches 1, 2 are arranged on the sides of the respective first and second semiconductor chips facing away from the circuit carrier 5.It is also possible that the gate contact 13 of the first semiconductor switch 1 is located on the side of the associated semiconductor chip facing the circuit carrier 5, and that the gate contact 23 of the second semiconductor switch 2 is located on the side of the associated semiconductor chip 2 facing away from the circuit carrier 5. Conversely, it is equally possible that the gate contact 13 of the first semiconductor switch 1 is located on the side of the associated semiconductor chip facing away from the circuit carrier 5, and that the gate contact 23 of the second semiconductor switch 2 is located on the side of the associated semiconductor chip facing the circuit carrier 5. Each of the described alternatives can be applied to each of the half-bridge circuits I, II, III of the arrangement, regardless of the structure and design of the other half-bridge circuits in the arrangement.

[0032] It is further noted that each first and second semiconductor chip can be a "vertical" semiconductor chip, in which the first and second main contacts 11 / 12 and 21 / 22, respectively, are arranged on opposite sides of the semiconductor chip 1, 2. However, "lateral" semiconductor chips can also be used in other configurations.

[0033] In accordance with the order Fig. 4. The inner metallization layer 81 serves to transmit a positive supply potential DC+ to each of the half-bridge circuits I, II, III. For this purpose, the positive supply potential DC+ can be applied via a first terminal 71, which is electrically connected to the inner metallization layer 81. The first terminal 71 can be soldered or sintered to the inner metallization layer 81 using a bonding layer 75, which could be, for example, a solder layer or a sintered layer containing a noble metal such as silver. Alternatively, the first terminal 71 can also be welded directly to the inner metallization layer 81. In this case, the bonding layer 75 is not required.

[0034] Bond wires 6 can be used to electrically connect the half-bridge circuits I, II, III to the inner metallization layer 81. A bond wire can, for example, consist of copper or aluminum, or of at least 90 atomic percent copper, or of at least 90 atomic percent aluminum.

[0035] As in Fig. As shown in Figure 4, such a bond wire 6 can be bonded to the inner metallization layer 81 at a first bonding point 61, and optionally to the first metallization 91 of one of the sub-carriers 9 at a second bonding point 62. At the first bonding points 61, the material of the bond wire 6 is in physical contact with the material of the inner metallization layer 81 at the second bonding point 62. Similarly, the material of the bond wire 6 is in physical contact with the material of the first metallization layer 41.

[0036] If two or more subcarriers 9 are present, one of the first bond points 61 can be located between two adjacent circuit carriers 9. The two corresponding adjacent circuit carriers 9 can be spaced apart from each other. The corresponding distance is denoted by d. For example, the distance d can be less than or equal to 30 mm and / or at least 3 mm.

[0037] At the in Fig. In the embodiment shown in Figure 4, the inner metallization layer 81 is electrically connected to the first main contact of the second semiconductor switch 2, that is, to the second circuit node 32 of the respective half-bridge circuit I, II, III. The first main contact 21 of the second semiconductor switch 2 is located on the side of the semiconductor chip of the second semiconductor switch 2 facing the circuit carrier 5.

[0038] To connect the individual half-bridge circuits I, II, III to a negative supply potential DC-, second connection tabs 72 are provided. Each of the second connection tabs 72 is electrically connected to the first main contact 11 of the first semiconductor switch of a first semiconductor switch 1 of another of the sub-carriers, that is, to the first circuit node 31 of the respective half-bridge circuit I, II, III. Thus, the second connection tabs 72 can be soldered or sintered to the first metallization 91 of the respective sub-carrier 9 using a bonding layer 75, such as a solder layer or a sintered layer containing a noble metal like silver. Alternatively, the second connection tabs 72 can also be welded directly to the first metallization 91 of the respective sub-carrier 9. In the arrangement according to Fig. 4 The first main contact 11 of the first semiconductor switch 1 is located on the side of the semiconductor chip of the first semiconductor switch 1 facing away from the circuit carrier 5. In order to connect the second terminal tabs 72 to a common supply potential, which in this embodiment is provided by DC, a bus rail 72a is provided, which electrically connects the second terminal tabs 72 to each other.

[0039] Furthermore, a third connection lug 73 is provided for each of the half-bridge circuits I, II, III. Each of the third connection lugs 73 is electrically connected to the third circuit node 33 of another of the half-bridge circuits I, II, III, that is, to another of the sub-carriers 9. For this purpose, the third connection lug 73 can be soldered or sintered to the first metallization 91 of the respective sub-carrier 9 using a connecting layer 75, which can be, for example, a solder layer or a sintered layer containing a precious metal such as silver. Alternatively, the third connection lugs 73 could be welded directly to the first metallization layer 41. Fig. 4 The first main terminal 11 of the first semiconductor switch 1 is located on the side of the semiconductor chip of the first semiconductor switch 1 facing away from the circuit carrier 5. The third terminal tabs 73 serve as phase outputs Ph. For example, the phase outputs Ph can be connected to a load such as a motor, etc.

[0040] According to another, in Fig. In the embodiment shown in Figure 5, the inner metallization layer 81 can alternatively be used to conduct a negative supply potential DC- to each of the half-bridge circuits I, II, III. In this case, the negative supply potential DC- can be supplied via the first terminal 71, which is electrically connected to the inner metallization layer 81, as described above with reference to Figure 5. Fig. 4 was explained. Bond wires 6 can be used to electrically connect each of the half-bridge circuits I, II, III to the inner metallization layer 81. As in Fig. As shown in Figure 5, such a bond wire 6 can be bonded to the inner metallization layer 81 at a first bonding point 61, and optionally to the side of the first semiconductor chip 1 facing away from the circuit carrier 5 at a second bonding point 62.

[0041] If two or more sub-carriers 9 are present, at least one of the first bond points 61 can be located between two adjacent sub-carriers 9. The corresponding two sub-carriers 9 can be at a distance d, which can have the same range of values ​​as the preceding one with reference to Fig. 4 explained distance d, to be spaced apart.

[0042] To connect the second connecting tabs 72 electrically to a supply potential, which in this embodiment is given by DC+, a bus rail 72a is provided, which electrically connects the second connecting tabs 72 to each other.

[0043] Another one, in Fig. The embodiment shown in section 6 differs from the embodiment according to Fig. 4 only because the sub-beams 9 have no second metallizations 92 (see Fig. 4) exhibit. Instead, the dielectric 93 of each of the sub-carriers 9 is directly bonded to the inner metallization layer 81 and is in physical contact with it. As already mentioned above with reference to Fig. As described in section 4, the sub-beams 9 can each be spaced apart from each other by a distance d, where this distance d can lie in the same range of values ​​as the one previously described with reference to Fig. 4 mentioned distance d.

[0044] The order according to Fig. 5 could be modified in the same way, that is, instead of providing second metallizations 92 and compound layers 45, each of the dielectrics 93 could be bonded directly to the inner metallization layer 81. The result is in Fig. 7 shown.

[0045] In each embodiment, in particular in the embodiments described above with reference to the figures, the first metallization layer 41, the second metallization layer 82, the inner metallization layer 81 and the optional second metallization 42 can independently have one or more of the following features in any combination with each other: (a) A thickness of at least 0.1 mm. (b) A thickness of less than or equal to 0.8 mm. (c) A material consisting of copper or consisting of at least 90 wt.% (weight percent) of copper or consisting of aluminium or consisting of at least 90 wt.% of aluminium.

[0046] Furthermore, in each embodiment, in particular in the embodiments explained with reference to the figures, the first insulating layer 83 and the second insulating layer 43 can independently of each other and in any combination have one or more of the following features: (a) A thickness of at least 0.2 mm. (b) A thickness of less than or equal to 2 mm. (c) No electrical vias. (d) A ceramic material. For example, the ceramic material may consist of one or more of the following materials, or may incorporate one or more of the following: aluminum oxide (Al2O3); aluminum nitride (AlN); silicon nitride (Si3N4); zirconium oxide (ZrO2); aluminum titanate (Al2TiO5); sintered silicon carbide (SSiC); reaction-bonded silicon carbide (SiSiC).

[0047] Furthermore, in configurations with one or more sub-supports 9, each sub-support can be designed as a DCB substrate (DCB = directly copper bonded), as an AMB substrate (AMB = active metal brazed), or as a DAB substrate (DAB = directly aluminum bonded). In such a DCB substrate, the second insulating layer 43 consists of aluminum oxide (Al₂O₃). The first metallization 41 and the optional second metallization 42 are then copper layers that are bonded directly to the aluminum oxide of the second insulating layer 43 under high pressure and at high temperatures of approximately 1064°C.

[0048] Accordingly, the base substrate 8 can also be a DCB substrate, an AMB substrate, or a DAB substrate. In the case of a DCB substrate, the first insulating layer 83 consists of aluminum oxide (Al2O3), while the inner metallization layer 1 and the second metallization layer 82 are copper layers that are bonded directly to the aluminum oxide of the first insulating layer 83 at high temperatures of approximately 1064°C.

[0049] In other embodiments, where the sub-carriers 9 do not have second metallizations 92, the circuit carrier 5 can be a multilayer DCB substrate in which the first insulating layer 83 and the second insulating layer 43 consist of aluminium oxide, in which the first metallization layer 41 and the inner metallization layer 81 are directly copper-bonded to the second insulating layer 43, and in which the inner metallization layer 81 and the second metallization layer 82 are directly copper-bonded to the first insulating layer 83.

Claims

[1] Semiconductor arrangement comprising: a circuit carrier (5) comprising a first metallization layer (41), a second metallization layer (82), an inner metallization layer (81) arranged between the first metallization layer (41) and the second metallization layer (82), a first insulating layer (83) arranged between the inner metallization layer (81) and the second metallization layer (82), and a second insulating layer (43) arranged between the first metallization layer (41) and the inner metallization layer (81); a bond wire (6); at least N half-bridge circuits (I, II, III), where N ≥ 1, and where each of the half-bridge circuits (I, II, III) comprises the following: - a first circuit node (31), a second circuit node (32) and a third circuit node (33); - a controllable first semiconductor switch (1) having a first main contact (11) which is electrically connected to the first circuit node (31), a second main contact (12) which is electrically connected to the third circuit node (33); and a gate contact (13) for controlling an electric current between the first main contact (11) and the second main contact (12); - a controllable second semiconductor switch (2) having a first main contact (21) which is electrically connected to the second circuit node (32), a second main contact (22) which is electrically connected to the third circuit node (33), and a gate contact (23) for controlling an electric current between the first main contact (21) and the second main contact (22); wherein the first semiconductor switch (1) and the second semiconductor switch (2) of each of the half-bridge circuits (I, II, III) is arranged on the side of the first metallization layer (41) facing away from the second insulating layer (43); and the bond wire (6) is bonded directly to the inner metallization layer (81) at a first bonding point (61), so that a material of the bond wire (6) at the first bonding point (61) is in physical contact with a material of the inner metallization layer (81). [2] Semiconductor arrangement according to claim 1, wherein the bond wire (6) is bonded directly to the first metallization layer (41) at a second bonding point (62), so that the material of the bond wire (6) at the second bonding point (62) is in physical contact with a material of the first metallization layer (41). [3] Semiconductor arrangement according to claim 1, wherein the bond wire (6) is bonded directly to the side of the first semiconductor switch (1) facing away from the circuit carrier (5) at a second bonding point (62). [4] Semiconductor arrangement according to one of the preceding claims, further comprising a first connecting tab (71) which is electrically conductively connected to the inner metallization layer (81). [5] Semiconductor arrangement according to claim 4, wherein the first connecting tab (71) is electrically connected either to the first main contact (11) of the first semiconductor switch (1) or to the first main contact (21) of the second semiconductor switch (2). [6] Semiconductor arrangement according to claim 4 or 5 with a second terminal tab (72), wherein either (a) the first terminal (71) is electrically connected to the first main contact (11) of the first semiconductor switch (1) and the second terminal (72) is electrically connected to the first main contact (21) of the second semiconductor switch (2); or (b) the first connecting tab (71) is electrically connected to the first main contact (21) of the second semiconductor switch (2) and the second connecting tab (72) is electrically connected to the first main contact (11) of the first semiconductor switch (1). [7] Semiconductor arrangement according to claim 6, wherein in case (a) the first terminal (71) is electrically connected to the side of the first semiconductor switch (1) facing away from the circuit carrier (5); and the second terminal (72) is electrically connected to the side of the second semiconductor switch (2) facing the circuit carrier (5); or in case (b) the first connecting tab (71) is electrically connected to the side of the second semiconductor switch (2) facing the circuit carrier (5) and the second connecting tab (72) is electrically connected to the side of the first semiconductor switch (1) facing away from the circuit carrier (5). [8] Semiconductor arrangement according to any of the preceding claims, wherein each of the first, second and inner metallization layers (41, 82, 81) has a thickness of at least 0.1 mm and / or a thickness of less than or equal to 0.8 mm. [9] Semiconductor arrangement according to any of the preceding claims, wherein each of the first, second and inner metallization layers (41, 82, 81) is independently, made of copper; or contains at least 90 wt.% copper; or made of aluminum; or consists of at least 90% by weight of aluminium. [10] Semiconductor arrangement according to one of the preceding claims, wherein each of the first and second insulating layers (83, 43) has a thickness of at least 0.2 mm and / or a thickness of less than or equal to 2 mm. [11] Semiconductor arrangement according to one of the preceding claims, wherein each of the first and second insulating layers (83, 43) is made of ceramic and / or wherein the inner metallization layer (81) is a closed, non-perforated metal layer. [12] Semiconductor arrangement according to any of the preceding claims, wherein N ≥ 2 or N ≥ 3; each of the half-bridge circuits (I, II, III) is arranged on a different one of N sub-carriers (9) which are part of the circuit carrier (5); each of the N sub-carriers (9) has a first metallization (91) and a dielectric (93): the first and second semiconductor switches (1, 2) of each of the N half-bridge circuits (I, II, III) are arranged on the side of the first metallization (91) of the respective sub-support (9) facing away from the dielectric (93); and the first bonding point (61) is arranged between two adjacent, spaced-apart sub-carriers (9). [13] Semiconductor arrangement according to claim 12, wherein the first metallizations (91) of the sub-carriers (9) of the N half-bridge circuits (I, II, III) together form the first metallization layer (41). [14] Semiconductor arrangement according to claim 12 or 13, further comprising a compound layer (45), wherein Each of the N subcarriers (9) has a second metallization (92) which is arranged on the side of the dielectric (93) of the respective subcarrier (9) facing away from the first metallization (91) of the respective subcarrier (9); the connecting layer (45) is arranged between the second metallizations (92) of the subcarriers (9) of each of the N half-bridge circuits (I, II, III) and the inner metallization layer (81) and electrically and mechanically connects the second metallization (92) of each of the N subcarriers (9) to the inner metallization layer (81). [15] Semiconductor arrangement according to one of claims 12 to 13, wherein a material of the dielectric (93) of each of the N subcarriers (9) is in physical contact with the material of the inner metallization layer (81). [16] Semiconductor arrangement according to any one of claims 12 to 15, wherein the distance between two adjacent sub-carriers (9) is at least 3 mm and / or less than or equal to 30 mm. [17] Semiconductor arrangement according to any one of claims 12 to 16, in which none of the dielectrics (93) of the N sub-carriers (9) has a through-hole connection that electrically connects the first metallization (91) of the respective sub-carrier (9) to the inner metallization layer (81); and / or in which the first insulating layer (83) is a closed, non-perforated dielectric layer without any vias.

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