Analysis of clock signal jitter and power supply noise

Abstract

A procedure with: Receiving a first signal by a noise analysis unit (120); generating a second signal based on the first signal by the noise analysis unit (120); temporally shifting the second signal by a base delay time of a base delay element (912) to generate a further signal; and temporally shifting the further signal within a period of the first signal by a plurality of fine delay elements (450) arranged in series with the basic delay element (912) to generate delayed versions of the further signal; measuring the delayed versions of the further signal with the first signal to generate measured values ​​of the delayed versions of the further signal for each period of the first signal; Determining one or more noise characteristics by comparing, by means of a comparator (960), each of the measured values ​​with respective values ​​of an ideal signal, wherein the ideal signal is a version of the further signal that would be generated from a first signal if the first signal were free of high-frequency noise and low-frequency noise; and Generating a noise signature based on the one or more noise characteristics.

Description

TECHNICAL FIELD

[0001] This disclosure relates generally to data processing devices and, more particularly, to a method and a noise analysis system for detecting and analyzing noise signatures. BACKGROUND

[0002] Applications for signal processing are numerous and constantly growing. Examples of signal processing applications include the transmission and reception of messages by mobile devices, speech recognition, and clock signals used to time the internal operations of CPUs and GPUs.

[0003] Signals can be composed of multiple frequencies. The smallest frequency that forms part of the signal is known as the fundamental frequency of the signal. Signals can also contain unwanted components, such as noise. The presence of noise in a signal can reduce the signal's performance in an application. A noisy signal can carry erroneous or incomplete information. Noise can have special properties that can be understood as a signature. For example, noise can be characterized as low-frequency or high-frequency noise. Low-frequency noise can be noise that occurs at a frequency lower than a signal's fundamental frequency. High-frequency noise can then be all noise that is not low-frequency noise.The detection and analysis of a noise signature allows the source of the noise to be identified, eliminated, and / or reduced. Reference is also made in the present technical field to US 2010 / 0 001 780 A1, US 2005 / 0 273 320 A1, US 2003 / 0 198 309 A1, and US 2008 / 0 111 601 A1. US 6 795 496 B1 discloses a device for determining jitter that uses a Hilbert transform. One object of the invention is to detect various types of noise. OVERVIEW

[0004] A method according to claim 1 and a noise analysis system according to claim 6 for detecting and analyzing noise signatures are disclosed.

[0005] In one aspect, a method for detecting and analyzing noise signatures according to claim 1 is disclosed. In this aspect, the method comprises, among other things, receiving a first signal by a noise analysis unit. The method may further include: generating, by the noise analysis unit, a second signal based on the first signal and temporally shifting, by a base delay, the second signal by a base delay time. In one aspect, the method may further include: comparing, by means of a comparator, an actual measurement of the temporally shifted second signal with a theoretical value of a third theoretical signal, wherein the third theoretical signal is a version of the second signal that would be generated from the first signal if the first signal did not comprise any high-frequency noise and any low-frequency noise.

[0006] In another aspect, a noise analysis system is disclosed for detecting and analyzing noise signatures. In one aspect, the noise analysis system includes, among other things, a signal generator configured to receive a first signal and generate a second signal based on the first signal. In one aspect, the noise analysis system may further include a base delay element configured to shift the second signal by a first time delay; and a comparator configured to compare an actual measured value of the time-shifted second signal with a theoretical measured value of a third theoretical signal, wherein the third theoretical signal is a version of the second signal that would be generated from the first signal if the first signal did not include high-frequency noise and low-frequency noise.

[0007] The methods and systems disclosed herein may be implemented in any device to achieve various aspects and may be embodied in a form of non-transitory machine-readable medium containing a set of instructions that, when executed by a machine, cause the machine to perform any of the operations disclosed herein. Other features will be apparent from the accompanying drawings and from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The embodiments of this invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals indicate like elements and in which: Fig. 1 is a block diagram of a noise analysis unit according to one or more embodiments. Fig. 2 is a waveform showing a noise-free analog signal and points along the waveform at which a noise analysis unit makes measurements of the signal according to one or more embodiments. Fig. 3A is a waveform illustrating high frequency noise compared to a noise-free analog signal, according to one or more embodiments. Fig. 3B is a waveform illustrating low frequency noise compared to a noise-free analog signal, according to one or more embodiments. Fig. 3C is a waveform illustrating a combination of a signal and high frequency noise according to one or more embodiments. Fig. 3D is a waveform showing a combination of a signal and low frequency noise according to one or more embodiments. Fig. 3B is a waveform illustrating a combination of a signal with low frequency noise and high frequency noise and showing the position of measurements taken by the noise analysis unit according to one or more embodiments. Fig. 4A is a waveform illustrating a square wave that may represent a noise-free digital clock signal, according to one or more embodiments. Fig. 4B is a waveform showing a signal derived from the square wave of Fig. 4A according to one or more embodiments. Fig. 4C is a waveform that represents the signal from Fig. 4B, shifted by a base delay, showing the position of measurements that may be taken by a noise analysis unit according to one or more embodiments. Fig. 4D is a series of waveforms; waveform "s" may represent an initial signal, waveform "mts" may represent a meta-signal that may be obtained from information contained in the initial signal, and waveforms D1 to D8 may represent delayed versions of the signal mts according to one or more embodiments. Fig. Figure 4E is an enhanced detail view of a portion of the D1 waveform from Fig. 4B according to one or more embodiments. Fig. 4F is an enlarged detail of the location of measurements that may be taken by a noise analysis unit according to one or more embodiments. Fig. 5A is a waveform illustrating a square wave that may represent a noise-free digital clock signal, according to one or more embodiments. Fig. 5B is a waveform illustrating a square wave with high frequency noise that may represent a clock signal containing high frequency jitter, according to one or more embodiments. Fig. 5C is a waveform showing a square wave, which represents a signal derived from the waveform in Fig. 5B according to one or more embodiments. Fig. 5D is a waveform that represents the square wave from Fig. 5C offset by a base delay according to one or more embodiments, and also showing values ​​for measurements that can be taken from the waveform. Fig. Figure 5B is a series of waveforms illustrating how a noise analysis unit can take measurements after a base delay and a series of fine delays. Fig. 6A is a waveform illustrating a square wave that may represent a noise-free digital clock signal, according to one or more embodiments. Fig. 6B is a waveform that represents a square wave, which represents a signal derived from the waveform of Fig. 6A according to one or more embodiments. Fig. 6C is a waveform that shows areas of the waveform from Fig. 6B, which has been offset by delays that may represent high-frequency noise of the supply, and which also shows, according to the dashed lines, the positions that may be taken by the waveform when no noise is present, according to one or more embodiments. Fig. 6B is a waveform showing areas of the waveform from Fig. 6B when shifted according to delays that may represent high frequency noise of the supply, and also showing values ​​of measurements that may be taken from the waveform according to one or more embodiments. Fig. 7A is a waveform illustrating a square wave that may represent a noise-free digital clock signal, according to one or more embodiments. Fig. 7B is a waveform illustrating a square wave with low frequency noise, which may represent a clock signal with low frequency jitter, according to one or more embodiments. Fig. 7C is a waveform that represents a square wave, which represents a signal derived from the waveform in Fig. 7B according to one or more embodiments. Fig. 7D is a waveform that represents the square wave from Fig. 7C offset by a base delay, and also showing values ​​of measurements that may be taken from the waveform according to one or more embodiments. Fig. 8A is a waveform illustrating a square wave that may represent a noise-free digital clock signal, according to one or more embodiments. Fig. Figure 8B is a waveform showing a square wave representing a signal derived from the waveform of Fig. 8A according to one or more embodiments. Fig. 8C is a waveform that shows areas of the waveform from Fig. 8B, shifted by delays that may represent low-frequency noise of the supply, and also showing by the dashed lines the positions occupied by the waveform if no noise were present, according to one or more embodiments. Fig. 8D is a waveform that shows areas of the signal from Fig. 8B shifted by delays that may represent low frequency noise of the supply, and further showing values ​​of measurements that may be taken from the waveform, according to one or more embodiments. Fig. 9 is a block diagram of a noise analysis unit according to one or more embodiments. Fig. 10 is a flowchart showing a procedure that may be used by a noise analysis unit according to one or more embodiments. Fig. 11 is a block diagram of a noise analysis unit coupled to clocked logic elements, according to one or more embodiments. Fig. 12 is a process flow diagram of a noise analysis unit according to one or more embodiments.

[0009] Other features of the present invention will become apparent from the accompanying drawings and the following detailed description. DETAILED DESCRIPTION

[0010] Illustrative embodiments, as described below, may be employed to provide a method, system, and / or apparatus for analyzing noise within a signal. The illustrative embodiments may detect and analyze unique characteristics of noise contained within a signal, wherein the unique characteristics are used to determine a signature of a particular type of noise. The illustrative embodiments may detect the aforementioned characteristics by taking measurements of a signal, and / or by a meta-signal generated using information contained within the signal, and / or by noise, and / or by multiple and / or theoretical versions of the aforementioned aspects. The term "measurement," as used herein, is synonymous with the term "sampling."

[0011] Fig. 1 shows a block diagram of a system including a noise analysis unit 120 according to one or more embodiments. In this or other embodiments, a signal 102 received at the noise analysis unit 120 may be free of noise, where noise represents undesirable characteristics of an electrical signal. The signal 102 may be an analog or digital signal. The signal 102 may be represented by a waveform, the waveform including one or more frequencies, the lowest frequency of the waveform being a fundamental frequency. Low-frequency noise 106 represents noise that may occur at a frequency lower than the fundamental frequency of the signal 102. High-frequency noise 104 may be noise that occurs at a frequency greater than that of the low-frequency noise 106.The low-frequency noise 106 and / or the high-frequency noise 104 may be combined with the signal 102 at a position 108. The position 108 may be a physical position, a temporal position, or a combination of both. The aforementioned low-frequency noise 106 and / or the high-frequency noise 104 may be unintentionally generated and combined with the signal 102, and / or may be intentionally generated and combined with the signal 102. In one or more embodiments, the signal 102 may be an actual signal received at the noise analysis unit 120 and / or it may be a theoretical signal generated by the noise analysis unit 120 to represent a noise-free signal.

[0012] In one or more embodiments, the signal 102 and / or the signal and noise 110 may be received in real time by the noise analysis unit 120, or they may be received after one or more delays, and / or recorded by another device or system, which may then be accessed by the noise analysis unit 120. The noise analysis unit 120 may then perform operations on the signal and noise 110, thereby comparing the signal and noise 110 to the noise-free signal 102. The operations performed by the noise analysis unit 120 may compare the signal and noise 110 and the noise-free signal 102 to determine unique characteristics of the noise contained in the signal and noise 110. The aforementioned unique characteristics may be used to determine the source of the noise contained in the signal and noise 110.

[0013] In one or more embodiments, the operations performed by the noise analysis unit 120 may include generating a first new signal based on the signal and noise 110, temporally shifting the new signal with respect to the signal 102, generating a second new signal based on the signal 102, measuring the temporally shifted first new signal, measuring the second new signal, and comparing the aforementioned measurements to determine the unique characteristics of the noise contained in the signal and noise 110. In one or more embodiments, the noise analysis unit 120 may also temporally shift the second new signal.

[0014] In one example, signal 102 may be a clock signal of a computing system. The computing system may include memory, a timer, and a processor (the processor may be a CPU, a GPU, an ASIC, an FPGA, an analog system, or other device that performs computational operations). Clock signal 102 may be represented by a square wave, where the square wave has a high value, represented as 1, for periodically repeating defined time periods, and a low value, which may be represented as 0, for periodically repeating defined time periods. One cycle of a clock signal 102 may include a single high period combined with a single low period. The high value of clock signal 102 may represent a one (1) and the target value may represent a zero (0). Clock signal 102 may be used to synchronize operations in a computing system.In one example, the periods of clock signal 102 may be subject to random fluctuations. Random fluctuations that occur in a time period less than one clock cycle may be high-frequency noise 104, and random fluctuations that last longer than a single clock cycle may be low-frequency noise 106. The aforementioned low-frequency noise and / or high-frequency noise affecting clock signal 102 may be low-frequency jitter and / or high-frequency jitter.

[0015] In one example, the processing speed of a processor in a computing system may be affected by a power supply level. For example, if the computing system's power supply provides power at a higher level than a designed power level, the processor may operate at a higher speed than its design speed and may complete operations at a rate higher than a design rate. On the other hand, if the power provided by the power supply is less than the desired power level, the processor may operate at a lower speed than the design speed and complete operations at a slower rate than the design rate. Random fluctuations in supply power may be supply power noise.Power supply noise that lasts for a time period less than one clock cycle may be high-frequency noise 104. Power supply noise that lasts for a time period less than or equal to one clock cycle may be low-frequency noise 106.

[0016] Fig. 2 shows, according to one or more embodiments, a noise-free analog version of signal 102 represented as a sine wave. A base delay 202 may be applied to signal 102 by noise analysis unit 120. Noise analysis unit 120 may take measurements or samples 210 of signal 102 after base delay 202 and thereafter after a fine delay 204. Although the sine signal is shown in the figure as signal 102, it may represent a signal generated by noise analysis unit 120 based on signal 102 and / or may represent the signal and noise 110, and this may be phase-shifted by an amount corresponding to base delay 202, and / or may be phase-shifted by other amounts corresponding to fine delay 204, and / or may be shifted by other amounts.

[0017] Fig. 3A shows an analog example of high frequency noise 104 compared to signal 102, according to one or more embodiments.

[0018] Fig. 3B shows an analog example of low frequency noise 106 compared to signal 102, according to one or more embodiments.

[0019] Fig. 3C shows an example of analog high frequency noise 104 when combined with signal 102 to generate signal and noise 110, according to one or more embodiments.

[0020] Fig. 3D shows an example of analog low frequency noise 106 combined with signal 102 to generate signal and noise 110, according to one or more embodiments.

[0021] Fig. 3E shows an example of both analog high frequency noise 104 and analog low frequency noise 106 when combined with signal 102 to generate signal and noise 110, according to one or more embodiments. Fig. 3E also shows a series of measurements or samples 210 that may be taken by the noise analysis unit 120, where the solid lines and closed circular endpoints represent samples that would be obtained from a noise-free signal 102, and where the dashed lines and open circular endpoints may represent samples taken from the signal and noise 110. The noise analysis unit 120 may compare the aforementioned samples to determine a noise signature; i.e., whether the noise is high-frequency noise, whether the noise is low-frequency noise, and / or the possible source and / or sources of the noise.The aforementioned comparisons performed by the noise analysis unit 120 may, for example, include subtracting the samples obtained from a noise-free signal 102 from samples taken from the signal and noise 110 to then determine if there are differences between an ideal noise-free signal 102 and the signal and noise 110; and then further determining the time frame in which the differences in the samples exist. For example, the noise analysis unit 120 may determine that there are differences between a noise-free signal 102 and the signal and noise 110 that exist for a time period less than the fundamental frequency of the signal 102, and these differences may represent high-frequency noise 104.Alternatively, the noise analysis unit 120 may determine that there are differences between a noise-free signal 102 and the signal and noise 110 that exist for a period of time greater than the fundamental frequency of the signal 102, where these differences represent low-frequency noise 106. In another example, the noise analysis unit 120 may determine that both the aforementioned differences between the signal 102 and the signal and noise 110 are present, indicating the presence of both the high-frequency noise 104 and the low-frequency noise 106. The noise analysis unit 120 may take multiple groups of samples of the signal 102 and the signal and noise 110, with these measurements being repeated at specific times, where the time between measurements is related to the frequency or frequencies of the signal 102.

[0022] In one or more embodiments, the noise analysis unit 120 may generate a meta-signal and / or meta-signals based on the signal 102 and / or the signal and noise 110. In one or more embodiments, a meta-signal may contain information about the signal on which it is based, regarding the frequency, period, amplitude, and / or variability of the meta-signal. In one or more embodiments, the noise analysis unit 120 may time-shift one or more of the aforementioned meta-signals, take a series of samples 210 of the one or more of the meta-signals, and compare these samples 210 to equivalent samples of one or more other meta-signals and / or the signal 102 and / or the signal and noise 110 to determine unique characteristics of the signal and noise 110 that form a noise signature.

[0023] Analogue signal forms as they are used in the Fig. 2 - 3E can be converted to digital waveforms by assigning discrete values ​​to samples of the analog waveform taken at a specific sampling rate. In a simple example, a single value is assigned to a portion of the waveform above a certain level, and another value is assigned to remaining portions of the waveform. For example, values ​​of an analog waveform above a horizontal axis could be considered high, or one (1), and the remaining values ​​below or on the horizontal axis could be considered low, or zero (0); or vice versa. The demarcation line between high values ​​and low values ​​could also be set to a level different from the horizontal axis.The reverse process, i.e., converting a digital waveform to an analog waveform, can also be performed, for example, by interpolating the discrete values ​​of the digital waveform to generate a corresponding analog waveform. Therefore, embodiments described herein that are used for analog signals can also be applied to digital signals, and vice versa.

[0024] Fig. 4A shows a square wave signal, which may be a noise-free digital signal, which in turn may represent a noise-free clock signal, according to one or more embodiments.

[0025] Fig. 4B shows, according to one or more embodiments, a new signal generated by the noise analysis unit 120 from the clock signal of Fig. 4A can be generated. The new signal from Fig. 4B may be a square wave signal that has a high value for one period of the clock cycle Fig. 4A, then output a low value for the next period of the clock cycle Fig. 4A, where the high and low values ​​of the new signal are Fig. 4B alternate according to the clock cycles that are in Fig. 4A. The new signal form from Fig. 4B can be a meta-signal in that it can be a new signal that contains information based on the first signal from Fig. 4A.

[0026] Fig. 4C shows, according to one or more embodiments, the signal from Fig. 4B, if it is offset in time by a base delay 202. Fig. 4C further shows a series of fine delay elements 450. The series of fine delay elements 450 may indicate a temporal position at which the noise analysis unit 120 samples the signal 102, the signal and noise 110, and / or a new signal generated by the noise analysis unit 120 based on the signal 102 and / or the signal and noise 110. The fine delay elements 450 may, in a further embodiment, indicate a group of delays that may be applied to the signal 102, the signal and noise 110, and / or a new signal generated by the noise analysis unit 120 based on the signal 102 and / or the signal and noise 110. For clarity, an enhanced detailed view of the series of fine delay elements 450 is shown in Fig. 4F shown.

[0027] Vertical dashed lines in the Fig. 4A-4E and other enclosed figures showing waveforms represent common temporal positions of the illustrated waveforms and are designated by reference symbols T5, T10, T15, etc. The time periods between the temporal positions are designated by reference symbols P5, P10, P15, etc. The center points of the respective time periods (P5, P10, P15, etc.) are denoted by H5, H10, H15, etc.

[0028] In Fig. 4C, according to one or more embodiments, the base delay 202 and the series of fine delay elements 450 are set such that a portion of the signal that is Fig. 4B during an initial time period, passes through exactly half of the series of fine delay elements 450 in the subsequent time period or a later time period. In one example, a portion of the meta-signal may consist of Fig. 4B, which may be generated by the noise analysis unit 120 during the time period P5, to the center point H10, which lies exactly between T10 and T15, during the subsequent time period P10; the portion of the meta-signal generated during the time period P10 may propagate to the center point H15 during the time period P15, etc. In one or more embodiments, the aforementioned propagation of the meta-signal may be Fig. 4C, generated in a single time period, to a precise midpoint in the subsequent time period may result in selectively setting the base delay 202 and the series of fine delay elements 450 to achieve the precise propagation to half. The resulting precise propagation to half may, according to one or more embodiments, indicate that a noise-free initial signal is present, as indicated by Fig. 4A is illustrated.

[0029] Fig. 4D shows a series of waveforms, according to one or more embodiments, where a waveform "s" may represent an initial signal, a waveform "mts" may represent a meta-signal that may be generated by the noise analysis unit 120 from information contained in the initial signal s, and where waveforms D1 to D8 may represent delayed versions of mts. In one embodiment, the waveform s may be similar to that shown in Fig. 4A and may represent a noise-free clock signal. In one embodiment, the waveform mts may be similar to that shown in Fig. 4B and may represent a meta-signal containing information describing the waveform s. In one example, mts may be generated by the noise analysis unit 120 from s by alternating the value of mts between a low value and a high value for subsequent periods of the signal s, for example, by setting the value of mts high (or 1) for one period of s, and then setting the value of mts low (or 0) for the next period of s, by setting mts low for the subsequent period of s, and so on. Waveform D1 may represent the mts signal when delayed by the base delay 202. Waveform D2 may represent mts delayed by both the base delay 202 and one of the series of fine delays 450. Waveform D3 may represent mts delayed according to base delay 202 and two of the series of fine delays 450.Waveforms D4 may represent mts delayed by the base delay 202 and three of the series of fine delays 450. Waveform D5 may represent mts shifted by the base delay 202 and four of the fine delays 450. D6 may represent mts delayed by the base delay 202 plus five of the fine delays 450. D7 may represent the base delay 202 plus six of the fine delays 450. And finally, D8 may represent mts delayed by the base delay 202 plus seven of the series of fine delays 450. Vertical dotted lines in . Fig. 4D may represent successive periods of the aforementioned delays. Although the series of fine delays 450 is shown as being divided into equal time periods in Fig. 4D, different time periods may also be provided. For example, the second fine delay in the series of fine delays 450 may be a multiple of the first fine delay in the series of fine delays 450. In one embodiment, the meta signal mts may first be generated to have a high value starting at a time T5 and then switching to a low value at time T10, i.e., the time between T5 and T10 is a period P5. The meta signal mts may then, in one embodiment, be delayed by the base delay 202 and a series of fine delays 450 such that the mts values ​​generated during period P5 spread out such that at time T15, which is exactly half, one is on one side of time T15 and the other half is on the other side of time T15.At time T15, which may correspond to a rising edge of a clock signal represented by signal s, noise analysis unit 120 may take samples or measurements (404, 406, 408, 410, 412, 414, 416, 418). The aforementioned measurements, if taken at time T15 in . Fig. 4D have values ​​as shown in Table 1 below. Table 1 TABELLE 1 GEMESSENES BIT REFERENZNUMMER DERMESSUNG WERT 1 404 0 2 406 0 3 408 0 4 410 0 5 412 1 6 414 1 7 416 1 8 418 1

[0030] Although Table 1 above shows 8 bits being measured by the noise analysis unit 120, any other number of bit measurements may be made by the noise analysis unit 120. The number of fine delay elements required in the series of fine delay elements 450 is equal to the desired number of bits to be measured minus 1. For example, when measuring the 8 bits above, a single basic delay 202 may be used, and seven fine delay elements may be employed in the series of fine delay elements 450. To measure 10 bits, for example, the noise analysis unit 120 may use one basic delay 202 and nine fine delay elements from the series of fine delay elements 450. An enlarged detail of the waveform D1 425 from Fig. 4D is in Fig. 4E. An enlarged detail of the series of fine delay elements 450 is shown in Fig. 4F shown.

[0031] Fig. 4E shows, according to one or more embodiments, an enlarged detail 425 of a portion of the waveform D1 of Fig. 4D. Waveform D1 is a square wave, which in one embodiment may represent a meta-signal generated from an initial square wave, where the initial square wave may in turn represent a clock signal. In the example shown, the initial clock signal and the meta-signal may represent signals that have no noise. Waveform D1 may be a version of the meta-signal that has been delayed by a base delay 202. As in the previous Fig. As shown in Figure 4D, the noise analysis unit 120 may perform measurements on delayed waveforms at time T15. Fig. 4B shows the measurements (404-418) taken by the noise analysis unit 120 of various delayed versions (D1-D8) of the meta-signal mts at the specific time T15. An alternative way to obtain the measurements taken is, according to one or more embodiments, Fig. 4E. Measurement 404 may be taken on waveform D1 at time T15, and thereafter, measurement 406 may be taken on waveform D1 at time (T15 minus a single fine delay element), measurement 408 may be taken on waveform D1 at time (T15 minus two fine delay elements), and so on, until measurement 418 is taken at time T10. The result of taking measurements (404-418) by the aforementioned alternative technique may be the same as shown above in Table 1. The resulting representative measurements (404-418) are also shown in Fig. 4E as a series of 0s and 1s between T10 and T15. The values ​​of the representative measurements (404-418) shown between T10 and T15 can be read from right to left, as shown by directional arrow 422, to be consistent with the top-to-bottom order of the measurements (404-418) shown in Table 1. However, the convention used herein will be to show measurements acquired at a particular time listed from left to right, beginning at the time the measurements are taken; as shown, for example, by the measurements listed in a measurement field 432 taken at time T15. The measurements (404-418) taken at time T15 can be tabulated as shown below in Table 2. TABELLE 2 MESSINDEX GEMESSENE DAUER GEMESSENE WERTE 1 P10 0000 1111

[0032] In one or more embodiments, the measurements (404-418) may be recorded by the noise analysis unit 120 at times subsequent to and / or prior to the time period P14. In one or more embodiments, the noise analysis unit 120 may record multiple measurement points equivalent to the measurements (404-418). For example, if the equivalent measurements (404-418) for the time period P5-P40 of the Fig. 4C are recorded, the results shown in Table 3 below are obtained. TABELLE 3 (SIGNAL FORM from Fig. 4C) MESSINDEX MESSZEIT GEMESSENE WERTE 1 T5 0000 1111 2 T10 1111 0000 3 T15 0000 1111 4 T20 1111 0000 5 T25 0000 1111 6 T30 1111 0000 7 T35 0000 1111 8 T40 1111 0000

[0033] The measurements shown in Table 3 above may then, in one or more embodiments, represent measurements obtained by the noise analysis unit 120 from a noise-free meta-signal generated based on and indicative of a noise-free initial signal. A value of 1 in Table 2 may indicate a high value of the waveform from Fig. 4C, and a value of 0 can represent a low value of the waveform from Fig. 4C. Although the measured values ​​shown previously are ones and zeros representing measurements on a digital signal, the measurements can also be taken from an analog signal (as in Fig. 2), in which case the resulting measured values ​​could differ from one and zero.

[0034] The previously mentioned noise-free initial signal from Fig. 4A can be a square wave signal representing a noise-free clock signal, and the aforementioned meta-signal from Fig. 4C may be a square wave generated from the initial signal and having a period equal to a multiple of the initial signal. Therefore, the measurements shown in Table 3 may represent measurements that would be taken by the noise analysis unit 120 for a noise-free situation. In another embodiment, if the noise analysis unit 120 takes measurements of a signal with noise, such as the signal and noise 110, the results would differ from the results shown in Table 3, and the resulting differences could then be used as a signature to detect specific types of noise, such as low-frequency noise, high-frequency noise, and / or the source of the noise.

[0035] Fig. 4F shows, according to one or more embodiments, an enlarged detail of the series of fine delay elements 450 previously shown in Fig. 4C and Fig. 4D. In one embodiment, a signal may be delayed from an initial time position T5, for example, by a base delay 202 and / or a series of fine delays 450, where the fine delays 450 may include a fine delay 204 and further fine delays 440. In one or more embodiments, the base delay 202 may be used, or the time shift caused by the base delay 202 may be different from that used in Fig. 4F, or more than one base delay 202 may be used. Although seven total fine delays (one fine delay 204 and six fine delays 440) are used in Fig. 4E, any number of fine delay elements may be employed by the noise analysis unit 120 in other embodiments. Although the series of fine delays 450 in Fig. 4F are represented as causing equal time delays, the delays caused by the series of fine delays 450 may differ from one another in other embodiments. In one embodiment, the delayed signal may extend beyond a second time position T10, for example, and the noise analysis unit 120 may then take measurements (404-418) at the same or a different time and / or times. In one embodiment, the noise analysis unit 120 may take measurements (404-418) of a signal or signals. In one example, the noise analysis unit 120 may take measurements (404-418) of a delayed signal generated at time T5 at time T15. Although all measurements (404-418) are taken at the same time (e.g., T15, as previously described in Fig. 4D), this can be equivalent to measuring the delayed signal at different temporal positions between two separate time periods. For example, the delayed meta-signal mts can be Fig. 4D by the base delay 202 and the series of fine delays 450, and the noise analysis unit 120 may take measurements (404 - 418) at time T15 for each version of the delayed signal (D1 - D8), or the equivalent measurements (404 - 418) may be taken by the noise analysis unit 120 in time periods between T10 and T15, wherein each time division between the measurement time periods is equivalent to one of the series of fine delays 450. An example of the aforementioned equivalent measurement method is shown in Fig. 4E and Fig. 4F, where the measurements (404 - 418) are taken from a single version of the delayed meta-signal mts (for example, the waveform D1 from Fig. 4D) at different time periods between T10 and T15, where the time interval between the measurements (404 - 418) corresponds to the series of fine delays 450. For example, measurement 404 may be taken by noise analysis unit 120 at time T15, measurement 406 may be taken by noise analysis unit 120 at time T15 minus fine delay 204, measurement 408 may be taken by noise analysis unit 120 at time T15 minus (fine delay 204 plus one fine delay 440), measurement 410 may be taken by noise analysis unit 120 at time T15 minus (fine delay 204 plus two fine delays 440), and so on, until measurement 418 is taken by noise analysis unit 120 at time T15 - (fine delay 204 plus six fine delays 404)).Thus, in one or more embodiments, the equivalent measurements (404-418) may be taken by the noise analysis unit 120 at a single time (e.g., T15) of a signal subject to multiple delays, as shown in FIG. Fig. 4D; or at different time periods of a once delayed signal, as shown in the Fig. 4G and Fig. 4F is shown.

[0036] In one or more embodiments, the aforementioned measurements (404 - 418) may be performed as described in the Fig. 4D, Fig. 4E and Fig. 4F, are taken recursively by the noise analysis unit 120; for example, a finite group of measurements (404-418) may be taken arbitrarily at time T15 for the time period P10, at a subsequent time T20 for the subsequent time period P15, etc. In one embodiment, the series of fine delays 450 may be further subdivided into a series of even finer delays. Although a total of eight measurement points (404-418) are used in Fig. 4F, any number of measurement points may be employed. The time delays generated by the series of fine delay elements 450 between the measurement points (404 - 18) may be the same or different from each other. The time delays generated by the series of fine delay elements 450 may vary from one time period to another. The base delay 202 may also vary from time period to the next, or may be omitted in other embodiments.The time delay created by the series of fine delay elements 450 may be created in a circuit by inverters, capacitors, inductors, and / or a combination of these or other circuit elements; may be created by software, hardware, or a combination thereof; may be created as a result of a program acting on a recorded or transmitted signal; and / or may be created as a result of a processor configured to create such delays.

[0037] Fig. 5A shows a square wave signal according to one or more embodiments. In one or more embodiments, the square wave signal may be Fig. 5A can be a noise-free digital signal, which in turn can represent a noise-free clock signal.

[0038] Fig. 5B shows a square wave signal containing high-frequency noise according to one or more embodiments. The square wave signal may represent a clock signal subject to high-frequency jitter. High-frequency period jitter of a clock signal may refer to a situation in which the period of a clock signal deviates from its ideal value during one clock cycle and then returns to the ideal state in the subsequent cycle. Fig. 5B shows a clock signal that is shorter than the ideal length during a time period P15 according to a jitter 520, according to one or more embodiments. The clock signal may recover to its ideal state during the time period P20. Fig. 5B further shows, according to one or more embodiments, a clock signal that is longer than the ideal length during the rear part of the time period P25 and the initial part of the time period P30 corresponding to a jitter 530. The clock signal may then regain its ideal state at the end of the time period P30.

[0039] Fig. 5C shows, according to one or more embodiments, a signal generated by the noise analysis unit 120 based on the signal from Fig. 5B. In one or more embodiments, the signal may be Fig. 5B represent a clock signal. The new clock signal from Fig. 5C may be a square wave signal having a high value for one period of a clock cycle of the clock signal generated by Fig. 5B, and then a low value for the next period of the clock cycle from Fig. 5B, where the high and low values ​​of the new signal are Fig. 5C alternate with the clock cycles that are in Fig. 5B. In one or more embodiments, the waveform may be Fig. 5C a meta-signal of the waveform Fig. 5A, into which the signal form from Fig. 5C can be generated by the noise analysis unit 120 to obtain information about the signal shape Fig. 5A to be included.

[0040] Fig. 5D shows, according to one or more embodiments, the signal from Fig. 5C, which is shifted by a base delay 202. In one or more embodiments, the noise analysis unit 120 may apply fine delay elements 450 during the time periods (P5 - P40) to obtain measurements of the Fig. 5D, wherein said measurements may be taken by the noise analysis unit 120 from the signal after it has been successively delayed by each of the fine delay elements 450. In one or more embodiments, the aforementioned measurements may be taken by the noise analysis unit 120 on one or more of the rising edges of the Fig. 5A shown signal form.

[0041] In one or more embodiments, the jitter of a clock signal generated by the Fig. 5B shown waveform, have a double effect in that the jitter can cause a part of the meta-signal from Fig. 5C is shorter or longer than it would be if it were generated based on a jitter-free clock signal, and; the measurements taken by the noise analysis unit 120 may occur at a later or earlier time when driven by a clock signal containing jitter, compared to the case when the measurements are driven by a jitter-free clock signal. For example, the jitter 520 may cause the high portion of the meta-signal from Fig. 5C in the period P15 is shorter by the time difference between the times T18 and T20 than it would be if it were generated by a jitter-free signal (see for comparison of the signal form from Fig. 4B during the time period P15). Furthermore, the presence of the jitter 520 may cause the noise analysis unit 120 to take measurements at time T18 instead of time T20. In this example, the noise analysis unit 120 would take measurements of the time period P18 instead of measurements of the time period P20, and the portion of the meta-signal from Fig. 5D being measured would not extend exactly to the center H20. In this example, 6 bits are measured on one side of the center H20, and 2 bits are measured on the other side of the center H20, in contrast to the measurements made by a jitter-free noise-free signal (for example, the one from Fig. 4C during the time period P20, in which 4 bits on one side of the center point H20 and 4 bits on the other side of the center point H20 are measured).

[0042] In another example, the jitter 530 may cause a high proportion of the meta signal to Fig. 5C in the periods P25 and P30 is longer by the time difference between the times T30 and T32 than would be the case if it were generated by a signal without jitter (see for comparison the waveform from Fig. 4B during the time periods P25 and P30). Furthermore, the presence of jitter 520 may cause the noise analysis unit 120 to take its measurements at time T32 instead of time T30. In this example, the noise analysis unit 120 would take measurements of period P32 instead of period P30, and the portion of the meta-signal from Fig. 5D being measured extends beyond the center point H30. In this example, 6 bits are measured on one side of the center point H30 and 2 bits are measured on the other side of the center point H30, in contrast to measurements that would be obtained for a noise-free signal without jitter (for example, the one from Fig. 4C in time period P30, in which 4 bits on one side of the center point H30 and 4 bits on the other side of the center point H30 are measured. Thus, in one or more embodiments, the presence of clock signal jitter can affect both the value of a meta-signal and the time at which the meta-signal is measured.

[0043] In one embodiment, the fine delay elements 450 may be configured such that delays between measurements are equally spaced in time, and such that the number of measurements taken during one ideal clock period is equal to the number of measurements taken in another ideal clock period. In other embodiments, the fine delay elements 450 may be configured such that the time interval between measurements is variable. If, according to one or more embodiments, the fine delay elements 450 are configured such that the time interval between each measurement is the same, and if this configuration is applied to the signal from Fig. 5D is applied, the resulting measurements are as shown in Table 4 below. TABELLE 4A (SIGNAL FORM from Fig. 5D) MESSINDEX MESSZEIT GEMESSENE WERTE 1 T5 0000 1111 2 T10 1111 0000 3 T15 0000 1111 4 T18 1100 0000 5 T25 0000 0011 6 T32 1111 1100 7 T35 0011 1111 8 T40 1111 0000

[0044] It can be seen that according to one embodiment, the measurements taken by the noise analysis unit 120 from the waveform in Fig. 5D may differ from the measurements taken by the noise analysis unit 120 from the waveform Fig. 4C at indices 4, 5, 6, and 7. In one embodiment, these differences may represent a noise signature that may be used by noise analysis unit 120 to characterize high-frequency noise, which may be high-frequency clock jitter. In one or more embodiments, the aforementioned dual effect of high-frequency clock jitter resulting from a rising edge of a clock signal occurring earlier than an ideal time may, in the corresponding region, cause an associated meta-signal to be shorter than normal and that portion of the meta-signal to be sampled at an earlier time than normal; and the effect will also cause the subsequent portion of the meta-signal to be longer by a corresponding amount.The aforementioned dual effect of high-frequency clock signal jitter may, in one or more embodiments, result in a mirror image effect of the sampled values. For example, the samples taken at time T18, shown in Table 4A, are 1 1 0 0 0 0 0 0, and the samples taken at the subsequent time T25 are a mirror image of these values, i.e., 0 0 0 0 0 0 1 1. In another example, the samples taken at time T33, shown in Table 4A, are 1 1 1 1 1 1 0 0; and the samples taken at time T35 are a mirror image of these values, i.e., 0 0 1 1 1 1 1 1.The aforementioned mirror image effect of the measurements taken at a single sampling time, which is equal to the inverse of the measurements of an immediately preceding or succeeding sampling time, may be the result unique to high-frequency clock signal jitter and may be a noise signature that the noise analysis unit 120 may use to characterize high-frequency clock signal jitter.

[0045] Fig. Figure 5E shows a series of waveforms illustrating how the noise analysis unit 120 may take measurements after a base delay 202 and a series of fine delays 450, according to one or more embodiments. In one or more embodiments, the waveform D1 may be a version of the waveform from Fig. 5C, which has been delayed by a base delay 202. The waveform D2 may be a version of the waveform from Fig. 5C, which has been delayed by a base delay 202 and one of the three fine delays 450, D3 can be the waveform from Fig. 5C, which has been delayed by a base delay 202 and two of the series of fine delays 450, and so on, until D8, as shown, is a version of the waveform from Fig. 5C, delayed by a base delay 202 and seven of the series of fine delays 450. According to one or more embodiments, the noise analysis unit 120 may take measurements on the delayed versions of the aforementioned waveform at one or more specific times. For example, the noise analysis unit 120 may take measurements (404-418) of all waveforms D1-D8 at time T18; and may then take equivalent measurements (404-418) at another time T32. The results of the aforementioned measurements (404-418) are shown in Table 4B below. TABELLE 4B Measurements of signal shapes in Fig. 5B at times T18 and T32 Signalform Messungsreferenznummer Zeit T18 Zeit T32 D1 404 1 1 D2 406 1 1 D3 408 0 1 D4 410 0 1 D5 412 0 1 D6 414 0 1 D7 416 0 0 D8 418 0 0

[0046] Although Table 4B above shows eight measurements (404 - 418) derived from the waveforms Fig. 5E were taken at two times T18 and T33; the noise analysis unit 120 can take any number of measurements at any time. The measurements (404 - 418) shown in Table 4B can also be represented in a horizontal row to the right of the measurement time for the waveform for which measurements were taken. For example, Fig. 5E, according to one or more embodiments, the values ​​of measurements (404 - 118) of 1 1 0 0 0 0 0 to the right of time T18, and the values ​​of measurements (404 - 118) of 1 1 1 1 1 0 0 to the right of time T32. A similar method for displaying measurements taken at specific times may be used in other figures of this application that also show waveforms, for example the Fig. 5D.

[0047] Fig. 6A shows a square wave signal according to one or more embodiments. In one or more embodiments, the square wave signal may be Fig. 6A can be a noise-free digital signal, which in turn can represent a noise-free clock signal.

[0048] Fig. 6B shows a square wave signal according to one or more embodiments, which may represent a meta-signal generated based on the previously described Fig. 6A. In one or more embodiments, a meta-signal in the form of a square wave may be generated from Fig. 6B by the noise analysis unit 120 such that a wavelength of a part of the meta-signal from Fig. 6B a multiple of the wavelength of the signal form Fig. 6A. In one example, the wavelength of the meta-signal can be Fig. 6B twice the wavelength of the initial signal in Fig. 6A.

[0049] Fig. Figure 6C shows a delayed version of the meta-signal from Fig. 6B according to one or more embodiments, wherein the signal form of Fig. 6 It can thus be considered as a meta-signal. In one or more embodiments, each cycle of the meta-signal is Fig. 6B is delayed by a base delay 202, resulting in the shifted signal form Fig. 6C. In one or more embodiments, the base delay 202 may be generated by the noise analysis unit 120 through one or more logic circuits. In one or more embodiments, the base delay 202 may be applied to the meta-signal from Fig. 6B on a rising edge of the clock signal, the clock signal potentially being influenced by the waveform of Fig. 6A. In one or more embodiments, the aforementioned logic circuit may receive power from a power supply. In one or more embodiments, the power from the power supply may vary over time, and the fluctuations may affect the base delay 202 generated by the aforementioned logic circuit. For example, if the power supply sends less power than an ideal amount to the logic circuit, the delay of a signal through the logic circuit may be greater than an ideal base delay 202, as shown by a long base delay 605. In another example, the power supply may send more power to the logic circuit compared to an ideal amount, resulting in a delay that is less than an ideal base delay 202, as shown by the short base delay 610. An illustrative noise pattern, as shown in Fig. 6C, in which a power supply level deviates from an ideal level, causing a fluctuation compared to an ideal base delay 202 during an initial time period, and then returns to an ideal power level and the base delay 202 returns to its ideal value within the subsequent time period, may represent a high-frequency supply order. In one or more embodiments, each cycle of a meta-signal, as shown in Fig. 6B, be delayed by another base delay (202, 605, 610), the result being Fig. 6C is shown.

[0050] Fig. 6D shows, according to one or more embodiments, the signal form of Fig. 6C, in which the separately delayed cycles from Fig. 6B, which may result from high-frequency noise from the power supply, are combined to produce a single waveform of Fig. 6B. It can be seen that, according to one or more embodiments, the power supply noise generated by the Fig. 6C and Fig. 6D shown meta-signals, can have a single effect on measurements taken by the noise analysis unit 120; by the power supply noise only affects the duration of the high and low values ​​of the meta-signals from the Fig. 6C and Fig. 6D, in contrast to the noise caused by clock signal jitter, which is caused by the meta signals in the Fig. 5B - 5D, and has a double effect, that is, on both the duration of the high and low values ​​of the meta-signals of the Fig. 5B - 5D, and also on the time at which the noise analysis unit 120 takes the measurements. Fig. 6D further shows, according to one or more embodiments, the values ​​that result when the noise analysis unit 120 measures the waveform of the Fig. 6D. The aforementioned measurements can be taken by the noise analysis unit 120 in a similar manner to the measurements (404 - 418) taken in the Fig. 4D - 4F. In the example shown, the waveform measurements can be Fig. 6D on a rising edge of the Fig. 6A. The waveform from Fig. Figure 6A represents an ideal square wave signal, generated, for example, by a digital clock signal. The resulting illustrative measurements from Fig. 6D, which can be taken in a similar way as in Fig. 5B are shown in tabular form in Table 5 below. TABELLE 5 (SIGNAL FORM from Fig. 6D) MESSINDEX MESSZEIT GEMESSENE WERTE 1 T15 0000 1111 2 T20 1100 0000 3 T25 0011 1111 4 T30 1111 0000 5 T35 0000 1111 6 T40 1111 1100 7 T45 1111 0011 8 T50 0000 1111

[0051] It can be seen that the signal shape determined by the noise analysis unit 120 in Fig. 6D differ from the measurements taken by the noise analysis unit 120 on the waveform from Fig. 4C with measurement indices 2, 3, 6, and 7. These differences may, in one or more embodiments, represent a noise signature that may be used by noise analysis unit 120 to indicate high-frequency power supply noise.

[0052] Fig. Figure 7A shows a square wave signal according to one or more embodiments. In one or more embodiments, the square wave signal may be Fig. 7A may be a noise-free digital signal that can represent a noise-free clock signal.

[0053] Fig. 7B shows a square wave signal containing low-frequency noise, which may represent a clock signal, according to one or more embodiments. Low-frequency period jitter of a clock signal may refer to a situation where the period of the clock signal deviates from its ideal value during one cycle and then returns to its ideal state in the subsequent cycle. Fig. 7B shows, according to one or more embodiments, a clock signal that is shorter than the ideal length during time period P15, corresponding to a jitter 720. In one embodiment, the clock signal does not return to its ideal state during time period P20, and the rising edge of the clock signal occurs earlier than the rising edge of an ideal clock signal, corresponding to a jitter 725. Fig. 7B further illustrates, in accordance with one or more embodiments, a clock signal that has not returned to its ideal state in a time period P25. In one example, the rising edge of the clock signal exits Fig. 7B during the period P25 earlier than the rising edge of the ideal clock signal from Fig. 7A corresponding to an amount of jitter 730. In one example, the clock signal then returns Fig. 7B returns to its ideal state at the end of the time period P30.

[0054] Fig. 7C shows, according to one or more embodiments, a signal generated by the noise analysis unit 120 based on the signal from Fig. 7B. In an example, the signal from Fig. 7B a digital clock signal. The new signal from Fig. 7C can be a square wave signal that has a high value for one period of the clock cycle Fig. 7B, then outputs a low value for the next period of the clock cycle Fig. 7B, where the high and low values ​​of the new signal are Fig. 7C with the clock cycles that are in Fig. 7B alternate. The signal from Fig. 7C may be a meta-signal that can be generated so that it carries information about the signal from Fig. 7B contains.

[0055] Fig. 7D shows, according to one or more embodiments, the signal from Fig. 7C, which is shifted by the base delay 202. The noise analysis unit 120 can apply the fine delay elements 450 during the time period (P5 - P40) to make measurements of the signal as shown in Fig. 7D, wherein the time interval between measurements corresponds to the fine delay elements 450. In one embodiment, the fine delay elements 450 may be configured such that delays between measurements are equally spaced in time, such that the number of measurements taken during an ideal clock period is equal to the number of measurements contained in each other ideal clock period. In other embodiments, the fine delay elements 450 may be configured such that the time interval between measurements is variable. If, according to one or more embodiments, the fine delay elements 450 are configured such that the time interval between each measurement is the same, and if this configuration is applied to the signal from Fig. 7D is applied, the resulting measurements can be taken in a similar way as in Fig. 5E, in the form shown in Table 6 below. TABLE 6 (SIGNAL SHAPE from Fig. 7D) MESSINDEX MESSZEIT GEMESSENE WERTE 1 T5 0000 1111 2 T10 1111 0000 3 T15 0000 1111 4 T18 1110 0000 5 T22 0001 1111 6 T28 1111 1000 7 T35 0000 0111 8 T40 1111 0000

[0056] It can be seen that the illustrative measurements taken by the noise analysis unit 120 from the signal form Fig. 7D are different from the measurements taken by the noise analysis unit 120 from the waveform of Fig. 4C at measurement indices 4, 5, 6, and 7. In one or more embodiments, these differences may represent a noise signature that may be used by the noise analysis unit 120 to characterize low-frequency noise, which may be low-frequency clock signal jitter. Although eight measurements are shown above in Table 6, any number of measurements may be taken by the noise analysis unit 120. Further, it should be noted that, according to one or more embodiments, the differences in the measurements between the Fig. 7D and Fig. 4C due to a double effect that can lead to low-frequency clock signal jitter, similar to the double effect that can lead to high-frequency clock signal jitter, as previously discussed with reference to the Fig. 5B - 5D; in that a clock signal jitter affects both the values ​​of the generated meta-signal, as shown in the Fig. 7B - 7D, as well as affecting the timing at which the noise analysis unit 120 takes measurements of the meta-signal.

[0057] Fig. 8A shows a square wave signal according to one or more embodiments. In one or more embodiments, the square wave signal may be Fig. 8A may be a noise-free digital signal that can represent a noise-free clock signal.

[0058] Fig. Figure 8B shows, according to one or more embodiments, a square wave signal that may represent a meta-signal formed based on the previously shown waveforms in Fig. 8A can be generated by converting the signal waveform from Fig. 8B contains information that determines the signal form Fig. 8A. In one or more embodiments, a meta-signal may be in the form of a square wave signal from Fig. 8B by the noise analysis unit 120 such that a wavelength of a part of the meta-signal from Fig. 8B a multiple of the wavelength of the signal form Fig. 8A. In one example, the wavelength of the meta-signal can be Fig. 8B twice the wavelength of the initial signal in Fig. 8A.

[0059] Fig. Figure 8C shows a delayed version of the meta-signal from Fig. 8B according to one or more embodiments. In one or more embodiments, each cycle of the meta signal may be Fig. 8B by a base delay 202, resulting in the shifted signal form Fig. 8C. In one or more embodiments, the base delay 202 may be generated by the noise analysis unit 120 through one or more logic circuits. In one or more embodiments, the base delay 202 may be applied to the meta-signal of the Fig. 8B can be applied to a rising edge of a clock signal, the clock signal potentially being influenced by the waveform of Fig. 8A. In one or more embodiments, the aforementioned logic circuit may receive power from a power supply. In one or more embodiments, the power from the power supply may vary over time, and the variations may affect the base delay 202 generated by the aforementioned logic circuit. For example, if the power supply transfers less power than an ideal amount to the logic circuit, the delay of a signal through the logic circuit may be greater than an ideal base delay 202, as shown by the long base delay 805. In another example, the power supply may send more power than an ideal amount to the logic circuit, which may result in delay that is less than an ideal base delay 202, as shown by the short base delay 810. An illustrative noise pattern, as shown in Fig. 8C, in which a supply power level may deviate from an ideal level, whereby a fluctuation compared to an ideal base delay 202 may occur during an initial time period in the form of the long base delay 805, and wherein in a time period immediately following the initial time period, the power supply does not return to its ideal level, whereby a further deviation from the ideal base delay 202 occurs, such as the short base delay 810; may represent low-frequency supply noise. Each cycle of a meta-signal included in Fig. 8B may be delayed according to another base delay (202, 805, 810), an illustrative result being shown in Fig. 8C is shown.

[0060] Fig. 8D shows the signal form Fig. 8C according to one or more embodiments, wherein the separately delayed cycles consist of Fig. 8B are combined to produce a single waveform of the Fig. to create 8D. Fig. 8D further shows the values ​​according to one or more embodiments resulting from measurements that the noise analysis unit 120 performs on the waveform of Fig. 8D. The measurements mentioned can be taken in a similar way to the measurements (404 - 418) described in the Fig. 4D - 4F. In the example shown, the waveform measurements of the Fig. 8D on a rising edge of the Fig. 8A. The waveform from Fig. Figure 8A can represent an ideal square wave signal, generated, for example, from a digital clock signal. The resulting illustrative measurements from the Fig. 8D, which can be taken in a similar way to those found in Fig. 5E are shown in tabular form in Table 7 below. TABLE 7(SIGNAL FORM from Fig. 8D) MESSINDEX MESSZEIT GEMESSENE WERTE 1 T15 0000 1111 2 T20 1111 0000 3 T25 0000 1111 4 T30 1100 0000 5 T35 0011 1111 6 T40 1111 1100 7 T45 1111 0011 8 T50 0000 1111

[0061] It can be seen that the measured values ​​of the signal shape taken by the noise analysis unit 120 in Fig. 8D differ from the measurements made by the noise analysis unit 120 on the signal form from Fig. 4C at measurement indices 4, 5, 6, and 7. These differences may, according to one or more embodiments, represent a noise signature that may be used by the noise analysis unit 120 to characterize low-frequency noise of the power supply. Although eight measurements are shown in Table 7 above, any number of measurements may be taken by the noise analysis unit 120. As further noted, according to one or more embodiments, the differences in the measurements between the Fig. 8D and the Fig. 4C can be attributed to the single effect resulting from the low frequency noise of the power supply similar to the single effect resulting from the high frequency noise of the power supply, as described with reference to the Fig. 6B - 6D previously described, in that the power supply noise can affect the values ​​of the generated meta-signal, as shown in the Fig. 8B-8D, but not the timing at which the noise analysis unit 120 takes the meta-signal measurements.

[0062] A summary of measurements taken by the noise analysis unit 120 is shown in Table 8 below, according to one or more embodiments. In one or more embodiments, the measurements from the Fig. 4C a noise-free signal. In one or more embodiments, the measurements may be Fig. 5D represent a signal containing high-frequency clock signal noise, which may also be referred to as high-frequency jitter. In one or more embodiments, the measurements from the Fig. 6D represent a signal containing high-frequency noise from the power supply. In one or more embodiments, the measurements from the Fig. 7D represent a signal that contains low-frequency noise of the clock signal, which may also be referred to as low-frequency jitter. In one or more embodiments, the measurements from Fig. 8D represent a signal containing low-frequency noise from the power supply. Although the measurements made on the waveforms of the Fig. 4D, Fig. 5D, Fig. 6D, Fig. 7D and Fig. 8D, as shown in Table 3, Table 4A and Tables 5-7 above, may begin at different times (for example, the measurements in Table 6 begin at a time T5, and the measurements in Table 7 begin at a time T15), each group of measurements begins at an equivalent noise-free time, as represented by the series of measurements 0 0 0 0 1 1 1 1, and thus the comparisons of each group of measurements at a given measurement index are permissible. It should be noted from the examination of Table 8 below that each column of measurements taken by the noise analysis unit 120 from Fig. 5D, Fig. 6D, Fig. 7D. Fig. 8D can be taken, contain differences compared to what a noise-free signal from Fig. 4C, and also to each of the other columns of measurements.

[0063] In one or more embodiments, the differences in the measurements shown in Table 8 below may represent noise signatures that may be used and / or generated by noise analysis unit 120 to determine the frequency and / or source of noise in a signal. Although eight measurement indices are shown in Table 8, noise analysis unit 120 may use any number of measurement indices and may also take any number of measurements. TABELLE 8 MESSINDEX Fig. 4C (noise-free) Fig. 5D Fig. 6D Fig. 7D Fig. 8D 1 0000 1111 0000 1111 0000 1111 0000 1111 0000 1111 2 1111 0000 1111 0000 1100 0000 1111 0000 1111 0000 3 0000 1111 0000 1111 0011 1111 0000 1111 0000 1111 4 1111 0000 1100 0000 1111 0000 1110 0000 1100 0000 5 0000 1111 0000 0011 0000 1111 0001 1111 0011 1111 6 1111 0000 1111 1100 1111 1100 1111 1000 1111 1100 7 0000 1111 0011 1111 1111 0011 0000 0111 1111 0011 8 1111 0000 1111 0000 0000 1111 1111 0000 0000 1111

[0064] In some embodiments, for the measurements taken by the noise analysis unit 120 on a low frequency clock signal noise, as indicated by the column for Fig. 7D in Table 8 above, it may be possible that they have the same signature as measurements taken by the noise analysis unit 120 for a low frequency noise of the power supply, as indicated by the column for the Fig. 8D in Table 8. In these embodiments, the noise analysis unit 120 may switch between one power supply and a second power supply to determine the source of the noise. In one embodiment, if the noise signature measured by the noise analysis unit 120 is due to low-frequency clock signal noise, the noise signature will not change when the noise analysis unit 120 switches between one power supply and a second power supply. However, in one embodiment, if the noise signature measured by the noise analysis unit 120 is due to low-frequency power supply noise, the noise signature will vary when the noise analysis unit switches between one power supply and a second power supply.

[0065] Fig. 9 shows a block diagram of a noise analysis unit 120 according to one or more embodiments. In one or more embodiments, an input signal 902 is received by a signal generator 905. The signal generator 905 may generate a new signal based on the input signal 902, and the new signal may be a meta-signal containing information related to the input signal 902. In one embodiment, the signal generator 905 may generate a new signal based on the input signal 902 by doubling the period of the input signal 902. In other embodiments, the signal generator 902 may generate a new signal based on the input signal 902 by performing a mathematical operation on the input signal 902. The new signal from the signal generator 905 may then be passed to a basic delay element 912.The basic delay element 912 may delay the signal from the signal generator 905, effectively phase-shifting or time-shifting the signal from the signal generator 905. In one or more embodiments, the amount of delay or time-shifting introduced by the basic delay element 912 may correspond to the aforementioned basic delay 202. In one or more embodiments, the delay introduced by the basic delay element 912 may be variable. In one or more embodiments, the basic delay element 912 may be omitted. The output from the basic delay element 912 may be fed to a series of fine delay elements 450 and a comparator 960. The series of fine delay elements 450 may be constructed from one or more fine delay elements.Each of the fine delay elements in the series of fine delay elements 450 may be independently controllable. In one or more embodiments, the delay provided by each of the fine delay elements 450 in the series may be variable and / or may be different for each delay in the series of fine delay elements. In one or more embodiments, the number of elements used in the series of fine delay elements 450 may be zero.The series of fine delay elements 450 may be generated by one or more inverters, capacitors, inductors, and / or a combination of other circuit elements; may be caused by software, hardware, or a combination thereof; may be generated as a result of a program acting on a recorded or transmitted signal; and / or may be caused as a result of a processor configured to generate such delays.

[0066] Fig. 9 further illustrates, according to one or more embodiments, the output from the base delay element 912 being fed to a fine delay element 904. In one or more embodiments, the fine delay element 904 imposes a fine delay or temporal shift on the output received from the base delay element 912. In one or more embodiments, the amount of delay or temporal shift imparted by the fine delay element 904 may correspond to the aforementioned fine delay 204. The output from the fine delay element 904 may then be split and sent to both a fine delay element 930 and the comparator 960. The fine delay element 930 may impose a further delay or temporal shift on the output received from the fine delay element 904.The output from fine delay element 930 may then be split and sent to a fine delay element 935 and the comparator 960. The fine delay element 935 may then impose a further delay on the output received from the fine delay element 930. The output from the fine delay element 935 may then be split and sent to further fine delay elements and the comparator 960. Any number of fine delay elements may be provided between the fine delay element 935 and a fine delay element 950, with each fine delay element receiving an input from the preceding fine delay element and sending the output to the subsequent fine delay element and the comparator 960.The fine delay element 950 may receive an input from the second-to-last fine delay element in the series of fine delay elements, may induce a further delay, and then send the signal to the comparator 960. The comparator 960 may receive a non-delayed input signal 902, the output from the basic delay element 912, and the output from the fine delay elements 450. In one or more embodiments, the input signal 902 is a square wave signal representative of a digital clock signal. The comparator 960 may take measurements on the output from the basic delay element 912, the fine delay elements 450, and / or from the input signal 902, and / or perform other operations on the output signal from the fine delay elements 450 and / or the input signal 902.The comparator 960 may be configured to determine unique characteristics indicative of specific types of noise present or combined in the input signal 902, where such characteristics may form a signature that may then be used to detect specific types of noise. In another embodiment, the input signal and / or the output signal for the series of fine delay elements 450 and / or for the basic delay element 912 may be sampled by an n-bit synchronization unit, with the resulting samples then being received by the comparator 960. In one or more embodiments, the comparator 960 may include a sampling unit 962. The sampling unit 962 may take samples or measurements of the input signal, the meta-signals, and the output signals of the fine delays 450 and / or the basic delay element 912.In one or more embodiments, sampling unit 962 may be an n-bit synchronization unit. In one or more embodiments, comparator 960 may perform operations on the aforementioned samples obtained from an n-bit synchronization unit, according to other examples and embodiments as described herein. Comparator 960 may be configured to detect noise, such as high-frequency noise, low-frequency noise, clock signal jitter, power supply noise, and / or other types of noise. In one or more embodiments, comparator 960, base delay element 912, and series of fine delays 450 may be configured to perform delays, generate meta-signals, and take and compare measurements, as is consistent with methods, devices, and systems previously described in connection with the . Fig. 4A-8D. In one embodiment, the output signal from the base delay 202 and the series of fine delay elements 450 may be fed back into an adjustment controller 910. The adjustment controller 910 may dynamically change the amount of the base delay 202 introduced by the base delay element 912. In one or more embodiments, the adjustment controller 910 may change the amount of the base delay 202 introduced by the base delay element 912 to compensate for any type of high-frequency noise and / or low-frequency noise, as previously described. For example, in a situation where low-frequency noise is present, similar to the Fig. 8C, the adjustment controller 910 may change the long base delay 805 and / or the short base delay 810 to return them to delay values ​​equal to the base delay 202.

[0067] Fig. 10 is a flowchart illustrating one illustrative embodiment of a method for analyzing noise. The flowchart includes operations 1010-1060 arranged according to one illustrative embodiment. Other embodiments may perform two or more operations in parallel. The illustrative process is applicable in software, firmware, and / or hardware implementations.

[0068] Operation 1010 may generate a signal. The generated signal may be analog or digital and may be generated independently of any external signal and / or may be generated based on a signal received from an external source. Operation 1030 may add noise to the signal generated by operation 1010. The noise may be high-frequency noise, low-frequency noise, or a combination thereof. The aforementioned noise may be added unintentionally and / or intentionally in operation 1030. Operation 1040 applies a base delay to the output signal of operation 1030. The amount of delay applied by operation 1040 may be zero or a larger amount of delay. Operation 1050 applies a series of fine delays to the output signal of operation 1040.The number of fine delays applied in operation 1050 may be zero or a greater number of delays. The time durations of the fine delays applied in operation 1050 may be the same or they may be different from each other. Operation 1060 may receive the delayed output signal from operation 1050 and the original signal generated in operation 1010. Operation 1060 may perform a series of comparisons, measurements, or operations on the output signal received from operations 1050 and 1010 to detect and analyze noise signatures indicative of the type of noise added in operation 1030.

[0069] Fig. 11 shows a data processor according to one or more embodiments, which may include the noise analysis unit 120. In one or more embodiments, a clock 1104 may generate a signal that controls the operation of a group of input registers 1110 and a group of output registers 1130. In one example, the input registers 1110 and the output registers 1130 may include storage elements configured to store digital data. In one or more embodiments, the input registers 1110 may be configured to receive data from an external source and / or feed data to a group of logic elements 1120, wherein the aforementioned input / output operations occur based on a signal from the clock 1104.In one or more embodiments, the output registers 1130 may be configured to receive data from the logic elements 1120 and / or output data to an external destination, with the aforementioned input / output operations occurring based on a signal from the clock 1104. In one or more embodiments, the signal generated by the clock 1104 may be a square wave similar to the waveform previously described in . Fig. 4A. In one or more embodiments, the clock 1104 may generate a square wave signal, and the input registers 1110 may be configured to read in or output data on a rising or falling edge of the aforementioned square wave signal. In one or more embodiments, the clock 1104 may generate a square wave signal, and the output registers 1130 may be configured to read in or output data on a rising or falling edge of the aforementioned square wave signal. In one or more embodiments, the input and / or output of the input registers 1110 may be configured to occur on an initial cycle in the signal generated by the clock 1104, and the input and / or output of the output registers 1130 may be configured to occur on a cycle subsequent to the initial cycle.The input registers 1110 and / or the output registers 1130 may repeatedly input and / or output data, with the input and / or output controlled by recurring signals generated by the clock 1104. In one or more embodiments, fluctuations in the signal generated by the clock 1104 may affect the timing of the input and / or output of the input registers 1110 and / or the output registers 1130.

[0070] Fig. 11 further shows, according to one or more embodiments, a power supply 1106 connected to the logic elements 1120. The logic elements 1120 may be configured to receive data from the input register 1110, process the received data, and output the results of the data processing to the output registers 1130. The power supply 1106 may supply power, electrical or other power, to the logic elements 1120, wherein the supplied power is required by the logic elements 1120 to process the received data. In one or more embodiments, the amount of power supplied by the power supply 1106 to the logic elements 1120 may affect the speed of data processing by the logic elements 1120.For example, the power supply 1106 may supply a theoretically ideal power level to the logic elements 1120 so that the logic elements 1120 are capable of processing data at an ideal speed. When the logic elements 1120 are supplied with the aforementioned theoretically ideal power level, in one or more embodiments, they may be configured to complete a group of data processing operations during a time period when the clock 1104 sends a signal to the input registers 1110 to input data to the logic elements 1120, and at a subsequent time when the clock 1104 sends a signal to the output registers 1130, data may be received from the logic elements 1120.In one example, if the power supplied to logic elements 1120 from power supply 1106 is greater than a theoretically ideal level, then logic elements 1120 may perform the aforementioned data processing operations at a rate higher than the ideal rate. In another example, if the power supplied to logic elements 1120 from power supply 1106 is less than a theoretically ideal level, then logic elements 1120 may perform the aforementioned data processing operations at a rate slower than the ideal rate. In either example, if logic elements 1120 operate at a rate higher or slower than the ideal rate, errors may occur in the data output for output registers 1130, and / or the entire data processor may fail. Fig. 11 works slower than it would under ideal conditions.

[0071] Fig. 11 further shows, according to one or more embodiments, a noise analysis unit 120, which may be configured to receive a signal from the clock 1104, the power supply 1106, and / or the logic elements 1120. In one embodiment, the noise analysis unit 120 may generate a second signal based on a first signal received from the clock 1104, the power supply 1106, and / or the logic elements 1120. The aforementioned second signal generated by the noise analysis unit 120 may be a meta-signal of the received first signal, e.g., the second signal is generated to contain information about the first signal in coded form. In one or more embodiments, the noise analysis unit 120 may generate more than one meta-signal. In one embodiment, the first signal received by the noise analysis unit 120 may be a square-wave signal, which characterizes a digital signal.In one embodiment, the second signal, i.e., the meta-signal, generated by the noise analysis unit 120 may have a period that is a multiple of the period of the first signal received in the noise analysis unit 120. The noise analysis unit 120 may further apply a time delay or delays to the meta-signal and / or the first signal received in the noise analysis unit 120 from the clock 1104, the power supply 1106, and / or the logic elements 1120. In one or more embodiments, the noise analysis unit 120 may take measurements on the aforementioned meta-signal and / or the delayed meta-signal; and compare the taken measurements with measurements that would result if the meta-signal were generated by a theoretically ideal signal from the clock 1104, the power supply 1106, and / or the logic elements 1120.

[0072] In one or more embodiments, the noise analysis unit 120 may analyze the aforementioned measurements in comparison to theoretically ideal measurements to determine whether the first signal received by the noise analysis unit 120 and / or the second signal generated by the noise analysis unit 120 contains noise or is free of noise. In one embodiment, if the noise analysis unit 120 determines that noise is present, it may further analyze that noise to determine whether the noise is high-frequency noise and / or low-frequency noise. In one or more embodiments, the noise analysis unit 120 may examine the meta-signal and measurements collected from the meta-signal to detect noise signatures that indicate whether the source of the noise is the clock 1104 and / or power supply 1106.In one embodiment, the signatures may be in a format as previously described in connection with the . Fig. 4A - 8D described above.

[0073] In one or more embodiments, if the noise analysis unit 120 detects high-frequency and / or low-frequency noise that has the clock 1104 and / or the power supply 1106 as its source, the noise analysis unit 120 may feed a signal back to the clock 1104, the power supply 1106, and / or the logic elements 1120 to perform correction or compensation for the detected noise. For example, if the noise analysis unit 120 detects noise with the clock 1104 as its source, the noise analysis unit 120 may send a signal to reset the clock 1104. In another example, if the noise analysis unit 120 determines that noise is present with the power supply 1106 as a source, then the noise analysis unit 120 may send a signal to the power supply 1106 to increase or decrease the supply voltage of the power supply 1106.Alternatively, in another example, if the noise analysis unit 120 determines that any source of noise is causing the logic elements 1120 to complete data processing too quickly, such that the data in the output registers 1130 may be recorded with error, then the noise analysis unit 120 may send a signal to the logic elements 1120 to delay the output to the output registers 1130 by an appropriate amount of time.

[0074] Fig.12 illustrates a process flow diagram detailing the operations of a process for noise analysis, according to one or more embodiments. In one or more embodiments, operation 1210 may include the noise analysis unit 120 receiving a first signal. In one or more embodiments, operation 1220 may include the noise analysis unit generating a second signal based on the first signal. In one or more embodiments, operation 1230 may include time-shifting the second signal by a base delay time using a base delay.In one or more embodiments, operation 1240 may include comparing, by a comparator, an actual measurement of the time-shifted second signal with a theoretical measurement of a third theoretical signal, where the third theoretical signal is a version of the second signal that would be generated from the first signal if the first signal had no high-frequency noise and no low-frequency noise.

[0075] Although the present embodiments are described with reference to specific illustrative embodiments, it will be appreciated that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the various embodiments. For example, the various devices and modules described herein may be enabled and implemented by hardware circuitry (e.g., CMOS-based logic circuitry), firmware, software, or a combination of hardware, firmware, and software (e.g., embodied in a non-transitory machine-readable medium). For example, the various electrical structures and methods may be implemented by transistors, logic gates, and electrical circuitry (e.g., an application-specific integrated circuit (ASIC) and / or a digital signal processor (DSP) circuit).

[0076] It should also be understood that the various operations, processes, and methods disclosed herein may be embodied in a non-transitory machine-readable medium and / or a machine-accessible medium compatible with a data processing system (e.g., a computer system) and / or may be performed in any order. Therefore, the description and drawings are to be considered in an illustrative and not a limiting sense.

[0077] A number of embodiments have been described. Nevertheless, it should be understood that various modifications may be made without departing from the spirit and scope of the claimed invention. Furthermore, the logical processes depicted in the figures do not require the particular order or sequential sequence shown to achieve desired results. Furthermore, other steps may be provided, or steps may be omitted from the described processes, and other components may be added or removed from the described systems. Accordingly, other embodiments are also within the scope of the following claims.

[0078] The structures and modules in the figures are shown as separate units and are shown as connecting only to some specific structures and not to others. The structures may be connected to each other, may perform overlapping functions, and may also be connected to other structures not shown connected in the figures. Therefore, the description and / or drawings should be considered illustrative rather than limiting.

Claims

[1] A procedure with: Receiving a first signal by a noise analysis unit (120); generating a second signal based on the first signal by the noise analysis unit (120); temporally shifting the second signal by a base delay time of a base delay element (912) to generate a further signal; and temporally shifting the further signal within a period of the first signal by a plurality of fine delay elements (450) arranged in series with the basic delay element (912) to generate delayed versions of the further signal; measuring the delayed versions of the further signal with the first signal to generate measured values ​​of the delayed versions of the further signal for each period of the first signal; Determining one or more noise characteristics by comparing, by means of a comparator (960), each of the measured values ​​with respective values ​​of an ideal signal, wherein the ideal signal is a version of the further signal that would be generated from a first signal if the first signal were free of high-frequency noise and low-frequency noise; and Generating a noise signature based on the one or more noise characteristics. [2] The method of claim 1, wherein the first signal is a periodic signal, the second signal is a second periodic signal, and the second signal has a period that is a multiple of the period of the first signal. [3] The method according to any one of claims 1-2, wherein the first signal comprises a periodic square wave of a digital clock signal and wherein the second signal comprises a square wave generated by the noise analysis unit, the second signal having a period that is a multiple of the period of the first periodic square wave. [4] The method of claim 3, wherein the base delay time is equal to the period of the first signal. [5] The method according to any one of claims 1-4, wherein the first signal comprises a low frequency noise and / or a high frequency noise. [6] A noise analysis system with: a signal generator (905) configured to receive a first signal and generate a second signal based on the first signal; a base delay element (912) configured to temporally shift the second signal by a first time delay to generate a further signal; a plurality of fine delay elements (450) arranged in series with the base delay element (912) and configured to time-shift the further signal within the period of the first signal to generate delayed versions of the further signal; a sampling unit configured to measure the delayed versions of the further signal with the first signal to generate measured values ​​of the delayed versions of the further signal for each period of the first signal; and a comparator (960) configured to generate one or more noise characteristics, to compare each of the measured values ​​with the respective values ​​of an ideal signal, wherein the ideal signal is a version of the further signal that would be generated from the first signal if the first signal did not have any high-frequency noise and any low-frequency noise, and to generate a noise signature based on the one or more noise characteristics. [7] The noise analysis system of claim 6, wherein the first signal is a periodic signal, wherein the second signal is a second periodic signal, and wherein the second signal has a period that is a multiple of the period of the first signal. [8] The noise analysis system according to any one of claims 6-7, wherein the first signal comprises a periodic square wave of a digital clock signal and wherein the second signal comprises a square wave generated by the signal generator, the second signal having a period that is a multiple of the period of the first periodic square wave. [9] The noise analysis system of claim 8, wherein the first time delay is equal to the period of the first signal. [10] The noise analysis system according to any one of claims 6-9, wherein the first signal comprises a low frequency noise and / or a high frequency noise.

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