Electronic component and method for manufacturing an electronic component

Abstract

Semiconductor component that includes: an electrically conductive carrier (10); a semiconductor chip (30) arranged above the carrier (10); and a porous diffusion slot layer (22, 122) arranged between the support (10) and the semiconductor chip (30), wherein the porous diffusion slot layer (22, 122) comprises particles with an intermetallic phase.

Description

[0001] The present invention relates to the technique of bonding a semiconductor chip to a substrate and in particular to the technique of diffusion soldering.

[0002] Semiconductor manufacturers constantly strive to improve the performance of their products while reducing manufacturing costs. One cost-intensive aspect of semiconductor manufacturing is the encapsulation of the semiconductor chips. As experts know, integrated circuits are fabricated on wafers, which are then separated to create semiconductor chips. These chips can then be mounted onto electrically conductive substrates. Mounting semiconductor chips on these substrates is desirable to provide low-stress, mechanically stable, and thermally and electrically conductive bonding junctions at high yields and low costs.

[0003] US 6 340 113 B1 discloses a two-component solder compound wherein the particles contained therein form a porous metallic foam when heated.

[0004] US 6 166 334 A describes semiconductor devices with cylindrical porous solder mounds, which consist of a first low-density material and a second material surrounding it.

[0005] In US 2002 / 0 158 110 A1, a connection structure for electronic components is shown, which includes solder balls, a porous shell surrounding the solder balls, and structures in the porous shell that regulate the volume of the solder balls during the melting process.

[0006] US 7 214 962 B2 describes a solder joint between a semiconductor device and a substrate, in which the solder material consists of a B-step material filled with metal particles.

[0007] One of the problems underlying the invention can therefore be seen as creating a semiconductor device with good thermal, electrical, and mechanical bonding of a chip to a substrate. Furthermore, a method for bonding a semiconductor chip to a substrate is to be specified, by which good thermal, electrical, and mechanical bonding of the chip to the substrate is achieved.

[0008] The problem addressed by the invention is solved by the features of the independent claims. Further developments and embodiments are the subject of the dependent claims.

[0009] The accompanying drawings are intended to provide a more detailed understanding of the embodiments. The drawings illustrate embodiments and, together with the description, serve to explain the principles of these embodiments. Other embodiments and many of the intended advantages of embodiments will become readily apparent when they are better understood by reference to the following description. Identical reference numerals denote identical or corresponding parts.

[0010] It should be noted that the various elements and structures shown in the figures are not necessarily drawn to scale. Features and / or elements are depicted with specific dimensions relative to each other primarily for the sake of clarity and ease of understanding; consequently, relative dimensions in actual implementations may differ significantly from those shown herein. The Fig. Figures 1A-1E schematically show cross-sectional views of an embodiment of a method for bonding a semiconductor chip to an electrically conductive substrate; the Fig. Figures 2A-2D schematically show cross-sectional views of an embodiment of a method for bonding a semiconductor chip to an electrically conductive substrate; the Fig. Figures 3A-3D schematically show cross-sectional views of an embodiment of a method for bonding a semiconductor chip to an electrically conductive substrate; the Fig. Figures 4A-4D schematically show cross-sectional views of an embodiment of a method for providing a semiconductor chip with a porous diffusion solder bond layer; the Fig. Images 5A-5C are cross-sectional electron microscope images of a porous diffusion solder layer at increasing magnification; and the Fig. Figures 6A-6D schematically show cross-sectional views of an embodiment of a method for providing a semiconductor chip with a porous bonding layer.

[0011] The following description refers to the accompanying drawings, which illustrate specific embodiments of the invention. In this respect, directional terminology such as "top," "bottom," "front," "back," "front," "rear," etc., is used with reference to the orientation of the described figure(s). Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. It is understood that other embodiments can be used and structural or logical modifications can be made without departing from the concept of the present invention. Therefore, the following detailed description is not to be understood as limiting.

[0012] It is understood that the features of the various embodiments described herein can be combined with one another, unless specifically stated otherwise.

[0013] As used in this patent specification, the terms “coupled” and / or “electrically coupled” are not intended to imply that the elements must be directly coupled to one another; intermediate elements may be provided between the “coupled” or “electrically coupled” elements.

[0014] Components containing semiconductor chips are described below. In particular, semiconductor chips with a vertical structure can be used, meaning that the semiconductor chips can be manufactured in such a way that electric current can flow in a direction perpendicular to the main surfaces of the semiconductor chips. A semiconductor chip with a vertical structure has electrodes on its two main surfaces, that is, on its top and bottom surfaces.

[0015] In particular, power semiconductor chips can be used. Power semiconductor chips can have a vertical structure. These vertical power semiconductor chips can be configured, for example, as power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Gate Field Effect Transistors), power bipolar transistors, or power diodes. For instance, the source and gate electrodes of a power MOSFET can be located on one main surface, while the drain electrode of the power MOSFET is located on the other main surface. The semiconductor chips do not need to be made of a specific semiconductor material, such as Si, SiC, SiGe, or GaAs, and can also contain inorganic and / or organic materials that are not semiconductors.Semiconductor chips can be of different types and can be manufactured using various technologies.

[0016] The semiconductor chips can have contact pads (or electrodes) that allow electrical contact with the integrated circuits contained within the semiconductor chips. The contact pads can contain one or more metal layers deposited onto the semiconductor material of the semiconductor chips. The metal layers can be manufactured with any desired geometric shape and material composition. For example, the metal layers can be in the form of a layer covering an area. Any metal capable of forming a diffusion solder bond, such as Cu, NiP, NiSn, Au, Ag, Pt, Pd, and an alloy of one or more of these metals, can be used as the material.The metal layers do not need to be homogeneous or made from only one material; that is, different compositions and concentrations of the materials contained in the metal layers are possible.

[0017] A porous diffusion solder layer can be used to electrically and mechanically connect the semiconductor chip to a substrate. The electrically conductive porous diffusion solder layer can provide low-stress, mechanically stable, and thermally and electrically highly conductive bonding points.

[0018] In particular, the stress (mechanical stress) σ transmitted through the porous diffusion layer is proportional to ρ -2, where ρ is the pore density in the porous diffusion slot layer. This means that increasing (e.g., doubling) the pore density in the porous diffusion slot layer significantly reduces the stress (mechanical strain) between the semiconductor chip and the electrically conductive substrate (e.g., by a factor of 2). 2 = 4). Stress reduction is advantageous to increase the production yield and lifetime of the package and to prevent failure during operation.

[0019] The porous diffusion solder layer can comprise metal particles with a mean diameter in the range of 0.1 to 30 µm, particularly between 1 and 10 µm. Most or almost all of these particles contain an intermetallic phase. Because of the presence of an intermetallic phase within the particles, the porous solder layer is referred to as a porous diffusion solder layer.

[0020] The intermetallic phase consists of a first metal component, a second metal component, and optionally a third or additional metal components. The first metal component can comprise or consist of at least one or more of Ag, Cu, Au, and In. The second metal component can comprise or consist of at least one or more of Sn and Zn.

[0021] The porous diffusion-seal layer can comprise a chemical composition of 25% to 50% by weight of the second metal component. Specifically, the porous diffusion-seal layer can comprise a chemical composition of 50% to 75% by weight of the first metal component, 25% to 50% of the second metal component, and optionally one or more residual metal components. This composition is the composition of the intermetallic phase provided in most or nearly all of the particles that form the porous diffusion-seal layer.

[0022] Most or nearly all of the particles forming the porous diffusion patch layer can be sintered. Thus, the porous diffusion patch layer can have a sintered or interdiffused structure. The particle sintering process and the formation of the intermetallic phase within the particles can be carried out simultaneously by applying heat and pressure to a preliminary layer from which the porous diffusion patch layer is produced. During the application of heat and pressure, the particles in the preliminary layer can coalesce, diffusion can occur at the transition regions between adjacent particles and within the particles to exchange and distribute the primary and secondary metal components between and within the particles, and the particles can sinter.

[0023] The temperature applied for sintering and the formation of the intermetallic phase can be significantly lower than the melting point of the metal of the second component (if provided in macroscopic dimensions). For example, temperatures in the range of 100°C to 200°C, 100°C to 180°C, or 100°C to 150°C can be applied or used.

[0024] The pressure applied for sintering and the formation of the intermetallic phase can be selected based on the applied temperature, the desired porosity, the desired electrical conductivity, the layer thickness, the average particle size, etc. For example, pressures in the range of 3 to 40 MPa or 5 to 20 MPa can be applied. In some embodiments, a pressure of approximately 10 MPa was used.

[0025] Characteristic properties of the porosity of the porous diffusion layer, such as the pore density and / or the mean particle size, can largely be controlled by the temperature and pressure applied during the formation of the intermetallic phase (and, for example, during sintering). Furthermore, such characteristic properties can be achieved by selecting the particle size of the applied particles before the application of temperature and / or pressure. For example, mean particle sizes in the first and second metal components in the range of 0.5 to 30 µm, particularly between 2 and 10 µm, can be used in the preliminary layer.

[0026] The porous diffusion seal layer can have a thickness in the range of 1 µm to 50 µm, particularly 1 µm to 20 µm, and especially 1 µm to 5 µm. The smaller the thickness, the better the electrical and thermal conductivity of the porous diffusion seal layer.

[0027] The Fig. Figures 1A-1E schematically show a method for mounting a semiconductor chip on an electrically conductive substrate according to the disclosure. Fig. Figure 1A schematically shows an electrically conductive support 10. The electrically conductive support 10 can be, for example, a die pad of a leadframe, a PCB (printed circuit board), a DCB substrate (direct copper bonded substrate), which is a ceramic substrate with copper layers on its top and bottom surfaces, etc. The electrically conductive support 10 can be made of any desired metal or can have a surface 11 of this metal capable of forming a diffusion solder bond, for example, Cu, NiP, Sn, Au, Ag, Pt, Pd, etc., or any alloy of one or more of these metals. Furthermore, as will be explained in more detail below, the top surface 11 of the electrically conductive support 10 can be covered with a coating having a low melting point.The coating may, for example, contain or be made from Sn, Zn, or an alloy of one or more of these materials.

[0028] In Fig. 1B A solder paste layer 21 is formed over the upper surface 11 of the support 10. The solder paste layer 21 can be formed by applying a paste containing metal particles dispersed in a polymer material. The paste can be liquid, viscous, or waxy. The paste can comprise metal particles of a first metal component, a second metal component, and optionally, further metal components. The first metal component can comprise at least one or more of Ag, Cu, Au, and In. The second metal component can comprise at least one or more of Sn and Zn. The polymer material can be, for example, a resin such as a B-grade resin, α-terpineol, etc. The polymer material can be unfilled, i.e., it can be free of filler particles.

[0029] Pastes containing metal particles can be obtained, for example, from companies such as Coocson Electronic, Advanced Nano-Particles (ANP), Harima Chemicals, or NBE Technologies. The size (mean diameter) of the metal particles can be less than 30 µm, 10 µm, 5 µm, or, in particular, less than 1.0 µm or 0.5 µm. The size (mean diameter) of the metal particles can also be greater than 0.1 µm, 0.5 µm, 1.0 µm, or, in particular, greater than 2 µm or 5 µm.

[0030] For example, the metal particle-containing paste can be produced by mixing two or more commercially available pastes, each containing particles of one or more of the metals mentioned above. If, for example, a porous diffusion seal layer containing metal particles with an intermetallic Ag3Sn phase is to be produced, three parts of a first paste containing the metal (Ag) of the first metal component are mixed with one part of the paste containing the metal (Sn) of the second metal component.

[0031] The application of the solder paste layer 21, which contains the (e.g., various) metal particles dispersed in the liquid, viscous, or waxy polymer or combinations thereof, can be carried out by printing technologies such as stencil printing, screen printing, inkjet printing, etc. Other techniques for applying the paste, such as film peeling or dispensing techniques, are also feasible. All these techniques equally allow the application of a controllable amount of paste material to the upper surface 11 of the electrically conductive substrate 10.

[0032] The thickness of the solder paste layer 21 can be essentially uniform. Otherwise, leveling techniques can be used to provide a uniform (constant) solder paste layer thickness. Leveling techniques may be suitable, particularly if dispensing techniques are used to apply the solder paste layer 21.

[0033] Optionally, the carrier can be 10, as exemplified in Fig. Figure 1B shows a lower surface 12 which is electrically conductive. A solder paste layer 21 can also be applied to the lower surface 12. For the composition of the solder paste layer 21 and the techniques and methods for applying the solder paste layer 21 to the lower surface 12, reference is made to the description above to avoid repetition.

[0034] As mentioned above, the polymer material can, for example, be a B-stage polymer. Here, curable B-stage polymers are understood to be polymers that can generally be cured in two stages, referred to as the pre-curing stage and the (final) curing stage. Such polymers are generally flowable after deposition, for example, on a substrate surface (such as surface 11 or 12 of the substrate 10), and / or flowable during pre-curing. Pre-curing can transform the B-stage polymer into a solid state, causing the solder paste layer 21 to adhere to the electrically conductive substrate 10. During and after final curing, when the crosslinking of the polymer material is generally complete, the material is no longer flowable.

[0035] A thermosetting B-step polymer can comprise one or more different materials, including, for example, polymers of the α-terpineol type, cyanoacrylates, polyimides, polyimide polymers, etc. The polymer can include an adhesive. For example, the adhesive can be an epoxy adhesive in the form of a B-step resin, an acrylic or cyanoacrylate adhesive in the form of a B-step resin, a thermosetting polymer with an epoxy resin and a polyamine hardener, etc.

[0036] According to Fig. In 1C, the curable B-stage polymer in the solder paste layer can be pre-cured by the application of, for example, heat, UV radiation, gamma radiation, or other techniques. According to various embodiments, pre-curing can be achieved, for example, by applying heat at an initial temperature Tc. For instance, Tc can be less than or equal to approximately 100°C. The polymer material can also be a solvent or a liquid that can evaporate during pre-curing.

[0037] Pre-cured solder paste layers are designated with reference numeral 21a. If no B-grade polymer material is used, the reference numeral 21a is omitted. Fig. The process shown in 1C and the reference numeral 21a refers to a solder paste layer that is identical to the solder paste layer 21.

[0038] According to Fig. In step 1D, a semiconductor chip 30 is placed on the pre-cured solder paste layer 21a (or on the solder paste layer 21 if no B-stage polymer material is used). For example, the semiconductor chip 30 may have a chip electrode (not shown) on a lower surface 32 of the semiconductor chip 30. Optionally, the chip electrode on the lower surface 32 of the semiconductor chip 30 may be covered by an intermediate layer 40 consisting of one or more materials of the first metal component (e.g., Ag, Cu, Au, In) and / or of one or more materials of the second metal component (e.g., Sn, Zn). For example, the intermediate layer 40 may comprise or consist of Ag, or of Ag-coated Sn, etc. The intermediate layer 40 may be arranged abutting the pre-cured solder paste layer 21a (or solder paste layer 21).

[0039] The semiconductor chip 30 can further comprise one or more chip electrodes on an upper surface 31 of the semiconductor chip 30. As described above, the semiconductor chip 30 can be a vertical semiconductor element and / or a power device. For example, a source electrode and gate electrode of a power MOSFET can be located on the upper surface 31, while the drain electrode of the power MOSFET can be located on the lower main surface 32.

[0040] Fig. Figure 1E schematically shows that the pre-cured solder paste layer 21a (or the solder paste layer 21 if no pre-curing is performed) is heated to a temperature Ts in order to firmly attach the semiconductor chip 30 to the electrically conductive substrate 10. For example, heat can be applied by a heating plate on which the electrically conductive substrate 10 and the semiconductor chip 30 are placed.

[0041] Unless otherwise specified, the term solder paste layer 21 hereafter includes both a non-precured solder paste layer 21 and a precured solder paste layer 21a. During the application of heat, the solder paste layer 21 undergoes a diffusion soldering process. In particular, the metal material of the second component does not melt because the temperature Ts is kept below the melting point of the second metal component. For example, sn has a melting point of 232°C. The solder paste layer 21 is exposed to a maximum temperature Ts that is below 232°C. For example, the maximum temperature acting on the solder paste layer may be below 220°C, 200°C, 180°C, or 150°C.

[0042] At the applied temperature Ts, even the particles of the first metal component (e.g., Ag, Cu, Au, In) cannot melt. Therefore, the grain-like particle structure of the solder paste layer 21 is degraded during the application of heat. Fig. 1E essentially maintained.

[0043] An external pressure P can be exerted during the application of heat. For example, the external pressure can be in the range of 3 to 40 MPa, particularly 5 to 20 MPa. Even if no external pressure P is exerted, the grain-like, particle-like structure of the solder paste layer 21 is maintained. However, the exertion of pressure can increase the density, porosity, or the internal contact area between particles of the Fig. 1E form porous diffusion layer influence.

[0044] The intermetallic phase forms when exposed to heat and, for example, pressure. Increasing the temperature and pressure promotes or accelerates the formation of the intermetallic phase. The higher the temperature, the greater the diffusion dynamics within and between adjacent particles. The higher the pressure, the more intense the contact between adjacent particles, which also promotes the formation of the metallic phase, particularly at the boundaries between adjacent particles (of different metals).

[0045] Simultaneously with the formation of an intermetallic phase, the solder paste layer 21 is sintered. Sintering can also occur between particles of the same metal. Both sintering and the formation of the intermetallic phase result in the solder paste layer acquiring high electrical and thermal conductivity and advanced mechanical properties. In particular, the porous diffusion solder layer ensures a mechanically secure, strong, and durable bond between the semiconductor chip 30 and the electrically conductive substrate 10, while allowing for low-stress (i.e., low-voltage) bonding between the semiconductor chip 30 and the electrically conductive substrate 10. Thus, low-stress, mechanically stable, and thermally and electrically highly conductive bond joints can be obtained at high yields and low costs.

[0046] With further reference to Fig. It should be noted that the application of heat can also cause the polymer material to evaporate from the porous diffusion layer 22. In particular, depending on the polymer material used (e.g., in the case of a B-stage material), the polymer material can be largely or almost completely removed from the porous diffusion layer 22 during the application of heat. As is known in sintering technology, the polymer material can act as an organic burnout material, which can have an effect on the structure (e.g., porosity, mean pore volume, pore density) of the porous diffusion layer 22. The porous diffusion layer 22 can thus consist of sintered particles comprising an intermetallic phase of a first metal component, a second metal component, and optionally further metal components, and of cavities formed in the spaces between the sintered metal particles.

[0047] The Fig. Figures 2A-2D exemplify stages of a process for attaching a semiconductor chip 30 to an electrically conductive substrate 10. In conjunction with Fig. Aspects of the process described in 2A-2D can be combined with the processes described herein in conjunction with other figures, and vice versa.

[0048] In Fig. 2A provides an electrically conductive carrier 10. Refer to the corresponding description. Fig. Reference is made to 1A.

[0049] In Fig. In 2B, a solder paste layer 21 is deposited on an upper surface 11 of the electrically conductive substrate 10. In contrast to the one in Fig. In the example shown in Figure 1B, the solder paste layer 21 is structured. This means that, either during deposition or with the help of subsequent processing such as masking, etching, etc., the solder paste layer 21 can be designed to have a specific desired lateral shape and extent. For example, the solder paste layer 21 can be structured in Fig. 2B have the form of a contact patch, i.e., a flat contact layer, or an elongated conductor. The solder paste layer 21 may be deposited only on the upper surface 11 of the electrically conductive support 10. That is, the lower surface 12 of the electrically conductive support 10 may, in contrast, Fig. 1B remain exposed. Of course, in all embodiments, an arbitrary number of surfaces of the electrically conductive carrier 10 can be covered by a solder paste layer 21.

[0050] In Fig. In step 2C, the semiconductor chip 30 is placed on the structured solder paste layer 21. As previously described, the semiconductor chip 30 may or may not be equipped with an intermediate layer 40 arranged between the solder paste layer 21 and a lower electrode of the semiconductor chip 30 (not shown). It is also possible for the intermediate layer 40 to be deposited on the upper surface of the solder paste layer 21, and for the semiconductor chip 30 to be placed on the previously deposited intermediate layer 40. Furthermore, the intermediate layer 40 may be a sintered layer. Regarding the materials from which the intermediate layer 40 can be formed, reference is made to the disclosure above.

[0051] Continue to Fig. 2C the solder paste layer 21 can be a pre-cured solder paste layer 21a, as previously described with reference to Fig. 1C and Fig. Described in 1D.

[0052] According to Fig. In 2D, the semiconductor chip 30 is fixed to the electrically conductive substrate 10 by the application of heat T and, for example, pressure P. During this process, the porous diffusion solder layer 22 is formed. The structure, composition, thickness, and all other properties of the porous diffusion solder layer 22 are described in Fig. The 2D representations may be identical to the corresponding properties outlined above.

[0053] The Fig. 3A-3D, exemplify stages of a process for attaching a semiconductor chip 30 to an electrically conductive substrate 10. In conjunction with Fig. Aspects of the process described in 1A-1E and 2A-2D can be combined with processes described below, and vice versa.

[0054] In Fig. 3A provides an electrically conductive carrier 10. Refer to the corresponding description. Fig. 1A and Fig. Reference is made to 2A.

[0055] In Fig. 3B is an upper surface 11 of the electrically conductive substrate 10 covered by a coating layer 50. The coating layer 50 can comprise or consist of metals with a low melting point, such as sn or zn. The coating layer 50 can further comprise a thin (e.g., approximately 10–200 nm, e.g., approximately 100 nm) corrosion protection layer, which comprises or consists of a noble metal, such as ag, au, pd, etc. The corrosion protection layer prevents the oxidation of the underlying low-melting-point metal of the coating layer 50.

[0056] For example, how in Fig. As shown in Figure 3B, the lower surface 12 of the electrically conductive carrier 10 is also covered by a coating layer 50.

[0057] In Fig. In step 3C, the semiconductor chip 30 is placed on the electrically conductive substrate 10. As previously described, the semiconductor chip 30 can have an upper surface 31 and a lower surface 32. Each of these surfaces 31, 32 can contain one or more chip electrodes (not shown). Fig. 3C covers a solder paste layer 121 on an electrode on the lower surface 32 of the semiconductor chip 30. The solder paste layer 121 can be identical in all properties to the solder paste layer 21 or pre-cured solder paste layers 21a. In the latter case, a pre-curing temperature process, as in connection with Fig. 1C described, can be carried out. An example of manufacturing the semiconductor chip 30 with the solder paste layer 121 is described further below in connection with Fig. 4C described.

[0058] In Fig. In 3D, the semiconductor chip 30 is attached to the electrically conductive substrate 10 by the application of heat (temperature Ts at the solder paste layer 121) and pressure P. In this way, as explained above, the solder paste layer 121 (or pre-cured solder paste layer 121a) is transformed into the porous diffusion solder layer 122. The porous diffusion solder layer 122 can be identical in all properties to the porous diffusion solder layer 22; therefore, reference is made to the corresponding disclosure herein to avoid repetition.

[0059] As exemplified in the Fig. In 3B-3D representation, the lower surface 12 of the carrier 10 can optionally be covered by a coating layer 50. In this case, similar to the one in connection with Fig. In the exemplary process described in 1A-1E, a semiconductor chip 30 is also fixed (e.g. simultaneously) to the lower surface 12 of the electrically conductive carrier 10.

[0060] The Fig. Figures 4A-4D exemplify stages of a process for providing a semiconductor chip 30 equipped with a solder paste layer 121 (including a pre-cured solder paste layer 121a), as shown in Fig. 3C of the process described above is used.

[0061] In Fig. 4A provides a semiconductor wafer 200. The semiconductor wafer 200 may contain integrated circuits formed in previous semiconductor wafer processing steps. Furthermore, chip electrodes associated with the respective integrated circuits were also produced in previous wafer processing steps and can be located on the lower main surface and optionally also on the upper main surface of the semiconductor wafer 200.

[0062] In Fig. 4B A solder paste layer 221 is deposited on the lower main surface of the semiconductor wafer 200. The solder paste layer 221 and the techniques for applying the solder paste layer 221 to the wafer 200 can be identical to those disclosed above. Other layer formation and processing techniques known in wafer technology, such as spin coating, sputtering, chemical and / or mechanical polishing (CMP), can also be used. In particular, the solder paste layer 221 can have the same composition and thickness and can optionally (not shown) be applied in the same manner as described above. Fig. 1A-1E and 2A-2E are explained in a structured manner.

[0063] In Fig. 4C can be similar to Fig. 1C The solder paste layer 221 is pre-cured to produce a pre-cured solder paste layer 221a. Pre-curing can be used, for example, if the solder paste layer 221 contains a B-grade polymer material. Pre-curing takes place at a temperature Tc. For example, Tc is less than 100°C or approximately 100°C. All in connection with Fig. The process steps described in 4A-4C can be performed at the wafer level.

[0064] As in Fig. As shown in Figure 4D, the semiconductor chips 30 are then separated from each other by disassembling the semiconductor wafer 200 and possibly the solder paste layer 221 (or the pre-cured solder paste layer 221a). Sawing, cutting, etching, or laser beam cutting can be used as examples for the separation step. Of course, disassembling the solder paste layer 221 (or the pre-cured solder paste layer 221a) may not be necessary if the solder paste layer 221 has been structured before disassembly. Fig. Figure 4D shows a number of individual semiconductor chips 30 equipped with a pre-cured solder paste layer 121a, as used in the process of Fig. 3C can be used.

[0065] Of course, the pre-curing of the solder paste layer 221, as in Fig. 4C shown, omitted or can be carried out after the semiconductor wafer 200 has been cut into individual semiconductor chips 30. In particular, the steps shown in Fig. The processes shown in 4B-4C can also be carried out after the decomposition step. The one in Fig. The process shown in 4A-4D can also be used for semiconductor chips 30 coated with a non-pre-cured solder paste layer 121.

[0066] The Fig. Figures 5A-5C show scanning electron microscope (SEM) images showing the structure of the porous diffusion solder layer 22, 122 at different magnifications.

[0067] Fig. Figure 5A shows a SEM image of a porous diffusion solder layer 22, 122 provided between a leadframe 10 and a semiconductor chip 30. Also visible are a leadframe plating corresponding to the coating layer 50 and a chip backside metallization 70 corresponding to a chip electrode. In this example, the porous diffusion solder layer 22, 122 has a composition of 50 wt% Ag and 50 wt% Sn. The process parameters Ts = 150°C and P = 10 MPa were used.

[0068] As from Fig. As can be seen in Figure 5A, the porous diffusion-seal layer 22, 122 can be quite inhomogeneous on a macroscopic scale. In particular, large voids on the order of dozens of micrometers (i.e., on the order of the layer thickness) are visible.

[0069] Fig. 5B is a SEM image showing a partial view of Fig. Figure 5A shows this at higher magnification. As is evident, the porous diffusion slot layer 22, 122 exhibits microscopic porosity over at least a significant portion of the diffusion slot layer 22, 122.

[0070] Fig. 5C is a magnification of a section of Fig. 5B. As in Fig. As can be seen in SEM 5C, a microscopic porous structure formed by sintered particles is provided in the porous diffusion-seal layer 22, 122. As the image shows, the porous structure is formed by sintered particles and cavities. The particles are at least partially in contact with each other. Investigations have verified the formation of intermetallic phases within the particles. Here, the SEM image illustrates, for example, that the porous structure includes some particles of an intermetallic Ag3Sn phase. Of course, the structure and composition of the porous diffusion-seal layer may not be completely homogeneous across the entire thickness of the layer. Regions of the porous diffusion-seal layer may be denser / less porous than other regions, and there may also be highly compressed regions with virtually no or very low porosity.Even in the case of a somewhat inhomogeneous distribution of porosity in the layer, the mechanical properties of the layer as a whole are significantly altered by the porous structure.

[0071] The Fig. Figures 6A-6D exemplify stages of a process for mounting a semiconductor chip 30 onto an electrically conductive substrate 10. As in Fig. As shown in 6A, an electrically conductive carrier 10 is provided.

[0072] According to Fig. 6B the electrically conductive carrier 10 can be provided with one or two coating layers 50, as previously described with reference to Fig. 3B described.

[0073] In Fig. In step 6C, a semiconductor chip 30 is placed on the electrically conductive substrate 10. The semiconductor chip 30 is equipped with a porous layer 321. The porous layer 321 can consist, for example, of a porous ceramic material or porous silicon. Porous silicon can be obtained by etching the corresponding surface (e.g., the lower surface 32) of the semiconductor wafer 200 or the semiconductor chip 30.

[0074] In particular, the semiconductor chip 30 with the porous layer 321 can be similar to the one in Fig. The process shown in 4A-4D is used. If the porous layer 321 is a porous silicon layer, the process shown in Fig. The process shown in Figure 4B is converted into the production of this porous silicon layer 321, for example by silicon etching (instead of applying the solder paste layer 221), and the one shown in Fig. The process shown in 4D is converted into the individualization or disassembly of the corresponding semiconductor chips 30 with corresponding sections of the porous silicon layer 321. If the porous layer 321 is a porous ceramic layer, the process shown in Fig. The process shown in 4B is converted into the application of a porous ceramic layer 321 (instead of the solder paste layer 221) on the lower surface of the semiconductor wafer 200, and the in Fig. The process shown in 4D is converted into the disassembly of the individual semiconductor chips 30 equipped with corresponding sections of the porous ceramic layer 321.

[0075] Back to the in Fig.Returning to the process shown in Figures 6A-6D, the semiconductor chip 30 can be attached to the electrically conductive substrate 10 by applying heat (temperature Ts) and pressure P. Here, the low-melting-point material (e.g., solder material) of the coating layer 50 bonds with a chip electrode (not shown) at the base of the porous layer 321, thereby fixing the semiconductor chip 30 to the electrically conductive substrate 10. The porous layer 321 is located between the chip electrode (not shown) and the bulk material of the semiconductor chip 30 and ensures a low-stress and mechanically stable bond between the semiconductor chip 30 and the electrically conductive substrate 10.

[0076] Although a particular feature or aspect of an embodiment of the invention may have been disclosed with respect to only one of several implementations, this feature or aspect may be combined with one or more other features or aspects of the other implementations, as may be desired and advantageous for any given or particular application.

[0077] While specific embodiments have been presented and described here, the person skilled in the art understands that, in view of the specific embodiments shown and described, many modifications can be made, adaptations carried out, and variations implemented without departing from the concept of the present invention.

Claims

[1] Semiconductor device comprising: an electrically conductive carrier (10); a semiconductor chip (30) arranged above the carrier (10); and a porous diffusion slot layer (22, 122) arranged between the support (10) and the semiconductor chip (30), wherein the porous diffusion slot layer (22, 122) comprises particles with an intermetallic phase. [2] Semiconductor device according to claim 1, wherein the particles comprise a first metal component selected from the group consisting of Ag, Cu, Au and In and a second metal component selected from the group consisting of Sn and Zn. [3] Semiconductor device according to claim 1 or 2, wherein the porous diffusion solder layer (22, 122) comprises a chemical composition in weight percent of 50% to 75% of the first metal component and of 25% to 50% of the second metal component. [4] Semiconductor device according to one of the preceding claims, wherein the particles of the porous diffusion solder layer (22, 122) are sintered or interdiffused. [5] Semiconductor device according to any one of the preceding claims, further comprising: a first intermediate layer (50) arranged between the support (10) and the porous diffusion layer (22, 122), wherein the first intermediate layer (50) comprises Sn or Zn. [6] Semiconductor device according to claim 5, wherein the first intermediate layer (50) comprises a surface formed by a corrosion protection layer. [7] Semiconductor device according to one of the preceding claims, wherein the porous diffusion solder layer (22, 122) comprises a thickness in the range of 1 µm to 50 µm. [8] Semiconductor device according to any of the preceding claims, wherein the support (10) is a leadframe. [9] Semiconductor device according to one of the preceding claims, further comprising a second intermediate layer (40) arranged between the porous diffusion solder layer (22, 122) and the semiconductor chip (30), wherein the second intermediate layer (40) comprises a sintered or interdiffused metal layer. [10] Semiconductor arrangement comprising: a semiconductor body (30), and a solder paste layer (21, 121) arranged over at least one major surface of the semiconductor body (30), wherein the solder paste layer (21, 121) comprises first particles of a first metal component selected from the group consisting of Ag, Cu, Au and In, second particles of a second metal component selected from the group consisting of Sn and Zn and a polymer material embedding the first particles and the second particles, wherein the polymer material comprises a B-stage polymer material, and wherein the solder paste layer (21, 121) is configured to form a porous diffusion solder layer (22, 122) comprising particles with an intermetallic phase. [11] Semiconductor arrangement according to claim 10, wherein the B-step polymer material is pre-cured. [12] Semiconductor arrangement according to one of claims 10 and 11, wherein the polymer material acts as an organic burnout material. [13] Semiconductor arrangement according to one of claims 10 to 12, wherein the total metal contribution of the solder paste layer (21, 121) comprises a chemical composition in weight percent of 50% to 75% of the first metal component and of 25% to 50% of the second metal component. [14] Method for bonding a semiconductor chip (30) to an electrically conductive substrate (10), the method comprising: Forming a solder paste layer (21, 121) on the electrically conductive support, 10), wherein the solder paste layer (21, 121) comprises first particles of a first metal component and second particles of a second metal component; Placing the semiconductor chip (30) on the solder paste layer (21, 121); and Heating the solder paste layer (21, 121) so that the solder paste layer (21, 121) is transformed into a porous diffusion solder layer (22, 122) comprising particles with an intermetallic phase. [15] Method according to claim 14, wherein a maximum temperature acting on the solder paste layer (21, 121) during heating is below 220°C. [16] Method according to claim 14 or 15, further comprising: Applying external pressure to the solder paste layer (21, 121) during heating. [17] Method according to claim 16, wherein the external pressure is in a range of 3 to 40 MPa. [18] Method according to any one of claims 14 to 17, wherein the solder paste layer (21, 121) further comprises a polymer material embedding the first particles and the second particles. [19] Method according to any one of claims 14 to 18, wherein the first particles comprise a metal component selected from the group consisting of Ag, Cu, Au and In and the second particles comprise a second metal component selected from the group consisting of Sn and Zn. [20] Method for applying a solder paste layer (221) to a semiconductor chip (30), the method comprising: Applying a solder paste layer (221) comprising first particles of a first metal component selected from the group consisting of Ag, Cu, Au and In, second particles of a second metal component selected from the group consisting of Sn and Zn and a B-stage polymer material, onto a wafer surface, wherein the solder paste layer (221) is configured to form a porous diffusion solder layer (122) comprising particles with an intermetallic phase; Heating the solder paste layer (221) to pre-cure the B-step polymer material; and Separating the wafer (200) into several semiconductor chips (30) . [21] Method according to claim 20, wherein the application of the solder paste layer (221) comprises printing, film peeling, dispensing, spin coating or sputtering. [22] Method according to claim 20 or 21, wherein the total metal contribution of the solder paste layer (221) comprises a chemical composition in weight percent of 50% to 75% of the first metal component and of 25% to 50% of the second metal component.

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