Method for producing a rounded conductor track

Abstract

Method for producing a rounded conductor track (411) of a semiconductor device comprising the steps: Providing a partially completed semiconductor device with a bottom surface (12) and a top surface (11') spaced apart in a vertical direction (v) from the bottom surface (12); Providing an etching agent; Arranging a dielectric layer (2) on the top surface (11'), wherein the dielectric layer (2) - has at least two different areas (21, 22, 23, 24, 25) which, when etched with the etchant, exhibit different etch rates; as well as - a base material which is doped with at least one dopant which has a non-constant concentration profile (c) in the vertical direction (v) with a gradient (dc(v) / dv) of at least 1 wt.% per µm, wherein the dopant influences the etch rate of the doped base material when it is etched with the etchant; Arranging a mask layer (31) having an opening (311) on the dielectric layer (2); Creating a trench (13) in the dielectric layer (2) below the opening (311) by means of an anisotropic plasma etching process and using the mask layer (31) as an etching mask such that the trench (13) - intersects each of the different areas (21, 22, 23, 24, 25); and - extends into a section of the dielectric layer (2) in which the at least one dopant has in the vertical direction (v) both a gradient (c1') of at least 1 wt.% per µm and a gradient (dc(v) / dv) of less than or equal to -1 wt.% per µm; Widening the trench (13) by etching the trench (13) with the etching agent such that at least two of the different areas (21, 22, 23, 24, 25) are etched with different etching rates; Creating the conductor track (411) by filling an electrically conductive material into the widened trench (13).

Description

TECHNICAL AREA

[0001] Embodiments of the invention relate to methods for producing a rounded conductor track of a semiconductor device. BACKGROUND

[0002] Many semiconductor devices are subjected to high voltages between their conductive traces during operation. Since such high voltages can lead to electrical breakdown, there is a need for improvement.

[0003] US Patent 6,960,519 B1 describes a process in which a cylindrical opening is etched into a layer consisting of three successively arranged dielectric sublayers. To create a conductive trace, the opening is then filled with metal. The sublayers are each based on SiO2, with the middle sublayer doped with 6% phosphorus, while the top and bottom sublayers contain 0% phosphorus. To create the opening, an open hard mask layer is produced on the top sublayer. Using this hard mask layer, the top, middle, and bottom sublayers are then etched sequentially, with the etching of the middle and bottom sublayers being isotropic.

[0004] US 2011 / 0156854A1 concerns a coil formed on a chip over a semiconductor substrate and used in an integrated circuit designed for the radio frequency (RF) band.

[0005] US patent 2006 / 0038621A1 discloses a semiconductor device incorporating coils. These coils are used to receive and transmit high-frequency signals in the RF range (GHz band). OVERVIEW OF THE INVENTION

[0006] It has been found that the electric field occurring in the dielectric between the relevant conductor tracks can be reduced by avoiding sharp edges, points, etc., at least in certain areas of at least one of the conductor tracks. Therefore, one aspect of the invention relates to a method for producing a rounded conductor track of a semiconductor device. In this method, a partially completed semiconductor device is provided. The partially completed semiconductor device has a bottom surface and a top surface spaced vertically apart from the bottom surface. An etching agent is also provided. A dielectric layer is arranged on the top surface. The dielectric layer has at least two different regions which, when etched with the etching agent, exhibit different etch rates.The dielectric layer comprises a base material doped with at least one dopant exhibiting a non-constant concentration profile in the vertical direction with a gradient of at least 1 wt.% per µm. The dopant influences the etch rate of the doped base material when etched with the etchant. A mask layer with an opening is produced on the dielectric layer. Subsequently, a trench is formed in the dielectric layer below the opening using the mask layer as an etching mask via an anisotropic plasma etching process. The trench intersects each of the different regions and extends into a section of the dielectric layer where the at least one dopant exhibits both a gradient of at least 1 wt.% per µm and a gradient (dc(v) / dv) of less than or equal to -1 wt.% per µm in the vertical direction.In this context, "cutting an area" also means "immersing in an area," i.e., the trench cuts an area even if it merely dips into it without cutting through it. After the trench is created, it is widened by etching it with the etchant at various etching rates. In principle, any isotropic wet etching process and / or isotropic dry etching process is suitable. A suitable isotropic dry etching process is, for example, chemical dry etching (CDE). In this context, "isotropic" means that the etching rate is isotropic, provided that the material being etched is isotropic. This means that in an "isotropic etching process," the process itself is isotropic. However, even when an isotropic etching process is used to etch an anisotropic material, the etching rate is generally anisotropic.After widening the trench, a conductor track is created by filling the widened trench with an electrically conductive material.

[0007] According to another aspect of the invention, the conductor track can be an outer winding of a coil of a coreless transformer of the semiconductor device. SUMMARY OF THE CHARACTERS

[0008] The principle of the invention is explained below with reference to the accompanying figures and exemplary embodiments. The representation in the figures is not necessarily to scale. In the figures, identical reference numerals indicate corresponding parts. Fig. Figure 1 shows a perspective view of coils of a coreless transformer of a semiconductor device. Fig. Figure 2 shows a sectional view of the coils of the coreless transformer according to Fig. 1. Fig. Figures 3A to 3H illustrate different steps in the production of a rounded conductor track on a semiconductor chip. Fig. Figure 4A shows another example of a rounded conductor track on a semiconductor chip. Fig. 4B shows the arrangement according to Fig. 4A after removing one layer of mask. Fig. Figure 5 shows a sectional view through a section of a coreless transformer of a semiconductor chip, with the windings of one of the transformer's coils rounded. Fig. Figure 6 shows a cross-sectional view through a section of a coreless transformer of a semiconductor chip, which differs from the section of the coreless transformer according to Fig. 5 differs in that a shielding ring is also rounded in cross-section. Fig. Figures 7A to 7F illustrate various steps of another process for manufacturing a rounded conductor track of a semiconductor chip. Fig. 8A and Fig. Figure 8B illustrates various steps of a process for producing a dielectric layer with varying doping. Fig. Figure 9 shows a sectional view of a coil of a coreless transformer, which extends from the coil of the coreless transformer according to Fig. 2 differs in that all windings of the upper coils are at least partially rounded. Fig. Figure 10 shows a sectional view of a capacitor monolithically integrated into a semiconductor body and featuring a rounded electrode. DETAILED DESCRIPTION OF THE FIGURES

[0009] The following detailed description refers to the accompanying drawings, which form part of the description and illustrate specific embodiments with which the invention can be implemented. In this context, directional terminology such as "top," "bottom," "front," "back," "anterior," "rear," etc., is used in relation to the orientation of the respective figures.

[0010] The Fig. 1 and Fig. Figure 2 shows coils 41, 42, 51, 52, 61, 62 of a coreless transformer of a semiconductor device 1. For the sake of clarity, the other parts of the semiconductor device are not shown. Fig. Figure 2 shows a sectional view of the semiconductor device 1 with the coreless transformer embedded in a semiconductor body 10 of the semiconductor device 1.

[0011] In principle, a coreless transformer requires at least two coils: one coil used to transmit a signal and another used to receive the signal. In the embodiment shown below... Fig. In the diagram, there are two transmitting coils 41, 42 and four receiving coils 51, 52, 61, 62. Each of the coils 41, 42, 51, 52, 61, 62 can have the form of a flat spiral with one or more turns. Coils 41, 51, 61 share a common coil axis 91, while coils 42, 52, 62 share a common coil axis 92. A current signal, fed into a transmitting coil 41 or 42 via connection contacts 45, 46, 47 (e.g., bond pads or solder pads), induces an electric current in the respective receiving coil 51, 61 or 52, 62, which is galvanically isolated from the transmitting coil 41, 42. To suppress stray radiation, a ring-shaped shielding ring 30, which may optionally be connected to ground (GND), surrounds the transmitting coils 41, 42.

[0012] During operation of the semiconductor device, the absolute value of the difference between the electrical potentials of a receiving coil 51, 52, 61, 62 and ground (GND) is typically not above a few volts or a few tens of volts, whereas the difference between the electrical potentials of a transmitting coil 41, 42 and ground (GND) can exceed a few hundred volts, a few thousand volts, or even a few tens of thousands of volts. Therefore, the difference between the electrical potentials of a transmitting coil 41, 42 and the potential of the shielding ring 30 can also exceed a few hundred volts, a few thousand volts, or even a few tens of thousands of volts. In conventional arrangements, most electrical breakdowns between a transmitting coil 41, 42 and the shielding ring 30 occur at or near the top surface 11 of the semiconductor device 1. Therefore, it is advantageous if at least the outermost windings 411 and 421 of the transmitting coils 41 and 421 respectively are42 at least in those sections of their parts which are closest to the shielding ring 30, i.e. in their parts which are turned away from the coil axis 91 or 92 in question, have rounded cross-sections.

[0013] Fig. Figure 2 shows a cross-section through the coreless transformer according to Fig. 1 in a cross-sectional plane that is parallel to both the vertical direction v and the coil axes 91 and 92. The vertical direction v is also perpendicular to a top surface 11 and / or a bottom surface 12 of the semiconductor body 10. In this context, the top surface 11 and the bottom surface 12 are considered to be essentially planar. This is shown schematically in Fig. 2. Furthermore, the boundary line of the semiconductor device 1. The semiconductor body 10 of the semiconductor device 1 can be made of any semiconductor material such as silicon, germanium, silicon carbide, gallium arsenide, etc., and it can have p-doped semiconductor regions, n-doped semiconductor regions, dielectric layers, for example silicon oxide layers, nitride layers, or imide layers, as well as electrically conductive layers and regions made of metal and / or polycrystalline semiconductor material. Optionally, the semiconductor device can have one or a combination of active devices such as IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), J-FETs (Junction Field Effect Transistors), thyristors, diodes, etc.Alternatively or additionally, the semiconductor device can include one or a combination of passive components such as resistors, capacitors, inductors, etc. In particular, such a component can be a controllable semiconductor device that has a control electrode such as a gate or a base. At least one of the coils 41, 42, 51, 52, 61, 62 can be electrically connected to such a control electrode directly (i.e., simply via an electrically conductive trace) or indirectly (i.e., via one or more active and / or passive components such as a driver circuit for driving the controllable semiconductor device).

[0014] How Fig. As can be seen from Figure 2, coil 41 has spiral turns 411, 412, 413, and 414. Similarly, coil 42 has spiral turns 421, 422, 423, and 424; coil 51 has spiral turns 511, 512, 513, and 514; coil 52 has spiral turns 521, 522, 523, and 524; coil 61 has spiral turns 611, 612, 613, and 614; and coil 62 has spiral turns 621, 622, 623, and 624. The upper coils 41, 42, i.e., those of coils 41, 42, 51, 52, 61, 62 that are located closer to the top 11, are connected by a Shielding ring 30 surrounds the coils and can optionally be connected to ground potential (GND). Equally optionally, the shielding ring 30 can extend in the opposite direction v to approximately the level of the lower coils 51, 52, 61, 62. To improve the shielding effect, the shielding ring 30 can be electrically connected to ground (GND).

[0015] As in Fig. As also shown schematically in Figure 2, the outer winding 411, 421 of at least one of the transmitting coils 41, 42 has a rounded cross-section, i.e., in at least one section plane that runs parallel to the respective coil axis 91 or 92 and perpendicular to the direction of travel of the respective coil 411, 421, the surfaces 40 of this outer winding 411 or 421 are at least partially rounded. For example, the respective surface 40 in the section plane has a radius of curvature of at least 0.4 µm, and / or of less than or equal to 3.2 µm, e.g., approximately 1.6 µm, at at least one point P1, P2.

[0016] Next, with reference to the Fig. Sections 3A to 3H describe a method for manufacturing a component with a conductor track that is at least partially rounded in cross-section, using the outer winding of the transmitting coil 41 as an example. Fig. 1 and Fig. 2. The starting point is a partially completed semiconductor body 10 with a bottom surface 12 and a top surface 11', which is spaced away from the bottom surface 12 in the vertical direction v. In Fig. 2 is the plane of the (former) top surface 11', which runs perpendicular to the vertical direction v and is marked by a dashed line. As in Fig. 3B, which has one in Fig. Figure 3A, which represents the enlarged section 12' of the device 1 indicated by a dashed line, shows a dielectric layer 2 arranged on the top surface 11'. In the example shown, the reference numeral 11' denotes a top surface of the semiconductor body 10. Generally, the reference numeral 11' denotes the top surface of a partially completed semiconductor device 1; that is, the top surface can consist of or comprise dielectric material, conductive material, doped semiconductor material, undoped semiconductor material, metal, or polycrystalline semiconductor material, alone or in any combination thereof.

[0017] The dielectric layer 2 has various sublayers 21, 22, 23, 24, 25, whereby immediately adjacent sublayers 21 and 22, 22 and 23, 23 and 24, 24 and 25 exhibit different etch rates when etched with the same etchant. For this purpose, immediately adjacent sublayers 21, 22, 23, 24, 25 can consist of different material compositions, which—for a selected etchant used to later etch the dielectric layer 2 in order to widen a groove 13 formed in the dielectric layer 2—exhibit different etch rates. In this context, two immediately adjacent sublayers 21 / 22, 22 / 23, 23 / 24, and 24 / 25 are also considered to consist of different material compositions if they have the same base material but are doped differently.In this context, "differently doped" includes the meanings "doped with the same dopant but with different dopant concentrations" and / or "doped with different dopants." Also included are combinations in which one of the immediately adjacent sublayers 21 at 22, 22 at 23, 23 at 24, 24 at 25 consists solely of an undoped base material, and the other immediately adjacent sublayer 21 at 22, 22 at 23, 23 at 24, 24 at 25 consists of the same base material, but doped with a dopant. In each case, the material of the dielectric layer 2 has a non-constant etch rate in the vertical direction v for the selected etchant.In the present embodiment, each of the sublayers 21, 22, 23, 24, 25 has a thickness of at least 100 nm or at least 400 nm in the vertical direction v, and / or of less than or equal to 2 µm. For example, this thickness can be in the range of 100 µm to 2 µm. However, any other thickness can also be used in principle.

[0018] At the in Fig. In the embodiment shown in Figure 3B, the dielectric layer 2 is made of a base material, for example silicon oxide, which is doped with a dopant, for example phosphorus (P), boron (B), silver (Ag), arsenic (As), argon (Ar), or a combination of these materials, and which influences the wet and / or dry etch rate of the dielectric layer 2. In the vertical direction v, the dopant of the dielectric layer 2 has a non-constant concentration profile. Therefore, if the dielectric layer 2 is subsequently wet and / or dry etched, even if the etching process itself is isotropic, different etch rates can be obtained during the same, common etching step with the same etchant, since the sublayers 21, 22, 23, 24, 25 of the dielectric layer 2 have different dopant concentrations.

[0019] The dielectric layer 2 can be produced by first depositing the sublayer 25 on the top surface 11', then depositing the sublayer 24 on the sublayer 25, then depositing the sublayer 23 on the sublayer 24, then depositing the sublayer 22 on the sublayer 23, and finally depositing the sublayer 21 on the sublayer 22. As shown on the right side of Fig. As shown in Figure 3B, sublayers 21 and 25 can have a dopant concentration of 0 wt.% (weight percent), and sublayers 22 and 24 can have a dopant concentration of 2 wt.%. Sublayer 23 has a dopant concentration of 4 wt.%, which, in the example shown, represents the maximum dopant concentration of the dielectric layer 2. In this context, the term "wt.%" in the present embodiment means that 1 kg of doped silicon dioxide (SiO₂) contains 40 g of the dopant. In other embodiments, the maximum dopant concentration can, for example, be greater than 4 wt.%, such as at least 8 wt.%.

[0020] In the vertical direction v, the maximum dopant concentration can be found over a thickness dc. maxextend, for example, to at least 100 nm. Furthermore, the range of maximum dopant concentration can extend from both the former top side 11' and the bottom side 12 (see Fig. 2) be spaced apart on the far side of the dielectric layer 2.

[0021] If the same base material, for example silicon oxide, is used for all sublayers 21, 22, 23, 24, 25 of the dielectric layer 2, the base material for all sublayers 21, 22, 23, 24, 25 can be continuously deposited on the top surface 11', e.g., by means of a vapor deposition process, by depositing the dielectric layer 2 from the gas phase and varying the concentration of the dopants contained in the gas phase during the deposition process such that the resulting dielectric layer 2 has a sublayer structure 21, 22, 23, 24, 25 as described above. In contrast to the embodiment shown, the number of adjacent sublayers 21, 22, 23, 24, 25 exhibiting different etch rates can also be less than or greater than 5. Basically, the dielectric layer 2 has at least two such sublayers 21, 22, 23, 24, 25.However, the roundness of the conductor track to be produced can be increased by using an increased number of sublayers 21, 22, 23, 24, 25.

[0022] As shown below, based on the Fig. 3C to 3E is explained on the dielectric layer 2 ( Fig. 3C) an etching mask layer 31, for example a silicon nitride layer or another suitable layer, arranged and then structured, for example photolithographically, so that it has an opening 311 in which the dielectric layer 2 is exposed (see Fig. 3D). Then, as in Fig. Figure 3E shows that a trench 13 is etched below the opening 311 using the structured etching mask layer 31. The trench 13 can have a depth of at least 0.5 µm or at least 3 µm in the vertical direction v, for example. However, the lower limit of the depth of the trench 13 can also be below or above these values.

[0023] The etching process in question can be a dry etching process, such as an anisotropic plasma etching process, e.g., reactive ion etching (RIE), deep reactive ion etching (DRIE), or high-density plasma etching (HDP). Fig. 3E is the underside of the trench 13 spaced from the top side 11'. However, the trench 13 can also extend through the top side 11' into the semiconductor body 10. If the conductor track to be produced is a spiral coil, such as the coil of a coreless transformer as described above, the orientation of the trench 13 changes with the orientation of the spiral. However, the trench 13 and the conductor track to be produced in the trench 13 can just as easily have any other orientation.

[0024] In a subsequent wet and / or dry etching process, the selected etchant is introduced into the groove 13 in such a way that the groove 13 is filled with the liquid or gaseous etchant and the etchant coats the surface 131 (see Fig. 3E) of trench 13. Suitable etchants are, for example, hydrofluoric acid (HF), or a mixture of ammonium fluoride (NH4F) and hydrofluoric acid (HF), for example in a ratio of 30 vol.% to 6 vol.% (volume percent).

[0025] During the etching process, adjacent sublayers 21, 22, 23, 24, 25 are etched at different rates due to their different material compositions (here, for example, different dopant concentrations). Regardless of whether the different etch rates of adjacent sublayers 21, 22, 23, 24, 25 are achieved through different dopant concentrations in the various sublayers 21, 22, 23, 24, 25, and / or through any other measure described above, the Fig. The trench 13 shown in Figure 3E widens during the wet and / or dry etching process. The widened trench 13 is in Fig. 3F is shown. As shown, the wet and / or dry etching process can be carried out with the structured mask layer 31 arranged on the top surface 11', or, alternatively, after the mask layer 31 has been partially or completely removed from the semiconductor body 10 (not shown). As in Fig. As shown in Figure 3F, the surface of the widened trench 13 can have one or more locations S1, S1' in a section plane perpendicular to the direction of the trench 13, where the radius of curvature R of the surface of the trench 13 is at least 0.4 µm and / or less than or equal to 3.2 µm. In some embodiments, this radius of curvature R can be, for example, approximately 1.6 µm. After the trench 13 is completed, a barrier layer 35 can optionally be added (see Figure 3F). Fig. 3F) is deposited on the surface of the widened trench 13 so that it covers the entire surface of the trench 13. Such a barrier layer 35 prevents or reduces the diffusion of the conductive material, which is subsequently placed in the trench 13, into the semiconductor body 10. For example, the diffusion of copper could impair the function of a semiconductor device implemented in the semiconductor body 10. Therefore, if the conductor material contains copper, for example, and if the semiconductor body 10 is to contain a semiconductor device, the use of a barrier layer 35 is highly recommended. However, a barrier layer 35 can also be used with other conductor materials that do not contain copper.Suitable barrier materials against the diffusion of copper or any other electrically conductive material include, for example, tantalum (Ta), titanium (Ti), tungsten (W), tantalum nitride (TaN), titanium nitride (TiN), tungsten nitride (WN), titanium tungsten (TiW), titanium-tungsten nitride (TiWN), silicon nitride (SiN), or a combination of layers of these materials. An example of such a combination would be a bilayer comprising a partial layer of tantalum (Ta) and a partial layer of tantalum nitride (TaN), or a bilayer comprising a partial layer of titanium (Ti) and a partial layer of (TiN).

[0026] As in Fig. As shown in 3F, the openings 311 have a minimum width W in a section plane (the drawing plane) perpendicular to the direction of travel (perpendicular to the drawing plane). min and the widened trench 13 has, in an area between the openings 311 and the underside 12 (see Fig. 2), a maximum width W max , which is larger than the minimum width W min In other words, the unit formed by trench 13 and opening 311 has an undercut. The maximum width W can be max be greater than the difference between both (a) the distance between the bottom surface 12 (see Fig. 2) and the opening 311, as well as (b) the distance between the underside 12 and the conductor track 411.

[0027] Referring to Fig. In 3G, a conductor track 411 is now fabricated in the widened trench 13. For this purpose, the widened trench 13 is filled with an electrically conductive material, for example, copper, aluminum, graphite, graphene, or a mixture or combination containing any two or more of the aforementioned materials or allotropes. If the conductor track 411 does not need to have a particularly high current-carrying capacity, doped or undoped polycrystalline semiconductor material can also be used as the electrically conductive material.

[0028] The filling of the widened trench 13 can be carried out while the structured mask layer 31 is still on the dielectric 2, or after the structured mask layer 31 has been partially or completely removed. Provided the opening 311 of the structured mask layer 31 is still present, the electrically conductive material can be poured into the widened trench 13 through this opening 311. As shown in Fig. As shown in Figure 3G, the widened trench 13 can be overfilled so that the electrically conductive material forms a conductive layer 48, which covers the dielectric layer 2 and, optionally, the structured mask layer 31 or its residues if the structured mask layer 31 was not removed or not completely removed before the backfilling process.

[0029] As further in Fig. As shown in 3H, the arrangement can be found on its underside 12 (see Fig. 3A) The side facing away from the surface can be flattened, for example by grinding, polishing, lapping, etc. In doing so, the conductive layer 48, if present, can be partially or completely removed above the filled trench 13.

[0030] The completed conductor track 411 has a surface 40 that is at least partially rounded. At at least one point P1, P1' on the surface 40, the surface 40 has a radius of curvature R in a section plane (here: the plane of the drawing) which extends perpendicular to the direction of travel of the conductor track 411 (here: the direction of travel is perpendicular to the plane of the drawing), which can lie in the same range as the one above with reference to Fig. The radius of curvature R is called 3F, since the thickness of an optional barrier layer 35 can be neglected.

[0031] According to another, in Fig. In the embodiment shown in Figure 4A, the dielectric layer 2 contains two sublayers 21 and 22. The sublayer 21 consists of an undoped base material, for example silicon oxide, and the sublayer 22 is made of the same base material, but additionally doped with a dopant, for example phosphorus (P), boron (B), silver (Ag), arsenic (As), argon (Ar), or a combination with at least two of these dopant materials.Alternatively, both the first sublayer 21 and the second sublayer 22 can be made of a base material doped with a dopant, for example phosphorus (P), boron (B), silver (Ag), arsenic (As), argon (Ar), or a combination of at least two of these dopants, wherein the doping of the first and second sublayers 21, 22 is selected such that when they are etched with the same etchant that is later used to widen the trench 13, the etch rate of the second sublayer 22 is higher than the etch rate of the first sublayer 21. Due to the different etch rates, the material removal rate of the second sublayer 22 is greater than the material removal rate of the sublayer 21. The widened trench 13, in which the conductor track 411 is arranged, was produced by first creating a trench 13 as described above with reference to the... Fig. 3D and Fig. 3E explains, into which the dielectric layer 2 was etched, into which the dielectric layer 2 was etched, as well as by subsequent widening of this trench 13 and / or dry etching, and by the optional coating of the surface of the trench 13 with a barrier layer 35, as previously explained with reference to Fig. 3F explained, as well as by filling trench 13 with an electrically conductive material, as previously explained with reference to the Fig. 3G and Fig. 3H was explained.

[0032] According to another, in Fig. In option 4B shown, the mask layer 31, which was used for the dry etching process, can be completely or at least partially removed.

[0033] Fig. Figure 5 shows a section 1' of a semiconductor device 1. This section 1' corresponds to the one in Fig. Section 1' shown in Figure 2. Before the windings 411, 412, 413 of a coil of a coreless transformer were fabricated, the partially completed semiconductor device had a top surface 11'. On this earlier top surface 11', the winding 411 of the coil was fabricated in the same way as the conductor track 411 according to Figure 2. Fig. 4B. Optionally, as also in Fig. As shown in Figure 5, some or all of the other windings 412, 413 of the coil are manufactured in the same way as the outermost winding 411, so that they have at least a partially rounded surface.

[0034] The coil 411 (see also the Fig. 1 and Fig. 2) is surrounded by an electrically conductive shielding ring 30 arranged in a groove. Such a shielding ring 30 can be produced using a damascus process, for example, by producing a groove using an anisotropic dry etching process and subsequently filling this groove with an electrically conductive material, which may be, for example, copper, aluminum, graphite, graphene, or a mixture or combination containing two or more of the aforementioned materials or allotropes thereof. If the shielding ring 30 does not need to have a high current-carrying capacity, doped or undoped polycrystalline semiconductor material can also be used as the electrically conductive material. Preferably, the shielding ring 30 consists of the same electrically conductive material that is also used for producing the windings 411, 412, 413.However, various electrically conductive materials can also be used for this purpose. Optionally, the surface of the trench can be coated with a barrier layer 35 in the same way and using the same materials as described above with reference to . Fig. 3F was explained.

[0035] After the coil 41, which comprises the turns 411, 412, 413, has been manufactured, the component can be further processed in any desired manner. In the example according to Fig. 5 a silicon nitride layer 33, a silicon oxide layer 72, a hydrogen-containing silicon nitride layer 34 and an imide layer 73 are successively deposited on the dielectric layer 2, the windings 411, 412, 413 and the shielding ring 30.

[0036] Alternatively, as in Fig. Figure 6 shows that a shielding ring 30, at least partially rounded in cross-section, can be manufactured using the same principle, steps and materials as the at least partially rounded outer winding 411; see in particular the Fig. 3A to 3H, 4A and 4B, i.e. by etching a trench, etching widening of the trench, optional coating of the surface of the trench with a barrier layer, and by filling the trench with an electrically conductive material.

[0037] In the above, referring to the Fig. In the embodiments described in 3B to 3H, 4A and 4B, a conductor track 411, at least partially rounded, was produced starting from a dielectric layer 2, which has two or more sublayers 21, 22, 23, 24, 25, wherein each pair of immediately adjacent sublayers 21, 22, 23, 24, 25 have different etch rates when etched with the selected etchant.

[0038] The following will now refer to the Fig. Sections 7A to 7F explain a further embodiment. Starting from an arrangement as described above with reference to Fig. As explained in section 3A, on the upper side 11' there is a Fig. The dielectric layer 2 shown in 7A is produced. The dielectric layer 2 is formed from a base material, for example silicon oxide, which is doped with a dopant such as phosphorus (P), boron (B), silver (Ag), arsenic (As), argon (Ar), or a combination thereof. In contrast to the above with reference to the Fig. In the embodiments described in sections 3B to 3H, 4A, and 4B, the dopant profile of the dielectric layer 2 does not have a stepped structure, but rather a profile that changes continuously and smoothly in the vertical direction v. That is, within the dielectric layer 2, the dopant concentration c of the dielectric layer 2 represents a differentiable function in the vertical direction v. In the vertical direction v, the dopant concentration initially has an increasing branch in which a gradient c1' = dc(v) / dv is greater than zero and reaches a value of at least 1 wt.% per µm, or at least 2 wt.% per µm, where c(v) describes the course of the dopant concentration c as a function of the vertical direction v. After passing through the maximum dopant concentration, the dopant concentration c has a decreasing branch in which a gradient c2' = dc(v) / dv is less than zero and has a value of less than or equal to -1 wt.% per µm is achieved, or even less than or equal to -2 wt.% per µm.

[0039] The following steps are performed in the same way as described above with reference to the Fig. 3C to 3H were explained. The only difference between the designs of the Fig. 3C, Fig. 3D, Fig. 3E, Fig. 3F and Fig. 3H and the design of the corresponding Fig. 7B, Fig. 7C, Fig. 7D, Fig. 7E and 7F differ in the structure of the respective dielectric layer 2. Due to the differentiable profile of the dopant concentration c of the dielectric layer 2, the surface of the trench 13 (see Fig. 7E) and the surface 40 of the electrically conductive conductor track 411 is smoother than the corresponding surfaces in the Fig. Surfaces shown in 3F or 3G.

[0040] In order to produce a dielectric layer 2 in which the dopant concentration c of the dielectric layer 2 is a differentiable function of the vertical direction v, the application of the dielectric layer 2 to the surface 11' can be carried out by deposition from a gas phase containing the dopant or dopants and in which the concentration of the dopant or dopants is changed during the deposition process such that the desired dopant profile is obtained.

[0041] As well as from Fig. As can be seen in 7F, in a cross-sectional plane (the drawing plane) perpendicular to the direction of travel of the trench 13 (see Fig. 7E), for each point P1, P2 of a continuous surface path b40 (represented by a bold line) along the surface 40 of an electrical conductor 411, the radius of curvature of the conductor 411 is at least 0.4 µm. Optionally, for each point P1, P2 of the continuous surface path b40, the radius of curvature R of the conductor 411 can be less than or equal to 3.2 µm. For example, for each point P1, P2 of the continuous surface path b40, the radius of curvature R of the conductor 411 can be in a range from 0.4 µm to 3.2 µm. In the vertical direction v, the continuous surface path b40 can extend over a distance d29 of at least 100 nm or even at least 0.8 µm.

[0042] Another alternative, as described in Fig. Figure 8A shows how to create an undoped or homogeneously doped dielectric layer 2' on the surface 11'. Then, as shown in Fig. As shown in Figure 8B, one or more types of dopants are implanted into the dielectric layer 2'. Since the implantation depth depends on the energy of the implanted dopants, the desired dopant profile can be easily adjusted by continuously changing the particle energy at a differentiable rate (particle energy per unit time) during the implantation process.

[0043] However, the implantation of dopant particles can also be used to produce an arrangement with an essentially stepwise dopant concentration c(v), for example an arrangement as described above with reference to Fig. 3B was explained and which also serves as a starting point for the discussion with reference to the Fig. The procedures described in sections 3B to 3H can be used.

[0044] In the case of a conventional coreless transformer, electrical breakdowns occur primarily at parts 410 of the outermost windings 411 and 421 of the transformer coils 41 and 42 respectively, which are adjacent to both the underside 12 and the coil axis 91, 92 of the coil 41, 42 in question (see the Fig. 1 and Fig. 2) are turned away. Therefore, in every embodiment of the present invention, at least the outermost winding 411, 421 of the respective coil 41 or 42 can be rounded at least on the upper sections 410 of the parts of the outermost windings 411, 421 of the transformer coils 41 or 42 that face away from both the underside 12 and the axis 91, 92 of the respective coil 41 or 42. On this upper section 410, the respective outermost winding 411, 421 can have a radius of curvature R as already described above.

[0045] Instead of rounding only the outermost turns 411, 421 of the coils 41 or 42 of a coreless transformer, two, more or all turns of this coil 41 or 42 can be partially, or, as in Fig. As shown in 9, it should be completely rounded. The arrangement according to Fig. 9 is identical to the arrangement according to Fig. 2 with the only difference that all turns 411, 412, 413, 414 of the coil 41 and all turns 421, 422, 423, 424 of the coil 42 in a section plane which runs parallel to the vertical direction v and to the coil axis 91 or 92 of the coil in question, as well as the turn 411 described in the preceding examples, have rounded surfaces.

[0046] Another embodiment of a rounded conductor track 71 is shown in Fig. Figure 10 shows that in this embodiment, the conductor track 71 forms part of a capacitor consisting of plate-like parallel conductor tracks 71 and 78, which extend substantially perpendicular to the plane of the drawing. The upper conductor track 71 has a terminal contact 75, and the lower conductor track 78 has a terminal contact 76. To produce a surface 70 of the upper conductor track 71 with points P71 at which the surface 70 has a radius of curvature R in the previously described area, one of the methods described above with reference to the production of an at least partially rounded conductor track 411 can be used. As also described in Figure 10, the following methods can be used: Fig.As shown in Figure 10, the lower conductor track 78 can be rounded in the same or a similar way as the upper conductor track 71. However, the lower conductor track 78 can also have a square cross-section. Just like a coreless transformer, the capacitor 71, 78 can also be used to galvanically decouple a circuit for driving a controllable semiconductor device from a control electrode of this controllable semiconductor device. Such a semiconductor device can be implemented in the same semiconductor package as the capacitor 71, 78 or the coreless transformer, or in a different semiconductor package.

Claims

[1] Method for producing a rounded conductor track (411) of a semiconductor component, comprising the steps: Providing a partially completed semiconductor component having a bottom side (12) and a top side (11') spaced from the bottom side (12) in a vertical direction (v); Providing an etchant; Arranging a dielectric layer (2) on the top side (11'), wherein the dielectric layer (2) - has at least two different regions (21, 22, 23, 24, 25) which, when etched with the etchant, have different etching rates; and - a base material doped with at least one dopant having a non-constant concentration profile (c) in the vertical direction (v) with a gradient (dc(v) / dv) of at least 1 wt.% per µm, wherein the dopant influences the etching rate of the doped base material when it is etched with the etchant; Arranging a mask layer (31) having an opening (311) on the dielectric layer (2); Creating a trench (13) in the dielectric layer (2) below the opening (311) by means of an anisotropic plasma etching process and using the mask layer (31) as an etching mask such that the trench (13) - intersects each of the different areas (21, 22, 23, 24, 25); and - extends into a section of the dielectric layer (2) in which the at least one dopant in the vertical direction (v) has both a gradient (c1') of at least 1 wt.% per µm and a gradient (dc(v) / dv) of less than or equal to -1 wt.% per µm; Widening the trench (13) by etching the trench (13) with the etchant such that at least two of the different regions (21, 22, 23, 24, 25) are etched at different etching rates; Producing the conductor track (411) by filling an electrically conductive material into the widened trench (13). [2] Method according to claim 1, wherein the different regions (21, 22, 23, 24, 25) are formed as partial layers of the dielectric layer (2); and the concentration (c) of the dopant in adjacent partial layers (21, 22, 23, 24, 25) is different. [3] Method according to claim 1 or 2, wherein the at least one dopant has a gradient (dc(v) / dv) of at least 2 wt.% per µm in the vertical direction (v). [4] Method according to one of the preceding claims, wherein the at least one dopant has a gradient (dc(v) / dv) of less than or equal to -2 wt.% per µm in the vertical direction (v). [5] Method according to one of the preceding claims, in which the dopant has a maximum dopant concentration within the dielectric layer (2) and along a line parallel to the vertical direction (v); and the location of the maximum dopant concentration is spaced from the top side (11'). [6] A method according to any one of the preceding claims, wherein the dopant consists of one of the following materials: phosphorus (P), boron (B), silver (Ag), arsenic (As), argon (Ar). [7] Method according to one of the preceding claims, in which the filling of the widened trench (13) is carried out by filling the electrically conductive material through the opening (311) into the widened trench (13). [8] Method according to one of the preceding claims, in which the mask layer (31) and a part of the electrically conductive material arranged in the openings (311) are partially or completely removed. [9] Method according to one of the preceding claims, in which, in a sectional plane perpendicular to the direction (r1, r2, r3) of the widened trench (13), (a) the opening (311) has a minimum width (W min ); and (b) the widened trench (13) has a maximum width (W max ) which is greater than the minimum width (W min ). [10] Method according to claim 9, wherein the maximum width (Wmax ) in the section plane perpendicular to the direction (r1, r2, r3) of the widened trench (13) is greater than the difference between (a) the distance between the bottom (12) and the openings (311); and (b) the distance between the underside (12) and the conductor track (411). [11] Method according to one of the preceding claims, in which no additional material is applied to the surface of the widened trench (13) before filling the electrically conductive material into the widened trench (13). [12] Method according to one of the preceding claims, in which the dielectric layer (2) is a silicon oxide (SiO x ). [13] Method according to one of the preceding claims, in which the conductor track (411) has, in a sectional plane perpendicular to the direction of extension (r1, r2, r3) of the widened trench (13), a surface location (P1, P1', P2) at which the surface of the conductor track (411) has a radius of curvature (R) in the range from 0.4 µm to 3.2 µm. [14] Method according to one of the preceding claims, in which the conductor track (411) has, in a sectional plane perpendicular to a direction of extension (r1, r2, r3) of the widened trench (13), a continuous surface path (b40) which extends in the vertical direction (v) over a distance (d29) of at least 100 nm or of at least 0.8 µm and which has a radius of curvature (R) in the range from 0.4 µm to 3.2 µm at each point. [15] A method according to any one of the preceding claims, wherein the electrically conductive material (a) made of copper or aluminium; or (b) contains copper or aluminium; or (c) consists of copper and aluminium; or (d) contains copper and aluminium; or (e) comprises or consists of polycrystalline semiconductor material. [16] Method according to one of the preceding claims, in which the manufactured conductor track (411) represents the outer turn of a coil (41) of a coreless transformer of the semiconductor component (1). [17] The method of claim 16, wherein the coreless transformer galvanically decouples a control circuit for controlling a controllable semiconductor device from a control electrode of the controllable semiconductor device. [18] Method according to one of claims 1 to 15, wherein the conductor track (71) produced represents an electrode of a capacitor. [19] The method of claim 18, wherein the capacitor galvanically decouples a control circuit for controlling a controllable semiconductor component from a control electrode of the controllable semiconductor component. [20] Method for producing a rounded conductor track (411) of a semiconductor component, comprising the steps: Providing a partially completed semiconductor component having a bottom side (12) and a top side (11') spaced from the bottom side (12) in a vertical direction (v); Arranging a dielectric layer (2) on the upper side (11'), wherein the dielectric layer (2) is doped with a dopant which has a non-constant concentration profile (c(v)) in the vertical direction (v); Arranging a mask layer (31) having an opening (311) on the dielectric layer (2); Producing a trench (13) in the dielectric layer (2) below the opening (311) by means of an anisotropic plasma etching process and using the mask layer (31) as an etching mask such that the trench (13) intersects regions of the dielectric layer (2), wherein the dopant has different dopant concentrations in these regions and wherein the trench extends into a section of the dielectric layer (2) in which the dopant concentration in the vertical direction (v) has both a gradient (dc(v) / dv) of at least 1 wt.% per µm and a gradient (dc(v) / dv) of less than or equal to -1 wt.% per µm; Widening the trench (13) by etching the trench (13) with different etching rates which are caused by the non-constant profile of the concentration (c(v)) of the dopant; Producing the conductor track (411) by filling an electrically conductive material into the widened trench (13). [21] Method according to claim 20, wherein the conductor track (411) has, in a sectional plane perpendicular to a direction of extension (r1, r2, r3) of the widened trench, a surface location (P1, P1', P2) at which a radius of curvature (R) of the surface lies in a range from 0.4 µm to 3.2 µm. [22] A method according to claim 21, wherein the trench is spiral-shaped; and the conductor track (411) is spiral-shaped and represents an outer turn of a coil (41) of a coreless transformer of the semiconductor component. [23] A method for producing a rounded conductor track (411) of a semiconductor device, the method comprising the steps of: Providing a partially completed semiconductor component having a bottom side (12) and a top side (11') spaced from the bottom side (12) in a vertical direction (v); Providing an etchant; Producing a dielectric layer (2) doped with a dopant and comprising a base material on the upper side (11') by successively depositing a number of at least two partial layers (21, 22, 23, 24, 25), wherein in each case two mutually adjacent partial layers (21, 22, 23, 24, 25) the concentration of the dopant (a) different; or (b) in one of the two adjacent sub-layers (21, 22, 23, 24, 25) is equal to zero and in the other of the two adjacent sub-layers (21, 22, 23, 24, 25) is greater than zero, wherein the dopant influences the etching rate of the doped base material when this is etched with the etchant, and wherein a concentration profile (c) of the dopant in the vertical direction (v) has both a gradient (dc(v) / dv) of at least 1 wt.% per µm and a gradient (dc(v) / dv) of less than or equal to -1 wt.% per µm; Forming a trench (13) in the dielectric layer (2) such that the trench (13) intersects each of the sublayers (21, 22, 23, 24, 25); Widening the trench (13) by etching the trench (13) with the etchant at different etching rates caused by different concentrations of the dopant; Producing the conductor track (411) by filling an electrically conductive material into the widened trench (13). [24] Method according to claim 23, wherein the conductor track (411) has a surface in the cutting plane with a surface location (P1, P2) at which a radius of curvature (R) of the surface is in the range of 0.4 µm to 3.2 µm.

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