Semiconductor device and substrate biasing method therefor

Abstract

Semiconductor component (100) comprising: a functional module (110) including a plurality of transistors; a temperature sensor (120) configured to detect an operating temperature of the functional module (110) in real time; and an adaptive substrate bias generator (130) configured to provide a substrate bias to adaptively adjust leakage currents from the transistors according to the sensed operating temperatures, wherein the substrate bias voltage is generated by the adaptive substrate bias voltage generator (130) according to the sensed operating temperature and according to a predetermined minimum leakage current corresponding to the sensed operating temperature.

Description

BACKGROUND

[0001] Example embodiments relate to a semiconductor device. In particular, example embodiments relate to a semiconductor device capable of adjusting a substrate bias voltage according to a temperature, and to a substrate biasing method therefor.

[0002] In recent years, the use of mobile devices such as smartphones, tablet PCs, digital cameras, MP3 players, PDAs, etc. has increased. As multimedia usage and data throughput increase, high-speed processors can be used for mobile devices. The mobile device may incorporate semiconductor devices (e.g., random access memory (DRAM), non-volatile memory, an application processor, etc.) to execute various programs. Since high efficiency is required in a mobile environment, the integration level and operating frequency of semiconductor devices will increase.

[0003] In the prior art, controlling leakage current in a mobile device can be very important for reducing power consumption and controlling temperature. Therefore, in the prior art, semiconductor devices are downsized to achieve a high degree of integration and high efficiency. However, downsizing the semiconductor device in the prior art can cause leakage current in the semiconductor device. Therefore, a technique for controlling the leakage current of the semiconductor device is needed.

[0004] US 7 106 128 B2 shows the use of multiple threshold voltage temperatures in throttling processor devices by means of a higher substrate bias voltage.

[0005] US 7 616 048 B2 shows a substrate bias control unit that uses a look-ahead table.

[0006] US 2002 / 0 029 352 A1 describes the control of processor parameters by means of controlling the substrate bias voltage.

[0007] US 2007 / 0 069 764 A1 shows a substrate bias generator that generates a substrate bias voltage depending on temperature signals and reference signals.

[0008] US 2011 / 0 063 937 A1 describes a control system that is integrated together with an integrated circuit on a chip and compensates for process and environmental fluctuations.

[0009] It is an object of the present invention to enable improved control of a substrate bias voltage.

[0010] This problem is solved by the subject matter of the main claim and the subject matter of the subordinate claims.

[0011] Preferred embodiments are the subject of the subclaims. SUMMARY

[0012] One aspect of an exemplary embodiment may provide a semiconductor device comprising a functional device including a plurality of transistors; a temperature sensor configured to sense an operating temperature of the functional device in real time; and an adaptive substrate bias generator configured to provide a substrate bias to adaptively adjust leakage currents from the transistors according to the sensed operating temperatures, wherein the adaptive substrate bias generator is further configured to generate the substrate bias according to a predetermined minimum leakage current according to the operating temperature.

[0013] Another aspect of an exemplary embodiment may provide a substrate biasing method of a semiconductor device, comprising sensing an operating temperature of the semiconductor device; generating a substrate bias voltage for adjusting leakage currents from a plurality of transistors present in the semiconductor device at the operating temperature; and applying the substrate bias voltage to the transistors of the semiconductor device.

[0014] Another aspect of an exemplary embodiment may provide a system-on-chip comprising: a plurality of functional devices; a temperature sensor configured to sense a respective operating temperature of each of the functional devices in real time; and a substrate bias generator configured to generate a respective substrate bias to adaptively adjust leakage currents of each of the functional devices according to a respective operating temperature.

[0015] Yet another aspect of an exemplary embodiment may provide a functional device including: at least one NMOS transistor configured to receive an NMOS bias from an adaptive substrate bias generator; at least one PMOS transistor configured to receive a PMOS bias from the adaptive substrate bias generator; and a temperature sensor configured to sense an operating temperature of the functional device in real time and provide the sensed operating temperature to the adaptive substrate bias generator. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects and features of the exemplary embodiments will become apparent from the following description with reference to the following figures, wherein like reference numerals refer to like parts in the various figures unless otherwise indicated, and wherein Fig. 1 is a diagram schematically illustrating a semiconductor device according to an embodiment; Fig. 2 is a circuit diagram schematically showing a transistor in a functional block of Fig. 1 represents; Fig. 3A and Fig. 3B Cross-sectional views of PMOS and NMOS transistors from Fig. 2 are; Fig. 3A is a sectional view of a PMOS transistor; Fig. 3B is a sectional view of an NMOS transistor; Fig. 4 is a graph illustrating a substrate bias characteristic according to an embodiment; Fig. 5 is a block diagram schematically illustrating a temperature sensor according to one embodiment; Fig. 6 is a block diagram schematically illustrating an adaptive substrate bias generator, according to one embodiment; Fig. 7 is a block diagram schematically illustrating an adaptive substrate bias generator according to another embodiment; Fig. 8 is a diagram schematically showing an input / output characteristic of a function generator of Fig. 7 represents; Fig. 9 is a table schematically illustrating a method for setting constants of a function generator, according to one embodiment; Fig. 10 is a table schematically illustrating leakage current and percentage leakage loss based on temperature and substrate bias voltage; Fig. 11 is a graph illustrating an effect according to a substrate bias voltage; Fig. 12 is a flow diagram schematically illustrating a substrate biasing method according to one embodiment; Fig. 13 is a block diagram schematically illustrating a semiconductor device according to another embodiment; Fig. 14 is a block diagram schematically illustrating a semiconductor device according to yet another embodiment; Fig. 15 is a block diagram schematically illustrating a handheld terminal incorporating a semiconductor device according to one embodiment; and Fig. 16 is a block diagram illustrating a computer system executing a substrate biasing method according to one embodiment. DETAILED DESCRIPTION

[0017] Example embodiments are described in detail with reference to the accompanying drawings and are directed to those skilled in the art. Accordingly, well-known processes, elements, and techniques are not described in some embodiments of the example embodiments. Unless otherwise described, like reference numerals refer to like elements throughout the attached drawings and the written description, and descriptions are therefore not repeated. In the drawings, the sizes and relative sizes of layers and regions are exaggerated for clarity.

[0018] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or sections, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, a first element, component, region, layer, or section, as discussed below, could be referred to as a second element, component, region, layer, or section without departing from the teachings of the exemplary embodiments.

[0019] Spatially relative terms such as "beneath," "underneath," "lower," "below," "above," "upper," etc., are used herein for convenience of description to describe the relationship of one element or feature to another element or feature as described in the figures. It should be understood that the spatially relative terms are intended to encompass various orientations of the device during use or operation, in addition to the orientation illustrated in the figures. For example, if the device is inverted in the figures, elements referred to as "below" or "below" or "under" other elements or features are then referred to as "above" the other elements or features. Therefore, the exemplary terms "below" and "below" can encompass both the orientations "above" and "below."The device may be oriented differently (rotated 90 degrees, or in another orientation), and the spatially relative notations used herein may be interpreted accordingly. Additionally, it is understood that when reference is made to a layer that is between two layers, it may be the only layer between the two layers, or one or more intervening layers may be present.

[0020] As used herein, the singular forms "a" and "a," are intended to include the plural forms as well, unless the context clearly indicates otherwise. It is further understood that the terms "includes" and / or "including," when used in this specification, indicate the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any combination of one or more of the associated listed items. Additionally, the term "exemplary" is intended to refer to an example or explanation.

[0021] It is understood that when an element or layer is described as being "on," "connected to," "attached to," or "adjacent to" another element or layer, it may be directly on, connected to, attached to, or adjacent to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is described as being "directly on," "directly connected to," "directly attached to," or "proximately adjacent" to another element or layer, there are no intervening elements or layers.

[0022] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as understood by one of ordinary skill in the art to which the exemplary embodiments belong. It is further understood that terms, such as those defined in commonly used dictionaries, are understood to have a meaning consistent with their meaning in the context of the relevant art and / or the underlying description and should not be interpreted in an idealized or overly formal manner unless expressly defined herein.

[0023] Fig. 1 is a block diagram schematically illustrating a semiconductor device according to an embodiment.

[0024] Related to Fig. 1, a semiconductor device 100 may include a functional block 110, a temperature sensor 120, and an adaptive body bias generator (ABBG) 130. Using the adaptive body bias generator 130, the semiconductor device 100 may adjust leakage currents of transistors of the functional block 110 by adjusting a body bias according to temperature.

[0025] Functional block 110 may be a series of circuits that perform a variety of operations according to data or a control signal sent to the semiconductor device. Functional block 110 may include a variety of circuits to perform an overall function of semiconductor device 110. The smallest logic unit constituting functional block 110 may be a transistor. A transistor included in functional block 110 may be, for example, a PMOS transistor or an NMOS transistor.

[0026] The functional module 110 can be supplied with a substrate bias voltage Vbb from the adaptive substrate bias generator 130. NMOS or PMOS transistors of the functional module 110 can be supplied with the substrate bias voltage Vbb, which varies according to temperature.

[0027] The temperature sensor 120 may detect an internal temperature of the semiconductor device 100. As a result of the detection, the temperature sensor 120 may transmit temperature information T to the adaptive substrate bias generator 130. The temperature sensor 120 may use a thermoelectric voltage sensor (or a thermocouple) that senses an open-circuit voltage (electromotive force) that changes with temperature, or a pyroelectric conductivity sensor to measure the resistance value that changes with temperature, etc. The temperature sensor 120 may use a bandgap reference type semiconductor sensor configured to use a current mirror type semiconductor sensor and a diode. However, the exemplary embodiments are not limited thereto.

[0028] The adaptive substrate bias generator 130 can supply the functional module 110 with the substrate bias voltage Vbb. The adaptive substrate bias generator 130 can generate the substrate bias voltage Vbb based on a real-time temperature T of the temperature sensor 120. A leakage current of a transistor consisting of a semiconductor can be very temperature-sensitive. In a test process, a substrate bias voltage can be fixed at a predetermined value. This allows the substrate bias voltage to be provided regardless of the installation environment in which the semiconductor device 100 is operated.

[0029] The adaptive substrate bias generator 130 of the exemplary embodiment can generate a substrate bias optimized for a temperature. The adaptive substrate bias generator 130 of the exemplary embodiments can generate the substrate bias such that a leakage current is minimal at a measured temperature. Alternatively, the adaptive substrate bias generator 130 of the exemplary embodiments can provide an approximate value of the substrate bias to fix a minimum leakage current at a measured temperature. In one embodiment, leakage currents of the transistors of the functional device 110 can be stably controlled even during a rapid change in operating temperature.

[0030] Basic parts of the semiconductor device 100 are described according to exemplary embodiments. However, it should be understood that the semiconductor device 100 includes numerous other components connected to the components described above. The semiconductor device 100 may be formed from a system-on-chip (SoC) that includes a plurality of functional components (hereinafter referred to as intellectual properties (IPs)). The semiconductor device 100 may be part of the system-on-chip or correspond to one of the numerous IPs.

[0031] The semiconductor device 100 of the exemplary embodiments can generate the substrate bias voltage Vbb for optimizing the amount of leakage current according to a change in operating temperature. The amount of leakage current flowing to the transistor can be minimized by applying the substrate bias voltage Vbb, which is optimized based on a current operating temperature T. The amount of leakage current of the semiconductor device 100 may increase as the semiconductor device is downsized. A leakage current of the semiconductor device 100 may be very temperature-sensitive. Consequently, an effect (e.g., thermal recirculation) that causes an increase in temperature and an increase in leakage current may degrade the semiconductor device performance. With one embodiment, a chain reaction can be prevented so that an increase in leakage current due to an increase in temperature does not occur.

[0032] Fig. 2 is a circuit diagram schematically showing transistors in a functional module made of Fig. 1 represents.

[0033] Related to Fig. 2, a functional module 110 may include a plurality of PMOS transistors 112 and a plurality of NMOS transistors 114. Although this is not Fig. 2, it should be clear that the functional block 110 contains various other components besides transistors.

[0034] The PMOS transistors 112 may include some or all of the PMOS transistors in the functional module 110. A control voltage VDD may be applied to sources of some of the PMOS transistors 112. Sources of some other PMOS transistors may be connected to a drain or source of a PMOS or NMOS transistor included in the functional module 110. Drains of the PMOS transistor may be grounded or may be connected to a drain or source of a PMOS or NMOS transistor included in the functional module 110. A PMOS substrate bias voltage Vbbp from an adaptive substrate bias generator 130 may be applied to the substrates of the PMOS transistors 112 included in the functional module 110.

[0035] The NMOS transistors 114 may include some or all of the NMOS transistors included in the functional module 110. Drains of some of the NMOS transistors 114 may be connected to a drain or source of a PMOS or NMOS transistor included in the functional module 110. Sources of the NMOS transistor 114 may be grounded, or connected to a drain or source of a PMOS or NMOS transistor included in the functional module 110. Drains of the PMOS transistor may be grounded, or connected to a drain or source of a PMOS or NMOS transistor included in the functional module 110. An NMOS substrate bias voltage Vbbn of the adaptive substrate bias generator 130 may be applied to the substrates of the NMOS transistors 112 included in the functional module 110.

[0036] Basic transistor components constituting a functional building block will now be described. Components supplied with a substrate bias voltage of the exemplary embodiments, however, should not be limited to the illustrated transistors. Substrate bias voltages Vbbp and Vbbn of the exemplary embodiments can be used to stably control operating characteristics that vary with temperature changes.

[0037] Fig. 3A and Fig. 3B are cross-sectional views of PMOS and NMOS transistors from Fig. 2. Fig. 3A is a sectional view of a PMOS transistor 112', Fig. Figure 3B is a cross-sectional view of an NMOS transistor 114'.

[0038] Related to Fig. 3A, an N-well 112a may be embedded in a P-type substrate P-Sub to form a PMOS transistor 112'. The N-well 112a may be formed by embedding an N-type dopant into the P-type substrate P-Sub. P+ dopant regions 112b forming a source and a drain of a PMOS transistor 112c may be formed in the N-well 112a. A P+ dopant region 112d providing a PMOS substrate bias voltage Vbbp may be formed in the N-well 112a. A gate insulating layer 112e and a gate electrode 112f may be sequentially layered. The gate insulating layer 112e may be formed from an oxide layer, a nitride layer, or a layered arrangement of the two. In addition, the gate insulation layer 112e may be made of a metallic oxide layer having a high dielectric constant, a coated stacked arrangement, or a mixed layer thereof.The gate electrode 112f may consist of a polysilicon layer or metal layer doped with impurities (P, As, B, etc.).

[0039] It is assumed that a gate voltage Vg is applied to the gate electrode 112f of the PMOS transistor 112', and drain and source voltages Vd and Vs are applied to the P+ impurity regions 112b and 112c. Furthermore, a PMOS substrate bias voltage Vbbp may be applied to the N+ impurity region 112d as a substrate electrode of the PMOS transistor 112'. At this time, the gate voltage Vg applied to the gate electrode may have a voltage value (e.g., VDD) capable of turning off the PMOS transistor 112'. The source voltage Vs applied to the source electrode may be a control voltage VDD, and the drain voltage VDD applied to the drain electrode may be a ground voltage Vss.

[0040] A current flowing to a drain terminal when voltages Vg, Vd, Vs, and Vbbp are applied to the corresponding electrodes may be referred to as steady-state leakage current IDS. The steady-state leakage current IDS may be affected by a bias state of the PMOS transistor 112'. To be specific, the steady-state leakage current IDS may be temperature-sensitive. In the event that an operating frequency of the semiconductor device 100 increases, an operating temperature of the semiconductor device 100 may increase. An increase in the steady-state leakage current IDS corresponding to a temperature may be relatively significant.

[0041] Related to Fig. 3B, N+ impurity regions 114b and 114c, which form a drain terminal and a source terminal, may be formed in a P-type substrate P-Sub to form an NMOS transistor 114'. The P-type substrate P-Sub may be provided with a P+ impurity region 114d for supplying a substrate bias voltage Vbbn. A gate insulating layer 114e and a gate electrode 114f may be continuously formed. If a negative substrate bias voltage Vbbn is applied, a reverse bias voltage is formed between the N+ impurity regions 114b and 114c and the P-type substrate P-Sub. In this case, a leakage current flowing between a source and a drain of the NMOS transistor 114' composed of the N+ impurity regions 114b and 114c is reduced.

[0042] Fig. 4 is a graph illustrating a substrate bias characteristic according to one embodiment. Referring to Fig. 4, an adaptable substrate bias generator 130 (relative to Fig. 1) of the exemplary embodiments vary a substrate bias voltage according to an operating temperature. The adaptive substrate bias generator 130 of the exemplary embodiments can minimize a leakage current of the semiconductor device operating at different temperatures by adjusting a substrate bias voltage according to a temperature.

[0043] A curve C1 can show a characteristic of the leakage current of a PMOS transistor at 25 °C. The value of the leakage current IDS of the PMOS transistor at 25 °C can be varied exponentially according to the PMOS substrate bias voltage Vbbp. Therefore, a voltage V1 at which the leakage current I1 generated at 25 °C is the lowest can be used as the base substrate bias voltage.

[0044] However, there may be a variety of examples where a semiconductor device 100 is operated at a higher temperature. In the case where the semiconductor device 100 is operated at a high speed, the temperature may rise up to 80°C. A curve C2 may show a change in a value of the leakage current according to a substrate bias voltage of the PMOS transistor at 85°C. However, at the same substrate bias voltage V1, a relatively large leakage current I3 may flow at 85°C. A point P1 may show this characteristic. However, at the substrate bias voltage V1, a minimal leakage current I1 may flow at 25°C. A point P3 may show this characteristic. If the substrate bias voltage V1 is fixed with a change in temperature, a large leakage current may flow due to an increase in temperature.

[0045] On the other hand, if a substrate bias voltage V2 is applied that specifies the lowest leakage current l2, an increase in the leakage current at 85°C may be small. According to one embodiment, a substrate bias voltage Vbbp that specifies a minimum leakage current may be applied at different temperatures at which the semiconductor device 100 is operated. Substrate bias voltages of transistors in a functional module 110 may be varied according to real-time temperature information provided by the temperature sensor 120 (with respect to Fig. 1). Accordingly, one embodiment makes it possible to prevent power consumption or failure of the semiconductor device due to leakage currents caused by a temperature change.

[0046] At a test level of the semiconductor device 100, a leakage current value may be measured at a temperature of 25°C. A substrate bias voltage V1 may then assume a value that specifies a minimum leakage current at 25°C. However, if the semiconductor device 100 is operated in an installation environment, an operating temperature may rise to a higher temperature. The semiconductor device 100 of the exemplary embodiments may be set to detect an operating temperature in an installation environment. The semiconductor device 100 of the exemplary embodiments may adaptively adjust a substrate bias voltage such that a minimum leakage current flows at a detected temperature.

[0047] Fig. 5 is a block diagram schematically illustrating a temperature sensor according to one embodiment. With reference to Fig. 5, a temperature sensor 120 may include a temperature sensor 122 and a temperature indicator generator 124.

[0048] The temperature sensor 122 can detect a current temperature. The semiconductor-based temperature sensor 122 can utilize the temperature dependence of a resistance or the temperature dependence of a reverse voltage. The temperature sensor 122 can output an electrical signal type of the temperature signal T(t), which has a value corresponding to the current temperature.

[0049] The temperature index generator 124 can convert an analog signal T(t) into digital information according to a detected current temperature. A semiconductor device 100 that performs a digital operation can detect a temperature as binary data. A binary data type of the temperature index Tn may be required to perform various operations for comparing or processing temperature information. Accordingly, the temperature index generator 124 can convert the analog signal T(t) into a binary temperature index Tn.

[0050] The temperature sensor 120 can provide the temperature signal T(t) or the temperature characteristic Tn, depending on where an adaptive substrate bias generator 130 is installed. If the adaptive substrate bias generator 130 generates a substrate bias voltage Vbb in an analog manner, the temperature sensor 120 can provide the temperature signal T(t). If the adaptive substrate bias generator 130 generates the substrate bias voltage Vbb in a digital manner, the temperature sensor 120 can provide the temperature characteristic Tn.

[0051] Fig. 6 is a block diagram schematically illustrating an adaptive substrate bias generator according to one embodiment. With reference to Fig. 6, an adaptive substrate bias generator 130 may include a lookup table 132 and a voltage generator 134.

[0052] The lookup table 132 can output a substrate bias voltage according to a temperature characteristic Tn. For example, in the case where a temperature characteristic T2 is output from a temperature sensor 120, mapping information regarding a substrate bias voltage V2 optimized for T2 can be stored in the lookup table 132. Also, when a temperature characteristic Tn corresponding to a specific temperature is input, the lookup table 132 can transmit a voltage characteristic Vn corresponding to the input temperature characteristic Tn to the voltage generator 134.

[0053] The voltage generator 134 may generate a substrate bias voltage according to a voltage characteristic Vn provided by the lookup table 132. The voltage generator 134 may selectively generate different values ​​of the substrate bias voltage in response to the voltage characteristic Vn. For example, the voltage generator 134 may consist of a voltage divider controlled by the voltage characteristic Vn.

[0054] As in Fig. As shown in Figure 4, the substrate bias voltage Vbb applied according to the temperature characteristic Tn may be a voltage adjusted to minimize leakage current. Accordingly, a semiconductor device 100 of the exemplary embodiments may adaptively output a bias voltage according to a temperature change using the adaptive substrate bias generator 130a.

[0055] Fig. 7 is a block diagram schematically illustrating an adaptive substrate bias generator according to another embodiment. Referring to Fig. 7, an adaptive substrate bias generator 130b may receive an analog temperature signal T(t) to generate an analog substrate bias Vbb(t). The adaptive substrate bias generator 130b may include a function generator 136.

[0056] The function generator 136 may consist of a function circuit for generating a substrate bias voltage Vbb(t) according to an input temperature signal T(t). For example, the function generator 136 may include a linear function having a constant slope and intercept of a substrate bias voltage Vbb(t) at a temperature signal T(t). For example, the function generator 136 may include passive elements having a linear function type of input / output characteristic. Accordingly, the implementation of the function generator may be simple.

[0057] The function generator 136 may include registers Reg1 and Reg2, which store constants a and b for implementing a function of an ideal substrate bias voltage Vbb(t) according to temperature. A temperature signal T(t) actually received is a variable that changes over time, but the constants a and b, which correspond to a slope and an intercept, may be inherent values ​​according to processing errors of semiconductor devices. The constants a and b may be measured at a measurement level and set as initial data. Alternatively, the constants a and b may be set as numerical values ​​selected as ideal values ​​through a test procedure.

[0058] By implementing a substrate bias voltage Vbb(t) as the output of a simple linear function type with respect to the temperature signal T(t), a substrate bias voltage generator can be used that has a high-speed response characteristic with a simple structure. In addition, a quantization error arising due to discrete conversion of the temperature signal T(t) into an analog signal can be minimized, so that the substrate bias voltage generator 130b has a high degree of accuracy.

[0059] Fig. Figure 8 is a diagram schematically showing an input / output characteristic of a function generator of Fig. 7. Related to Fig. 8, a function generator 136 (related to Fig. 7) show a substrate voltage characteristic of a PMOS transistor having different processing parameters.

[0060] A linear function, as shown in a curve C3, may show an input / output characteristic of a function generator set to the constants a2 and b2. The function generator 136 set to the constants a2 and b2 may generate a substrate bias voltage that increases linearly according to a temperature increase through a linear function having a slope a2 and an intercept b2. Referring to a curve C3, a substrate bias voltage b2 may be applied to a substrate of a PMOS transistor when the temperature is 0°C. As the temperature increases, the function generator 136 may generate the substrate bias voltage Vbb(t) that increases with a constant slope a2.

[0061] Curve C4 may show an input / output characteristic of the function generator 136 set to the constants a1 and b1. The function generator 136 set to the constants a1 and b1 may generate a substrate bias voltage Vbb(t) that increases linearly according to a temperature increase through a linear function having a slope a1 and an intercept b1. Referring to curve C4, a substrate bias voltage b1 may be applied to a substrate of the PMOS transistor when the temperature is 0°C. A voltage b1 may be lower than a voltage b2. This characteristic may indicate a difference between the leakage currents variably generated due to a production defect of a PMOS transistor. As the temperature increases, the function generator 136 may generate the substrate bias voltage Vbb(t) that increases at a constant slope b1.The curve C4, whose slope is smaller than that of curve C3, may indicate that a change in a leakage current due to a temperature change is smaller compared with a semiconductor device with the curve C3.

[0062] An example is described in which a substrate bias voltage of the waveform generator 136 is generated assuming a deviation, such as a manufacturing error. Although the substrate bias voltage of a PMOS transistor is described as an example, the exemplary embodiments can be applied to an NMOS transistor as well. In the case of an NMOS transistor, there is an output negative substrate bias voltage Vbb(t), the absolute value of which increases with a temperature increase.

[0063] Fig. 9 is a table schematically illustrating a method for setting constants of a function generator, according to one embodiment. With reference to Fig. 9, a semiconductor device 100 can be divided into, for example, five groups by transistor leakage currents. If a leakage current of an NMOS transistor and a leakage current of a PMOS transistor are marked by continuous alphabets, semiconductor chips are divided into SS, SF, NN, FS, and FF groups according to the leakage currents of the transistors. The SS group may indicate a case where leakage currents of NMOS and PMOS transistors are minimal. The SF group may indicate a case where a leakage current of an NMOS transistor is minimal and a leakage current of a PMOS transistor is maximal. The NN group may indicate a case where leakage currents of NMOS and TMOS transistors are moderate. The FS group may indicate a case where a leakage current of an NMOS transistor is maximal and a leakage current of a PMOS transistor is minimal. The SF group may indicate a case where leakage currents of NMOS and PMOS transistors are maximal.

[0064] When semiconductor chips are classified based on leakage current IDS, production yield can be improved by using adaptive temperature-based substrate bias control. If a temperature-based adaptive substrate bias technique is applied to a chip that is not a good chip, normal operation may be possible. Consequently, it is possible to reduce the defect rate due to varying production parameters.

[0065] NMOS and PMOS transistors can be assigned different constants to adaptively adjust a substrate bias voltage. For example, assume that (a1, b1) are used as constants for generating a substrate bias voltage Vbb(t) of a PMOS transistor in the SS group. In this case, (-a1, -b1) can be used as constants stored in a function generator 136 to generate a substrate bias voltage Vbb(t) of a PMOS transistor in the SS group. As a result, a substrate bias voltage Vbbn(t) applied to an NMOS transistor in the same group can be implemented by a symmetric function on a temperature axis TE(T) of a substrate bias voltage Vbbpn(t) of a PMOS transistor. The function setting method described above can be applied to the SS, SF, NN, FS, and FF groups. However, the exemplary embodiments are not limited thereto.Optimized functions of semiconductor devices can be implemented through various offsets and approximations.

[0066] Fig. 10 is a table schematically illustrating leakage current and percentage leakage loss based on temperature and substrate bias. Referring to Fig. 10, the percentage leakage is highest when the temperature is 25°C and the substrate bias is 1.1V (e.g., 100% leakage current). In contrast, when the substrate bias, as detected by temperature sensor 120, is 1.6V at 85°C, the percentage leakage is only 44%.

[0067] Fig. 11 is a graph illustrating an influence according to a substrate bias voltage. Referring to Fig. 11, a variation of the leakage current IDS according to temperature can be slightly reduced by applying a substrate bias voltage, according to one embodiment.

[0068] Curve C5 may indicate a change in the steady-state leakage current IDS of a semiconductor device that provides an ideal substrate bias voltage according to a temperature. An increase in the leakage current due to an increase in temperature may be unavoidable. However, an increased value of the leakage current IDS can be reduced by adjusting the substrate bias voltage to achieve an optimized value. Curve C6 may indicate a case where the substrate bias voltage is not adjusted according to a change in temperature. In this case, the steady-state leakage current IDS may vary greatly due to an increase in temperature.

[0069] With the exemplary embodiments in which a substrate bias voltage is controlled according to temperature, a transistor substrate can be supplied with an ideal substrate bias voltage at all temperatures at which the semiconductor device is used. Therefore, it is possible to minimize an increase in the leakage current IDS due to a change in the operating temperature. Power consumption of the semiconductor device can be reduced by lowering the leakage current IDS. Consequently, abnormal operation due to leakage current is prevented.

[0070] Fig. 12 is a flow diagram schematically illustrating a substrate biasing method according to one embodiment. Referring to Fig. 12, an adaptive substrate bias generator 130 (with respect to Fig. 1) provide a substrate bias voltage such that a leakage current is minimized at a current temperature of the semiconductor device 100.

[0071] In operation S110, a temperature sensor 120 may detect an internal operating temperature Temp of the semiconductor device 100. The adaptive substrate bias generator 130 may determine the internal operating temperature Temp of the semiconductor device 100 based on an operating temperature transmitted from the temperature sensor 120. The internal operating temperature Temp may be transmitted using a binary temperature index Tn or an analog temperature signal T(t).

[0072] In operation S120, the adaptive substrate bias generator 130 may select a substrate bias Vbb (Vbb) optimized for the current temperature based on temperature information transmitted from the temperature sensor 120. At this time, the adaptive substrate bias generator 130 may select a substrate bias for adjusting production parameters of NMOS and PMOS transistors and for minimal leakage current at a current operating temperature.

[0073] The adaptive substrate bias generator 130 can be manipulated in a manner as shown in Fig. 6 or Fig. 7. In the case where the binary temperature characteristic Tn is used in transmitting temperature information, the adaptive substrate bias generator 130 generates a substrate bias using a scanning operation (e.g., a lookup table). On the other hand, if the temperature information is transmitted using an analog temperature signal T(t), a substrate bias Vbb(t) corresponding to a temperature is provided in the form of a continuous function. The continuous function can take many forms and can be modeled as a linear function to simplify its implementation.

[0074] In operation S130, the adaptive substrate bias generator 130 may generate the selected substrate bias voltage Vbb and apply the substrate bias voltage Vbb to the functional block 110. Optimized substrate bias voltages capable of minimizing leakage current may be applied to the substrates of the PMOS and NMOS transistors of the functional block 110.

[0075] In operation S140, the adaptive substrate bias generator 130 may determine whether to continue measuring a temperature in real time or to stop controlling a substrate bias. In the case of a shutdown mode in which the power supply to the semiconductor device 100 is turned off, the adaptive substrate bias generator 130 may abort the entire operation. On the other hand, if the power supply is still present and the semiconductor device 100 is operating in normal operation, the method may proceed to operation S110 to measure a temperature.

[0076] Fig. 13 is a block diagram schematically illustrating a semiconductor device according to another embodiment. Referring to Fig. 13, a semiconductor device 200 may include a functional block group 210, a temperature sensor 220, and an adaptive substrate bias generator 230. The functional block group 210 may include a plurality of functional blocks 212, 214, 216, and 218 which are independently supplied with substrate voltages Vbb1, Vbb2, Vbb3, and Vbb4.

[0077] The functional block group 210 of the exemplary embodiments may include the functional blocks 212, 214, 216, and 218. Each of the functional blocks 212, 214, 216, and 218 may, for example, correspond to an intellectual property unit. Alternatively, each of the functional blocks 212, 214, 216, and 218 may be implemented by a functional block that is larger or smaller than an intellectual property of a system-on-chip. Since the functions of the functional blocks 212, 214, 216, and 218 in the semiconductor device 200 are different, their operating frequencies, operating speeds, and operating voltages may be different from each other. In this case, leakage current can be regulated by applying different substrate bias voltages to the functional blocks 212, 214, 216, and 218.

[0078] The temperature sensor 220 can be installed in a specific environment of the functional block group 210 to measure a temperature corresponding to the specific environment. The temperature sensor 220 can transmit the measured temperature Tc to the adaptive substrate bias generator 230.

[0079] The adaptive substrate bias generator 230 can generate substrate bias voltages optimized for the functional blocks 212, 214, 216, and 218 using temperature information from the temperature sensor 220. Substrate bias voltages Vbb1, Vbb2, Vbb3, and Vbb4 generated by the adaptive substrate bias generator 230 can be transmitted to the corresponding functional blocks.

[0080] Even if functional blocks are contained on the same chip and operate at the same temperature, leakage current values ​​may vary due to operating frequency, operating voltage, and frequency of a driving clock. The adaptive substrate bias generator 230 can apply different substrate bias voltages to the functional blocks 212, 214, 216, and 218, taking their operating characteristics into account.

[0081] As described above, semiconductor device 200 may apply different substrate bias voltages to functional devices 212, 214, 216, and 218 with different operating characteristics. In exemplary embodiments, at least two substrate bias voltages may have the same value, according to functional device characteristics.

[0082] Fig. 14 is a block diagram schematically illustrating a semiconductor device according to yet another embodiment. Referring to Fig. 14, a semiconductor device 300 may include a functional block group 310, a plurality of temperature sensors 322, 324, 326, and 328, and an adaptive substrate bias generator 330. The functional block group 310 may include a plurality of functional blocks 312, 314, 316, and 318 supplied with independent substrate voltages Vbb1, Vbb2, Vbb3, and Vbb4.

[0083] The functional block group 310 of the exemplary embodiments may include the functional blocks 312, 314, 416, and 318. Each of the functional blocks 312, 314, 416, and 318 may, for example, correspond to an intellectual property unit. Alternatively, each of the functional blocks 312, 314, 416, and 318 may be implemented by a functional block that is larger or smaller than an intellectual property of a system-on-chip. Since the functions of the functional blocks 312, 314, 416, and 318 in the semiconductor device 300 are different, their operating frequencies, operating speeds, and operating voltages differ from each other. In this case, leakage current can be controlled by applying different substrate bias voltages to the functional blocks 312, 314, 416, and 318.

[0084] Temperature sensors 322, 324, 326, and 328 may be included in function blocks 312, 314, 316, and 318 of function block group 310, respectively. The first temperature sensor 322 may be included in the first function block 312, the second temperature sensor 324 may be included in the second function block 314, the third temperature sensor 326 may be included in the third function block 316, and the fourth sensor 328 may be included in the fourth function block 318. Temperature sensors 322, 324, 326, and 328 may detect current temperatures Tc1, Tc2, Tc3, and Tc4 and transmit them to the adaptive substrate bias generator 330 in real time.

[0085] The adaptive substrate bias generator 330 can generate substrate bias voltages optimized to the function blocks 312, 314, 316, and 318 based on the temperature information from the temperature sensors 322, 324, 326, and 328. Substrate bias voltages Vbb1, Vbb2, Vbb3, and Vbb4 generated by the adaptive substrate bias generator 330 can be applied to the corresponding function blocks.

[0086] Operating temperatures of functional components may vary according to a power supply voltage, a clock frequency, etc. For example, in the case where semiconductor device 300 is a multi-core processor, the temperature of a core performing a main arithmetic operation may differ from that of a core performing a subordinate arithmetic operation. In this case, the substrate bias voltage can be applied independently according to the temperatures of the cores, thus successfully controlling leakage current and reducing power consumption.

[0087] Fig. 15 is a block diagram schematically illustrating a handheld terminal incorporating a semiconductor device according to one embodiment. Fig. 15, a handheld terminal 1000 may include an image processing module 1100, a wireless transceiver module 1200, an audio processing module 1300, an image file creation unit 1400, a memory 1500, a user interface 1600, and a control circuit 1700.

[0088] The image processing module 1100 may include an image sensor 1120, an image processor 1130, and a display unit 1140. The wireless transceiver module 1200 may include an antenna 1210, a transceiver 1220, and a modem 1230. The audio processing module 1300 may include an audio processor 1310, a microphone 1320, and a speaker 1330.

[0089] The handheld terminal 1000 may incorporate various types of semiconductor devices. An application processor that performs a function of the control circuit 1700 requires low power and is highly efficient. The control circuit 1700 may have a multi-core structure according to a scaled-down process. If a substrate bias method of the exemplary embodiments is incorporated, the amount of leakage current generated in the control circuit 1700 can be reduced. Since the leakage current is reduced, it is possible to reduce the power consumption of the control circuit 1700 and lower the temperature.

[0090] An example is described herein in which the substrate bias method of the exemplary embodiments is applied to the control circuit 1700. However, the exemplary embodiments are not limited thereto. A method of controlling a substrate bias according to temperature is also applicable, for example, to chips included in the image processing chip 1100, the wireless transceiver chip 1200, the audio processing chip 1300, and the image file generation unit 1400, etc.

[0091] Fig. 16 is a block diagram illustrating a computing system executing a substrate biasing process, according to one embodiment. Computing system 2000 may include a non-volatile storage device 2010, a CPU 2020, a RAM 2030, a user interface 2040, and a modem at 1050, such as a baseband chipset, electrically connected to a system bus 2060.

[0092] If the computer system 2000 is a mobile device, this may additionally include a battery (not shown) that powers the computer system 2000. Although this is not Fig. 16, the computer system 2000 may additionally include an application chipset, a camera image processor (CIS), a mobile DRAM, etc.

[0093] A method for controlling a substrate bias voltage according to a temperature can be applied to components such as the non-volatile storage device 2010, the CPU 2020, the RAM 2030, the user interface 2040, and the modem 2050.

[0094] A semiconductor device can be packaged using one of many different packages, such as PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP), etc.

[0095] Although the exemplary embodiments have been described, it will be apparent to those skilled in the art that numerous changes and modifications can be made without departing from the scope of the present invention, which is defined by the claims.

Claims

[1] Semiconductor device (100) comprising: a functional module (110) including a plurality of transistors; a temperature sensor (120) configured to detect an operating temperature of the functional module (110) in real time; and an adaptive substrate bias generator (130) configured to provide a substrate bias to adaptively adjust leakage currents from the transistors according to the sensed operating temperatures, wherein the substrate bias voltage is generated by the adaptive substrate bias voltage generator (130) according to the detected operating temperature and according to a predetermined minimum leakage current corresponding to the detected operating temperature. [2] The semiconductor device (100) of claim 1, wherein the adaptive substrate bias generator (130) is further configured to store value information of the substrate bias voltage corresponding to the operating temperature so that the predetermined minimum leakage current is minimal. [3] The semiconductor device (100) of claim 1, wherein the temperature sensor (120) is further configured to detect the operating temperature and output a temperature characteristic from binary data as a result of the detection, and wherein the adaptive substrate bias generator (130) comprises: a lookup table (132) configured to output a value index of the substrate bias voltage according to a temperature index; and a voltage generator (134) configured to generate the substrate bias voltage according to the value index output from the lookup table (132). [4] The semiconductor device (100) of claim 1, wherein the temperature sensor (120) is further configured to sense the operating temperature to provide an analog temperature signal. [5] The semiconductor device (100) of claim 4, wherein the adaptive substrate bias generator (130) comprises: a function generator (136) configured to generate a continuous function type of the substrate bias voltage based on the analog temperature signal. [6] The semiconductor device (100) of claim 5, wherein the function generator (136) is further configured to generate the substrate bias voltage according to the analog temperature signal, and the substrate bias voltage is generated based on a continuous linear function of the analog temperature signal. [7] The semiconductor device (100) of claim 6, wherein the function generator (136) includes a directory for setting a slope and an intercept of the continuous linear function. [8] The semiconductor device (100) of claim 7, wherein the slope or intercept is adjusted according to manufacturing parameters of the transistors. [9] A substrate biasing method of a semiconductor device, comprising: Detecting an operating temperature of the semiconductor device; Generating a substrate bias voltage for adjusting leakage currents from a plurality of transistors present in the semiconductor device at the operating temperature, wherein the substrate bias voltage is generated according to the detected operating temperature and according to predetermined minimum leakage currents corresponding to the detected operating temperature; and Applying the substrate bias voltage to the transistors of the semiconductor device. [10] The substrate biasing method of claim 9, wherein in detecting the operating temperature of the semiconductor device, the operating temperature is provided using an analog temperature signal. [11] The substrate biasing method of claim 10, wherein during the generation of the substrate bias, the substrate bias is generated as a continuous linear function based on the analog temperature signal. [12] The substrate biasing method according to claim 11, wherein an intercept and a slope of the continuous linear function are adjusted according to manufacturing characteristics of the semiconductor device. [13] The substrate biasing method of claim 9, wherein during the detection of the operating temperature of the semiconductor device, the operating temperature is provided using a digital temperature index. [14] The substrate biasing method of claim 13, wherein generating the substrate bias includes: Generating a value index according to the digital temperature index; and generating the substrate bias according to the value index. [15] The substrate biasing method of claim 14, wherein the value index corresponding to the digital temperature index is provided by a lookup table. [16] The substrate bias method according to claim 9, wherein the substrate bias has value information corresponding to the operating temperature so that the leakage currents of the transistors are minimal. [17] System on a chip, which includes: a variety of function blocks (212, 214, 216, 218); a temperature sensor (220) configured to detect a corresponding operating temperature of each of the functional modules (212, 214, 216, 218) in real time; and a substrate bias generator (230) configured to generate a corresponding substrate bias to adaptively adjust leakage currents from each of the functional devices (212, 214, 216, 218), wherein the substrate bias is generated by the substrate bias generator (230) according to the sensed operating temperature and according to predetermined minimum leakage currents corresponding to the sensed operating temperature. [18] The system-on-chip according to claim 17, wherein the substrate bias generator (230) is further configured to generate the corresponding substrate bias having a predetermined value according to the corresponding operating temperature of each of the functional devices (212, 214, 216, 218). [19] A system-on-chip according to claim 18, wherein the temperature sensor (220) comprises: a plurality of temperature sensors configured to detect a plurality of respective temperatures of the functional modules (212, 214, 216, 218). [20] The system-on-chip of claim 19, wherein the substrate bias generator (230) is further configured to generate a plurality of substrate bias voltages having different values ​​according to the respective operating temperatures of each of the functional devices (212, 214, 216, 218). [21] A system-on-chip according to claim 18, wherein the corresponding substrate bias voltage having the predetermined value during a test enables the leakage current to be minimized at the corresponding operating temperature. [22] The system-on-chip of claim 17, wherein the leakage currents correspond to a steady-state leakage current flowing into a drain terminal of a transistor included in each functional device (212, 214, 216, 218). [23] The system-on-chip according to claim 17, wherein the temperature sensor (220) includes at least one temperature sensor. [24] Function block (110), which contains: at least one NMOS transistor (114) configured to receive an NMOS bias voltage from an adaptive substrate bias voltage generator (130); at least one PMOS transistor (112) configured to receive a PMOS bias voltage from the adaptive substrate bias voltage generator (130); and a temperature sensor (120) configured to sense an operating temperature of the functional component (110) in real time and provide the sensed operating temperature to the adaptive substrate bias generator (130), wherein the NMOS bias voltage and the PMOS bias voltage are generated by the adaptive substrate bias generator (130) according to the sensed operating temperature and according to predetermined minimum leakage currents corresponding to the sensed operating temperature. [25] The functional module (110) of claim 24, wherein the functional module (110), the adaptive substrate bias generator (130), the at least one NMOS transistor (114) and the at least one PMOS transistor (112) are supplied with an operating voltage. [26] The functional module (110) of claim 24, wherein the adaptive substrate bias generator (130) comprises a lookup table (132) and a voltage generator (134) for converting the determined operating temperature into a substrate bias voltage. [27] The functional module (110) of claim 24, wherein the adaptive substrate bias generator (130) comprises a function generator (136) for converting the sensed operating temperature into a substrate bias voltage.

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