Transmitter / receiver and communication device that sends and receives data encoded by a transmission code

Abstract

A transceiver (20) that sends and receives data used in a communication system, wherein the data is encoded by a transmission line code and a signal level of the transmission line code changes in a bit duration at a predetermined transmission time, wherein the transceiver (20) has: a clock generator (51) that generates an internal clock used for internal circuitry; a timing generator (50) which, using the internal clock generated by the clock generator (51), generates a timing signal synchronized with a reference clock provided externally; a coding circuit (35) which, using the timing signal generated by the timing generator (50), encodes transmission data which is synchronized with the reference clock to be the transmission line code; and a signal shaping unit (36) which performs signal shaping of a signal waveform for predetermined transmission timing of the transmission data based on the reference clock, characterized by the fact that the signal shaping unit (36) includes: a release signal generation unit (361) that generates a release signal specifying a release period including a predetermined period; and a signal waveform composition circuit (362) which combines a signal waveform of the reference clock and a signal waveform of the transmission data such that the reference clock is selected during the release period specified by the release signal generated by the release signal generation circuit and the transmission data encoded by the coding circuit (35) is selected outside the release period and a selected signal is output to combine the signal waveform of the reference clock and the signal waveform of the transmission data.

Description

(Technical field)

[0001] The present disclosure relates to a communication system and in particular a transmitter-receiver and a communication device used for a communication system, wherein data encoded by a transmission line code whose signal level changes at a bit boundary is sent / received. (Description of the state of the art)

[0002] Traditionally, vehicle-based communication systems used transmission lines via a bus line, such as CAN (Control Area Network) or LIN (Local Interconnect Network). For example, a technical document entitled "On-vehicle Network System Detailed Explanation" by Michio Sato, CQ Publishing Co., Ltd., published on December 1, 2005, details the configuration of the aforementioned communication system using the bus line. The communication system generally includes a node, which forms the communication system; a transceiver, which sends / receives data via the transmission line; and a control unit, which executes communication with another node via the transceiver.

[0003] In this type of communication system, for efficient communication, it is desirable to synchronize the operations of transceivers located at the corresponding nodes for sending and receiving signals via a communication bus. As a method for synchronizing the operations of the transceivers located at the nodes, one node transmits (sends) a signal, encoded by the transmission line code and containing a clock component, to the transmission line. The other node extracts the clock component from the signal on the transmission line. The other node then processes the free-running clock generated at its own node (for example, by frequency division), creating a bus clock that is synchronized with the extracted clock component. Thus, the transceiver can operate based on the bus clock.

[0004] One configuration for such high-performance transceivers can be the use of an internal clock generated by an integrated, individual clock source. In this case, to process the signal provided by the control unit, the internal clock should be synchronized with a reference clock used for transmit data provided by the control unit and for generating the transmit data.

[0005] However, if encoding is performed using the internal clock synchronized with the reference clock, an error in the clock component contained in the encoded signal is essentially the same as an error in the internal clock superimposed on the reference clock.

[0006] A crystal oscillator, which generates a clock signal with a precise frequency, is generally used as the clock source for the control unit. However, to reduce manufacturing costs, an oscillator circuit with lower frequency accuracy than the crystal oscillator is used as the clock source for transceivers.

[0007] Consequently, at a node operating with the clock component extracted from the signal received via the transmission line, the accuracy of the clock regenerated from that component deteriorates, preventing the encoded transmission data received via the transmission line from being sampled with adequate timing. Therefore, the following problems arise in the communication system described above: the accuracy of the encoding process can degrade, and a higher communication speed cannot be guaranteed if the accuracy of the decoding process is to be ensured.

[0008] Reference is further made to US 6,937,664 B1 and DE 10 2013 214 888 A1, which were identified as prior art. In particular, US 6,937,664 B1 describes an object according to the preamble of claim 1. OVERVIEW OF THE INVENTION

[0009] The object of the invention is to provide a transmitter-receiver and a communication device in which a clock component, used for the reference of the operation, can be transmitted without degrading its accuracy.

[0010] The problem is solved by the subject matter of the independent claims. Advantageous further developments can be found in the dependent claims.

[0011] The transceiver according to this disclosure is used in a communication system in which coded transmission data is transmitted and received. This transmission data is encoded by a transmission line code whose signal level changes in one bit duration at a predetermined transmission time. The timing generator, using the internal clock generated by the clock generator, produces a timing signal synchronized with an externally provided reference clock. The encoding circuit, using the timing signal generated by the timing generator, encodes transmission data, synchronized with the reference clock, into the transmission line code. The waveform shaping unit shapes a waveform of the transmission data at the predetermined transmission time based on the reference clock.

[0012] According to the transmitter-receiver of the configuration described above, since the signal waveform of the transmission timing in the coded data transmitted to the transmission line does not contain an error in the internal clock, but does contain an error in the reference clock, a highly accurate clock component can be provided to the other nodes connected to the transmission line.

[0013] Consequently, the accuracy of decoding processing in a communication device that synchronizes to the clock component (transmission timing) extracted from the encoded data can be improved. Furthermore, the communication speed on the transmission line can be increased.

[0014] Since the waveform shaping unit can be configured to perform waveform shaping on the transmission data to be transmitted to the transmission line, the waveform shaping unit can, for example, be configured to apply waveform shaping to the timing signal generated by the timing generator and used for the coding unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] They show: Fig. 1 a block diagram representing an overall configuration of the vehicle-bound communication system; Fig. 2A an explanatory diagram representing a transmission line code used for communication via transmission line; Fig. 2B an explanatory diagram showing a communication framework that is sent / received via the transmission line; Fig. 2C is an explanatory diagram that represents a configuration of the communication frame that is sent / received between the UART (Universal Asynchronous Receiver Transmitter) and the transmitter / receiver; Fig. 3 a block diagram representing a configuration of a node; Fig. 4 a block diagram representing a configuration of a coding unit; Fig. 5A a timing diagram that schematically represents an operation of the coding unit at the clock master node; Fig. 5B a timing diagram that schematically represents an operation of the coding unit at an ordinary node; Fig. 6 a time diagram representing an operation of a signal shaping unit taking into account the influence of the error contained in the clock signal; and Fig. 7 a time diagram representing an operation of the signal shaping unit of the modification example. DETAILED DESCRIPTION OF THE PREFERRED EXECUTION FORMS (Execution Form)

[0016] With reference to the drawings, an embodiment of the present disclosure is described below. An overall configuration of the vehicle-mounted communication system 1, to which the present disclosure is adapted, is described below. As in Fig. As shown in Figure 1, the vehicle-integrated communication system 1 consists of several nodes 3 that are mutually interconnected by means of a transmission line 5, i.e., a bus line. The several nodes 3 include ECUs (electronic control units) that execute applications used for body control, i.e., body control ECUs, and associated equipment (e.g., switches, sensors) used to detect / control the vehicle's state.

[0017] From the multitude of nodes 3, the body control ECU includes a body / windshield wiper ECU, a seat ECU, a sliding door ECU, a mirror ECU, a rear door ECU, a lamp ECU 2, and a steering position control ECU (power steering position adjustment unit). Associated equipment includes a lamp switch, a windshield wiper switch, a lamp sensor, and a rain sensor.

[0018] Regarding the bus line, transmission line 5 is configured such that the signal level on transmission line 5 becomes low when a high-level signal (high-level signal, first level) and a low-level signal (low-level signal, second level) are simultaneously output from different nodes 3. Bus allocation is accomplished through this configuration of transmission line 5.

[0019] In transmission line 5, as in Fig. As shown in Figure 2A, PWM (pulse width modulation) encoding is used as the transmission line code, with the signal level changing from high to low at the bit boundary and from low to high between bit boundaries. That is, two logical values ​​(i.e., logic 1 / logic 0) are expressed using two codes with mutually distinct duty cycles. The signal with the lower low-level duty cycle (low-level duration) is defined as a recessive code (first code), and the signal with the higher low-level duty cycle is defined as the dominant code (second code). According to this embodiment, the recessive code corresponds to logic 1, and the dominant code corresponds to logic 0.In the transmission line code, a signal edge where the signal changes from a high level to a low level is defined as a threshold edge, and a signal edge where the signal changes from a low level to a high level is defined as an intermediate edge.

[0020] Specifically, in the recessive code, 1 / 3 of a bit length (bit duration) is low and 2 / 3 of the bit length is high. Similarly, in the dominant code, 2 / 3 of a bit length is low and 1 / 3 of the bit length is high. If the recessive code and the dominant code collide on transmission line 5, the dominant signal wins the allocation.

[0021] A period during which the recessive code remains active for longer than a predetermined period (for example, 11 bits according to the embodiment) is defined as the IFS (interframe space), and the state when the IFS is detected is defined as the idle state. According to the vehicle-based communication system 1, the corresponding node 3 is controlled so that it is able to transmit data when the transmission line 5 is in the idle state. Furthermore, according to the vehicle-based communication system 1, the system employs CSMA / CA (Carrier Sense Multiple Access with Collision Avoidance) access control, in which, after data transmission, a node 3 that has lost the allocation immediately stops the data transmission, and only the node 3 that has gained the allocation can continue with the data transmission.

[0022] As in Fig. As shown in Figure 2B, the communication framework used for communication between nodes 3 consists of a header field that specifies the data to be transmitted and a variable-length response field for transmitting the data specified by the header.

[0023] The header contains an identifier (ID) of the data to be transmitted, which is used to determine bus allocation based on its value. Meanwhile, the response field contains at least size information representing the data (response) size and a CRC (cyclic redundancy check) code used for error detection.

[0024] Node 3 includes one node that provides a clock signal to the other node via transmission line 5 (body / windshield wiper ECU), and another node that performs communication in synchronization with the clock signal provided via transmission line 5. Hereinafter, the former node is referred to as Clock Master 3a and the latter as Regular Node 3b. Clock Master 3a and Regular Node 3b differ in some aspects of their configuration; however, the two nodes have a similar overall configuration. Therefore, configurations commonly used for both nodes are primarily explained here, and configuration differences between the two nodes are further detailed below.

[0025] As in Fig. As shown in Figure 3, node 3 includes a signal processing unit 10 and a transceiver 20. The signal processing unit 10 performs various processing operations assigned to its own node 3, based on information obtained through communication between its own node 3 and the other node 3 via the transmission line 5. The transceiver 20 encodes transmission data TXD, which is NRZ (non-return to zero) encoded and transmitted by the signal processing unit 10, into transmission data TX, which is PWM encoded and to be output to the transmission line 5, and decodes received data RX, which is PWM encoded and received via the transmission line 5, into received data RXD, which is NRZ encoded and to be transmitted to the signal processing unit 10.

[0026] The signal processing unit 10 consists of a generally known microcomputer with a CPU (central processing unit), a ROM (read-only memory), a RAM (random access memory) and an IO (input / output) port, a UART (Universal Asynchronous Receiver Transmitter) 11 in which start-stop synchronization (asynchronous) serial communication is performed, and an oscillator circuit 12 consisting of a crystal oscillator that generates an operating clock used to operate the signal processing unit 10.

[0027] As in Fig. As shown in Figure 2C, UART 11 transmits / receives 10-bit block data as a single transmit / receive unit. The block data includes a start bit (low level) representing the start of the data, a stop bit (high level) representing the end of the data, and 8 bits of data inserted between the start and stop bits. It is important to note that the 8 bits of data are configured as LSB first transmission, meaning that the LSB (least significant bit) is transmitted first and the MSB (most significant bit) is transmitted last. UART 11 corresponds to the data generator.

[0028] The header, which is within the framework described above ( Fig. 2B) consists of a single data block in which 7 bits, which in the 8-bit data are exclusively the start / stop bits, are used as an ID (identification), and one bit, which is also in the 8-bit data, is used as a parity bit. The response field contains one or more data blocks in which size information is specified in the first data block.

[0029] In the clock master 3a, the oscillator circuit 12 generates, in addition to the operational clock described above, the reference clock CK, which is provided to the transceiver 20. The transceiver 20 has a communication speed (at 20 kbps) identical to the communication speed of the UART 11. The oscillator circuit 12 corresponds to the reference clock generator.

[0030] As in Fig. As shown in Figure 3, the transceiver 20 includes an encoding unit 31, which encodes the transmission data TXD; a decoding unit 32, which decodes the reception data RX; a digital processing unit 30, including an allocation unit or arbitration unit 33, which detects data collisions bit by bit; a transmission buffer 41, which outputs the transmission data TX, encoded by the digital processing unit 30, to the transmission line 5; an analog processing unit 40, including a reception buffer 42, which receives data on the transmission line 5; and a timing generation unit 50, which generates various timing signals necessary for the operation of the digital processing unit 30. The timing generation unit 50 corresponds to the timing generator.

[0031] The timing generation unit 50 includes an oscillator circuit 51 (clock generator) formed by a ring oscillator in which several inverter circuits are connected to form a ring shape. The oscillator circuit 51 shares an internal clock, which it generates to produce different timing signals synchronized with an object clock (that is, in the clock master 3a with the reference clock CK provided by the signal processing unit 10; in the normal node 3b with the received data RX obtained from the transmission line 5 via the receive buffer 42).

[0032] In particular, the timing generation unit 50 generates the first clock RCK and the second clock DCK as a timing signal, which are synchronized with the reference clock CK and have the same period as the reference clock CK. The first clock RCK has waveforms identical to the recessive code, and the second clock DCK has waveforms identical to the dominant code (cf. Fig. 5A).

[0033] Assuming that the error of the reference clock CK, generated by the oscillator circuit 12 of the signal processing unit 10, is α, and that the error of the internal clock, generated by the oscillator circuit 51 of the timing generation unit 50, is β (>α), the reference clock CK is affected only by the error α. However, since the first clock RCK and the second clock DCK are generated using both the reference clock CK and the internal clock, the first clock RCK and the second clock DCK are affected by the error α+β.

[0034] In the digital processing unit 30, the allocation unit 33 compares the transmission data TXD with the reception data RXD bit by bit and stops supplying the coding unit 31 with the transmission data TXD if the signal levels between the transmission data TXD and the reception data RXD do not match.

[0035] The decoding unit 32 decodes the received data RX (PWM code) obtained by the receive buffer 42 into NRZ code and provides the decoded received data RXD to the signal processing unit 10. Specifically, the decoding unit 42 generates an edge detection signal ED, representing the detection timing of a falling edge of the received data RX (i.e., a threshold edge representing the bit boundary), measures a low-level duration of the received data RX starting from the initial point, which is determined by the timing of the threshold edge represented by the edge detection signal ED. The decoding unit 32 then decodes the received data RX to be logic 1 if the measurement result is greater than or equal to the decoding threshold T-th, and decodes the received data RX to be logic 1 if the measurement result is less than the threshold T-th.

[0036] Regarding coding unit 31, since the clock master 3a and the regular node 3b differ partially in their configuration, the configurations of both units are considered individually and explained below. As in Fig. As shown in Figure 4, the coding unit 31 of the clock master 3a includes a coding circuit 35, a release signal generation unit 361 and a signal waveform shaping unit 36, which has a signal waveform composition circuit 362.

[0037] As in Fig. As shown in Figure 5A, the coding circuit 35 selects the first clock signal RCK when the transmission data TXD (NRZ code) provided by the signal processing unit 10 is logic 1, and selects the second clock signal DCK when the transmission data TXD is logic 0, thereby generating a coded signal TXr. It should be noted that logic 1 is coded as a recessive signal and logic 0 is coded as a dominant signal.

[0038] The coding circuit 35 is configured such that its input terminal becomes logic 1 when no transmission data TXD is received from the signal processing unit 10. That is, if the signal processing unit 10 is not transmitting data, the coding unit 31 of the clock master 3a continues to output recessive code, which is used for a clock signal provided to the other nodes.

[0039] The enable signal generation unit 361 of the signal waveform shaping unit 36 ​​generates an enable signal based on the edge detection signal ED and the reference clock CK. This enable signal transitions to the active level (e.g., the high level) when the bit boundary is likely to appear. It should be noted that a period during which the enable signal EN transitions to the active level is defined as an enable period.

[0040] In particular, as in Fig. As shown in Figure 6, the enable signal generation unit 361 is configured such that the enable signal level EN changes from an active level to an inactive level when the first predetermined period elapses from a threshold detection time specified by the edge detection signal ED, and the enable signal level EN changes from an inactive level to an active level when the second predetermined period elapses from a rising edge of the reference clock CK. It should be noted that the first predetermined period is set to be longer than a period corresponding to the falling edge of the signal TXr and shorter than a low-level duration of the recessive code. Likewise, the second predetermined period is set to be longer than a period in which the dominant code is reliably high-level (i.e.,Low-level duration + period of the rising edge of the signal level) is, and is shorter than one period of the reference clock CK.

[0041] The enable signal EN is set to be active during a predetermined period (a period that does not include a rising edge) around a boundary edge (falling edge) that represents the bit boundary of the signal TXr.

[0042] Meanwhile, the waveform composition circuit 362 combines the signal TXr and the reference clock CK based on the enable signal EN. Specifically, the waveform composition circuit 362 selects the signal TXr when the enable signal EN has an inactive level (outside the enable period), selects the reference clock CK when the enable signal EN is active (within the enable period), and outputs the selected signal, thereby generating transmission data TX in which waveforms of both signals are combined.

[0043] This means that since the boundary edge (falling edge) and the intermediate edge (rising edge) of the signal TXr are generated with the first clock RCK or the second clock CDK, these edges are affected by the errors α+α+β. However, since the boundary edge of the transmitted data TX is generated with the reference clock CK, the transmitted data TX is not affected by the error β of the internal clock, but only by the error α.

[0044] Meanwhile, the coding unit 31 of the regular node 3b consists only of the coding circuit 35 without the signal shaping unit 36 ​​(not shown). As in Fig. As shown in Figure 5C, the coding circuit 35 outputs a high-level signal of one bit length as transmit data TX when the transmit data TXD, provided by the signal processing unit 10, is logic 1. Likewise, the coding unit 31 outputs a signal generated by the dominant code (second clock DCK) as transmit data TX when the transmit data TXD is logic 0.

[0045] If the transmission data TX, which is encoded by the regular node 3b, is superimposed on the recessive code on transmission line 5, which is output by the clock master 3a, the recessive code is transmitted directly on transmission line 5 for one period corresponding to logical 1 and the dominant code is transmitted on transmission line 5 for one period corresponding to logical 0.

[0046] As described above, since the transmit receiver 20 of the clock master 3a is configured to apply waveform shaping using the reference clock CK to the waveforms of the edge of the transmission data TX transmitted to the transmission line 5, a timing error represented by the edge of the transmission data TX can be suppressed within an error range contained in the reference clock CK, whose frequency has high accuracy.

[0047] Clock master 3a can provide a highly accurate clock component (i.e., edge-timed timing) to regular node 3b, which is connected to transmission line 5. Consequently, the accuracy of processing operations, such as decoding at regular node 3b, which operates synchronously with the clock component extracted from the signal on transmission line 5, can be improved. In other words, the communication speed on transmission line 5 can be increased without compromising the accuracy of processing operations. (Other embodiments)

[0048] One embodiment of the present disclosure is explained above. The present disclosure is not limited to the embodiment explained above, but various modifications are possible without departing from the scope of the present disclosure.

[0049] For example, the low-level period corresponding to a transmission line code bit length defined as 1 / 3 of the bit length for the recessive code and 2 / 3 of the bit length for the dominant code is not limited to these ratios. For example, 1 / 4 of the bit length can be used for recessive code and 1 / 2 of the bit length for dominant code.

[0050] According to the embodiment described above, the release period (a period in which the release signal is active) is defined such that it only includes the boundary edge. However, as described in Fig. As shown in Figure 7, the reference clock CK is set to have the same signal waveforms as the recessive code, and the release period can be set to be longer so that it includes not only the boundary edge but also the intermediate edge of the recessive code.

[0051] In this case, the signal level of the enable signal EN can be set such that, during an intermediate time between the intermediate edge of the recessive code and the intermediate edge of the dominant code, the signal level changes from the active level to the inactive level, and during an intermediate time between the intermediate edge of the dominant codes and the limit edge, it changes from the inactive level to the active level. The enable signal EN can be generated based on the edge detection signal ED and the timing of the falling edge of the reference clock CK, similar to the embodiment described above, or, as shown in the dashed line, it can be generated based on the timing of the falling edge of the reference clock CK without using the edge detection signal ED.

[0052] Thus, if a release range determined by the release signal EN is extended, since an error β of the internal clock does not affect the boundary edge and the rising edge of the recessive code, the accuracy of the decoding processing can be further improved compared to the embodiment described above, in which the intermediate edges of the recessive code and the dominant code exhibit the error α+β.

[0053] According to the embodiment described above, the transmission data TX is defined such that the signal waveforms of the bit boundary of the signal TXr, which is encoded using the first clock RCK and the second clock DCK, are replaced by the reference clock CK; however, the transmission data TX can be defined such that a signal is encoded using signal waveforms of the bit boundary of the first clock RCK or the second clock DCK, which are replaced by the reference clock CK.

[0054] According to the embodiment described above, the pulse-width modulation code is used for the transmission code, and the transmission timing is determined as a timing of the edge representing the bit boundary. The edge waveforms are then shaped with the waveforms of the reference clock CK (i.e., waveform shaping). However, the transmission timing is not limited to edge timing. For example, if a transmission code is used in which a signal level changes at a predetermined timing during a bit duration consisting exclusively of edge transitions, edge timings that occur periodically within the bit duration can be used as the transmission timing.

[0055] The invention can be summarized as a transmitter-receiver that sends and receives data used in a communication system in which the data is encoded by a transmission line code and a signal level of the transmission code changes in a bit duration at a predetermined transmission time.The transceiver includes: a clock generator that produces an internal clock used for internal circuitry; a timing generator that, using the internal clock generated by the clock generator, produces a timing signal synchronized with an externally provided reference clock; a coding circuit that, using the timing signal generated by the timing generator, encodes transmission data synchronized with the reference clock to form the transmission line code; and a waveform shaping unit that performs waveform shaping of a signal waveform to achieve predetermined transmission timing of the transmission data based on the reference clock.

Claims

[1] Transceiver (20) which sends and receives data which is used in a communication system, wherein the data is encoded by a transmission line code and a signal level of the transmission line code changes in a bit duration at a predetermined transmission time, wherein the transceiver (20) has: a clock generator (51) that generates an internal clock used for internal circuitry; a timing generator (50) which, using the internal clock generated by the clock generator (51), generates a timing signal synchronized with a reference clock provided externally; a coding circuit (35) which, using the timing signal generated by the timing generator (50), encodes transmission data which is synchronized with the reference clock to be the transmission line code; and a signal shaping unit (36) which performs signal shaping of a signal waveform for predetermined transmission timing of the transmission data based on the reference clock, characterized by , that the signal shaping unit (36) includes: a release signal generation unit (361) that generates a release signal specifying a release period including a predetermined period; and a signal waveform composition circuit (362) which combines a signal waveform of the reference clock and a signal waveform of the transmission data such that the reference clock is selected during the release period specified by the release signal generated by the release signal generation circuit and the transmission data encoded by the coding circuit (35) is selected outside the release period and a selected signal is output to combine the signal waveform of the reference clock and the signal waveform of the transmission data. [2] Transceiver (20) according to claim 1, characterized by , that the predetermined transmission timing is a boundary edge timing that represents a bit boundary of the transmission line code. [3] Transceiver (20) according to claim 2, characterized by , that The transmission line code consists of a pulse width modulation code that expresses two values ​​depending on a difference in duty cycles; The pulse width modulation code includes a first code and a second code, wherein the first code and the second code each have a period determined from a boundary edge representing the bit boundary to an intermediate edge representing a timing at which a signal level changes in response to a duty cycle, and the period of the first code is shorter than that of the second code; The reference clock contains a signal waveform that is identical to a signal waveform of the first code; and the enable signal generation unit (361) is configured to generate the enable signal such that the enable period includes a timing in which the intermediate edge of the first code occurs. [4] Communication device comprising: the transmit receiver (20) according to one of the preceding claims; a reference clock generator (12) that generates a reference clock; a data generator (11) that generates transmission data synchronized with the reference clock generated by the reference clock generator (12).

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