Resistive RAM cells with bottom electrodes and method of manufacturing the same

Abstract

Resistive RAM cell (300) comprising: a lower electrode (304) disposed over a lower metal interconnect layer (302) surrounded by a lower dielectric interlayer (204); a lower dielectric layer (306) disposed over the lower metal interconnect layer or the lower interlayer dielectric layer (204); a dielectric data storage layer (308) having a variable resistance, wherein a lower surface of the dielectric data storage layer (308) is adjacent to upper surfaces of the lower dielectric layer (306) and the lower electrode (304); and an upper electrode (312) disposed above the dielectric data storage layer (308), wherein the dielectric data storage layer (308) and the top electrode (312) comprise non-planar layers; wherein the lower electrode (304) has a flat upper surface connected to a lower surface by curved side walls; and wherein the lower surface comprises a curved surface such that the side walls and the lower surface form a continuous curved surface extending between opposite sides of the planar upper surface.

Description

BACKGROUND

[0001] Many of today's electronic devices include electronic memory configured to store data. Electronic memory can be volatile memory or non-volatile memory. Volatile memory stores data while receiving power, while non-volatile memory can store data when the power is turned off. Resistive RAM (RRAM) is a promising candidate for next-generation non-volatile memory technologies due to its simple structure and the processing technology used, which is compatible with CMOS logic. An RRAM cell comprises a dielectric data storage layer that has a variable resistance and is sandwiched between two electrodes arranged in back-end-of-the-line (BEOL) metallization layers.

[0002] From the documents US 2013 / 0 009 125 A1, US 2009 / 0 140 234 A1, US 2012 / 0 305 880 A1, US 2010 / 0 096 613 A1 and US 2010 / 0 015 755 A1 devices are known which comprise planar or substantially planar data storage layers and planar or substantially planar upper electrode layers arranged thereover.

[0003] A contact structure with a non-planar layer having a variable resistance and a non-planar electrode lying thereon is known from the document DE 10 2004 019 862 A1 and the document DE 102 97 198 B4.

[0004] The task is to improve the corresponding storage. SUMMARY OF THE INVENTION

[0005] The object is achieved by a resistive RAM cell according to claim 1, a resistive RAM cell according to claim 9 and a method for forming a resistive RAM cell according to claim 15. Further embodiments of the invention are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. Note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of description. Fig. Figure 1 shows a cross-sectional view of some embodiments of a resistive RAM (RRAM) cell having a bottom electrode with a flat top surface, resulting in low leakage current. Fig. 2 shows a cross-sectional view of some embodiments of the RRAM cell having a bottom electrode disposed in a bottom dielectric layer. Fig. 3 shows a cross-sectional view of some embodiments of the RRAM cell having a bottom electrode disposed in a bottom metal interconnect layer. Fig. 4 shows a flowchart of some embodiments of a method for forming an RRAM cell having a bottom electrode comprising a planar top surface connected to a bottom surface by curved sidewalls. Fig. 5 shows a flowchart of some alternative embodiments of a method for forming an RRAM cell having a bottom electrode disposed in a bottom dielectric layer. Fig. 6-13 show cross-sectional views of some alternative embodiments illustrating a method of forming an RRAM cell having a bottom electrode disposed in a bottom dielectric layer. Fig. 14 shows a flowchart of some alternative embodiments of a method for forming an RRAM cell having a bottom electrode disposed in a bottom metal interconnect layer. Fig. 15-24 show cross-sectional views of some alternative embodiments illustrating a method of forming an RRAM cell having a bottom electrode disposed in a bottom metal interconnect layer. DETAILED DESCRIPTION

[0007] The following disclosure contemplates many different embodiments or examples for implementing various features of the specified subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features need not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for simplicity and clarity and as such does not impose any relationship between the various embodiments and / or configurations described.

[0008] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated in addition to the orientation shown in the figures. The device may be differently oriented (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may also be interpreted accordingly.

[0009] Resistive RAM (RRAM) cells have a bottom electrode separated from an overlying top electrode by a dielectric data storage layer having a variable resistance. Typically, RRAM cells are separated from an underlying metal layer by a bottom dielectric layer that includes an opening that provides contact between the bottom electrode and the underlying metal interconnect layer. The bottom electrode is formed over the opening, resulting in the bottom electrode having a "U-shape" that extends from within the opening to a position above the bottom dielectric layer.

[0010] A bottom electrode with such a U-shape can lead to a variety of problems in RRAM cells. For example, the distance between extensions of the bottom electrode, which lies above the bottom dielectric layer, and the top electrode is relatively small and can induce leakage currents between the bottom electrode and the top electrode, leading to degradation of the RRAM cell. To reduce leakage currents in an RRAM cell, the top electrode is usually flanked by insulating sidewall spacers, which increase the leakage current path (i.e., the distance through which a leakage current travels) between the top electrode and the extension of the bottom electrode. However, insulating sidewall spacers increase the height and width of the RRAM cell, making integration into advanced technology nodes (e.g., the 28 nm node, the 20 nm node, etc.) more difficult. In addition, the U-shape can lead to small trenches.“micro-trenching”) in the underlying metal interconnect layer, which can lead to failure of the RRAM after many cycles (e.g. 10,000 cycles).

[0011] Thus, the present disclosure relates to a resistive random access memory (RRAM) cell having a bottom electrode with a flat top surface that provides low leakage currents in the RRAM cell without the use of insulating sidewall spacers, and an associated formation method. In some embodiments, the RRAM cell includes a bottom electrode disposed over a bottom metal interconnect layer surrounded by a bottom interlayer dielectric (ILD) layer. A bottom dielectric layer is disposed over the bottom metal interconnect layer and / or the bottom ILD layer. A data storage dielectric layer having a variable resistance is disposed over the bottom dielectric layer and the bottom electrode, and a top electrode is disposed over the data storage dielectric layer.Placing the data storage dielectric layer on the bottom dielectric layer increases the leakage current path between the bottom electrode and the top electrode, providing low leakage current for the RRAM cell without using sidewall spacers that increase the size of the RRAM cell.

[0012] Fig. Figure 1 shows a cross-sectional view of a resistive RAM (RRAM) cell 100 having a bottom electrode 102 with a flat top surface that provides low leakage current.

[0013] The RRAM cell 100 includes a bottom electrode 102 disposed over a bottom metal interconnect layer 108 surrounded by a bottom interlayer dielectric (ILD) layer 110. The bottom electrode 102 includes a top surface 102b and a bottom surface 102a. According to the invention, the top surface 102b includes a planar surface connected to the bottom surface 102a by curved sidewalls 102s (i.e., sidewalls that have a slope that changes depending on the height). According to the invention, the bottom surface 102a is also curved, such that the sidewalls 102s and the bottom surface 102a form a continuous curved surface extending between opposite sides of the top surface 102b.

[0014] A bottom dielectric layer 112 is disposed over the bottom metal interconnect layer 108 and / or the bottom interlayer dielectric layer (ILD) 110. A variable resistance dielectric layer 104, configured to store a data state dependent on an applied voltage, overlies the top surface 102b of the bottom electrode 102 and the bottom dielectric layer 112. A top electrode 106 is disposed over the variable resistance dielectric layer 104. Disposing the variable resistance dielectric layer 104 on the bottom dielectric layer 112 provides a relatively large leakage current path d1 (i.e., distance through which a leakage current must travel) between the bottom electrode 102 and the top electrode 106, thereby providing low leakage current for the RRAM cell 100.

[0015] In some embodiments, a top dielectric layer 114 is disposed over the top electrode 106. The top dielectric layer 114 extends continuously from a position above the top electrode 106 to positions adjacent to sidewalls of the top electrode 106 and the variable resistance dielectric layer 104. The top dielectric layer 114 separates the top electrode 106 and the variable resistance dielectric layer 104 from an upper interlayer dielectric layer (ILD) 120 surrounding a top metal interconnect layer 117 having a top metal via 116 and a top metal wire 118.

[0016] Fig. 2 shows a cross-sectional view of some embodiments of the RRAM cell 200 having a bottom electrode 206 disposed in a bottom dielectric layer 208.

[0017] The RRAM cell 200 includes a bottom electrode 206 disposed on a bottom metal interconnect layer 202 surrounded by a bottom interlayer dielectric (ILD) layer 204 in a BEOL metallization stack. In some embodiments, the bottom metal interconnect layer 202 may comprise one of a plurality of metal interconnect layers disposed between the bottom electrode 206 and an underlying semiconductor substrate (not shown).

[0018] The bottom electrode 206 includes a planar upper surface connected to a lower surface by curved sidewalls. The curved sidewalls are adjacent to a surrounding lower dielectric layer 208. The planar upper surface of the bottom electrode 206 and an upper surface of the surrounding lower dielectric layer 208 are aligned along a planar surface 207. In some embodiments, the bottom electrode 206 may include a first bottom electrode layer 206a and a second bottom electrode layer 206b. The first bottom electrode layer 206a includes a U-shaped layer adjacent to the bottom metal interconnect layer 202 and the bottom dielectric layer 208. The second bottom electrode layer 206b is embedded in the opening of the U-shape of the first bottom electrode layer 206a. The first and second lower electrode layers 206a and 206b have flat upper surfaces arranged along the planar surface 207.

[0019] A variable resistance dielectric data storage layer 210 is disposed on the upper surface of the lower electrode 206 and the lower dielectric layer 208. Depending on an applied voltage, the data storage dielectric layer 210 undergoes a reversible change between a high resistance state corresponding to a first data state (e.g., a "0") and a low resistance state corresponding to a second data state (e.g., a "1"). For example, a voltage applied to the data storage dielectric layer 210 induces conductive paths (e.g., oxygen vacancies) to form in the data storage dielectric layer 210, thereby reducing the resistance of the data storage dielectric layer 210.The dielectric data storage layer 210 has a width that is greater than the width of the bottom electrode, so that the dielectric data storage layer 210 extends beyond the bottom electrode on opposite sides.

[0020] In some embodiments, a cap layer 212 may be disposed over the dielectric data storage layer 210. The cap layer 212 is configured to store oxygen, which may facilitate changes in resistance in the dielectric data storage layer 210. In some embodiments, the cap layer 212 may comprise a metal or a metal oxide having a relatively low oxygen content.

[0021] A top electrode 214 is disposed above the cap layer 212. The top electrode 214, the cap layer 212, and the data storage dielectric layer 210 include sidewalls that are laterally aligned with each other (i.e., along a vertical plane). Because the data storage dielectric layer 210 extends beyond the bottom electrode 206 on opposite sides, the top electrode 214 is separated from the bottom electrode 206 by a relatively large leakage current path d1. The relatively large leakage current path d1 reduces the leakage current in the RRAM cell 200 without the use of sidewall spacers, thereby allowing the RRAM cell 200 to be smaller in size than RRAM cells that use sidewall spacers.

[0022] A mask layer 216 (e.g., a hard mask layer) is disposed over the top electrode 214 at positions adjacent to opposite sidewalls of a top metal via 222. The mask layer 216 has sidewalls 216a aligned with sidewalls of the top electrode 214. In some embodiments, the mask layer 216 may comprise a silicon oxynitride (SiON) hard mask layer or a silicon dioxide (SiO2) hard mask layer. In other embodiments, the mask layer 216 may comprise a hard mask layer that substantially contains no oxygen. For example, the mask layer 216 may comprise a silicon carbide (SiC) hard mask layer, a silicon nitride (SiN) hard mask layer, or a composite dielectric film that substantially contains no oxygen. Although the use of a mask layer 216 that substantially contains no oxygen is described with reference to the RRAM cell of Fig. 2, it should be appreciated that the use of a mask layer 216 having substantially no oxygen is not limited to such an RRAM cell structure. Rather, the use of a mask layer 216 having substantially no oxygen may be used with any RRAM cell structure (e.g., an RRAM cell having any bottom electrode shape, an RRAM cell having a bottom electrode extending beyond the bottom dielectric layer 208, etc.).

[0023] A top dielectric layer 218 is disposed on the mask layer 216. The top dielectric layer 218 extends continuously along sidewalls of the data storage dielectric layer 210, the cap layer 212, the top electrode 214, and the mask layer 216 from a first position adjacent to an upper surface of the mask layer 216 to a second position adjacent to an upper surface of the bottom dielectric layer 218. The top dielectric layer 218 separates the data storage dielectric layer 210, the cap layer 212, the top electrode 214, and the mask layer 216 from an upper interlayer dielectric layer (ILD) 220. The upper ILD layer 220 surrounds a top metal interconnect layer 221 disposed on the top electrode 214.The upper metal interconnect layer 221 includes the upper metal via 222, which extends from the upper electrode 214 through the mask layer 216 and the upper dielectric layer 218 to an upper metal wire 118.

[0024] Fig. 3 shows a cross-sectional view of some embodiments of an RRAM cell 300 having a bottom electrode 304 disposed in a bottom metal interconnect layer 302.

[0025] The RRAM cell 300 includes a bottom electrode 304 disposed within a bottom metal interconnect layer 302 surrounded by a bottom interlayer dielectric (ILD) layer 204. The bottom electrode 304 includes a flat top surface connected to a curved bottom surface by curved sidewalls such that the sidewalls and the bottom surface form a continuous curved surface extending between opposite sides of the flat top surface. The bottom surface of the bottom electrode 304 has a convex curvature adjacent to a concave top surface of the bottom metal interconnect layer 302. The flat top surface of the bottom electrode 304 is aligned with a top surface of the bottom ILD layer 204 along a planar surface 305.In some embodiments, the bottom electrode 304 may include a first bottom electrode layer 304a having a U-shaped layer disposed on the bottom metal interconnect layer 302, and a second bottom electrode layer 304b embedded in the opening of the U-shape of the first bottom electrode layer 304a. The first and second bottom electrode layers 304a and 304b have flat top surfaces disposed along the planar surface 305.

[0026] A bottom dielectric layer 306 is disposed over the bottom ILD layer 204 and the bottom electrode 304. The bottom dielectric layer 306 includes an opening that provides contact between the bottom electrode 304 and a data storage dielectric layer 308. The data storage dielectric layer 308 is disposed over the opening, resulting in the data storage dielectric layer 308 having a non-planar topography extending from within the opening to a position above the bottom dielectric layer 306. A cap layer 310 having a non-planar topography is disposed over the data storage dielectric layer 308, and a top electrode 312 having a non-planar topography is disposed over the data storage dielectric layer 308.Because the lower dielectric layer 306 is disposed between the upper electrode 312 and the lower electrode 304, the upper electrode 312 is separated from the lower electrode 304 by a relatively large leakage current path d1. The relatively large leakage current path d1 reduces the leakage current in the RRAM cell 300 without the use of sidewall spacers, thereby allowing the RRAM cell 300 to be smaller in size than RRAM cells that use sidewall spacers.

[0027] A mask layer 314 having a non-planar topography is disposed over the top electrode 312. In some embodiments, the mask layer 314 may comprise a hard mask layer having substantially no oxygen. A top dielectric layer 316 extends continuously from a first position adjacent to an upper surface of the mask layer 314 to a second position adjacent to an upper surface of the bottom dielectric layer 306. The top dielectric layer 316 has a first side adjacent to the data storage dielectric layer 308, the cap layer 310, the top electrode 312, and the mask layer 314, and a second side adjacent to an upper interlayer dielectric layer (ILD) 318.The upper ILD layer 318 surrounds an upper metal interconnect layer 319, which includes an upper metal via 320 configured to extend from the upper electrode 312 through the mask layer 314 and the upper dielectric layer 316 to an upper metal wire 118.

[0028] Fig. 4 shows a flowchart of some embodiments of a method 400 for forming an RRAM cell having a bottom electrode with a flat top surface that provides low leakage current.

[0029] At 402, a bottom electrode is formed over a bottom metal interconnect layer provided in a bottom interlayer dielectric layer (ILD). In some embodiments, the bottom electrode may have a planar top surface connected to a bottom surface via curved sidewalls.

[0030] At 404, a lower dielectric layer is formed over the lower metal interconnect layer or the lower ILD layer.

[0031] At 406, a variable resistance dielectric data storage layer is formed over the bottom dielectric layer and the bottom electrode. In some embodiments, the dielectric data storage layer may be formed on and in direct contact with the bottom dielectric layer and the bottom electrode.

[0032] At 408, a top electrode is formed over the dielectric data storage layer.

[0033] At 410, an upper metal interconnect layer is formed over the upper electrode.

[0034] Fig. 5 shows a flowchart of some embodiments of a method 500 for forming an RRAM cell having a bottom electrode disposed in a bottom dielectric layer.

[0035] While the disclosed methods (e.g., methods 400, 500, and 1400) are shown and described below as a sequence of acts or events, it should be understood that the shown order of these acts or events is not intended to be limiting. For example, some acts may occur in a different order and / or concurrently with other acts or events than those shown and / or described herein. In addition, not all acts shown need implement one or more aspects or embodiments of this description. Further, one or more acts shown herein may be performed in one or more separate acts and / or phases.

[0036] At 502, a lower metal interconnect layer is formed in a lower interlayer dielectric layer (ILD) disposed over a semiconductor substrate.

[0037] At 504, a lower dielectric layer is formed over the lower metal interconnect layer and / or the lower ILD layer.

[0038] At 506, the lower dielectric layer is selectively etched to form an opening extending through the lower dielectric layer to expose the lower metal interconnect layer.

[0039] At 508, a first bottom electrode layer having curved sidewalls is formed in the opening. In some embodiments, the first bottom electrode layer may comprise a first material.

[0040] At 510, in some embodiments, a second bottom electrode layer may be formed in the opening at a position above the first bottom electrode layer. The second bottom electrode layer is embedded in the first bottom electrode layer and also has curved sidewalls. In some embodiments, the second bottom electrode layer may comprise a second material that is different from the first material.

[0041] At 512, a planarization process is performed to remove excess material from the first bottom electrode layer and the second bottom electrode layer. The planarization process forms a bottom electrode having a planar top surface disposed along a plane aligned with a top surface of the bottom dielectric layer.

[0042] At 514, a stack is formed over the bottom electrode layer and the bottom dielectric layer. The stack includes a planar dielectric data storage layer, a planar cap layer disposed on the planar dielectric data storage layer, a planar top electrode layer disposed on the planar cap layer, and a planar mask layer disposed on the planar top electrode.

[0043] At 516, the stack is selectively patterned according to the planar mask layer to form a patterned stack having a data storage dielectric layer adjacent to upper surfaces of the bottom electrode and the bottom dielectric layer.

[0044] At 518, a top dielectric layer is formed over the patterned stack. The top dielectric layer extends continuously from a position adjacent to the planar mask layer to a position adjacent to the bottom dielectric layer.

[0045] At 520, an upper interlayer dielectric layer (ILD) is formed over the upper dielectric layer.

[0046] At 522, an upper metal interconnect layer is formed on the upper electrode. The upper metal interconnect layer includes a top metal via formed at a position in contact with the upper electrode and a top metal wire formed in contact with the top metal via.

[0047] Fig. 6-13 show some embodiments of cross-sectional views illustrating a method of forming an RRAM cell having a bottom electrode disposed in a bottom dielectric layer. Although the Fig. 6-13 with reference to the method 500, it becomes clear that the structures described in Fig. 6-13 are not limited to such a method, but instead can stand alone as structures independent of the method.

[0048] Fig. 6 shows some embodiments of a sectional view 600 associated with operations 502-504.

[0049] As shown in cross-sectional view 600, a bottom metal interconnect layer 202 is formed in a bottom interlayer dielectric (ILD) layer 204. In some embodiments, the bottom metal interconnect layer 202 may be formed by selectively etching the bottom ILD layer 204 (e.g., an oxide, a low-k dielectric, or an ultra-low-k dielectric) to form an opening in the bottom ILD layer 204. A metal (e.g., copper, aluminum, etc.) is then deposited to fill the opening, and a planarization process is performed to remove excess metal to form the bottom metal interconnect layer 202.

[0050] A lower dielectric layer 602 is formed on the lower metal interconnect layer 202 and / or the lower ILD layer 204. In some embodiments, the lower dielectric layer 602 may comprise silicon nitride (SiN), silicon carbide (SiC), or a similar composite dielectric film. In some embodiments, the lower dielectric layer 602 may be formed by a vapor deposition technique (e.g., physical vapor deposition, chemical vapor deposition, etc.).

[0051] Fig. 7 shows some embodiments of a sectional view 700 associated with operation 506.

[0052] As shown in cross-sectional view 700, a first mask layer 704 is formed over the lower dielectric layer 702. The lower dielectric layer 702 is then selectively exposed to an etchant 706 (e.g., a dry etchant) in areas not covered by the first mask layer 704. The etchant 706 forms an opening 708 in the lower dielectric layer 702 that extends through the lower dielectric layer 702 to the lower metal interconnect layer 202. The opening 708 may have curved sidewalls 702s (e.g., sidewalls with a slope that changes depending on the height).

[0053] Fig. 8 shows some embodiments of a sectional view 800 associated with operations 508-510.

[0054] As shown in cross-sectional view 800, a bottom electrode layer 802 is formed in the opening 708. The first bottom electrode layer 802 extends from within the opening 708 to a position above the bottom dielectric layer 702. In some embodiments, the bottom electrode layer 802 may comprise, for example, tantalum (Ta) or tantalum nitride (TaN). A second bottom electrode layer 804 is formed in the opening at a position above the first bottom electrode layer 802. The second bottom electrode layer 804 extends from within the opening 708 to a position above the bottom dielectric layer 702. In some embodiments, the second bottom electrode layer 804 may comprise, for example, titanium (Ti) or titanium nitride (TiN).

[0055] Fig. 9 shows some embodiments of a sectional view 900 associated with operation 512.

[0056] As shown in cross-sectional view 900, a planarization process is performed to form a flat surface along line 902 by removing excess material from the first and second bottom electrode layers 206a and 206b. The planarization process results in a bottom electrode 206 having a flat top surface connected to the bottom surface by curved sidewalls. The flat top surface of the bottom electrode 206 is aligned with the top surface of the bottom dielectric layer 702. In some embodiments, the planarization process may include a chemical mechanical polishing (CMP) process.

[0057] Fig. 10 shows some embodiments of a sectional view 1000 associated with operation 514.

[0058] As shown in cross-sectional view 1000, a stack 1001 is formed over the bottom electrode 206 and the bottom dielectric layer 702. The stack 1001 includes a planar data storage dielectric layer 1002, a planar cap layer 1004 overlying the planar data storage dielectric layer 1002, a planar top electrode layer 1006 overlying the planar cap layer 1004, and a planar mask layer 1008 overlying the planar top electrode layer 1006. The planar mask layer 1008 is configured to define a top electrode of the RRAM cell. In some embodiments, the different layers of the stack 1001 may be deposited using vapor deposition techniques (e.g., physical vapor deposition, chemical vapor deposition, etc.).

[0059] In some embodiments, the planar dielectric data storage layer 1002 may comprise a high-k dielectric having a variable resistance. In some embodiments, the planar dielectric data storage layer 1002 may comprise, for example, hafnium oxide (HfO x ), zirconium oxide (ZrO x ), aluminum oxide (AlO x ), nickel oxide (NiO x ), tantalum oxide (TaO x ) or titanium oxide (TiO x ). In some embodiments, the planar cap layer 1004 may comprise a metal, such as titanium (Ti), hafnium (Hf), platinum (Pt), ruthenium (Ru), and / or aluminum (Al). In other embodiments, the planar cap layer 1004 may comprise a metal oxide, such as titanium oxide (TiO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO x ), germanium oxide (GeO x ) or cesium oxide (CeO x). In various embodiments, the planar top electrode layer 1006 may comprise a metal nitride (e.g., titanium nitride (TiN) or tantalum nitride (TaN)) or a metal (e.g., titanium (Ti) or tantalum (Ta)). In some embodiments, the planar mask layer 1008 may comprise a hard mask layer containing oxygen, such as silicon oxide (SiO2) or silicon oxynitride (SiON). In other embodiments, the planar mask layer 1008 may comprise a hard mask layer substantially free of oxygen, such as silicon nitride (SiN), silicon carbide (SiC), or a composite dielectric film substantially free of oxygen.

[0060] Fig. 11 shows some embodiments of a sectional view 1100 associated with operation 516.

[0061] As shown in cross-sectional view 1100, the stack 1001 is patterned according to the planar mask layer 1104. The stack 1001 may be patterned to form a patterned stack 1001' by selectively exposing the stack 1001 to an etchant 1102 in areas not covered by the planar mask layer 1104. The patterned stack 1001' has a data storage dielectric layer 210 adjacent to upper surfaces of the bottom electrode 206 and the bottom dielectric layer 208. In some embodiments, the etchant 1102 may comprise a dry etchant.

[0062] It has been recognized that the use of a planar mask layer 1008 that is substantially free of oxygen can increase the yield of a corresponding RRAM cell. This is because, during patterning of stack 1001, etchant 1102 can dissolve oxygen radicals from an oxygen-containing mask layer (e.g., SiO2 or SiON). The dissolved oxygen radicals can then be implanted into top electrode 214, cap layer 212, and / or dielectric layer 210, where the oxygen radicals lead to device failure (e.g., disrupting RRAM line formation and RRAM line reset). Using a planar mask layer 1008 that is substantially free of oxygen, such oxygen radicals are absent during patterning of stack 1001, resulting in increased yield (e.g., up to 30% or more).

[0063] Although the use of a planar mask layer 1008 having substantially no oxygen is preferred with respect to the Fig. 10-11, it will be appreciated that the use of a planar mask layer 1008 substantially free of oxygen (e.g., to pattern a top electrode and / or a bottom electrode) is not limited to such a method or RRAM cell structure. Rather, the use of a planar mask layer 1008 substantially free of oxygen may be used in any method of forming an RRAM and / or with any RRAM cell structure.

[0064] Fig. 12 shows some embodiments of a sectional view 1200 associated with operations 518-520.

[0065] As shown in cross-sectional view 1200, a top dielectric layer 1202 is formed over the patterned stack 1001'. An upper interlayer dielectric layer (ILD) 1204 is disposed over the top dielectric layer 1202. The top dielectric layer 1202 has a first side adjacent to the data storage dielectric layer 210, the cap layer 212, the top electrode 214, and the mask layer 1104, and a second side adjacent to the top ILD layer 1204.

[0066] Fig. 13 shows some embodiments of a sectional view 1300 associated with operation 522.

[0067] As shown in cross-sectional view 1300, a top metal interconnect layer 221 is formed at a position adjacent to the top electrode 214. In some embodiments, the top metal interconnect layer 221 includes a top metal via 222 and a top metal wire 118. In some embodiments, the top metal interconnect layer 221 may be formed by etching the top ILD layer 220 to form an opening extending through the top dielectric layer 218 and the mask layer 216 to the top electrode 214. The opening is then filled with a metal to form a top metal via 222 extending from the top surface of the top electrode 214 to the top metal wire 118.

[0068] Fig. 14 shows a flowchart of some alternative embodiments of a method 1400 for forming an RRAM cell having a bottom electrode disposed in a bottom metal interconnect layer.

[0069] At 1402, a metal is deposited in an opening in a lower interlayer dielectric layer (ILD) over a semiconductor substrate.

[0070] At 1404, a first planarization process is performed to remove excess metal to form a lower metal interconnect layer. The first planarization process forms a curved recess in a top surface of the lower metal interconnect layer.

[0071] At 1406, a first bottom electrode layer is formed in the curved recess. In some embodiments, the first bottom electrode layer may comprise a first material.

[0072] At 1408, in some embodiments, a second bottom electrode layer may be formed in the curved recess at a position overlying the first bottom electrode layer. The second bottom electrode layer is embedded in the first bottom electrode layer. In some embodiments, the second bottom electrode layer may comprise a second material that is different from the first material.

[0073] At 1410, a second planarization process is performed to remove excess material from the first bottom electrode layer and the second bottom electrode layer. The planarization process forms a bottom electrode having a planar top surface lying along a plane aligned with a top surface of the bottom ILD layer.

[0074] At 1412, a lower dielectric layer is formed over the lower electrode and / or the lower ILD layer.

[0075] At 1414, the lower dielectric layer is selectively etched to form an opening extending through the lower dielectric layer to expose the lower electrode.

[0076] At 1416, a stack is formed over the opening in the lower dielectric layer. The stack includes a non-planar data storage dielectric layer, a non-planar cap layer disposed on the non-planar data storage dielectric layer, a non-planar top electrode disposed on the non-planar cap layer, and a non-planar mask layer disposed on the non-planar top electrode.

[0077] At 1418, the stack is selectively patterned according to the non-planar mask layer to form a patterned stack having a data storage dielectric layer adjacent to upper surfaces of the bottom electrode and the bottom dielectric layer.

[0078] At 1420, a top dielectric layer is formed over the stack. The top dielectric layer extends continuously from a position adjacent to the non-planar mask layer to a position adjacent to the bottom dielectric layer.

[0079] At 1422, an upper interlayer dielectric layer (ILD) is formed over the upper dielectric layer.

[0080] At 1424, a top metal interconnect layer is formed on the top electrode. The top metal interconnect layer includes a top metal via formed at a position in contact with the top electrode and a top metal wire formed in contact with the top metal via.

[0081] The Fig. 15-24 show some embodiments of cross-sectional views illustrating a method for forming an RRAM cell disposed in a lower metal interconnect layer. Although the Fig. 15-24 with reference to method 1400, it becomes clear that the Fig. 15-24 are not limited to such a method, but instead can stand alone as structures independent of the method.

[0082] Fig. 15 shows some embodiments of a sectional view 1500 associated with operation 1402.

[0083] As shown in cross-sectional view 1500, a metal 1502 (e.g., copper) is deposited in an opening 1504 in a lower interlayer dielectric (ILD) layer 204 (e.g., an oxide, a low-k dielectric, or an ultra-low-k dielectric). The opening 1504 in the lower ILD layer 204 may be formed by selectively etching the lower ILD layer 204. The metal 1502 is deposited to a thickness that results in the metal 1502 in the opening 1504 being recessed by a distance d below a top surface 203 of the lower ILD layer 204.

[0084] Fig. 16 shows some embodiments of a sectional view 1600 associated with operation 1404.

[0085] As shown in cross-sectional view 1600, a first planarization process (e.g., a chemical mechanical polishing (CMP) process) is performed to remove excess metal 1502 to form a planar surface along line 1602. The first planarization process results in the formation of a bottom metal interconnect layer 302. Because the metal 1502 has been recessed below the top surface 203 of the bottom ILD layer 204, the planarization process results in a domed recess 1604 having a curved bottom surface that is adjacent to a top surface of the bottom metal interconnect layer 302.

[0086] Fig. 17 shows some embodiments of a sectional view 1700 associated with operations 1406-1408.

[0087] As shown in cross-sectional view 1700, a first bottom electrode layer 1702 is formed in the domed recess 1604. The first bottom electrode layer 1702 extends from within the domed recess 1604 to a position above the bottom ILD layer 204. The bottom surface of the first bottom electrode layer 1702 has a convex curvature that is adjacent to a concave top surface of the bottom metal interconnect layer 302. In some embodiments, the first bottom electrode layer 1702 may comprise a first material (e.g., Ta, TaN). A second bottom electrode layer 1704 is formed in the domed recess 1604 at a position that overlies the first bottom electrode layer 1702. The second lower electrode layer 1704 extends from within the curved recess 1604 to a position above the lower ILD layer 204. In some embodiments, the second lower electrode layer 1704 may comprise a second material (e.g.,Ti, TiN) which is different from the first material.

[0088] Fig. 18 shows some embodiments of a sectional view 1800 associated with operation 1410.

[0089] As shown in cross-sectional view 1800, a second planarization process (e.g., a CMP process) is performed to form a planar surface along line 1802 by removing excess material from the first and second bottom electrode layers 304a and 304b. The second planarization process results in a bottom electrode 304 having a flat top surface connected to the bottom surface by curved sidewalls. The flat top surface of the bottom electrode 304 is aligned with the top surface of the bottom ILD layer 204.

[0090] Fig. 19 shows some embodiments of a sectional view 1900 associated with operation 1412.

[0091] As shown in cross-sectional view 1900, a bottom dielectric layer 1902 is formed on the bottom electrode 304 and the bottom ILD layer 204. In some embodiments, the bottom dielectric layer 1902 may include a silicon nitride or silicon carbide layer formed by a vapor deposition technique (e.g., physical vapor deposition, chemical vapor deposition, etc.).

[0092] Fig. 20 shows some embodiments of a sectional view 2000 associated with operation 1414.

[0093] As shown in cross-sectional view 2000, a first mask layer 2004 is formed over the lower dielectric layer 2002. The lower dielectric layer 2002 is then selectively exposed to an etchant 2006 in areas not covered by the first mask layer 2004. The etchant 2006 forms an opening 2008 in the lower dielectric layer 2002 that extends through the lower dielectric layer 2002 to the lower electrode 304. The opening 2008 has curved sidewalls 2002s.

[0094] Fig. 21 shows some embodiments of a sectional view 2100 associated with operation 1416.

[0095] As shown in cross-sectional view 2100, a stack 2101 is formed over the bottom electrode 304 and the bottom dielectric layer 1902. The stack 2101 includes a non-planar data storage dielectric layer 2102 having a variable resistance, a non-planar cap layer 2104 over the non-planar data storage dielectric layer 2102, a non-planar top electrode layer 2106 over the non-planar cap layer 2104, and a non-planar mask layer 2108 over the non-planar top electrode layer 2106. The non-planar mask layer 2108 is configured to define a top electrode of the RRAM cell. In some embodiments, the non-planar mask layer 2108 may include a hard mask layer comprising oxygen, such as silicon oxide (SiO2) or silicon oxynitride (SiON).In other embodiments, the non-planar mask layer 2108 may comprise a material that is substantially free of oxygen, such as silicon nitride (SiN), silicon carbide (SiC), or a composite dielectric film that is substantially free of oxygen. In some embodiments, the different layers of the stack 2101 may be deposited using vapor deposition techniques (e.g., physical vapor deposition, chemical vapor deposition, etc.).

[0096] Fig. 22 shows some embodiments of a sectional view 2200 associated with operation 1418.

[0097] As shown in cross-sectional view 2200, the stack 2101 is patterned according to the non-planar mask layer 2204. The stack 2101 may be patterned to form a patterned stack 2101' by selectively exposing the stack 2101 to an etchant 2202 in areas not covered by the non-planar mask layer 2204. The patterned stack 2101' has a data storage dielectric layer 308 adjacent to upper surfaces of the bottom electrode 304 and the bottom dielectric layer 306.

[0098] Fig. 23 shows some embodiments of a sectional view 2300 associated with operations 1420-1422.

[0099] As shown in cross-sectional view 2300, a top dielectric layer 2302 is formed over the patterned stack 2101'. An upper interlayer dielectric layer (ILD) 2304 is disposed over the top dielectric layer 2302. The top dielectric layer 2302 has a first side adjacent to the data storage dielectric layer 308, the cap layer 310, the top electrode 312, and the mask layer 314, and a second side adjacent to the top ILD layer 2304.

[0100] Fig. 24 shows some embodiments of a sectional view 2400 associated with operation 1424.

[0101] As shown in cross-sectional view 2400, a top metal interconnect layer 319 is formed at a location adjacent to the top electrode 312. In some embodiments, the top metal interconnect layer 319 includes a top metal via 320 and a top metal wire 118. In some embodiments, the top metal interconnect layer 319 may be formed by etching the top ILD layer 318 to form an opening extending through the top dielectric layer 316 and the planar mask layer 314 to the top electrode 312. The opening is then filled to form a top metal via 320 extending from a top surface of the top electrode 312 to the top metal wire 118.

[0102] Thus, the present disclosure relates to a resistive RAM (RRAM) cell having a bottom electrode with a flat top surface that provides low leakage currents in the RRAM cell without the use of insulating sidewall spacers, and an associated formation method.

Claims

[1] Resistive RAM cell (300) comprising: a lower electrode (304) disposed over a lower metal interconnect layer (302) surrounded by a lower dielectric interlayer (204); a lower dielectric layer (306) disposed over the lower metal interconnect layer or the lower interlayer dielectric layer (204); a dielectric data storage layer (308) having a variable resistance, wherein a lower surface of the dielectric data storage layer (308) is adjacent to upper surfaces of the lower dielectric layer (306) and the lower electrode (304); and an upper electrode (312) disposed above the dielectric data storage layer (308), wherein the dielectric data storage layer (308) and the top electrode (312) comprise non-planar layers; wherein the lower electrode (304) has a flat upper surface connected to a lower surface by curved side walls; and wherein the lower surface comprises a curved surface such that the side walls and the lower surface form a continuous curved surface extending between opposite sides of the planar upper surface. [2] The resistive RAM cell (300) of claim 1, further comprising: a top dielectric layer (316) extending continuously from a first position above the top electrode (312) to a second position adjacent the data storage dielectric layer (308), the top dielectric layer adjacent a sidewall of the top electrode (312). [3] The resistive RAM cell (300) of claim 1 or 2, wherein the dielectric data storage layer (308) and the top electrode (312) have sidewalls that are laterally aligned with each other along a vertical plane. [4] Resistive RAM cell (300) according to claim 3, further comprising: a cover layer (310) disposed between the dielectric data storage layer (308) and the top electrode (312) and having a sidewall laterally aligned with the sidewalls of the dielectric data storage layer (308) and the top electrode (312). [5] Resistive RAM cell (300) according to one of the preceding claims, wherein the lower electrode (304) is surrounded by the lower dielectric layer (306); and wherein an upper surface of the lower electrode (304) shares a planar surface with an upper surface of the lower dielectric layer (306). [6] Resistive RAM cell (300) according to one of the preceding claims, wherein the lower electrode (304) has a smaller width than the dielectric data storage layer (308) such that the dielectric data storage layer (308) extends beyond the lower electrode (304) on opposite sides. [7] Resistive RAM cell (300) according to one of the preceding claims, wherein the lower electrode (304) comprises a convex lower surface adjacent to a concave upper surface of the lower metal interconnect layer; and wherein the upper surface of the lower electrode (304) shares a planar surface with an upper surface of the lower dielectric interlayer (204). [8] Resistive RAM cell (300) according to one of the preceding claims, wherein the lower electrode (304) comprises: a first lower electrode layer (304a) disposed on the lower metal interconnect layer, the first lower electrode layer comprising a first material; a second lower electrode layer (304b) embedded in the first lower electrode layer, the second lower electrode layer comprising a second material different from the first material; and wherein the first lower electrode layer and the second lower electrode layer have upper surfaces aligned along a planar surface. [9] Resistive RAM cell (300) comprising: a lower electrode (304) disposed over a lower metal interconnect layer surrounded by a lower dielectric interlayer (204), the lower electrode (304) having a flat upper surface connected to a lower surface by curved sidewalls; and wherein the lower surface comprises a curved surface such that the side walls and the lower surface forms a continuous curved surface extending between opposite sides of the flat upper surface; a lower dielectric layer (306) disposed over the lower metal interconnect layer or the lower interlayer dielectric layer (204); a dielectric data storage layer (308) having a variable resistance and disposed over the lower electrode (304); an upper electrode (312) disposed over the dielectric data storage layer (308); and a mask layer (314) having substantially no oxygen and disposed over the upper electrode (312), the mask layer having sidewalls vertically aligned with sidewalls of the upper electrode (312), wherein the dielectric data storage layer (308) and the top electrode (312) comprise non-planar layers. [10] The resistive RAM cell (300) of claim 9, wherein the lower electrode (304) has a flat upper surface connected to the lower surface by curved sidewalls. [11] Resistive RAM cell (300) according to claim 10, wherein the lower electrode (304) is surrounded by a lower dielectric layer (306) disposed over the lower metal interconnect layer or the lower dielectric interlayer (204); and wherein the planar upper surface of the lower electrode (304) shares a planar surface with an upper surface of the lower dielectric layer (306). [12] The resistive RAM cell (300) of claim 10 or 11, wherein the lower electrode (304) has a smaller width than the data storage dielectric layer (308) such that the data storage dielectric layer (308) extends beyond the lower electrode (304) on opposite sides. [13] Resistive RAM cell (300) according to one of claims 10 to 12, wherein the lower electrode (304) has a convex lower surface adjacent to a concave upper surface of the lower metal interconnect layer; and wherein the planar upper surface of the lower electrode (304) shares a planar surface with an upper surface of the lower dielectric interlayer (204). [14] The resistive RAM cell (300) of claim 13, wherein the bottom surface comprises a curved surface such that the sidewalls and the bottom surface form a continuous curved surface extending between opposite sides of the planar top surface. [15] A method of forming a resistive RAM cell (300), comprising: Forming a lower electrode (304) over a lower metal interconnect layer provided in a lower dielectric interlayer (204); Forming a lower dielectric layer (306) over the lower metal interconnect layer or the lower interlayer dielectric layer (204); Forming a dielectric data storage layer (308) having a variable resistance over the lower dielectric layer (306) and the lower electrode (304); and forming an upper electrode (312) over the dielectric data storage layer (308), wherein the dielectric data storage layer (308) and the upper electrode (312) comprise non-planar layers, wherein the lower electrode (304) has a flat upper surface connected to a lower surface by curved side walls; and wherein the lower surface comprises a curved surface such that the side walls and the lower surface form a continuous curved surface extending between opposite sides of the planar upper surface. [16] The method of claim 15, further comprising: Forming an upper dielectric layer (316) extending continuously from a first position above the upper electrode (312) to a second position adjacent to one side of the data storage dielectric layer (308); and wherein the upper dielectric layer is adjacent to a sidewall of the upper electrode (312).

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