Power semiconductor devices and processes

Abstract

Power semiconductor device, comprising: a semiconductor body (SB) with a first side (101), a second side (102) opposite the first side (101) and an outer edge (OR), wherein the semiconductor body (SB) comprises an active region (CR) and an edge termination region (RR) located between the active region (CR) and the outer edge (OR), wherein the semiconductor body (SB) comprises: a first doping region (SR) in the active region (CR) of the semiconductor body (SB) and connected to a first electrode (SE) located on the first side (101) of the semiconductor body (SB); a second doping region (DR) in the active region (CR) and the edge termination region (RR) and connected to a second electrode (DE) located on the second side (102) of the semiconductor body (SB); a drift region (DT) between the first doping region (SR) and the second doping region (DR), wherein the drift region (DT) comprises a first part adjacent to the first side (101) of the semiconductor body (SB) and a second part located between the first part and the second doping region (DR); at least one insulating region (IR) comprising a cavity and located in the edge termination region (RR) between the second doping region (DR) of the semiconductor body (SB) and the first part of the drift region (DT); and a further cavity located in the edge termination region (RR) between the first part of the drift region (DT) and the second side (102) of the semiconductor body (SB), wherein the cavity and the further cavity are located at different depths relative to the first side (101) of the semiconductor body (SB).

Description

TECHNICAL AREA

[0001] The embodiments described here relate to power semiconductor devices and methods for switching high electrical power. BACKGROUND

[0002] Power semiconductor switches, particularly field-effect controlled switching devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs), have been used in a variety of applications, including, but not limited to, their use as switches in power supplies and converters, electric vehicles, air conditioners, and even power grids used by renewable energy providers. Especially in power semiconductor devices capable of switching large currents and / or operating at higher voltages, current propagation in the edge termination region of a semiconductor body is a problem.

[0003] This makes semiconductor switches susceptible to overcurrents and overvoltages that could be caused by circuit faults. Although measures are typically provided to discharge overcurrents and voltages, these measures cannot always be fully implemented. JP 2007-042 826 A describes a semiconductor device in which vertical high-power elements, such as MOSFETs and IGBTs, and horizontal low-voltage elements are integrated on a single chip. US 5 561 077 A discloses a semiconductor device for high breakdown voltages and a corresponding fabrication method. In this method, a dielectric layer is deposited onto a semiconductor substrate, which provides a - -Semiconductor layer isolated from the substrate. Then an n + - Semiconductor region with a lower resistance than the n- - Semiconductor layer surrounded by a p +-Semiconductor region formed. The dielectric layer contains a thick region directly beneath the first semiconductor layer, thus increasing the breakdown voltage of the semiconductor device. EP 2 280 412 A2 discloses a semiconductor substrate with at least one cavity between the semiconductor substrate and a surface layer on the semiconductor substrate. The associated manufacturing process provides a structure with a cost-effective insulating layer that exhibits good physical and mechanical properties.

[0004] In light of the above, there is a need for improvements. SUMMARY

[0005] According to one embodiment, a power semiconductor device comprises a semiconductor body with a first side, a second side opposite the first side, and an outer edge. The semiconductor body includes an active region and an edge termination region located between the active region and the outer edge.The semiconductor body further comprises a first doping region in the active region, which is connected to a first electrode located on the first side of the semiconductor body, a second doping region in the active region and the edge termination region, which is connected to a second electrode located on the second side of the semiconductor body, a drift region between the first doping region and the second doping region, wherein the drift region has a first part adjacent to the first side of the semiconductor body and a second part located between the first part and the second doping region, and an insulating region located in the edge termination region between the second doping region of the semiconductor body and the first part of the drift region.

[0006] According to one embodiment, a power semiconductor device comprises a semiconductor body with a first side, a second side opposite the first side, and an outer edge. The semiconductor body includes an active region and an edge termination region located between the active region and the outer edge.The semiconductor body further comprises a first doping region in the active region and connected to a first electrode located on the first side of the semiconductor body, a second doping region in the active region and the edge termination region and connected to a second electrode located on the second side of the semiconductor body, a drift region between the first doping region and the second doping region, and an insulating region located in the edge termination region and at least partially within the second doping region, wherein the insulating region forms a blocking region in the edge termination region to at least partially block a vertical current transit of charge carriers.

[0007] According to one embodiment, a power semiconductor device comprises a semiconductor body with a first side, a second side opposite the first side, and an outer edge. The semiconductor body has an active region and an edge termination region located between the active region and the outer edge. The semiconductor body further comprises a first doped region in the active region and connected to a first electrode located on the first side of the semiconductor body, a second doped region in the active region and the edge termination region and connected to a second electrode located on the second side of the semiconductor body, a drift region between the first doped region and the second doped region, and a field stop zone located between the drift region and the second doped region.wherein the field stop zone has a higher doping concentration than the drift region and the same conductivity type as the drift region, and an isolation region adjacent to the drain region in the edge closure region and located at least partially within the field stop zone, wherein the isolation region forms a blocking region in the edge closure region to block at least partially a vertical current transit of charge carriers.

[0008] According to one embodiment, a method for fabricating a power semiconductor device includes the following: providing a semiconductor substrate with a surface; forming a first epitaxial layer on the surface of the semiconductor substrate; etching one or more trenches in the first epitaxial layer; annealing the first epitaxial layer, including the one or more trenches, in a hydrogen atmosphere to convert the one or more trenches into one or more cavities;Forming a second epitaxial layer on the first epitaxial layer after annealing the first epitaxial layer, wherein the substrate, the first epitaxial layer, and the second epitaxial layer form a semiconductor body with a first side, a second side opposite the first side, and an outer edge, the semiconductor body having an active region and an edge termination region located between the active region and the edge termination region; forming a first doping region in the active region; forming a first electrode located on the first side of the semiconductor body in contact with the first doping region; forming a second doping region in the active region and in the edge termination region; and forming a second electrode located on the second side of the semiconductor body in contact with the second doping region.

[0009] Experts in this field of technology will recognize additional features and advantages upon reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The components in the drawings are not necessarily shown to scale; instead, the focus is on illustrating the principles of the invention. Furthermore, identical reference numerals in the drawings denote corresponding parts. In the drawings: presents Fig. Figure 1A shows a cross-sectional view of a power semiconductor chip including an insulating region according to an embodiment; presents Fig. Figure 1B shows a cross-sectional view of a power semiconductor chip including an insulating region according to a further embodiment; presents Fig. Figure 1C shows a cross-sectional view of a power semiconductor chip including an insulating area according to yet another embodiment; presents Fig. 2 a perspective view of a part of a semiconductor chip including insulating areas according to an embodiment; presents Fig. Figure 3 shows a perspective view of part of a semiconductor chip, in which a work step for providing an isolation area according to an embodiment is depicted; presents Fig. Figure 4 shows a perspective view of part of a semiconductor chip, in which a work step for providing an isolation area according to an embodiment is depicted; presents Fig. Figure 5 shows a perspective view of part of a semiconductor chip, in which a work step for providing an isolation area according to an embodiment is depicted; is Fig. 6 a cross-sectional view of a power semiconductor chip, wherein the cross-sectional view includes a current density distribution graph to explain the current density distribution; is Fig. 7 a cross-sectional view of a power semiconductor chip, wherein the cross-sectional view includes a current density distribution graph according to an embodiment to explain the current density distribution; presents Fig. Figure 8 shows a graph with lateral current density distributions according to one embodiment; presents Fig. 9 shows a graph with time-dependent current density distributions according to one embodiment; presents Fig. 10 represents a semiconductor circuit element having an insulating region; and presents Fig. 11 represents another semiconductor circuit element that has an insulating region. DETAILED DESCRIPTION

[0011] The following detailed description refers to the accompanying drawings, which form part of this patent application and illustrate specific embodiments in which the invention can be used. In this context, directional terms such as "top," "bottom," "front," "rear," "leading," "attached," "lateral," "vertical," etc., are used to describe the orientation of the drawing(s). Since the components of the embodiments can be positioned in a number of different orientations, these directional terms are for illustrative purposes only and are not to be understood as limiting. It is to be expected that other embodiments can be used and structural or logical modifications can be made without departing from the scope of protection of the present invention.The following detailed description is therefore not to be understood in a limiting sense, and the scope of protection of the present invention is defined in the appended claims. Specific language is used for the described embodiments, which is not to be interpreted as limiting the scope of the appended claims.

[0012] The various embodiments will now be discussed in detail, one or more examples of which are illustrated in the drawings. Each example is provided for illustrative purposes and is not intended to limit the invention. Features illustrated or described, for example, as part of one embodiment may be used in or in combination with other embodiments to create yet another embodiment. The present invention is intended to include these modifications and variations. The examples are described in specific language, which is not to be interpreted as limiting the scope of the attached claims. The drawings are not to scale and are for illustrative purposes only.For the sake of clarity, unless otherwise stated, the same elements or manufacturing steps have been designated with the same reference numerals in the various drawings.

[0013] In the drawings, a lateral direction is designated by the reference symbol x. Furthermore, the vertical direction is designated by the reference symbol y.

[0014] In this specification, a second surface of a semiconductor substrate is assumed to be formed by the bottom or back face, while a first surface is considered to be formed by the top, front, or main face of the semiconductor substrate. The terms "above" and "below," as used in this specification, therefore describe the position of one structural feature relative to another, taking this orientation into account.

[0015] In the context of this specification, the term "MOS" (Metal-Oxide Semiconductor) should be understood to encompass the general term "MIS" (Metal-Insulator Semiconductor). For example, the term MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) should be understood to include FETs with a gate insulator that is not an oxide; that is, the term MOSFET is used in the more general sense of IGFET (Insulated-Gate Field Effect Transistor) or MISFET (Metal-Insulator Semiconductor Field Effect Transistor).

[0016] In the context of this specification, the term ‘metal’ for the gate material of the MOSFET should be understood to include, but not be limited to, electrically conductive materials such as metals, alloys, doped polycrystalline semiconductors and metal-semiconductor compounds such as metal silicides.

[0017] Field-effect controlled switching devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs) have been used in a variety of applications, including as switches in power supplies and converters, electric vehicles, air conditioners, and even stereo systems. Particularly for power devices capable of switching large currents and / or operating at higher voltages, a low forward resistance is often desirable. This means, for example, that for a given current to be switched, the voltage drop across the switched-on FET, i.e., the source-drain voltage, should be as low as possible. On the other hand, the losses that occur when the FET switches off or commutates must also often be kept low to minimize overall losses.

[0018] The term "power semiconductor device," as used in this specification, is intended to describe a semiconductor device on a single chip with high voltage and / or high current switching capabilities. In other words, power semiconductor devices are designed for high current, typically in the ampere range. In this specification, the terms "semiconductor switch," "semiconductor switching device," and "power semiconductor device" are used synonymously.

[0019] In the context of this specification, a semiconductor region in which an inversion channel can be formed and / or controlled via the field effect is also referred to as a body region. The term "field effect," as used in this specification, is intended to describe the formation of an "inversion channel" mediated by an electric field and / or the control of the conductivity and / or the shape of the inversion channel in a semiconductor region. The conductivity type of the channel region is typically changed, i.e., inverted, to form a unipolar current path between two semiconductor regions of the inverted conductivity type adjacent to the channel region.

[0020] In the context of this specification, the term "field-effect structure" shall describe a structure formed in a semiconductor substrate or semiconductor device that has a gate electrode insulated from the body region by at least one dielectric region or dielectric layer. Examples of dielectric material for forming a dielectric region or dielectric layer between the gate electrode and the body region include, in particular, silicon dioxide (SiO₂), silicon nitride (Si₃N₄), and silicon oxynitride (SiO₂). x N y ), Zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) and hafnium oxide (HfO2).

[0021] In the context of this specification, the term "gate electrode" shall describe an electrode that is located adjacent to and isolated from the body area and is configured to form and / or control a channel area passing through the body area.

[0022] In this specification, n-doped is designated as the first conductivity type, while p-doped is designated as the second conductivity type. Alternatively, the semiconductor devices can be formed with opposite doping relationships, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped. Furthermore, some diagrams illustrate the relative doping concentrations by indicating "-" or "+" next to the doping type. For example, "n" signifies a doping concentration that is less than the doping concentration of an "n" doped region, while an "n" +A “-doping region has a higher doping concentration than an “n” doping region. However, specifying the relative doping concentration does not mean that doping regions with the same relative doping concentration must have the same absolute doping concentration, unless otherwise stated. For example, two different n + -Doping areas exhibit different absolute doping concentrations. The same applies, for example, to an n + -doping- and a p + -Award area.

[0023] The terms "electrical connection" and "electrically connected" describe an ohmic connection between two elements.

[0024] In the sense used here, the term "field stop zone" refers to a region of the semiconductor material deposited above the substrate area. Incorporating a field stop zone into a semiconductor chip simplifies the use of substrate materials with low base doping or doping complementary to the field stop zone. This allows the field stop zone to be doped in a way that prevents the penetration of a space charge region into the substrate. In this way, a reduction in the breakdown voltage and / or punch-through of a semiconductor device on the chip can be avoided. Semiconductor devices that feature field stop zones are called field stop elements and include, but are not limited to, power MOSFETs, insulated-gate bipolar transistors (IGBTs), thyristors, diodes, or bipolar transistors.In the sense used here, the term "lateral field stop zone" refers to a zone of the semiconductor body that is located at an outer edge of the semiconductor body, at least partially within an edge termination region. Within the scope of this specification, the terms "field stop zone," "field stop layer," and "field stop region" are used synonymously.

[0025] Fig. Figure 1A illustrates a cross-sectional view of a power semiconductor device 100, which, according to one embodiment, has a semiconductor body SB with a first side 101, a second side 102 opposite the first side 101, and an outer edge OR. Furthermore, the semiconductor body SB has an active region CR and an edge termination region RR located between the active region CR and the outer edge OR of the semiconductor body SB. The semiconductor body SB can also have a first doping region SR in the active region CR of the semiconductor body SB, wherein the first doping region SR is connected to a first electrode SE located on the first side 101 of the semiconductor body SB.Furthermore, a second doped region DR can be provided in the active region CR and the edge termination region RR of the semiconductor body SB, wherein the second doped region DR is connected to a second electrode DE located on the second side 102 of the semiconductor body SB. A body region BR of the second conductivity type can be located between the first doped region SR and a weakly n-doped drift region DT. The drift region DT is located between the body region BR and the second doped region DR, which is connected to a second terminal DE. The drift region DT has a first part DT1 adjacent to the first side 101 of the semiconductor body SB and a second part DT2 located between the first part DT1 and the second doped region DR. The drift region DT can have an extension in a vertical direction y, i.e., a vertical drift region thickness TD, which is defined in . Fig. 1A is represented by a curly bracket DT, e.g., the drift region can have a certain maximum thickness in the vertical direction. Furthermore, the vertical thickness of the first part DT1 can be approximately 30% to 95% of the thickness TD of the vertical drift region DT, more specifically 60% to 90% of the thickness TD of the vertical drift region, and even more specifically, it can be 70% to 80% of the thickness TD of the vertical drift region. At least one isolation region IR is located in the edge termination region RR between the second doping region DR of the semiconductor body SB and the first part of the drift region DT1. The isolation region IR has a first side 701, i.e., an upper side with respect to the vertical direction y, and a second side 702, i.e., a lower side with respect to the vertical direction y. According to one embodiment, the first side 701 of the isolation area IR can be arranged opposite the first doping area SR, with a distance of approximatelyThe thickness of the drift region DT can be 30% to 120% of the given maximum thickness TD of the drift region DT, or approximately 60% to 95% of the given maximum thickness TD of the drift region DT. If the power semiconductor device 100 is provided as a transistor, for example, but not limited to, a MOSFET, MISFET, or JFET, the first electrode SE can be a source electrode, and the second electrode DE can be a drain electrode. Furthermore, a gate electrode GE can be provided. The semiconductor body SB can then be laterally subdivided into the active region CR or cell region and the edge termination region RR, which borders the active region CR.

[0026] Furthermore, the power semiconductor device 100 can be provided as an IGBT, JFET, HEMT, thyristor, and diode. According to an alternative embodiment, at least one isolation region IR can be located in the edge termination region RR of the semiconductor body SB and at least partially within the second doping region DR, wherein the isolation region IR forms a blocking region in the edge termination region RR to at least partially block vertical passage of charge carriers. According to a further alternative, the isolation region IR can extend at least partially from the second part DT2 of the drift region DT into the second doping region DR.

[0027] According to a Fig. In the embodiment illustrated in 1B, the power semiconductor device 100 is a device with two terminals, an example being a diode or a PIN diode. A body region BR of the second conductivity type can be located between the first doping region (in Fig. (1B not shown) and a weakly n-doped drift region DT. The drift region DT is located between the body region BR and the second doped region DR, which is connected to the second terminal DE. The first doped region, which is connected to a first terminal SE, can be of a second conductivity type, such as p-type, and be formed by a p-doped anode. The second doped region DR, which is connected to a second terminal DE, can be of the first conductivity type, such as n-type, and be formed by a highly n-doped cathode region. The drift region DT can be of the first doping type and have a lower doping concentration than the cathode region. The drift region DT forms a pn junction with the anode region.According to a further embodiment, the drift region DT can have a first part DT1 adjacent to the first side 101 of the semiconductor body SB, and a second part DT2 located between the first part DT1 and the second doping region DR. According to an embodiment that can be combined with other embodiments described herein, a field plate FP can be provided suitable for defining an edge termination.

[0028] According to a Fig. In the embodiment illustrated in Figure 1C, the power semiconductor device 100 is a three-terminal device, such as a field-effect transistor (FET) or an insulated-gate bipolar transistor (IGBT). The first doped region SR, connected to a first terminal, can be of the first conductivity type, such as n-type, and be formed by a highly n-doped source region. The drift region DT can be of the first doping type and have a lower doping concentration than the source region. A body region BR of the second conductivity type can be arranged between the source region and a weakly n-doped drift region. The drift region DT is arranged between the body region BR and the second doped region DR, which is connected to a second terminal DE and can be of the first conductivity type, e.g.,The drift region DT can be formed by a highly n-doped drain region in the case of a FET, or by a second conductivity type, e.g., a p-doped emitter region in the case of an IGBT. The drift region DT forms a pn junction with the body region BR. An optional field-stop region of the first conductivity type can be located between the first part DT1 of the drift region DT and the second doping region DR. The field-stop region has a higher doping concentration than the first part DT1 of the drift region DT. A gate region GR, electrically connected to a gate electrode GE and insulated from the body region BR by a gate dielectric GD, is connected to a third terminal. A channel region is formed in the body region BR next to the gate dielectric GD and connects the first doping region SR to the drift region DT. The conductivity of the channel region is controlled by a voltage applied to the gate electrode GE.

[0029] According to one embodiment, the power semiconductor device 100 is a bipolar device such as a diode or an IGBT. According to another embodiment, the power semiconductor device is a unipolar device such as a FET.

[0030] According to one embodiment, the gate region GR is a planar gate region and is located substantially parallel to a surface of the first side 101 of the semiconductor body SB, wherein the gate region is suitable for controlling an inversion channel in the body region BR, which is substantially parallel to the first surface 101. According to another embodiment, the gate region GR is partially arranged in a trench that extends vertically into the semiconductor body SB from the first side and controls the inversion channel in the body region BR, which is substantially perpendicular to the first surface 101.

[0031] The power semiconductor device 100 is provided in a vertical structure, i.e., the current flow is essentially perpendicular to the surface of a substrate S, in an arrow direction indicated by a reference symbol y. As shown in the Fig. As shown in Figures 1A-1C, the semiconductor body SB comprises a substrate S, the second doping region or drain region DR in the substrate S, wherein the drain region DR is connected to the drain electrode DE, the first doping region or source region SR, which is connected to the source electrode SE, the drift region DT between the source region SR and the drain region DR, and at least one insulating region IR. According to one embodiment, the drift region DT can have a given thickness TD, which depends on the nominal blocking capability of the power semiconductor device 100. The thickness TD of the drift region DT in micrometers (µm) can be selected linearly from a desired blocking voltage BV in volts (V) of the power semiconductor device 100 according to the following equation (1): TD=6…12×BV / 100

[0032] Example: Assuming a blocking voltage BV of 600 V, a typical thickness TD of the drift region DT of the power semiconductor device can be in the range of 48 µm to 72 µm.

[0033] According to one embodiment, the drift region DT can have a certain maximum thickness TD in a vertical direction, i.e., in a direction perpendicular to the surface of the semiconductor substrate, wherein the thickness of the first part DT1 of the drift region DT can be approximately 30% to 95% of the given maximum thickness TD of the drift region DT, more specifically 60% to 90% of the given maximum thickness TD, and even more specifically 70% to 80% of the given maximum thickness TD.

[0034] According to one embodiment, which can be combined with other embodiments described herein, the isolation region IR can be located at least partially within the drift region DT, preferably in the edge termination region or in the edge region RR and adjacent to the drain region DR, wherein the isolation region IR at least partially covers the drain region DR and is suitable for at least partially blocking vertical passage of charge carriers through the drift region DT in the edge termination region RR. The drain region DR can be contained at least partially within the substrate S, which extends in an x-direction. According to another embodiment, which can be combined with other embodiments described herein, the isolation region IR can extend laterally over the edge termination region RR and a portion of the active region CR. This allows a large part of a source-drain current to flow through the semiconductor body SB in the active region CR.

[0035] According to one embodiment, which can be combined with other embodiments described herein, the isolation region IR can be located at least partially within the drift region DT, preferably in the edge termination region or in the edge region RR and adjacent to the drain region DR, wherein the isolation region IR at least partially covers the second doping region DR and is suitable for at least partially blocking vertical passage of charge carriers through the drift region DT in the edge termination region RR. The region DR can be contained at least partially in the substrate S, which extends in an x-direction, and can, for example, form a p-doped emitter region of an IGBT. According to one embodiment, which can be combined with other embodiments described herein, the isolation region IR can extend laterally over the edge termination region RR and a part of the active region CR.This allows a large portion of the source-drain current to flow through the semiconductor body SB into the active region CR.

[0036] The gate electrode GE is positioned adjacent to and isolated from the semiconductor body region SB and is configured to form and / or control a channel region extending through the body region. The source electrode SE and the gate electrode GE are embedded in a dielectric layer, e.g., an insulating oxide OX, where the oxide OX is from the group consisting of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO3). x N y ), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), hafnium oxide (HfO2) or any combination of these substances is selected.

[0037] The semiconductor body SB of the FET is laterally subdivided into the active region CR and the edge termination region RR adjacent to the active region CR. Vertical passage of charge carriers through the drift region DT is at least partially blocked due to the isolation region IR. As shown in the Fig. As specified in 1A - 1C, the isolation region IR can extend laterally over the edge termination region RR and a portion of the active region CR. In this way, current flow from the drain electrode DE to the source electrode SE is limited to an area in the drain region DR that is not covered by the isolation region IR. According to yet another embodiment, which can be combined with the embodiments described here, the isolation region IR can extend laterally to the outer edge OR, as shown in Fig. 1A is shown, or can end at a distance from the outer edge OR, as shown in the Fig. 1B and Fig. 1C is shown.

[0038] According to one embodiment, a method for reducing the charge carrier concentration in the edge termination region RR of the power semiconductor device 100 is provided. The method comprises the steps of providing at least one isolation region IR, which is arranged between the drain region DR and the source region SR, at least partially covering the drain or emitter region DR, preferably in the edge termination region RR, by means of the isolation region IR, and at least partially blocking vertical passage of the charge carriers through the drift region DT in the edge termination region RR. According to an alternative, blocking the passage of the free charge carriers between the drain region DR and the drift region DT can further include the recombination of free charge carriers at least at one interface of the isolation region IR.

[0039] According to one embodiment, which can be combined with other embodiments described herein, a method for forming an insulating region within a semiconductor body SB, in particular in the edge termination region RR of the semiconductor body SB, can be provided. The method includes providing a substrate S, forming the semiconductor body SB by depositing at least one epitaxial layer on the substrate S, etching at least one trench into the deposited epitaxial layer, annealing the semiconductor body SB in a hydrogen atmosphere, and depositing at least one further epitaxial layer onto the annealed semiconductor body SB, wherein the insulating region is formed as a cavity in the first epitaxial layer and / or in the substrate at the position of the trench.According to a further embodiment, which can be combined with other embodiments described herein, a method for forming an insulating region within a semiconductor body SB, in particular in the edge termination region RR of the semiconductor body SB, can be provided. The method includes providing a substrate S, forming the semiconductor body SB by etching at least one trench in the substrate, annealing the semiconductor body SB in a hydrogen atmosphere, and depositing at least one further epitaxial layer onto the annealed semiconductor body SB, wherein the insulating region is formed as a cavity in the substrate at the position of the trench.

[0040] According to a further modification thereof, forming the cavity between the epitaxial layers at the position of the trench 104 involves providing a three-dimensional shape of the insulating region IR, selected from the group consisting of a spherical shape, a cylindrical shape, a cuboidal shape, a cavernous shape, a toroidal shape, and any combination thereof. According to one embodiment, a method for fabricating the power semiconductor device 100 can be provided. The method can include providing a semiconductor substrate with a surface, forming an optional first epitaxial layer on the surface of the semiconductor substrate, etching one or more trenches in the first epitaxial layer and / or in the substrate, and annealing the substrate and / or the first epitaxial layer, which has the one or more trenches, in a hydrogen atmosphere.to convert one or more trenches into one or more cavities, forming a second epitaxial layer on the substrate and / or the first epitaxial layer after the annealing step, wherein the substrate, the optional first epitaxial layer, and the second epitaxial layer form the semiconductor body SB; forming the first doped region SR in the active region CR of the semiconductor body SB, forming the first electrode SE, which is located on the first side 101 of the semiconductor body SB, in contact with the first doped region SR, forming the second doped region DR in the active region CR and in the edge termination region RR of the semiconductor body SB, and forming a second electrode DE, which is located on the second side 102 of the semiconductor body SB, in contact with the second doped region DR.

[0041] According to another embodiment, which can be combined with the embodiments described here, a further cavity can be arranged in the edge termination region RR between the first part DT1 of the drift region DT and the second side 102 of the semiconductor body SB, wherein the cavity and the further cavity are arranged at different depths with respect to the first side 101 of the semiconductor body. According to a modification, blocking the passage of free charge carriers between the drain region DR and the drift region DT also involves the recombination of free charge carriers at least at one interface of the insulating region IR. This reduces the electrical charges stored in the drift region DT.

[0042] According to one embodiment, which can be combined with other embodiments described herein, a method for fabricating a power semiconductor device is provided. The method includes providing a semiconductor substrate with a surface, etching one or more trenches into either a first epitaxial layer or into the substrate, annealing the semiconductor substrate, including the one or more trenches, in a hydrogen atmosphere to convert the one or more trenches into one or more cavities, forming a second epitaxial layer on the substrate after annealing in a hydrogen atmosphere, wherein the substrate, the first epitaxial layer, and the second epitaxial layer form a semiconductor body with a first side, a second side opposite the first side, and an outer edge, the semiconductor body having an active region and an edge termination region.that is located between the active region and the outer edge, the formation of a first doping region in the active region of the semiconductor body, the formation of a first electrode located on the first side of the semiconductor body and in contact with the first doping region, the formation of a second doping region in the active region and the edge termination region of the semiconductor body, and the formation of a second electrode located on the second side of the semiconductor body, in contact with the second doping region.

[0043] Fig. Figure 2 illustrates a perspective view of a region of a power semiconductor device 100 according to one embodiment. The power semiconductor device 100 has a semiconductor body SB comprising the substrate S and the drift region DT. For illustrative purposes only, the various structures of the insulating regions IR, which are to be embedded in the drift region DT adjacent to the substrate S, are shown. The substrate S is provided as either a drain region or an emitter region DR of the power semiconductor device 100.

[0044] The drain region or emitter region DR is electrically connected to the drain electrode or emitter electrode DE. On the left side of Fig. Figure 2 shows three cylindrical insulating areas. The processing steps required to achieve the formation of such cylindrical insulating structures are described below with reference to the following. Fig. 3, Fig. 4 to Fig. 5 described. The formation of a shallow cavity is described in the middle of Fig. 2 shown. The processing steps carried out to achieve the formation of such flat cavity structures are described below with reference to the Fig. 3, Fig. 4 to Fig. 5 described. The formation of spherical insulating structures is shown on the right side of Fig. 2 shown. The processing steps carried out to achieve the formation of such spherical insulating structures are further described with reference to the Fig. 3, Fig. 4 to Fig. 5 described.

[0045] According to one embodiment, the insulating region IR can be provided as a cavity with a specific shape. According to an alternative modification, the cavity can be filled with a gas selected from the group consisting of air, argon, nitrogen, oxygen, hydrogen, and any combination thereof. This can avoid or at least reduce thermal stress during the fabrication of the power semiconductor device 100, because gas can be compressed and is therefore less susceptible to stress and / or force transmission from / to the surrounding semiconductor material.

[0046] According to alternative embodiments, which can be combined with the embodiments described here, the isolation region IR can assume different shapes. A three-dimensional configuration of the isolation region IR can thus be selected from the group consisting of a spherical shape, a cylindrical shape, a cuboidal shape, a cavernous shape, a toroidal shape, and any combination thereof. According to another embodiment, which can be combined with the embodiments described here, the three-dimensional shape of the isolation region IR, selected from the group consisting of a spherical shape, a cylindrical shape, a cuboidal shape, a cavernous shape, a toroidal shape, and any combination thereof, can be internally supported by vertical columns made of semiconductor material from the substrate and / or the first epitaxial layer.

[0047] According to yet another embodiment, which can be combined with the embodiments described here, the shape of the IR isolation zone can have three-dimensionally rounded edges. This makes it possible to avoid or at least reduce high peak values ​​of electric field strengths.

[0048] According to a further embodiment, which can be combined with other embodiments described herein, the isolation regions IR, such as, but not limited to, cavities, can be at least partially surrounded by a p-doped zone. The p-doped zone further enhances the effect of the isolation region by preventing or at least reducing the passage of charge carriers in the edge closure region RR. This prevents a continuous n-path from the substrate S into the drift region DT.

[0049] Additionally or alternatively, the IR insulating region can be provided as an embedded dielectric layer or coated with a dielectric. The dielectric layer can be applied at the locations where the insulating regions are desired, prior to the application of subsequent layers. According to a further embodiment, an inner layer of the IR insulating regions is coated with a dielectric layer, e.g., by a vapor deposition process or a thermal oxidation process, which is carried out while a connection between the IR insulating regions still exists, e.g., via a trench remaining after annealing in a hydrogen atmosphere that has not collapsed or melted, or an additional trench that opens the IR insulating regions after annealing. The dielectric layer can, in particular, consist of silicon dioxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) and hafnium oxide (HfO2).

[0050] With reference to the Fig. 3, Fig. 4 to Fig. Section 5 now presents a process sequence for the formation of specific insulating structures according to one embodiment, which can be combined with other embodiments described here. As in the Fig. As indicated in 3 to 5, the semiconductor body SB can have a field stop zone FS between the drain region DR and the drift region DT. The values ​​in the Fig. 3, Fig. 4 to Fig. The five isolation regions IR shown can then be at least partially embedded in the field-stop zone FS. The field-stop zone FS can be provided as a zone of the semiconductor body SB that is deposited onto the drain region DR or the substrate S.

[0051] According to one embodiment, which can be combined with other embodiments described herein, a method for forming an insulating region IR within the semiconductor body SB, particularly in the edge termination region RR of the semiconductor body SB, is provided. The method includes providing the substrate S, which may be highly doped. The semiconductor body SB is then formed by depositing at least one first epitaxial layer onto the substrate S. The vertical thickness of the first epitaxial layer may be greater than the vertical extent of the cavity (insulating region IR).

[0052] Then at least one trench, as in Fig. Figure 3 illustrates the process of etching into the applied first epitaxial layer, with the trench being provided at a location where an isolation region IR is desired after completion of the process. The vertical extent of the etched trench may be larger than the vertical extent of the cavity (isolation region IR). For the purposes of this specification, "vertical" means an orientation that is substantially perpendicular to the main face of the semiconductor substrate S. The lateral width of the trench may be small enough to allow it to be bridged in the subsequent process step. For the purposes of this specification, "lateral" means an orientation that is substantially parallel to the main face of a semiconductor substrate S.

[0053] In the next step, the semiconductor body SB is annealed. This annealing step is carried out, for example, in a hydrogen atmosphere at a pressure of a few Torr and a temperature of approximately 900 to 1150 °C, so that a closed bridge is formed over the trench region. The situation after the annealing step is in Fig. 4 illustrated. Then at least one further epitaxial layer is applied to the annealed semiconductor body SB, and a power semiconductor device 100 is assembled as shown in Fig. 5. The vapor deposition process can be carried out shortly after the annealing step in the same process chamber. This creates an insulating zone IR as a cavity between the epitaxial layers at the trench location (see Fig. 5).

[0054] Incorporating a field-stop zone (FS) into the semiconductor body (SB) can facilitate the use of substrate materials with low base doping or doping complementary to the field-stop zone. This allows the field-stop zone (FS) to be doped in a way that prevents or at least reduces the penetration of a space charge region into the substrate. This can prevent a reduction in breakdown voltage and / or breakdown of the power semiconductor device. Semiconductor devices incorporating field-stop zones (FS) are called field-stop elements and include, but are not limited to, power MOSFETs, insulated-gate bipolar transistors (IGBTs), diodes, thyristors, or bipolar transistors.

[0055] This results in the semiconductor power device 100, which includes the source electrode SE (not in the Fig. 3, Fig. 4 to Fig. 5 shown), the drain electrode DE and the gate electrode GE (not shown in the Fig. 3, Fig. 4 to Fig. 5) and has a semiconductor body SB, which is laterally subdivided into the active region CR and an edge termination region RR adjacent to the active region CR. As shown in the Fig. 3, Fig. 4 to Fig. As shown in Figure 5, the semiconductor body SB comprises the following: the substrate S, the drain region or emitter region DR on the substrate, which is connected to the drain electrode or emitter electrode DE, the field-stop zone FS on the drain region DR, a drift region DT on the field-stop zone FS, and the insulating regions IR, which are substantially located within the field-stop zone FS. The insulating region IR can be located at least partially within the field-stop zone FS, preferably in the edge termination region RR and adjacent to the drain region DR, wherein the insulating region IR at least partially covers the drain region DR and is suitable for at least partially blocking vertical passage of charge carriers through the drift region DT in the edge termination region RR.

[0056] It should be noted that the introduction of an isolation zone IR is not limited to the field stop zone FS; rather, an isolation zone IR can be embedded within the drift zone DT, the drain zone DR, or the field stop zone FS. According to a modification of this, the isolation zone IR can be located at an interface between the drain zone DR and the field stop zone FS, or at an interface between the drain zone DR and the drift zone DT, or at an interface between the field stop zone FS and the drift zone DT. If the isolation zones IR are essentially embedded in the substrate S, the application of the first epitaxial layer is omitted. In this case, an epitaxial layer and / or the field stop zone FS and / or a layer providing the drift zone DT can be applied directly to the cavities that provide the isolation zones IR.

[0057] According to one embodiment, which can be combined with other embodiments described herein, longitudinal cavities can be supported by columns (not shown in the drawings). According to another alternative, a plurality of closely spaced trenches T can be formed in the semiconductor body SB or in the field-stop zone FS. Whether a trench T is converted into a single cavity or adjacent trenches T are joined to form a common cavity depends on the lateral spacing, i.e., the distance between the trenches T. When a plurality of closely spaced trenches T are arranged in an array, a cavity is formed as an insulating region IR, which, in plan view, has the two-dimensional extent of the array.

[0058] The isolation region IR can have a planar shape, as in the middle of Fig. Figure 4 illustrates this. For example, a rectangular array of closely spaced trenches T forms a substantially rectangular cavity with rounded corners (see perspective view of Figure 4). Fig. 4), while a series of closely spaced trenches T forms an essentially elongated cavity. Rounded corners can be provided in such a way as to avoid or at least reduce unwanted peak values ​​of electric fields. Therefore, by selecting the arrangement of the trenches T, almost any cavity arrangement and cavity shape can be formed.

[0059] Fig. Figure 6 illustrates a cross-section of a power semiconductor device 100. To illustrate and compare the current distribution with a current distribution when insulating regions IR are present, the figure is superimposed with a current density distribution diagram 200 with streamlines CT. The current density distribution diagram 200 is derived from a simulation of the current flow between the source electrode SE and the drain electrode DE when the body diode of the power semiconductor device 100 is in conducting mode, i.e., when the voltage across the source electrode SE of an n-channel MOSFET is more positive than the voltage across the drain electrode DE. The power semiconductor device 100 is divided into the active region CR and the edge termination region RR. The edge termination region RR may have a lateral field-stop zone LFS at its outer edge OR. Fig. Figure 6 presents a numerical simulation of a current density distribution in a situation where none of the insulating regions IR are present. Current paths originate from the source electrode SE and are then essentially distributed over the area of ​​the drain electrode DE. How Fig. As can be seen from Figure 6, the density of current paths increases at the location where the source electrode SE contacts the drift region DT.

[0060] Fig. Figure 7 illustrates a cross-section of a power semiconductor device 100, wherein, to illustrate and compare the current distribution with a current distribution in existing insulating regions IR, the figure is superimposed with a current density distribution diagram 200 with streamlines CT. Fig. Figure 7 presents a numerical simulation of a current density distribution in a situation where insulating regions IR are present. As can be seen from the generated current paths, the current density at the source electrode SE is lower compared to the current density at the source electrode SE in the Fig. The situation shown in Figure 6 is assumed to be without any insulating regions. Additionally, the generation of charge carriers in the edge termination region RR is reduced. In other words, current flow (indicated by the streamlines CT) in the edge termination region RR of the power semiconductor device 100 is avoided or at least reduced.

[0061] When the body diode of the power semiconductor device 100 is in conducting mode, i.e., when the voltage at the source electrode SE of an n-channel MOSFET is more positive than the voltage at the drain electrode DE, as shown in Fig. 6 and Fig. Figure 7 shows the drift region DT of the power semiconductor device 100 flooded with an electron-hole plasma. Since there is no significant electric field in the drift region DT in this operating mode, the concentration of electrons and holes is essentially equal and much higher than the background doping of the drift region DT.

[0062] Fig. Figure 8 presents a diagram illustrating various electron and hole densities 203 as a function of a lateral position x in a direction substantially parallel to the substrate surface. A first electron and hole density distribution 201, including two simulation curves, corresponds to the situation with an isolation region IR as shown in Fig. Figure 7 shows, while a second electron and hole density distribution 202, including two further simulation curves, corresponds to the situation without isolation regions IR as in Fig. Figure 6 shows the simulated electron and hole density distributions 201 and 202, respectively, as distribution curves that run along a dashed line BL in the x-direction, as shown in Fig. 6 or in Fig. Figure 7 shows that a comparison of the first and second electron and hole density distributions, 201 and 202 respectively, reveals a reduction in the electron and hole density in the situation where at least one insulating region IR is provided in the semiconductor body SB. A lateral position, indicated by the reference symbol x-SE, corresponds to an x-coordinate where the source electrode SE comes into contact with the drift region DT. At this contact point between the source electrode and the drift region DT, the electron and hole density in both situations shown in Figure 7 reaches a certain value. Fig. Figures 6 and 7 show the maximum value, however, the first electron and hole density distribution 201 has lower maximum values ​​compared to the second electron and hole density distribution 202.

[0063] Fig. Figure 9 illustrates the reverse recovery behavior of the two MOSFET body diodes when they are commutated from their forward mode to their reverse-biased mode via an auxiliary switch, e.g., another MOSFET acting as a switch which is turned on. Fig. Figure 9 shows the time dependence of both current I and energy E. Curves 401 and 402 represent cell region currents, i.e., currents flowing in a substantially vertical direction from the source electrode SE to the drain electrode DE in the cell region CR (see Figure 9). Fig. 6 and Fig. 7) flow, as a function of time t. Here, a first cell area flow 401 corresponds to the one in Fig. The situation shown in section 6, where no isolation region IR is provided in the boundary closure region RR, is different. On the other hand, a second cell area stream 402 corresponds to the one shown in Fig. The situation depicted in Figure 7 shows an isolation region IR in the boundary termination region RR within the drift region DT, which borders the drain region DR. Curves 301 and 302 represent currents in the boundary termination region, i.e., currents flowing in a substantially vertical direction from the source electrode SE to the drain electrode DE in the boundary termination region RR (see Figure 7). Fig. 6 and Fig. 7) flow, as a function of time t. Here, a first boundary closure area flow 301 corresponds to the one in Fig. The situation shown in section 6, where no isolation zone IR is provided in the boundary closure zone RR, is different. On the other hand, a second boundary closure zone stream 302 corresponds to the one shown in Fig. The situation depicted in Figure 7 shows an isolation region IR within the boundary termination region RR, located within the drift region DT, which borders the drain region DR. It should be noted that the currents are given in arbitrary units and that the starting point for the time axis is arbitrarily chosen. In this example, a forward current flows in the body diodes from the source electrode to the drain electrode up to a time step of 2.005 µs, where the current in Figure 7 is... Fig. The forward current shown in Figure 9 is represented as a current with a negative sign. At a time step of 2.005 µs, the commutation sequence begins, for example, when an auxiliary switch causes the current to change sign. In the present example, zero current is reached at a time step of approximately 2.020 µs. At a time point thereafter, an excess charge in the drift region DT of the edge termination region RR is removed. As can be seen from the energy curves (E) 501, 502, which begin to rise at a time step of approximately 2.080 µs to 2.090 µs, most of the charge stored in the cell region CR is removed, and the voltage at the drain electrode DE begins to rise significantly above the potential of the source electrode SE. In the case of the Fig. In the situation shown in Figure 6, the increasing voltage between the drain electrode DE and the source electrode removes the stored charges in the edge termination region RR, causing the first edge termination region current 301 to increase significantly until the excess charge is removed from the edge termination region RR. In contrast, the amount of excess charge that is in the Fig. In the situation shown in section 7, the charge stored is significantly lower, and thus the second boundary termination current 302 is significantly lower. After a time step of 2.105 µs or 2.125 µs, essentially the entire charge excess stored in the area shown in section 7 is removed. Fig. 7 or Fig. The data stored in the constructed component (6) is removed. Any stray inductances present lead to a continuous total current with a specific edge, for example by generating avalanche breakthroughs, until the zero level is reached again at approximately time step 2.140 µs and the commutation is complete.

[0064] As can be clearly seen from the time evolution of the two boundary region currents 301 and 302, the absolute value of the second boundary region current 302 is significantly lower and much smoother than that of the first boundary region current 301. This corresponds to the fact that the current density, and thus the amount of stored charge in the Fig. In the situation shown in section 7, where an isolation region IR is provided in the boundary region RR (boundary region) within the drift region DT, which borders the drain region DR, the current density and thus the amount of stored charge in the Fig. Figure 6 illustrates the situation where no isolation region IR is provided in the edge termination region RR. Since the two edge termination region currents 301, 302 are concentrated on the outermost parts of the cell region CR adjacent to the edge termination region RR, the second edge termination region current 302 has a lower current density and thus less stress on the power semiconductor device 100 compared to the first edge termination region current 301. This reduces the failure probability of the device by incorporating at least one isolation region IR according to the embodiments.

[0065] As can be clearly seen from the time evolution of the two cell region currents 401 and 402, the second cell region current 402 is smoother than the first cell region current 401. The second cell region current 402 shows a linear decrease from time step 2.105 µs, e.g., due to carriers generated by avalanche effects or provided by capacitive re-switching of the channel, while the first cell region current 401 begins to increase at a later time. It should be noted here that steep edges can lead to high stress in the component and to further problems such as electromagnetic interference, etc.

[0066] A source-drain total current through the semiconductor body SB for the in Fig. The situation shown in section 6 can be described by the sum of the respective cell area stream 401 and a respective boundary closure area stream, identified by the reference identifier 301 in Fig. 9, can be represented. Furthermore, the total source-drain current through the semiconductor body SB can be shown for the in Fig. The situation depicted in Figure 7 is represented by the sum of the respective cell area flow 402 and a respective boundary area flow, identified by the reference identifier 302. A time evolution of flows in the boundary area RR (see Figure 7) is shown. Fig. 6 and Fig. 7) can be explained as follows. Due to the sharp decrease over the time of the first cell area stream 401 (situation according to Fig. 6) The edge termination region current 301 shows an increase, and was such that the edge termination region RR of the semiconductor body SB carries the residual current, i.e., the "total current minus the first cell region current 401". The situation with regard to Fig. 7 differs from this: Here, one flank of the second cell area stream 402 is less steep than in the situation according to Fig. 6 (first cell area stream 401).

[0067] Fig. Figure 10 illustrates a cross-section of a power semiconductor device 110, which has an insulating region according to embodiments that can be combined with other embodiments described herein. A semiconductor body of the semiconductor device 110 has a first, upper side 101 and a second, lower side 102. The semiconductor device 110 without insulating regions or cavities is described in application DE 10 2006 036 347 B4, the disclosure of which is deemed to be included herein by this cross-reference to the extent that the application is not incompatible with the present disclosure. Fig. Figure 10 illustrates the introduction of the IR isolation region into a semiconductor device 110.

[0068] The semiconductor device 110 has electrodes 105 and 106 that project into the drift region DT of the semiconductor body. The electrodes include field electrodes 106 in the cell region CR and edge electrodes 105 in the edge termination region RR. The electrodes are surrounded by respective dielectric layers; that is, the field electrode 106 is surrounded by a dielectric field electrode layer 107, while the edge electrode 105 is surrounded by a dielectric edge electrode layer 108. In the application example in Fig. 10. The isolation region IR is embedded in the substrate S, e.g., within the drainage region DR. The drift region DT is represented as a cover of the isolation region IR, so that a cavity of a specified three-dimensional shape can be provided.

[0069] According to embodiments that can be combined with other embodiments described herein, the isolation region IR can have different shapes. A three-dimensional configuration of the isolation region IR can thus be selected from the group consisting of a spherical shape, a cylindrical shape, a cuboid shape, a cavern shape, a toroidal shape, and any combination thereof.

[0070] The in Fig. Figure 10 shows a semiconductor device 110 comprising a source electrode SE connected to a source metallization SM, a drain electrode DE, and gate electrodes GE. The semiconductor body, which is laterally subdivided into a cell region CR and an edge termination region RR adjacent to the cell region CR, comprises the drain region DR connected to the drain electrode DE and an epitaxial semiconductor layer 103 deposited onto the drain region DR. As shown in Fig. As shown in Figure 10, the semiconductor body has the substrate S, the drain region DR on the substrate which is connected to the drain electrode DE, the drift region DT on the drain region DR and the insulating region IR.

[0071] According to the embodiment according Fig. 10. The isolation region IR can be located at least partially within the drain region DR, preferably in the boundary region RR, wherein the isolation region IR at least partially covers the drain region DR and is suitable to at least partially block a vertical passage of charge carriers through the drift region DT in the boundary region RR. A lateral field stop zone LFS can be provided at the outer edge OR of the boundary region RR.

[0072] Fig. Figure 11 illustrates another semiconductor device 100, which has an insulating region. The one in Fig. The power semiconductor device 100 shown in Figure 11 is a three-terminal compensation device, such as a field-effect transistor (FET). The first doped region SR, connected to a first terminal, can be of the first conductivity type, such as n-type, and may be formed by a highly n-doped source region. In the cell region CR, the drift region DT has p-columns 601 and n-columns 602 arranged adjacent to each other. A body region BR of the second conductivity type can be arranged between the source region and a weakly n-doped drift region DT. The drift region DT is arranged between the body region BR and the second doped region DR, which is connected to a second terminal DE and may be of the first conductivity type, such as a highly n-doped drain region in the case of a FET. The n-column 602 of the drift region DT forms a pn-pass with the body region BR.An optional field-stop region of the first conductivity type can be located between the first part DT1 of the drift region DT and the second doping region DR. The field-stop region has a higher doping concentration than the net doping of the first part DT1 of the drift region DT. The net doping of the first part DT1 of the drift region DT can be calculated by adding the doping of the p-columns 601 and the n-columns 602, taking into account the signs of the doping regions. A gate region GR, electrically connected to a gate electrode GE and insulated from the body region BR by a gate dielectric GD, is connected to a third terminal. A channel region is formed in the body region BR adjacent to the gate dielectric GD and connects the first doping region SR to the n-columns 602 in the drift region DT. The conductivity of the channel region is controllable by a voltage applied to the gate electrode GE.

[0073] According to one embodiment, the gate region GR is a planar gate region and is located substantially parallel to the surface of the first side 101 of the semiconductor body SB, wherein the gate region is suitable for controlling an inversion channel in the body region BR, which is substantially parallel to the first surface 101. According to another embodiment, the gate region GR is partially arranged in a trench that extends vertically into the semiconductor body SB from the first side and controls the inversion channel in the body region BR, which is substantially perpendicular to the first surface 101.

[0074] According to yet another embodiment, which can be combined with other embodiments described herein, the edge termination region RR can also be provided with p-columns 601 and n-columns 602 arranged adjacent to one another. A doping level or net doping level of the first part DT1 of the drift region DT is adjusted to be lower than a doping level of the second part DT2 of the drift region DT of the edge termination region RR. The isolation region IR can extend laterally to the outer edge OR, as shown in Fig. 1A is shown, or can end at a distance from the outer edge OR, as shown in Fig. Figure 11 shows that higher mechanical stability of the power semiconductor device 100 can be provided if the insulation region IR does not extend to the outer edge OR.

[0075] The insulating regions IR according to the embodiments described herein can be used in edge termination regions or edge regions RR of semiconductor devices. Furthermore, the insulating regions IR can be applied to gate pads or in intelligent power ICs, where a cavity or an insulating region according to the embodiments described herein can be arranged between a substrate and an integrated circuit, including logic circuits.

[0076] Spatial terms such as "under," "below," "below," "above," "above," and similar terms are used to simplify the description and explain the positioning of one element relative to another. These terms are intended to cover various orientations of the building element, in addition to the different orientations shown in the drawings. Furthermore, terms such as "first," "second," and similar terms are used to describe different elements, areas, sections, etc., and are also not to be understood as restrictive. Similar terms refer to similar elements throughout the description.

[0077] For the purposes of this document, terms such as "have," "contain," "exhibit," "comprise," and similar open terms indicate the presence of the elements or characteristics mentioned, but do not exclude other elements or characteristics. The articles "a / an" and "the" are intended to include both the plural and the singular unless the context clearly indicates otherwise.

[0078] In view of the above range of variations and applications, it should be understood that the present invention is not limited by the above description or by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

[0079] The above written description uses specific embodiments to disclose the invention, including the best embodiment, and also to enable those skilled in the art to understand and use the invention. Although the invention has been described using various specific embodiments, those skilled in the art will recognize that the invention can be implemented in practice with modifications, in accordance with the spirit and scope of the claims. In particular, non-mutually exclusive features of the embodiments described above can be combined. The patentable scope of protection is defined by the claims and may include other examples that may come to mind for those skilled in the art.Such other examples shall fall within the scope of protection of the claims if they have structural elements that do not deviate from the wording of the claims, or if they have equivalent structural elements with insignificant deviations from the wording of the claims.

[0080] Furthermore, it is understood that the features of the various exemplary embodiments described here can be combined with each other, unless expressly stated otherwise.

[0081] Although specific embodiments have been illustrated and described herein, it is apparent to those skilled in the art that numerous alternative and / or equivalent implementations can replace the illustrated and described specific embodiments without deviating from the scope of protection of the present invention. The present application is intended to cover any adaptations or variants of the specific embodiments discussed herein. Therefore, it is intended that the present invention be limited only by the claims and their equivalents.

Claims

[1] Power semiconductor device comprising: a semiconductor body (SB) with a first side (101), a second side (102) opposite the first side (101) and an outer edge (OR), wherein the semiconductor body (SB) comprises an active region (CR) and an edge termination region (RR) located between the active region (CR) and the outer edge (OR), wherein the semiconductor body (SB) comprises: a first doping region (SR) in the active region (CR) of the semiconductor body (SB) and connected to a first electrode (SE) located on the first side (101) of the semiconductor body (SB); a second doping region (DR) in the active region (CR) and the edge termination region (RR) and connected to a second electrode (DE) located on the second side (102) of the semiconductor body (SB); a drift region (DT) between the first doping region (SR) and the second doping region (DR), wherein the drift region (DT) comprises a first part adjacent to the first side (101) of the semiconductor body (SB) and a second part located between the first part and the second doping region (DR); at least one insulating region (IR) comprising a cavity and located in the edge termination region (RR) between the second doping region (DR) of the semiconductor body (SB) and the first part of the drift region (DT); and a further cavity located in the edge termination region (RR) between the first part of the drift region (DT) and the second side (102) of the semiconductor body (SB), wherein the cavity and the further cavity are located at different depths relative to the first side (101) of the semiconductor body (SB). [2] Power semiconductor device according to claim 1, wherein the insulating region (IR) is an embedded dielectric layer. [3] Power semiconductor device according to claim 1 or 2, wherein the insulating region (IR) extends laterally over the edge termination region (RR) and a part of the active region (CR) adjacent to the edge termination region (RR). [4] Power semiconductor device according to any one of claims 1 to 3, wherein the cavity is filled with a gas selected from the group consisting of air, argon, nitrogen, oxygen, hydrogen and any combination thereof. [5] Power semiconductor device according to one of claims 1 to 4, wherein the insulating region (IR) is at least partially surrounded by a p-doped zone. [6] Power semiconductor device according to any one of claims 1 to 5, wherein the drift region (DT) has a given maximum thickness and wherein the thickness of the first part of the drift region (DT) is approximately 30% to 95% of the given maximum thickness of the drift region (DT). [7] Power semiconductor device according to any one of claims 1 to 6, wherein one form of the insulating region (IR) comprises three-dimensionally rounded edges. [8] Power semiconductor device according to any one of claims 1 to 7, wherein the power semiconductor device is selected from the group consisting of MOSFET, MISFET, IGBT, JFET, HEMT, thyristor and diode. [9] Power semiconductor device according to one of claims 1 to 8, wherein the insulating region (IR) extends at least partially from the second part of the drift region (DT) into the second doping region (DR). [10] Power semiconductor device comprising: a semiconductor body (SB) with a first side (101), a second side (102) opposite the first side (101) and an outer edge (OR), wherein the semiconductor body (SB) comprises an active region (CR) and an edge termination region (RR) located between the active region (CR) and the outer edge (OR), wherein the semiconductor body (SB) comprises: a first doping region (SR) in the active region (CR) of the semiconductor body (SB) and connected to a first electrode (SE) located on the first side (101) of the semiconductor body (SB); a second doping region (DR) in the active region (CR) and the edge termination region (RR) and connected to a second electrode (DE) located on the second side (102) of the semiconductor body (SB); a drift region (DT) between the first doping region (SR) and the second doping region (DR), wherein the drift region (DT) comprises a first part adjacent to the first side (101) of the semiconductor body (SB) and a second part located between the first part and the second doping region (DR); at least one insulating region (IR) comprising a cavity and located in the edge termination region (RR) of the semiconductor body (SB) and at least partially in the second doping region (DR), wherein the insulating region (IR) forms a blocking region in the edge termination region (RR) to at least partially block vertical passage of charge carriers; and a further cavity located in the edge termination region (RR) between the first part of the drift region (DT) and the second side (102) of the semiconductor body (SB), wherein the cavity and the further cavity are arranged at different depths relative to the first side (101) of the semiconductor body (SB). [11] Power semiconductor device according to claim 10, wherein the insulating region (IR) is an embedded dielectric layer. [12] Power semiconductor device according to claim 10 or 11, wherein the drift region (DT) has a given maximum thickness, wherein the insulating region (IR) has a first side (701) and a second side (702) opposite the first side (701), and wherein the first side (701) of the insulating region (IR) is arranged at a distance from the first doping region (SR), the distance being approximately 30% to 120% of the given maximum thickness of the drift region (DT). [13] Power semiconductor device according to one of claims 10 to 12, wherein the insulating region (IR) extends laterally over the edge termination region (RR) and a part of the active region (CR) that is arranged adjacent to the edge termination region (RR). [14] Power semiconductor device comprising: a semiconductor body (SB) with a first side (101), a second side (102) opposite the first side (101) and an outer edge (OR), wherein the semiconductor body (SB) comprises an active region (CR) and an edge termination region (RR) located between the active region (CR) and the outer edge (OR), wherein the semiconductor body (SB) comprises: a first doping region (SR) in the active region (CR) of the semiconductor body (SB) and connected to a first electrode (SE) located on the first side (101) of the semiconductor body (SB); a second doping region (DR) in the active region (CR) and the edge termination region (RR) and connected to a second electrode (DE) located on the second side (102) of the semiconductor body; a drift region (DT) between the first doping region (SR) and the second doping region (DR), wherein the drift region (DT) comprises a first part adjacent to the first side (101) of the semiconductor body (SB) and a second part located between the first part and the second doping region (DR); a field stop zone (FS) located between the drift region (DT) and the second doping region (DR), wherein the field stop zone (FS) has a higher doping concentration than the drift region (DT) and is of the same conductivity type as the drift region (DT); at least one isolation region (IR) comprising a cavity and located in the edge closure region (RR) adjacent to the drift region (DT) and at least partially within the field stop zone (FS), wherein the isolation region (IR) forms a barrier region in the edge closure region (RR) to at least partially block vertical passage of charge carriers; and a further cavity located in the edge termination region (RR) between the first part of the drift region (DT) and the second side (102) of the semiconductor body (SB), wherein the cavity and the further cavity are located at different depths relative to the first side (101) of the semiconductor body (SB). [15] Power semiconductor device according to claim 14, wherein the insulating region (IR) extends laterally over the edge termination region (RR) and a part of the active region (CR) adjacent to the edge termination region (RR). [16] Method for manufacturing a power semiconductor device, the method comprising: Providing a semiconductor substrate (S) with a surface; Formation of a first epitaxial layer on the surface of the semiconductor substrate (S); Etching one or more trenches into the first epitaxial layer; Annealing of the first epitaxial layer, comprising the one or more trenches, in a hydrogen atmosphere to convert the one or more trenches into a cavity and a further cavity; Forming a second epitaxial layer on the first epitaxial layer after annealing the first epitaxial layer, wherein the substrate (S), the first epitaxial layer and the second epitaxial layer form a semiconductor body (SB) having a first side, a second side (102) opposite the first side (101) and an outer edge (OR), wherein the semiconductor body (SB) comprises an active region (CR) and an edge termination region (RR) located between the active region (CR) and the outer edge (OR); Formation of an initial allocation area (SR) in the active area (CR); Forming a first electrode (SE) located on the first side (101) of the semiconductor body (SB) in contact with the first doping region (SR); Formation of a second doping area (DR) in the active area (CR) and in the boundary closure area (RR); and Forming a second electrode (DE) which is arranged on the second side (102) of the semiconductor body (SB) in contact with the second doping region (DR), wherein the cavity and the further cavity are formed at different depths relative to the first side (101) of the semiconductor body (SB).

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