Method for producing an optoelectronic semiconductor chip

Abstract

Method for producing an optoelectronic semiconductor chip (10) comprising the following steps in the specified order: A) producing a nucleation layer (2) on a growth substrate (1), B) applying a mask layer (3) to the nucleation layer (2), wherein the mask layer (3) is formed by a plurality of mask islands, C) growing a coalescence layer (4), wherein the coalescence layer (4) is grown starting from areas of the nucleation layer (2) not covered by the mask islands with a first main growth direction perpendicular to the nucleation layer (2), so that webs (41) are formed which form a lattice when viewed in plan view and which have trapezoidal cross-sectional areas (44), D) further growth of the coalescence layer (4) with a second main growth direction parallel to the nucleation layer (2) to form a coherent and continuous layer, E) Growing a multiple quantum well structure (5) on the coalescence layer (4), F) applying a mirror (7) which has metallic contact regions (71) for impressing a current into the multiple quantum well structure (5) and mirror islands (72) for the total reflection of radiation generated in the multiple quantum well structure (5), and G) Detaching the growth substrate (1) and producing a roughening (9) by etching, wherein the mask layer (3) serves as an etching mask, wherein between the mirror (7) and the multiple quantum well structure (5) there is a cover layer (6) which is made of p-doped GaN and which extends in places into the multiple quantum well structure (5), wherein in the region of the mirror islands (72), in the direction away from the cover layer (6), the mirror (7) consists of the following sublayers, in the specified order: - between 100 nm and 500 nm SiO2, - between 1 nm and 20 nm ZnO, - between 50 nm and 300 nm Ag, and - between 2 nm and 150 nm ZnO.

Description

[0001] A method for producing an optoelectronic semiconductor chip is specified.

[0002] The document DE 10 2012 217 644 A1 relates to an optoelectronic component.

[0003] The document DE 10 2012 217 640 A1 relates to an optoelectronic component and a method for its production.

[0004] The document WO 2010 / 077 287 A1 is directed to a highly reflective composite layer.

[0005] The document DE 10 2007 022 947 A1 relates to an optoelectronic component and a method for its production.

[0006] One task to be solved is to provide an optoelectronic semiconductor chip with high internal and external quantum efficiency.

[0007] This problem is solved, among other things, by a method having the features of the independent patent claim. Preferred developments are the subject of the dependent claims.

[0008] According to at least one embodiment, the method serves to produce an optoelectronic semiconductor chip. The semiconductor chip is preferably a radiation-emitting semiconductor chip. A wavelength of maximum intensity of the emitted radiation is, for example, at least 360 nm or 420 nm and / or at most 1500 nm or 750 nm or 550 nm or 495 nm. The optoelectronic semiconductor chip is particularly preferably a light-emitting diode, or LED for short.

[0009] According to at least one embodiment, the method comprises the step of generating a nucleation layer on a growth substrate. The growth substrate may be a foreign substrate with respect to a material of the nucleation layer. This means that the growth substrate is then based on a different material or material system than the nucleation layer. For example, the growth substrate is a sapphire substrate or a silicon substrate. The nucleation layer may comprise one or more sublayers. The sublayers may differ from one another in their material composition.

[0010] According to at least one embodiment, the method comprises the step of applying a mask layer to the nucleation layer. The mask layer can have one or more partial layers stacked one above the other. The mask layer is formed from a plurality of mask islands. The mask islands preferably represent material regions made of a material of the mask layer that are not connected to one another by any material of the mask layer itself. The mask islands are preferably all of the same design, particularly when viewed from above. Alternatively, it is also possible for the mask islands to have different shapes.

[0011] According to at least one embodiment, the method comprises the step of growing a coalescence layer. The coalescence layer is preferably formed from a semiconductor material and is preferably based on a similar or the same material system as the nucleation layer.

[0012] According to at least one embodiment, the coalescence layer is grown starting from regions of the nucleation layer not covered by the mask islands. In other words, the nucleation layer then forms a growth base for the coalescence layer.

[0013] According to at least one embodiment, the coalescence layer is grown in a first growth step with a first main growth direction. The first main growth direction is oriented perpendicular to the nucleation layer. In other words, a growth rate along the first main growth direction is then higher than growth in a direction parallel to the nucleation layer.

[0014] According to at least one embodiment, the first growth step of the coalescence layer forms ridges. The ridges preferably have a trapezoidal cross-sectional area when viewed in a cross-section perpendicular to the nucleation layer. Thus, the ridges have an upper side facing away from the nucleation layer, which is oriented parallel or substantially parallel to the nucleation layer.

[0015] According to at least one embodiment, the webs and the upper sides of the webs, viewed in plan view, form a grid. The grid is preferably a regular grid. In particular, the grid is a hexagonal grid.

[0016] According to at least one embodiment, the first growth step of the coalescence layer is followed by a second growth step. In the second growth step, growth occurs predominantly or exclusively along a second main growth direction oriented parallel to the nucleation layer. The second growth step begins from the ridges formed in the first growth step. In particular, the first and second growth steps follow one another directly. The two growth steps differ in their process parameters.

[0017] According to at least one embodiment, the coalescence layer is grown into a coherent and continuous layer in the second growth step. This means that, in particular, a coherent, hole-free, gapless coalescence layer is formed only in the second growth step. The resulting coherent layer, which is flat on a side facing away from the nucleation layer, forms a growth base with a comparatively low dislocation density or defect density for further layers.

[0018] According to at least one embodiment, a single quantum well structure or, preferably, a multiple quantum well structure is grown on the coalescence layer. It is possible to create a further layer between the multiple quantum well structure and the coalescence layer, in particular a current distribution layer for a current distribution in a direction parallel to the multiple quantum well structure. Alternatively, the coalescence layer itself may be a current spreading layer.

[0019] According to at least one embodiment, a mirror is produced. The mirror has contact regions. The contact regions are preferably formed from a metallic material or comprise a metallic material. The contact regions are configured to inject current into the multiple quantum well structure.

[0020] According to at least one embodiment, the mirror comprises a plurality of mirror islands. The mirror islands are configured for total reflection of radiation generated in the multiple quantum well structure during operation of the finished optoelectronic semiconductor chip. Preferably, the mirror islands are each surrounded by contact regions. The contact regions can be formed by a single, contiguous contact region.

[0021] According to at least one embodiment, the method comprises the step of detaching the growth substrate from the nucleation layer. It is possible that the nucleation layer is partially or completely detached and / or destroyed in the process.

[0022] According to at least one embodiment, a roughening is created. The roughening is created by etching, which can be performed using dry or wet etching methods. During this etching, by which the roughening is created, the mask layer serves as an etching mask.

[0023] The method is designed for producing an optoelectronic semiconductor chip. The method comprises at least the following steps, preferably in the specified order: A) Creating a nucleation layer on a growth substrate, B) Applying a mask layer to the nucleation layer, wherein the mask layer is formed by a plurality of mask islands, C) growing a coalescence layer, wherein the coalescence layer is grown starting from areas of the nucleation layer not covered by the mask islands with a first main growth direction perpendicular to the nucleation layer, so that webs are formed which form a lattice when viewed in plan view and which have trapezoidal cross-sectional areas, D) Further growth of the coalescence layer with a second main growth direction parallel to the nucleation layer to form a coherent and continuous layer, E) Growing a multiple quantum well structure on the coalescence layer, F) Applying a mirror having metallic contact areas for current injection into the multiple quantum well structure and mirror islands for total reflection of radiation generated in the multiple quantum well structure, and G) Detaching the growth substrate and creating a roughening by etching, whereby the mask layer serves as an etching mask.

[0024] In the area of ​​the mirror islands, in the direction away from the cover layer, the mirror is formed from the following sub-layers, in the given order: - between 100 nm and 500 nm SiO2, - between 1 nm and 20 nm ZnO, - between 50 nm and 300 nm Ag, and - between 2 nm and 150 nm ZnO.

[0025] In the process described here, regions with a comparatively high defect density, particularly so-called V-defects, also known as V-pits, form above the top surfaces of the ridges on the ridge tops. The V-defects are largely localized to regions above the top surfaces of the ridges. Between the ridge tops there are regions of reduced, low defect density. Along the V-defects there is increased charge carrier transport in the direction perpendicular to the multiple quantum well structure and into or through the multiple quantum well structure. These vertical current paths due to the V-defects allow more quantum wells to be supplied with current, thereby reducing the current density per quantum well structure. This makes it possible to improve the efficiency of the semiconductor chip at overall higher current densities. The defect-free regions between the top surfaces of the ridges, as seen in plan view, also enable improved low-current behavior.Due to the roughening, which preferentially correlates with the areas with high defect density, an increased radiation output efficiency can be achieved. Furthermore, reflection losses within the semiconductor chip are reduced by the totally reflective mirror islands. Thus, the process described here makes it possible to realize a semiconductor chip with increased internal and external quantum efficiency.

[0026] According to at least one embodiment, the grating formed by the webs is arranged with the top sides of the webs congruent with the contact regions of the mirror, as seen in plan view. This means, in particular, that the hexagonal grating formed by the top sides of the webs is congruent with the hexagonal grating formed by the contact regions, as seen in plan view. A displacement between the two gratings relative to one another is preferably 100%, 50%, 25%, or 5% of an average width of the top sides of the webs, in the direction parallel to the multiple quantum well structure.

[0027] According to at least one embodiment, the nucleation layer, the coalescence layer, the current spreading layer, the multiple quantum well structure and / or a cover layer on a side of the multiple quantum well structure facing away from the coalescence layer form a semiconductor layer sequence.

[0028] The semiconductor layer sequence is preferably based on a III-V compound semiconductor material. The semiconductor material is, for example, a nitride compound semiconductor material such as Al n In 1-n-m Ga m N or a phosphide compound semiconductor material such as Al n In 1-n-m Ga m P or an arsenide compound semiconductor material such as Al n In 1-n-m Ga m As, where 0 ≤ n ≤ 1, 0 ≤ m ≤ 1, and n + m ≤ 1. The semiconductor layer sequence can contain dopants as well as additional components. For the sake of simplicity, however, only the essential components of the crystal lattice of the semiconductor layer sequence, i.e., Al, As, Ga, In, N, or P, are listed, even though these may be partially replaced and / or supplemented by small amounts of other substances.

[0029] According to at least one embodiment, the semiconductor layer sequence is based on the AlInGaN material system. In this case, the nucleation layer preferably comprises one or more sublayers of aluminum nitride, aluminum oxynitride, and / or AlGaN. The nucleation layer can consist of one or more such sublayers.

[0030] According to at least one embodiment, the mask layer is made of a silicon oxide and / or a silicon nitride and / or a silicon oxynitride. Alternatively, the mask layer can also be formed from another metal oxide or metal nitride, such as aluminum oxide or aluminum nitride. The mask layer preferably has a thickness of at least 5 nm, 25 nm, or 100 nm and / or of at most 1 µm, 500 nm, or 300 nm.

[0031] According to at least one embodiment, the mask layer comprises a partial layer or the mask layer is formed from a material that absorbs visible light and / or near-infrared radiation. Such a mask layer can serve as a shadow mask in a lithography step and / or as a release layer in a laser lift-off process, or LLO for short.

[0032] According to at least one embodiment, the mask islands of the mask layer or at least a sublayer of the mask islands have an absorption coefficient of at least 60%, 85%, or 96% for at least one spectral subrange between 240 nm and 480 nm, as seen in transmission. For example, the absorption coefficient of the mask islands is at least 70% or 80% at a wavelength of 240 nm and / or at least 5% or 10% at a wavelength of 480 nm. Alternatively or additionally, the nucleation layer and / or the growth substrate have an absorption coefficient of at most 5% or 1% in this spectral subrange, as seen in transmission.

[0033] According to at least one embodiment, the coalescence layer is formed from GaN. Alternatively, the coalescence layer comprises GaN and AlGaN, optionally in multiple sublayers. The coalescence layer is preferably doped, in particular n-doped.

[0034] According to at least one embodiment, the multiple quantum well structure is based on the material system AlInGaN or InGaN. The multiple quantum well structure then comprises a plurality of alternating barrier layers and quantum well layers. In particular, the multiple quantum well structure is configured to generate blue light. The quantum well layers of the multiple quantum well structure can all have the same structure or can be configured to emit radiation of different wavelengths.

[0035] For example, the multiple quantum well structure has at least 4 or 7 and / or at most 20 or 12 or 10 radiation-active quantum well layers, for example, 9 radiation-active quantum well layers. Optionally, additional dark quantum well layers are present that generate no or only a small amount of radiation during normal operation of the semiconductor chip, for example, together generating a maximum of 2% of the total radiation generated in the multiple quantum well structure.

[0036] According to at least one embodiment, the cover layer directly adjoins the mirror and the multiple quantum well structure. The cover layer is preferably formed from the material system AlInGaN, preferably GaN. Furthermore, the cover layer is preferably doped, in particular p-doped.

[0037] According to at least one embodiment, the capping layer extends into the multiple quantum well structure in places. In particular, a material of the capping layer fills V-troughs or V-holes in the multiple quantum well structure that are formed in the region of the V-defects. These V-defects, viewed in cross-section, are therefore V-shaped. In particular, these defects or recesses of the multiple quantum well structure, into which the capping layer extends, have the shape of pyramids or truncated pyramids. Such defects are also referred to as V-pits. In other words, the capping layer or a material of the capping layer can extend into the multiple quantum well structure in a needle-like manner. These needles preferably do not completely penetrate the multiple quantum well structure.

[0038] According to at least one embodiment, the metallic contact regions of the mirror are formed from Ag, Al, and / or a transparent conductive oxide such as ZnO or ITO. In particular, the contact regions consist of Ag, Al, an Ag alloy, or an Al alloy. An adhesion promoter layer can be located between the metallic contact regions and the cover layer. Such an adhesion promoter layer is formed, for example, from a transparent conductive oxide, TCO for short, or from a metal such as Pt, Ti, or Ni. It is possible for the contact regions to be in direct, physical contact with the cover layer if no adhesion promoter layer is present. Otherwise, the adhesion promoter layer preferably borders directly on the cover layer and the metallic contact regions. The adhesion promoter layer, particularly at the metallic contact regions, can be thin, i.e., for example, a maximum of 10 nm or 5 nm thick.

[0039] According to at least one embodiment, the mirror islands are in direct contact with the cap layer. Furthermore, the mirror islands are designed to be electrically insulating in the direction perpendicular to the multiple quantum well structure during intended use of the semiconductor chip. A material of the mirror islands that borders the cap layer is particularly preferably a transparent, dielectric material such as silicon oxide or aluminum oxide.

[0040] According to at least one embodiment, the mirror islands are covered, preferably completely covered, by a terminal mirror layer on a side facing away from the multiple quantum well structure. The terminal mirror layer can directly border the mirror islands and can be formed from the same material as the metallic contact regions, in particular silver or aluminum. An adhesion-promoting layer, especially made of a TCO, can also be applied between a dielectric material of the mirror islands and the terminal mirror layer.

[0041] According to at least one embodiment, the mirror in the region of the mirror islands, in the direction away from the cover layer, is formed from the following sublayers, in the specified order: - SiO2 with a thickness of at least 100 nm or 150 nm or 500 nm and / or at most 600 nm or 1 µm, particularly preferably 580 nm, - TCO, in particular ZnO, with a thickness of at least 1 nm or 3 nm or 50 nm and / or 300 nm or 150 nm or at most 50 nm or 20 nm, preferably 80 nm to 120 nm, - Ag with a thickness of at least 50 nm or 100 nm and / or at most 300 nm or 200 nm, and - TCO, in particular ZnO, with a thickness of at least 2 nm or 5 nm or 50 nm and / or at most 300 nm or 150 nm or 100 nm or 40 nm.

[0042] According to at least one embodiment, the mask islands are formed by regular structures when viewed from above. For example, the mask islands are circular or formed as polygons such as hexagons or octagons. Furthermore, the mask islands are preferably arranged in a regular hexagonal grid, with the mask islands located at vertices of the grid.

[0043] According to at least one embodiment, an average diameter of the mask islands is at least 0.25 µm or 0.5 µm or 1 µm. Alternatively or additionally, the average diameter is at most 10 µm or 5 µm or 3 µm or 2 µm. An average distance between adjacent mask islands is alternatively or additionally at least 0.5 µm or 1 µm and / or at most 5 µm or 3 µm or 2 µm or 1.5 µm. A surface area of ​​the nucleation layer covered by the mask islands is preferably at most 60% or 40% or 30% and / or at least 15% or 30%.

[0044] According to at least one embodiment, an average width of the upper sides of the webs before step D) and after step C) is smaller than the average distance between adjacent mask islands of the mask layer. The average width of the webs is preferably at most 70%, 50%, or 35% of the average distance between the mask islands. Furthermore, the area proportion of the upper sides of the webs, viewed in plan view, is preferably at most 60%, 40%, 30%, or 20% of the total area of ​​the nucleation layer, viewed in plan view. Alternatively or additionally, the area proportion of the upper side, viewed in plan view, is at least 15% or 30%.

[0045] According to at least one embodiment, the webs have a truncated pyramid shape in the free spaces between the upper sides after step C) and before step D). In particular, these free spaces are hexagonal truncated pyramids.

[0046] According to at least one embodiment, the first growth step in process step C) takes place at a lower growth temperature than the second growth step in process step D).

[0047] According to at least one embodiment, a carrier is attached to the mirror prior to step I), i.e., prior to removing the growth substrate. For example, the carrier is soldered or bonded to the mirror. The carrier is preferably the component of the finished semiconductor chips that mechanically supports and mechanically stabilizes the semiconductor chips. Thus, the carrier preferably remains in the finished semiconductor chip.

[0048] According to at least one embodiment, the multiple quantum well structure is energized exclusively via the carrier and / or exclusively from the direction of the carrier. For this purpose, electrical connections for energizing a side of the multiple quantum well structure facing away from the carrier can be routed both through the mirror and through the multiple quantum well structure, in particular into the current spreading layer and / or the coalescence layer.

[0049] According to at least one embodiment, regions directly above the top surfaces of the ridges on a side of the coalescence layer facing away from the growth substrate have a higher dislocation density than regions located between the top surfaces of the ridges, as seen in plan view. As a result, the multiple quantum well structure also has a higher density, particularly at the V-defects, in the regions above the top surfaces of the ridges than in the regions between the top surfaces of the ridges, as seen in plan view.

[0050] According to at least one embodiment, the regions with the higher density of V-defects, starting from the metallic contact regions of the mirror, are configured to conduct current in a direction perpendicular to the mirror into the multiple quantum well structure and, less preferably, through the multiple quantum well structure. In other words, the V-defects serve as vertical current paths.

[0051] According to at least one embodiment, the mask layer is still partially or completely present in the finished semiconductor chip. This means that the mask layer is then a component of the finished semiconductor chip and, in particular, represents part of a radiation exit surface of the semiconductor chip. If the mask layer consists, for example, of a layer stack of SiO2 / SiN / SiO2, then at least the SiN partial layer, in which the LLO also acts, is preferably removed, in particular wet-chemically, so as not to function as an absorber in the finished semiconductor chip.

[0052] According to at least one embodiment, the nucleation layer is completely or partially removed, in particular by at least 90%. This means that the nucleation layer is then no longer present in the finished semiconductor chip or is present only to a negligible extent.

[0053] According to at least one embodiment, the roughening does not extend into the multiple quantum well structure. It is possible that the roughening is limited to the coalescence layer and then does not extend into the optional, additional current spreading layer.

[0054] According to at least one embodiment, the regions with the high density of V-defects extend from the metallic contact regions of the mirror through the multiple quantum well structure to the coalescence layer, in particular to the upper sides of the ridges. This makes it possible to achieve particularly high vertical current conductivity. Alternatively, the V-defects extend through the multiple quantum well structure but not to the ridges. For example, the V-defects then begin approximately 200 nm below the multiple quantum well structure, viewed along the growth direction. A maximum average distance between the multiple quantum well structure and the beginning of the V-defects, along the growth direction, is preferably at most 250 nm, 500 nm, or 1000 nm.

[0055] Furthermore, an optoelectronic semiconductor chip is specified. The semiconductor chip is manufactured using a method as specified in connection with one or more of the above-mentioned embodiments. Features of the semiconductor chip are therefore also disclosed for the method, and vice versa.

[0056] A method and an optoelectronic semiconductor chip described herein are explained in more detail below with reference to the drawings using exemplary embodiments. Like reference numerals indicate like elements in the individual figures. However, they are not drawn to scale; rather, individual elements may be exaggerated for clarity.

[0057] They show: Fig. 1 schematic representations of process steps of a method described here for producing an optoelectronic semiconductor chip described here, Fig. 2 a schematic plan view of a coalescence layer for a process described here, Fig. 3 schematic representations of a multiple quantum well structure for an optoelectronic semiconductor chip described here, and Fig. 4 a plan view of a roughening for an optoelectronic semiconductor chip described here.

[0058] In Fig. 1 schematically shows process steps for producing an optoelectronic semiconductor chip 10. According to Fig. 1A, a growth substrate 1 is provided. The growth substrate 1 is, for example, a sapphire substrate. Alternatively, a silicon substrate can also be used.

[0059] In the process step as in Fig. As shown in Figure 1B, a nucleation layer 2 is created directly on the growth substrate 1. The nucleation layer is, for example, an AlN layer.

[0060] According to Fig. 1C, a mask layer 3 is applied directly onto the nucleation layer 2. For example, the mask layer 3 is a layer stack of SiO2 - silicon nitride - SiO2, in particular each with a layer thickness of 25 nm to 250 nm, for example, approximately 100 nm each. The middle layer of the mask 3, in this case the silicon nitride layer, can have an absorbing effect on UV radiation.

[0061] In Fig. 1D shows that the mask layer 3 is preferably structured by photolithography and subsequent etching. Regarding the sectional view in Fig. 1D is a schematic plan view in Fig. 1E. The resulting mask layer 3 is thus formed by a plurality of circular mask islands arranged in a regular, hexagonal grid.

[0062] In the process step, as shown in the sectional view in Fig. As shown in Figure 1F, a coalescence layer 4 is grown starting from the nucleation layer 2. In a first growth step, primarily vertical growth occurs, i.e., growth in a direction perpendicular to the nucleation layer 2. Viewed in a cross-section 44, this results in a trapezoidal shape in a region above the mask layer 3, viewed in the direction away from the growth substrate 1.

[0063] As seen from the top view in Fig. 1G can be seen, where Fig. 1G is an SEM image, this first growth step from the Fig. 1F connected webs 41, which have an upper side 42 facing away from the growth substrate 1. This upper side 42 is aligned parallel to the nucleation layer 2. In Fig. 1H is a close-up of the Fig. 1G. The average width of the ridges, in the direction parallel to the nucleation layer 2, is approximately 500 nm.

[0064] This first, vertical growth results in dislocations 46, starting from the nucleation layer 2, which extend approximately vertically through the webs 41 to the top 42 and to the side flanks. To reduce the number of dislocations 46 in the subsequent layer, the growth step is repeated as shown in Fig. 1F, usually continues until the top side 42 disappears. However, in the method described here, this growth step is terminated prematurely, so that the top side 42 remains and the webs 41 are formed, as in connection with the Fig. 1F to 1H.

[0065] As in Fig. As shown in Figure 1I, in a second growth step, the coalescence layer 4 essentially grows horizontally. This causes the dislocations 46, which are formed on the side flanks of the webs 42, to bend. Fig. 1F, in an approximately horizontal direction. The coalescence layer 4 is preferably formed from undoped or at least not intentionally doped GaN.

[0066] Such nucleation layers, mask layers and coalescence layers are also specified in the document DE 10 2011 114 671 A1, see in particular paragraphs 43 to 48 and 55 to 61 and claims 2, 5, 7 and 10. In particular, middle layers may also be present in addition, as described in this document.

[0067] Furthermore, the growth of the coalescence layer and the construction of the mask layer can be carried out as described in the document WO 2014 / 048 805 A1, see in particular page 7, line 17 to page 9, line 25 and page 11, line 20 to page 13, line 24.

[0068] Growth conditions for the vertical and horizontal growth of GaN can be found in the article by Hiramatsu et al. in Journal of Crystal Growth, Vol. 221, pages 316 to 326 from 2000, and in the article by Gilbert in Reports on Progress in Physics, Vol. 67, pages 667 to 715 from 2004.

[0069] According to Fig. 1J is applied to the coalescence layer 4, which after the process step in Fig. 1I is a continuous and smooth layer, a multiple quantum well structure 5 is grown. The multiple quantum well structure 5 has alternating barrier layers 52 and quantum well layers 51, see also Fig. 3A. In the regions between the mask islands of mask layer 3, dislocations 46, also referred to as V-defects, are exposed on a top side of coalescence layer 4 facing away from nucleation layer 2. V-defects develop at these dislocations 46 in the multiple quantum well structure 5, which continue in the direction away from nucleation layer 2. Alternatively, the V-defects can also be grown in a special defect accretion layer (not shown). Such a defect accretion layer serves to generate an increased number of V-defects and, unlike the multiple quantum well structure 5, preferably does not have a superlattice structure. The defect accretion layer is located, along the growth direction of the semiconductor layer sequence, preferably approximately 200 nm in front of the multiple quantum well structure 5.

[0070] According to Fig. A capping layer 6 is grown directly onto the multiple quantum well structure 5 at a thickness of 1K. The capping layer 6 is based on p-doped GaN. The capping layer 6 is grown in such a way that it extends into the V defects in the multiple quantum well structure 5 and fills these V defects.

[0071] In areas with many V-defects, a different band structure results than in areas next to the defects, see the schematic representations of a band energy E C in the Fig. 3B and Fig. 3C along the intersection lines BB and CC Fig. 3A. Along these V-defects, improved current conduction through and into the multiple quantum well structure 5 thus occurs. As a result, the multiple quantum well structure 5 can have a larger number of energized and / or radiation-active quantum well layers 51, thereby increasing the radiation generation efficiency of the semiconductor layer sequence.

[0072] In the Fig. 1L and Fig. 1M shows that a mirror 7 is applied to the cover layer 6. According to Fig. 1L, a layer of a dielectric material, for example a silicon dioxide layer 72a, is first applied directly to the cover layer 6. A ZnO layer 72b is then applied continuously to this silicon dioxide layer 72a. A plurality of mirror islands 72 are then created by lithography and etching. The mirror islands 72 are arranged congruently or approximately congruently with the mask islands of the mask layer 3. In other words, the resulting structure of the mirror islands 72 can be shaped as shown in Fig. 1E for the mask islands of mask layer 3.

[0073] To photolithographically form the mirror islands 72, the mask islands can be used as a shadow mask for a photoresist, which is exposed from the growth substrate 1 to radiation to which the mask islands are opaque. Likewise, the phototechniques for the mirror islands 72 and the mask islands can be adjusted by exciting the multiple quantum well structure 5 to photoluminescence. In this case, areas with many V-defects, i.e., the areas above the top surfaces 42 of the ridges 41, appear darker.

[0074] According to Fig. 1M, contact areas 71 are created in the gaps between the mirror islands 72, which are configured to impress current into the cover layer 6. The contact areas 71 are preferably metallic contact areas. For example, the contact areas 71 are formed from a metal such as silver.

[0075] Silver is also deposited on the mirror islands 72, in the form of a final mirror layer 73a. To improve adhesion, a ZnO layer 73b is optionally deposited on the final mirror layer 73a. The contact areas 71, the mirror islands 72, and the final mirror layers 73a, 73b form the mirror 7 as a continuous, coherent structure.

[0076] Contrary to what is shown, it is optionally possible for a layer to be located between the metallic contact region 71 and the cover layer 6 to improve adhesion or electrical contact, for example a thin layer of a transparent conductive oxide such as ZnO.

[0077] In the contact regions 71, the material of the contact regions has a normal reflecting effect on radiation generated in the multiple quantum well structure 5. If radiation strikes the mirror islands 72 at comparatively shallow angles, total internal reflection occurs at the mirror islands 72. If radiation is incident at a comparatively steep angle, it passes through the mirror islands 72 and is reflected back at the final mirror layer 73a. Since a dielectric material such as silicon dioxide can be used for the mirror islands 72, the mirror islands 72 on the cover layer 6 can, on the one hand, have a lower refractive index, which leads to increased total internal reflection. On the other hand, materials such as TCOs can be avoided. Such TCOs exhibit increased radiation absorption compared to dielectric materials such as silicon dioxide.Due to the efficient current distribution along the V defects in the multiple quantum well structure, an electrically conductive material on the cover layer 6 in the region of the mirror islands 72 is unnecessary. In other words, the mirror islands 72 are designed to be electrically insulating in the direction perpendicular to the mirror 7.

[0078] In Fig. 1N shows that a permanent support 8 is attached to the mirror 7, for example, by soldering or bonding. A bonding layer between the mirror 7 and the support 8 is not shown for simplicity.

[0079] Mirrors with contact areas and mirror islands can also be found in the publication US 2010 / 0 208 763 A1.

[0080] In Fig. 10 shows that the growth substrate 1 and the nucleation layer 2 are removed from the mask layer 3 and the coalescence layer 4, for example by means of a laser lift-off process, wherein a material decomposition by the laser radiation can take place, for example, in a partial layer of the mask layer 3, preferably, or also in the nucleation layer 2.

[0081] Subsequently, a roughening 9 is created, in particular by wet-chemical etching, for example using KOH, wherein the roughening 9 is preferably limited to the coalescence layer 4. Alternatively, the roughening can also partially penetrate the coalescence layer 4, wherein the multiple quantum well structure 5 is preferably not affected by the roughening. A resulting structure is shown in an SEM image in Fig. 4 shown.

[0082] This roughening is preferably produced as described in document DE 10 2012 101 211 A1, see in particular paragraphs 15 and 53 to 67.

[0083] The finished semiconductor chip 10, as shown in Fig. 1P, is characterized by high external and internal quantum efficiency. This is achieved in particular by the improved mirror 7 with the electrically insulating mirror islands 72 and the metallic contact regions 71, in conjunction with the V-defects extending from the contact regions 71 to the roughened structures 9.

[0084] Due to the hexagonal grid 48 seen in plan view, see also the schematic plan view of the cover layer 6 in Fig.2, a uniform current injection into the multiple quantum well structure 5 is achievable, as seen in plan view. The dislocations 46 are localized along the hexagonal lattice 48, and the defect density between these regions is significantly reduced.

Claims

[1] Method for producing an optoelectronic semiconductor chip (10) comprising the following steps in the specified order: A) producing a nucleation layer (2) on a growth substrate (1), B) applying a mask layer (3) to the nucleation layer (2), wherein the mask layer (3) is formed by a plurality of mask islands, C) growing a coalescence layer (4), wherein the coalescence layer (4) is grown starting from areas of the nucleation layer (2) not covered by the mask islands with a first main growth direction perpendicular to the nucleation layer (2), so that webs (41) are formed which form a lattice when viewed in plan view and which have trapezoidal cross-sectional areas (44), D) further growth of the coalescence layer (4) with a second main growth direction parallel to the nucleation layer (2) to form a coherent and continuous layer, E) Growing a multiple quantum well structure (5) on the coalescence layer (4), F) applying a mirror (7) which has metallic contact regions (71) for impressing a current into the multiple quantum well structure (5) and mirror islands (72) for the total reflection of radiation generated in the multiple quantum well structure (5), and G) Detaching the growth substrate (1) and producing a roughening (9) by etching, wherein the mask layer (3) serves as an etching mask, wherein between the mirror (7) and the multiple quantum well structure (5) there is a cover layer (6) which is made of p-doped GaN and which extends in places into the multiple quantum well structure (5), wherein in the region of the mirror islands (72), in the direction away from the cover layer (6), the mirror (7) consists of the following sublayers, in the specified order: - between 100 nm and 500 nm SiO2, - between 1 nm and 20 nm ZnO, - between 50 nm and 300 nm Ag, and - between 2 nm and 150 nm ZnO. [2] Method according to the preceding claim, wherein the mirror islands (72) are designed to be electrically insulating in the direction perpendicular to the multiple quantum well structure during the intended use of the semiconductor chip. [3] Method according to one of the preceding claims, in which the grid formed by the webs (41) lies congruently over the contact areas (71), seen in plan view. [4] Method according to one of the preceding claims, in which - the nucleation layer (2) comprises or consists of one or more sub-layers of aluminium nitride, aluminium oxynitride and / or AlGaN, - the mask layer (3) is made of a silicon oxide and / or a silicon nitride, - the coalescence layer (4) is made of GaN or of GaN and AlGaN, - the multiple quantum well structure (5) is based on the material system AlInGaN and is designed to generate blue light. [5] Method according to the preceding claim, in which - the contact areas (71) comprise or consist of Ag, Al and / or ZnO and are in direct contact with the cover layer (6), - the cover layer (6) is applied directly to the multiple quantum well structure (5), - the mirror islands (72) are in direct contact with the cover layer (6) and are electrically insulating in the direction perpendicular to the multiple quantum well structure (5), and - the mirror islands (72) are covered on a side facing away from the multiple quantum well structure (5) by a terminating mirror layer (73) made of a material of the contact regions (71). [6] Method according to one of the preceding claims, in which the grid of the upper sides (42) of the webs (41) facing away from the growth substrate (1) and the contact regions (71) have a regular hexagonal structure when viewed in plan view. [7] Method according to one of the preceding claims, in which the mask islands are circular in plan view and are arranged in a regular hexagonal grid, wherein an average diameter of the mask islands is between 0.5 µm and 3 µm inclusive and an average distance between adjacent mask islands is between 0.5 µm and 3 µm inclusive. [8] Method according to the preceding claim, wherein after step C) and before step D) a width of an upper side (42) of the webs (41) is smaller than the average distance between adjacent mask islands of the mask layer, wherein, viewed in plan view, an area proportion of the upper sides (42) of the webs (4) is at most 10%, based on a total area of ​​the nucleation layer (2). [9] Method according to one of the preceding claims, in which after step C) and before step D) the webs (41) in free spaces between upper sides (42) are formed in the shape of a truncated pyramid, wherein step C) is carried out at a lower growth temperature than step D). [10] Method according to one of the preceding claims, in which a support (8) is attached to the mirror (7) before step G), wherein the multiple quantum well structure (5) is energized exclusively via the carrier (8), and wherein electrical connections for energizing a side of the multiple quantum well structure (5) facing away from the carrier (8) are guided through the mirror (7) and the multiple quantum well structure (5). [11] Method according to one of the preceding claims, wherein on a side of the coalescence layer (4) facing away from the growth substrate (1), there is a higher dislocation density in regions above the webs (41) than in regions between the webs (41), wherein the multiple quantum well structure (5) has a higher density of V-defects in the regions above the ridges (41) than in the regions between the ridges (41). [12] Method according to the preceding claim, in which the regions with the higher density of V-defects, starting from the contact regions (71), are arranged to conduct current in a direction perpendicular to the mirror (7) into the multiple quantum well structure (5). [13] Method according to one of claims 11 or 12, in which the mask layer (3) is partially present in the finished semiconductor chip (10), wherein the nucleation layer (2) is at least 90% removed and the roughening (9) does not extend into the multiple quantum well structure (5), and where the V defects extend from the mirror (7) through the multiple quantum well structure (5) to the coalescence layer (4). [14] Method according to one of the preceding claims, in which the mask islands of the mask layer (3) or a partial layer of the mask islands have an absorption factor of at least 60% for at least one spectral sub-range between 240 nm and 480 nm in transmission, wherein the nucleation layer (2) and the growth substrate (1) have an absorption coefficient of at most 5% in this spectral sub-range when viewed in transmission.

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