Invalidation data area for a cache

Abstract

Cache (104) comprising: a journal (206) configured to track data blocks (216) stored in the cache (104); and an invalidation data area (208) configured to track invalidated data blocks associated with the data blocks (216) tracked in the journal (206), the invalidation data area (208) being located in a region of the cache (104) separate from the journal (206).

Description

BACKGROUNDArea of ​​disclosure

[0001] The present disclosure relates to systems and methods for caching, and more particularly to providing a region for processing invalidated data for a cache. Related Disclosure

[0002] A cache can generally be used to accelerate access when reading or writing data to an underlying storage device, such as flash memory or a hard disk. Upon receiving a write operation from a host, the cache can update a stored data block to track whether the data block has changed (e.g., whether the data block is valid or invalid). Sometimes the cache can write the new data from the write operation to a different cache entry and postpone flushing or deleting the old cache entry. This is because flushing or deleting the old cache entry can cause a performance degradation while the cache waits for the underlying storage device to be updated. By taking advantage of this deferral, the cache can finish processing the write operation and perform a faster control return to the host.

[0003] Furthermore, the disclosure of US 2014 / 0 047 193 A1 may be helpful for understanding the present invention. This document describes a computer system having a cache with one or more memories, a cache journal for storing data associated with one or more portions of the cache, and a configuration manager for accessing the cache and the cache journal. The configuration manager can determine whether the cache journal contains data associated with a first portion of the cache and generate data in the cache journal associated with the first portion of the cache if the cache journal does not yet contain data associated with the first portion of the cache.The configuration manager is also capable of determining whether the first part of the cache is valid for use and communicating with a memory manager associated with the first part of the cache about whether the first part of the cache is valid for use. SUMMARY

[0004] Embodiments of the present disclosure relate to caches, methods, and systems for using an invalidation data area.

[0005] In particular, the present invention relates to a cache according to claim 1. Advantageous embodiments may comprise features of dependent claims.

[0006] In one embodiment, the present invention accordingly relates to a cache comprising a journal and an invalidation data area. The journal is configured to track data blocks stored in the cache. The invalidation data area is configured to track invalidated data blocks associated with the data blocks tracked in the journal, wherein the invalidation data area is located in a region of the cache separate from the journal.

[0007] The embodiments described herein may include further aspects. For example, the journal may be configured to track metadata for the data blocks, where the metadata may have a memory address corresponding to the data block, and the invalidation data area may be configured to track metadata corresponding to the invalidated data blocks, where the associated metadata may have a memory address corresponding to the invalidated data block.The journal may be configured to track the data blocks using journal blocks, wherein the journal blocks may be configured to store the metadata for the data blocks, and the invalidation data area may be configured to track the metadata associated with the non-valid data blocks using invalidation records and mapped journal blocks, wherein the mapped journal blocks may be configured to store the associated metadata for the non-valid data blocks and wherein the invalidation records may be configured to store the mapped journal blocks.The metadata tracked in the journal may further include an index into a collection of metadata stored in each journal block, and the metadata tracked in the invalidation data area may further include an index into a collection of metadata stored in each mapped journal block. The cache may be configured to determine an invalidation record number associated with an invalidation record in the invalidation data area based on a corresponding journal block number associated with a journal block. The cache may be configured to determine a mapped journal block number associated with a mapped journal block in the invalidation data area based on a corresponding journal block number associated with a journal block.The index tracked in the journal may be selected to have the same value as the index tracked in the invalidation data area. The memory address tracked in the invalidation data area may be truncated compared to the memory address tracked in the journal, and the truncation may be determined based on a storage size of an underlying storage device being cached or an offset determined based on a memory address of a block in the underlying storage device.Determining the mapped journal block may include determining a mapped journal block number for the mapped journal block by determining an invalidation record number by dividing a journal block number associated with the determined journal block by a capacity of the invalidation record in the invalidation data area and calculating a rounding function of the result of the division, wherein the invalidation record number identifies the invalidation record, and determining the mapped journal block number by calculating a modulo operation of the journal block number with the capacity of the invalidation record. Determining whether write operations are pending may include retrieving a field from an in-RAM data structure corresponding to the invalidation record.Consolidating the pending write operations may include queuing subsequent write operations, identifying write operations that operate on the same data block, and determining the individual write operation based on the write operations that operate on the same data block. The invalidation data area may be located in a separate region of the cache from the journal. The cache may be a content-locality cache, and the journal may track at least one of the allocated data blocks and independent data blocks in the content-locality cache. Determining the initial reconstruction may include restoring data blocks and metadata describing the data blocks, wherein the restored data blocks and metadata are restored from the journal.Determining whether the corresponding data block tracked in the journal is valid may include comparing metadata describing the corresponding data block tracked in the journal with metadata describing the corresponding data block tracked in the mapped journal block. Comparing the metadata may include comparing a first memory address and a first index for the corresponding data block tracked in the journal with a second memory address and a second index tracked in the mapped journal block. BRIEF DESCRIPTION OF THE CHARACTERS

[0008] Various objects, features, and advantages of the present disclosure will become more apparent by reference to the following detailed description taken in conjunction with the following drawings, in which like reference characters identify like elements. The following drawings are for illustrative purposes only and are not to be construed as limiting the invention, the scope of which is set forth in the following claims. Fig. 1 shows an example system with a cache according to some embodiments of the present disclosure. Fig. 2A-2B show example block diagrams of a cache according to some embodiments of the present disclosure. Fig. 3A-3B illustrate example mappings between a journal and an invalidation data area according to some embodiments of the present disclosure. Fig. 4 shows an exemplary method for invalidating using an invalidation data area according to some embodiments of the present disclosure. Fig. 5 shows an exemplary method for cache rebuilding according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0009] The present disclosure relates to systems and methods for using an invalidation data area for a cache. In some embodiments, the cache may include a journal area and an invalidation data area. The journal area may be a log-based journal for persistently tracking cache updates and cache operations in case of a cache rebuild requirement. The invalidation data area may store invalidation records for cache blocks that are removed or evicted from the cache. The invalidation data area may generally track information about cached data blocks that have been invalidated, for example, while caching is paused or otherwise interrupted. The invalidation data area may be attached to the journal area and occupy a separate region of the cache.Furthermore, in some embodiments, the invalidation data area may store a subset of metadata corresponding to a full set of metadata generally stored in the journal.

[0010] Fig. 1 shows an example system 100 including a cache 104, according to some embodiments of the present disclosure. The system 100 includes a host 102, the cache 104, and a storage device 106a-106c. The host 102 transmits read and write requests to the cache 104. The cache 104 processes the requests to read and write data to and from the underlying storage device 106a-106c. For example, to process a read request, the cache 104 may determine whether data corresponding to a requested memory address is stored in the cache. If the requested memory address is cached, this situation may sometimes be referred to as a "read hit." If the requested memory address is not cached, this situation may be referred to as a "read miss." Upon a read hit, the cache 104 may return the requested data more quickly directly from the cache 104.In contrast, in the case of a “read miss,” the cache 104 may read the requested data from the slower storage device 106a-106c.

[0011] In substantially the same way, to process a write request, cache 104 may determine whether a requested memory address is already stored in the cache. If the requested memory address is cached, this situation may sometimes be referred to as a "write hit." If the requested memory address is not cached, this situation may be referred to as a "write miss."

[0012] Fig. Figure 2A shows an example block diagram of cache 104 according to some embodiments of the present disclosure. In some embodiments, cache 104 may include a superblock 202, a reference data area 204, a journal 206, an invalidation data area 208, and a warm start area 210. Journal 206 may include journal blocks 212. Journal blocks 212 may include metadata 214 and data 216.

[0013] The cache 104 can employ a journal-based approach to provide durability, such that the cache 104 can be restored if necessary. Some embodiments of the journal 206 can be divided into journal blocks 212. For example, the journal blocks 212 can have a size of approximately 256 kB. Other sizes relative to the total size of the cache 104 can also be used. If a journal block 212 has a size of approximately 256 kB, the metadata 214 can occupy a size of approximately 4 kB and the data 216 can utilize approximately 252 kB. As previously stated, other sizes can also be used depending on the requirements of the journal 206 and the cache 104.

[0014] The data 216 may include the content associated with a cache block tracked in the journal 206. Examples of the metadata 214 may include a memory address (e.g., a logical block address (LBA)), a cache block type, an offset, and a hash value for error correction. An example of a cache block type may include tracking that a cache block is an independent block or a mapped block. An independent block and / or a mapped block may be used with a content locality cache. In some embodiments, the cache 104 may cache based on cache block similarity (content locality). A mapped block may track changes or deltas between baseline reference blocks.This content-locality caching may be in addition to determining when a cache block was last used (temporal locality) or identifying cache blocks with substantially the same memory addresses (spatial locality). An independent block may be a block cached based on temporal locality and / or spatial locality, but not content locality. The offset may identify a specific memory block of interest or a specific memory location within a memory block. For example, the offset may be substantially equal to a pointer into the data 216 relating to specific data of interest.

[0015] Because metadata 214 and data 216 can be combined into a single journal block 212, journal writes can occur in segments or batches, and the data and metadata can be combined into a single write operation. Storing both metadata 214 and data 216 in a single journal block 212 can therefore provide approximately a 50% reduction in separate write operations compared to writing metadata 214 and data 216 to different locations.

[0016] In some embodiments, the journal 206 may be a circular journal. That is, the cache 104 may generally write to the journal 206 sequentially, and upon reaching the end of the journal 206, the next write operation may wrap around to a starting point to begin the next round. The metadata and data corresponding to write hits to the cached data may be written to a new journal block 212 in the journal 206. Sequential writing may avoid the need to read metadata 214 otherwise stored in each journal block 212. However, support for sequential writes may also mean that the journal 206 has multiple journal blocks 212 corresponding to the same cache block. For example, a first write to a memory address 8 may be tracked in a journal block 1.A subsequent write to the same memory address, memory address 8, may be tracked in a journal block 3 (for example, if cache 104 has processed intervening cache block updates that used a journal block 2). Even if journal blocks 1 and 2 also track metadata and data corresponding to memory address 8, cache 104 can save processing time for the existing journal blocks. Instead, the design of journal 206 allows cache 104 to write the entry for journal block 3 directly to journal 206 without requiring any further metadata reading. Therefore, the sequential design can improve performance.

[0017] Journal 206 may also generally support multiple storage devices. That is, journal 206 does not distinguish between cache blocks from different cached target storage devices of interest. This multi-drive support may generally result in better space utilization in journal 206, as multi-drive support generally eliminates the need to pre-reserve space for different storage devices. Otherwise, journal 206 may contain unused space pre-reserved for a storage device that does not need the space, which may result in inefficient use of resources.

[0018] However, the journal 206 without the invalidation data area 208 may also exhibit reduced performance. An example use case includes caching multiple storage devices and operating in a write-back mode through the cache 104 (e.g., deferring the writing of updated cache data to the underlying storage device). If an eviction from the cache 104 to a storage device fails, the system cannot cache new data, not even new data for other storage devices. Instead, the system can preserve the old data so that it can be written back to the storage device. In the log-based non-volatile implementation described above, eviction can generally be expected to occur sequentially.In some embodiments, cache 104 may not discard data due to an unavailable storage device unless the user explicitly commands otherwise.

[0019] However, even in the case of an unavailable storage device, cache 104 may continue to maintain I / O operations to provide transparent service to other storage devices that are still available. This transparent caching may be achieved as follows: 1) In case of a cache miss, the cache 104 can pass the I / O operation. 2) Upon a read hit, the cache 104 may maintain the requested read operation from the cache 104. 3) On a write hit, the cache 104 can either (a) update or (b) invalidate the requested data from the cache.

[0020] Both operations may result in a read-modify-write cycle for the metadata 214 and a write operation for the data 216 (for example, in the case of an update request). Thus, each write hit may require 1 read and 1 write (for an invalidation) or 2 writes (for an update). Both scenarios may represent an overall performance penalty. Either of these approaches may deviate from the log-based approach of using a journal 206 without an invalidation data area 208 to write data. Furthermore, these scenarios may involve the risk of data loss, as the operations are not tiny and may benefit from being performed serially.

[0021] Fig. Figure 2B shows an example block diagram of a cache 104 according to some embodiments of the present disclosure. The cache 104 may include the invalidation data area 208. Invalidation data area 208 may generally store invalidation records 218 for cache blocks that are deleted or evicted from the cache 104.

[0022] The invalidation data area 208 may comprise a separate region of the cache 104 (e.g., separate from the journal 206). The system may map underlying journal blocks into this separate region using the invalidation records 218. In some embodiments, the cache may implement the separate region using a dedicated, predetermined namespace.

[0023] Accordingly, the invalidation data area 208 can offer the following advantages: 1) It maintains a protocol-based approach to writing journal data. That is, the design of the invalidation data area 208 can convert write operations that could otherwise potentially be random update or invalidation writes into sequential writes to the cache device. 2) It maps multiple journal blocks into a single invalidation record block (in Fig. 3A). For example, in some embodiments of the invalidation data area 208, three journal blocks may be mapped into one invalidation record. Consequently, the space used for the invalidation data area 208 may be approximately 0.5% of a total size of the cache 104. 3) Since the size of the invalidation data area 208 may be a small fraction of the total size of the cache 104, the invalidation data area 208 may generally be stored entirely in RAM. Furthermore, by generally storing the invalidation data area 208 in RAM, there may be no need to perform a read operation during invalidation. Even if the invalidation data area is not generally stored in RAM, the system may still exhibit a 66% reduction in the number of required reads. This is because records for three journal blocks can be mapped into one invalidation block. 4) By packing invalidation record block entries, the write overhead can be reduced so that multiple entries are written in a single write operation. Furthermore, there can be a 66% reduction in the number of write operations.

[0024] In general, the invalidation data area 208 can provide a transparent solution for error handling and maintaining data consistency. Furthermore, the invalidation data area 208 can provide these benefits without incurring a significant performance penalty.

[0025] Fig. 3A shows an example mapping between the journal 206 and the invalidation data area 208 according to some embodiments of the present disclosure. Fig. 3A shows the journal 206 and the invalidation data area 208. The journal 206 has journal blocks 1-3. The invalidation data area 208 has an invalidation record 1. The invalidation record 1 has mapped journal blocks 1-3.

[0026] In some embodiments, the invalidation records may generally be stored in the cache 104 in the separate invalidation data area. The invalidation records may generally use mapped journal blocks associated with an invalidation record to represent multiple journal blocks associated with the journal 206. For example, journal block 1 may correspond to mapped journal block 1, journal block 2 may correspond to mapped journal block 2, and journal block 3 may correspond to mapped journal block 3. Further, mapped journal blocks 1-3 may require less metadata to be stored than the corresponding underlying journal blocks 1-3. Accordingly, in some embodiments, the system may select a subset of the metadata of the underlying journal blocks 1-3 so that all three journal blocks can be stored in invalidation record 1.

[0027] Fig. 3B shows another example mapping between the journal 206 and the invalidation data area 208 according to some embodiments of the present disclosure. Fig. 3B includes journal 206 and invalidation data area 208. Journal 206 includes journal block 1 with metadata 214 and data 216. Invalidation data area 208 includes invalidation record 1. Invalidation record 1 includes mapped journal block 1. Mapped journal block 1 includes metadata 302.

[0028] Invalidation record 1 may have both a cached version and a relatively faster version loaded into random access memory (RAM). The in-RAM data structure may generally improve performance and reduce the need to read data from the relatively slower journal or cache 104. In some embodiments, an exemplary definition of invalidation record 1 may include the following:

[0029] An example invalidation record may have multiple mapped journal blocks (“journal_block”) and an error correction code (“checksum”).

[0030] In some embodiments of the invalidation record data structure, an exemplary definition of the mapped journal block referenced in the invalidation record data structure may include:

[0031] The mapped journal block may include a collection (e.g., an array) of memory addresses and offsets ("target_Iba"). The memory addresses may identify a memory block of interest, and the offset may identify specific memory blocks of interest or specific memory locations of interest within the memory blocks. The collection of memory addresses and offsets in the mapped journal block may be mapped to a corresponding collection of memory addresses and offsets stored in the underlying journal blocks. The mapped journal block may further include a timestamp ("epoch") that may match a corresponding timestamp stored in the underlying journal block.

[0032] In some embodiments, the in-RAM data structure representing an invalidation record may include the following.

[0033] The in-RAM data structure can generally improve performance and reduce the need to read data from the relatively slower journal or cache 104.

[0034] The mapped journal block may represent one journal block. In some embodiments, an invalidation record may have multiple mapped journal blocks. For example, Fig. 3A illustrates an invalidation record having a capacity of three mapped journal blocks (such that there may be a 3-to-1 mapping from journal blocks to an invalidation record). The mapped journal block may store entries of memory addresses that have been invalidated in the cache 104. In some embodiments, the memory addresses may be logical block addresses (LBAs). Although the present disclosure describes tracking three journal blocks using a single invalidation record, the invalidation record may have any number of mapped journal blocks, for example, determined based on the subset of metadata chosen to be stored in the mapped journal block. An exemplary journal block may be approximately 256 KB in size, and an exemplary invalidation record may be approximately 4 KB in size.Because there may be a 3-to-1 mapping between the journal blocks and the invalidation records, the invalidation data area 208 may be space-efficient. For example, the invalidation data area 208 may use only approximately 4 KB to yield 768 KB (3 journal blocks x 256 KB per journal block) of data in the journal 206. Accordingly, the space requirement for the invalidation data area 208 may be approximately 0.52% (4 KB / 768 KB). Furthermore, the 3-to-1 mapping between the mapped journal blocks and the invalidation records may reduce the number of read and write operations performed during the invalidation process by approximately 66%.In some embodiments, due to the small size of the invalidation data area 208 and the efficient space allocation, the entire invalidation data area 208 may be stored in random access memory (RAM) to reduce or even completely eliminate the number of read operations in the cache 104.

[0035] In some embodiments, the invalidation data area 208 may store a subset of the metadata 214 tracked in the journal 206. This efficiency may also contribute to the small size of the invalidation data area 208. For example, the metadata 214 tracked in the journal 206 may include a memory address (e.g., a logical block address (LBA)), a cache block type, an offset, and a hash value for error correction. In contrast, in some embodiments, the metadata 302 tracked in the invalidation data area 208 may include a subset of the metadata 214 tracked in the journal 206. For example, the system may choose to track only a corresponding memory address in the metadata 302. By tracking only a subset of the metadata, the space efficiency or capacity of the invalidation data area 208 may be improved.

[0036] Further modifications, depending on the use for and of the metadata stored in the journal 206 and the invalidation data area 208, may further affect this size. Examples of modifications may include increasing the size of the journal blocks, decreasing the size of the memory addresses stored in a mapped journal block, etc. In some embodiments of the system, the size of the memory addresses stored in a mapped journal block may be truncated. In one implementation, the truncation may be based on a memory size of the underlying storage device. For example, if the storage device is sufficiently small, the system may store approximately four bytes of memory addresses in the mapped journal block compared to a full memory address of approximately eight bytes stored in a corresponding journal block.

[0037] In another implementation, truncation may include determining an offset based on a memory address stored in the underlying storage device and storing the offset instead of the memory address. In embodiments of the cache, data blocks of approximately 4 kB in size may be stored. (If an I / O request is for a smaller size, the cache may retrieve the remaining data associated with the data block from the storage device and cache the entire contents of the 4 kB data block.) Thus, in some embodiments, truncation may include converting a memory address (such as an LBA) of the underlying storage device into offsets. In some embodiments, the offsets may be approximately 4 kB.For example, an offset 0 may represent the first 4 kB at the storage device, an offset 1 may represent the next 4 kB at the storage facility, etc. Accordingly, the cache may convert a memory address of, for example, a 512-byte LBA into a next available aligned 4-kB LBA. Instead of storing a full LBA, the system may convert a full LBA to an offset using a smaller number of bytes and store the offset in the invalidation record and the mapped journal block. For example, an LBA 0-7 in the underlying storage facility may correspond to an LBA 0 in the cache along with an optional offset. In some embodiments of the invalidation data area, a 4-byte offset field may thereby represent up to 16 terabytes of the underlying storage facility (2nd 32× 4,096). For larger storage devices, in some embodiments of the system, the cache block size can be increased to approximately 8 kB or more, the offset size can be increased to approximately 5 bytes, etc.

[0038] In some embodiments of cache 104, cache blocks may be invalidated by determining a mapping between journal 206 and invalidation data area 208. That is, cache 104 may determine an appropriate invalidation record, a mapped journal block, and a corresponding index in invalidation data area 208 for a data block based on the journal block and the index in journal 206.

[0039] For example, assume that cache 104 performs an invalidation of a data block located in journal block 1 at index 3 (304a). Based on the journal block and the index in journal 206, cache 104 may generally determine the corresponding invalidation record, the mapped journal block, and the index in the mapped journal block. First, cache 104 may determine an invalidation record based on the corresponding journal block. Because the journal blocks may perform a 3-to-1 mapping to the capacity of the invalidation records, in some embodiments of cache 104, a division operation and a rounding operation (e.g., rounding up) may be performed to determine the corresponding invalidation record. For example, for journal block 1, the system may calculate 1 / 3 = 0.33... and ⌈0.33...⌉=1 which maps journal block 1 to invalidation record 1. In another example, if the system maps journal block 5 to invalidation record, 5 / 3 = 1.66... ​​and ⌈1.66...⌉=2, whereby journal block 5 is mapped to invalidation record 2.

[0040] Next, cache 104 may determine a mapped journal block based on a journal block. In some embodiments, cache 104 may apply a modulo operation to determine a mapped journal block based on the journal block number. For example, for journal block 1, the system may calculate 1 mod 3 = 1, thereby mapping journal block 1 to mapped journal block 1. In substantially the same manner, if the system maps journal block 5 to mapped journal block 5, 5 mod 3 = 2, thereby mapping journal block 5 to mapped journal block 2 within invalidation record 2 (previously determined).

[0041] Finally, the cache 104 may determine an index in the mapped journal block that corresponds to an index in the underlying journal block. In some embodiments of the cache 104, the same index may be used in the mapped journal block as the index used in the underlying journal block. That is, when writing the corresponding journal block entries to the invalidation data area 208, the journal block entries may be added at the same index in the target_Iba array of the mapped journal block as in a corresponding target_Iba array of the journal block. Accordingly, the index in the mapped journal block may be easily and quickly determined based on the index in the underlying journal block.

[0042] To perform reverse mapping (i.e., determining a journal block and a corresponding index based on an invalidation record, a mapped journal block, and index), cache 104 may perform reverse operations to those described above. For example, cache 104 may identify information about a memory address for an invalidated cache block based on the metadata 302 stored in the mapped journal block. Cache 104 may determine the journal block number based on the invalidation record number, and the index for the journal block may be inferred from the index used for the mapped journal block.

[0043] Fig. 4 shows an example method 400 for invalidating using the invalidation data area according to some embodiments of the present disclosure. In some embodiments, the method 400 may include: determining a journal block for a memory address in a received write operation (step 402); determining a mapped journal block and an offset based on the determined journal block and a corresponding invalidation record from the invalidation data area (step 404); determining whether there are any outstanding write operations (step 406); if yes, merging the write operations and performing the write operations as a single write to the cache (step 408); if no, performing the received write operation (step 410).

[0044] First, method 400 determines a journal block for a memory address in a received write operation (step 402). In some embodiments of method 400, the journal block may be identified based on the logical block address (LBA) in the received write operation. Or, upon a write hit (meaning the LBA was previously cached), method 400 may identify the journal block based on the LBA at which the cache block is stored in the cache.

[0045] Then, the method 400 proceeds to determine a mapped journal block based on the determined journal block and a corresponding invalidation record from the invalidation data area (step 404). In some embodiments, the invalidation record may be determined by performing division and rounding operations on the journal block number. Furthermore, in some embodiments, the index for the mapped journal block may be determined using the index used in the underlying journal block. For example, if the system uses the same indexes for the mapped journal block and the underlying journal block, the index may be easily and quickly determined.

[0046] Then, in method 400, it may be determined whether there are any pending write operations (step 406). In some embodiments, this determination may be performed using an in-RAM data structure corresponding to the invalidation record. For example, the in-RAM data structure may include a field ("pending") that identifies whether any write operations are pending. One advantage of using the in-RAM data structure is avoiding a relatively slower read operation in the underlying cache to retrieve the stored invalidation record.

[0047] If the method 400 determines that write operations are pending (step 406: Yes), the write operations and the performance of the write operations may be merged into a single write to the cache (step 408). In some embodiments of the method 400, upon a determination that write operations are pending, subsequent writes are queued. When the previous write operation is complete, the method 400 writes the queued writes to the cache as a single write containing the merged information of all updates. In some embodiments, merging may include identifying write operations that occur to the same data block, ordering the write operations based on a timestamp, and determining the final result of the ordered write operations.In this way, this stacking or merging of write operations allows method 400 to further reduce the number of read and write operations used for invalidation. If it is determined that no write operations are pending (step 406: No), method 400 may proceed to perform the received write operation (step 410).

[0048] Fig.5 shows an exemplary method 500 for cache reconstruction according to some embodiments of the present disclosure. Cache reconstruction refers to a situation in which the cache may benefit from reconstruction based on the journal and the invalidation data region, for example, after a power failure, a spurious system shutdown, or another unexpected event. The method 500 may include reconstructing the cache based on the journal (step 502); then, for each mapped journal block in each invalidation record (step 504): determining, based on the mapped journal entry, whether a corresponding cache block is valid (step 506); if so, returning to step 504; if not, evicting the stale block from the cache (step 508).

[0049] First, in method 500, the cache is reconstructed based on the journal (step 502). In some embodiments of the system, the contents of the journal may be assumed to represent generally valid data to be reconstructed in the cache. In some embodiments, the system may reconstruct the cache by retrieving each journal block from the journal and iteratively processing the metadata in each journal block to reconstruct each cache block. However, the journal block metadata may contain cache blocks that may have been invalidated. The system may later correct this initial assumption of generally valid data based on the invalidation data region. For example, the system may identify invalid cache blocks based on the invalidation data region and evict these stale cache blocks from the cache.

[0050] Next, the method 500 iterates through each mapped journal block in each invalidation record (step 504). For each mapped journal block, the metadata in the mapped journal block is processed to determine whether the corresponding cache blocks are valid or invalid (step 506). In some embodiments, determining whether a cache block is valid may be performed by determining whether the metadata in the mapped journal block is consistent with the underlying metadata in the underlying journal block. For example, the consistency of the underlying metadata in the underlying journal block may be determined by locating the corresponding journal block number and index based on division operations, rounding operations, and modulo operations.The metadata stored at the determined journal block number and index may then be prepared with the metadata stored in the mapped journal block. For example, assume that in method 500, based on the mapped journal block, it is identified that memory address 8 is expected to be found at the underlying journal block 1, index 3. In method 500, the corresponding contents of journal block 1 at index 3 of the metadata may then be retrieved. If this journal block tracks a cache block corresponding to memory address 8, it may be determined that the cache block corresponding to memory address 8 is invalid because the expected cache block based on the invalidation data area and the mapped journal block matches the actual cache block tracked in the corresponding underlying journal block.On the other hand, assume that in method 500, it is identified based on the mapped journal block that a cache block corresponding to a memory address 16 is expected to be found at the underlying journal block 1, index 4. If the actual cache block stored at the underlying journal block 1, index 4 does not match the memory address 16, method 500 may proceed to process the next metadata, since the cache block may remain in the cache if the expected cache block based on the invalidation data area and the mapped journal block does not match the actual cache block tracked in the corresponding underlying journal block.

[0051] If the metadata matches, method 500 may determine that the cache block is invalid (step 506: No). Accordingly, method 500 may evict or discard the invalid (i.e., stale) block from the cache (step 508). If the metadata does not match, method 500 may proceed to process the next megadata corresponding to the mapped journal block or to process the next mapped journal block if method 500 has processed all of the metadata in the mapped journal block (step 506: Yes).

[0052] The invalidation data area may further provide several additional advantages related to (1) transparent caching and (2) dynamic cache mode switching between a write-back and a write-through mode. Transparent caching refers to an ability of an administrator or user to remove the cache from the system at will. Dynamic cache mode switching refers to an ability of an administrator or user to switch the cache mode between a write-back and a write-through mode without requiring the system to be powered down. The invalidation data area may enable transparent caching and dynamic cache mode switching without introducing significant latency to ongoing I / O operations. In some embodiments, the cache may avoid latency by discarding all data.If the cache is in write-back mode, the cache generally flushes its changed data to the underlying storage device (i.e., "writes" the data "back") before the cache can discard or evict the data. Previously, the cache removed its data by pausing all outstanding I / O operations before flushing. However, pausing or stopping all outstanding I / O operations may introduce undesirable latency because there is no upper limit to the period in which flushing occurs. Example factors that may affect flushing time may include the amount of changed data, randomness, disk speed, etc. In some embodiments, the invalidation data area enhances ongoing I / O operations by placing the cache in pause mode and maintaining I / O operations as follows: 1) The cache forwards cache misses 2) The cache maintains read hits 3) The cache uses the invalidation data area to invalidate write hits and forwards the writes to the underlying storage device.

[0053] When the cache flush is complete, the cache can safely discard all data.

[0054] Those skilled in the art will recognize that various representations described herein may be implemented as electronic hardware, computer software, or combinations of both. To illustrate this interchangeability of hardware and software, various illustrative blocks, modules, elements, components, methods, and algorithms have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware, software, or a combination depends on the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application.Different components and blocks may be arranged differently (for example, arranged in a different order or divided in a different way) without departing from the scope of the present technology.

[0055] Furthermore, an implementation of the invalidation data area can be realized centrally in a computer system or distributed, with various elements distributed across multiple interconnected computer systems. Any type of computer system or other device intended to carry out the methods described herein is suitable for performing the functions described herein.

[0056] A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when loaded and executed, controls the computer system to perform the methods described herein. The methods may further be embedded in a computer program product that has all of the features enabling implementation of the methods described herein and that, when loaded into a computer system, is capable of performing these methods.

[0057] Computer program or application in the present context means any expression in any language, code, or notation of a set of instructions for causing a system having information processing capability to perform a particular function, either directly or by one or both of the following: a) converting into another language, code, or notation; b) reproducing in another material form. Significantly, the systems and methods described herein may be further embodied in other specific forms without departing from the spirit or essential attributes thereof, and accordingly, reference should be made to the following claims rather than to the foregoing description for indicating the scope of the systems and methods.

Claims

[1] Cache (104), which includes: a journal (206) configured to track data blocks (216) stored in the cache (104); and an invalidation data area (208) configured to track invalidated data blocks associated with the data blocks (216) tracked in the journal (206), the invalidation data area (208) being located in a region of the cache (104) separate from the journal (206). [2] Cache (104) according to claim 1, wherein the journal (206) is configured to track metadata (214) for the data blocks (216), and wherein the metadata (214) comprises a memory address corresponding to the data block (216), and wherein the invalidation data area (208) is configured to track metadata (302) associated with the invalidated data blocks, and wherein the associated metadata (302) comprises a memory address corresponding to the invalidated data block. [3] Cache (104) according to claim 2, wherein the journal (206) is configured to track the data blocks (216) using journal blocks (212), the journal blocks (212) being configured to store the metadata (214) for the data blocks (216); and wherein the invalidation data area (208) is configured to track the metadata (302) associated with the invalidated data blocks using invalidation records and mapped journal blocks, wherein the mapped journal blocks are configured to store the associated metadata (302) for the invalidated data blocks, and wherein the invalidation records are configured to store the mapped journal blocks. [4] Cache (104) according to claim 3, wherein the metadata (214) tracked in the journal (206) further comprises an index (304a) into a collection of metadata (214) stored in each journal block (212), and wherein the metadata (302) tracked in the invalidation data area (208) further comprises an index (304b) into a collection of metadata (302) stored in each mapped journal block. [5] The cache (104) of claim 3, wherein the cache (104) is configured to determine an invalidation record number associated with an invalidation record in the invalidation data area (208) based on a corresponding journal block number associated with a journal block. [6] The cache (104) of claim 3, wherein the cache (104) is configured to determine a mapped journal block number associated with a mapped journal block in the invalidation area (208) based on a corresponding journal block number associated with a journal block. [7] The cache (104) of claim 4, wherein the index (304a) tracked in the journal (206) is selected to have the same value as the index (304b) tracked in the invalidation data area (208). [8] Cache (104) according to claim 1, wherein the memory address tracked in the invalidation data area (208) is shortened compared to the memory address tracked in the journal (206), and wherein the truncation is determined based on at least one of a storage size of an underlying cached storage device and an offset determined based on a memory address of a block in the underlying storage device.

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