Digitally controlled output amplitude of an analog sensor signal

Abstract

Device (100) comprising: - an analog main signal path (102) having an amplifier (112) and configured to amplify an analog sensor signal (195) of a sensor (111) and output it with an output amplitude (199), wherein the output amplitude (199) is digitally controllable by a digital control signal (190), - a digital control circuit (101) coupled to the main analog signal path (102) and configured to determine the digital control signal (190) and provide the digital control signal (190) to the main analog signal path (102) to reduce a gain error of the main analog signal path (102), wherein the analog main signal path (102) is configured to adjust the digitally controllable output amplitude (199) depending on the digital control signal (190), wherein the digital control circuit (101) comprises at least one analog-to-digital converter (315, 316) configured to convert at least one input signal (291-294) to obtain a digital representation of each of the at least one input signal (291-294), wherein the digital control circuit (101) comprises at least one processor (301) for determining the digital control signal (190) based on the digital representation of each of the at least one input signal (291-294), wherein the at least one analog-to-digital converter (315, 316) comprises a time-division multiplexed analog-to-digital converter (315, 316) having a plurality of analog inputs and configured to convert a plurality of input signals (291-294) received via the plurality of analog inputs to obtain the digital representation of each of the plurality of input signals (291-294).

Description

TECHNICAL FIELDVarious embodiments relate to an apparatus and a method. In particular, various embodiments relate to techniques of digitally controlling an output amplitude with which an analog sensor signal is output.BACKGROUNDMany present day electronic components use sensors to measure physical quantities and convert the measured physical quantities into sensor signals that are output to an electronic instrument, such as an integrated chip processor. In hand-held portable devices, such as mobile phones, sensors are typically operated at a low current to allow for a long battery life. Similar considerations apply to automotive applications, etc.One way to conserve energy is to rely on sensors that provide analog sensor signals with a small amplitude. If necessary, the analog sensor signal may then be amplified. However, in order to accurately transmit information using signals having a small amplitude, offset errors and gain errors should be kept low.US 8 350 563 B2 discloses a magnetic field sensor and a method connected to the magnetic field sensor which provides gain correction coefficients and / or offset correction coefficients stored in the magnetic field sensor in digital form. The gain correction coefficients and / or offset correction coefficients may be used to generate analog control signals to control a sensitivity and / or an offset of an analog signal path through the magnetic field sensor.However, such techniques have certain disadvantages and limitations. The insertion of the analog control signals may induce additional errors. The use of the analog control signals may also require additional circuitry in the form of digital-to-analog converters (DACs). Furthermore, the onset of offset correction coefficients may be inaccurate and subject to lifetime drifts.DE 10 2006 005 032 A1 discloses a method for automatically adjusting the level of a received signal in a receiving device and a receiving device for carrying out the method.US 965 H1 discloses a variable gain amplifier which can be controlled via a digital control system.US 5 923 213 A discloses a gain controllable amplifier receiving an analog input voltage which is controlled via a digital control word and outputs an analog output voltage.US 2002 / 0 175 758 A1 discloses a transconductance based variable gain amplifier which amplifies an input voltage by converting the voltage difference into a current and amplifying it.SUMMARYTherefore, there is a need for advanced techniques for amplifying and outputting analog sensor signals. In particular, there is a need for advanced techniques for reducing offset errors and / or gain errors in amplifying and outputting analog sensor signals.This need is met by the features of the independent claims. The dependent claims defined embodiments.According to one aspect, an apparatus is provided. The apparatus comprises a main analog signal path and a digital control circuit. The analog main signal path comprising an amplifier is configured to amplify an analog sensor signal of a sensor at a digitally controllable output amplitude and output it at an output amplitude. The output amplitude is digitally controllable by a digital control signal. The digital control circuit is coupled to the main analog signal path. The digital control circuit is configured to determine the digital control signal. The digital control circuit is further configured to provide the digital control signal to the analog main signal path to reduce a gain error of the analog main signal path. The analog main signal path is configured to adjust the digitally controllable output amplitude depending on the digital control signal. The digital control circuit includes at least one analog-to-digital converter configured to convert at least one input signal to obtain a digital representation of each of the at least one input signal. The digital control circuit also includes at least one processor to determine the digital control signal based on the digital representation of each of the at least one input signal. The at least one analog-to-digital converter includes a time division analog-to-digital converter having a plurality of analog inputs and configured to convert a plurality of input signals received via the plurality of analog inputs to obtain the digital representation of each of the plurality of input signals.According to one aspect, a method is provided. The method includes, by means of a time division analog-to-digital converter having a plurality of analog inputs, converting a plurality of input signals received via the plurality of analog inputs to obtain a digital representation of each of the plurality of input signals. The method further includes determining a digital control signal. The method further comprises amplifying an analog sensor signal and outputting the amplified analog sensor signal at a digitally controllable output amplitude in an analog main signal path. The method further comprises adjusting the digitally controllable output amplitude of an analog sensor signal in dependence on the digital control signal to reduce a gain error of the analog main signal path.In the following, various techniques are explained with respect to processing an analog sensor signal provided by a sensor. In particular, techniques of amplifying and outputting the analog sensor signal with a reduced gain error are disclosed.The gain error may occur due to lifetime drifts and / or changing environmental conditions such as humidity, temperature, etc. The gain error may correspond to a multiplicative error of amplifying and outputting the analog sensor signal. For example, in some scenarios, the gain error may result from a deviation from ideal ratiometric behavior and may therefore include a deviation from ratiometric behavior.In some scenarios, it is possible to reduce an offset error. The offset error may correspond to an additive error of amplifying and outputting the analog sensor signal. The offset error may correspond to a DC offset in the analog sensor signal or an AC voltage offset ripple signal caused by the amplitude limitation. The cause of the offset error may be the sensor and / or the amplification. The cause of the offset error may be lifetime drifts and / or changing environmental conditions. Furthermore, at least some contributions to the offset error may be inherent in an operating principle of the sensor.In certain scenarios, a device is provided. The apparatus comprises a main analog signal path and a digital control circuit. The analog main signal path is configured to amplify and output an analog sensor signal of a sensor at a digitally controllable output amplitude. The digital control circuit is coupled to the main analog signal path. The digital control circuit is configured to determine a digital control signal. The digital control circuit is further configured to provide the digital control signal to the analog main signal path to reduce a gain error of the analog main signal path. The analog main signal path is configured to adjust the digitally controllable output amplitude depending on the digital control signal.The main analog signal path may be fully analog, i.e., exclude any digital processing of the analog sensor signal, such as for relaying, amplifying, and outputting the analog sensor signal. The main analog signal path may be digitally supported by the digital control circuit (splitting architecture). The digital control circuit may perform control functionality with respect to the main analog signal path. The digital control circuit can in particular control the digitally controllable output amplitude via the digital control signal. For example, the digital control signal may digitally encode a set output amplitude. For example, the digital control signal may be a sequence of ZEROS and ONES.By providing the splitting architecture, long delays to output the sensor signal can be avoided. The reason for this is that the analog sensor signal is processed in the analog domain. For example, delays may be in the sub-millisecond system. The analog main signal path can output the analog sensor signal at a bandwidth of more than 1 kHz, preferably more than 100 kHz, more preferably more than 300 kHz, for example. High accuracy in propagating, outputting, and amplifying the analog sensor signal can still be achieved by the splitting architecture by employing the digital control circuit that digitally supports the main analog signal path.Various scenarios are conceivable for implementing the digitally controllable output amplitude. In some scenarios, amplifying the analog sensor signal may implement a digitally controllable gain; then, the output amplitude may be adjusted by adjusting the digitally controllable gain depending on the digital control signal. Alternatively or additionally, in some scenarios, the sensor may provide the analog sensor signal with a digitally controllable amplitude; then, the output amplitude may be adjusted by adjusting the digitally controllable amplitude with which the sensor provides the analog sensor signal depending on the digital control signal. Thus, in the various scenarios, depending on the particular architecture of the main analog signal path, various techniques for adjusting the digitally controllable output amplitude may be available.It is to be understood that the above-mentioned features and those explained below may be used not only in the respective displayed combinations but also in other combinations without departing from the scope of the invention.BRIEF DESCRIPTION OF THE DRAWINGSThe foregoing and additional features and effects of the invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings, in which like reference numerals refer to like elements. FIG. 1 schematically illustrates an apparatus according to various embodiments, wherein the apparatus comprises a digital control circuit and an analog main signal path comprising a sensor and an amplifier, wherein the digital control circuit is configured to provide a digital control signal to the analog main signal path to set a digitally controllable output amplitude with which the analog main signal path outputs an analog sensor signal of the sensor. FIG. 2 schematically illustrates the apparatus of FIG. 1 at a greater level of detail, the apparatus comprising chopper switches disposed in the main analog signal path to reduce offset error. FIG. 3 schematically illustrates the chopper switches arranged in the main analog signal path and further illustrates adding a further control signal to further reduce the offset error by compensating for chopper ripple according to various embodiments. FIG. 4 schematically illustrates the chopper switches arranged in the main analog signal path and further illustrates adding a further control signal to further reduce the offset error by compensating for chopper ripple according to various embodiments. FIG. 5 schematically illustrates in more detail the amplifier of the analog main signal path according to various embodiments, wherein the amplifier comprises a pair of compensation capacitors. FIG. 6A schematically illustrates the digital control circuit according to various comparative examples, wherein the digital control circuit comprises a plurality of analog-to-digital converters configured to convert a plurality of input signals to obtain digital representations of each of the plurality of input signals. FIG. 6B schematically illustrates the digital control circuit according to various examples, wherein the digital control circuit comprises a time division analog-to-digital converter having a plurality of analog inputs and configured to convert a plurality of input signals received via the plurality of analog inputs to obtain the digital representations of each of the plurality of input signals. FIG. 7 schematically illustrates a polynomial dependency between the input signals and the digital control signal used to determine the digital control signal by a processor of the digital control circuit. FIG. 8 is a flow diagram of a method according to various embodiments.DETAILED DESCRIPTION OF EMBODIMENTSHereinafter, embodiments of the invention will be described in detail with reference to the accompanying drawings. It should be understood that the following description of embodiments is not to be interpreted as limiting. The scope of the invention is not intended to be limited by the embodiments described below or by the drawings, which are intended to be illustrative only.The drawings are to be considered as schematic representations, and elements illustrated in the drawings are not necessarily to scale. Rather, the various elements are shown so that their function and general purpose will be apparent to those skilled in the art. Any connection or coupling between functional blocks, devices, components, or other physical or functional units shown in the drawings or described herein may also be implemented by an indirect connection or coupling. Coupling between components may also be established via a wireless connection. Function blocks may be implemented in hardware, firmware, software, or a combination thereof.FIG. 1 illustrates aspects of a device 100 including a sensor 111. The sensor 111 and an amplifier 112 form the analog main signal path 102 along which an analog sensor signal 195 provided by the sensor 111 is forwarded, amplified and ultimately output via a terminal 113. The analog sensor signal 195 is output via the terminal 113 with a specific amplitude 199 (output amplitude). The output amplitude 199 may be higher or lower than the amplitude 198 with which the sensor 111 provides the analog sensor signal 195 (input amplitude); the relationship between the output amplitude 199 and the input amplitude 198 is described by an overall gain of the analog main signal path 102.The output amplitude 199 is digitally controllable. The main analog signal path 102 receives the digital control signal 190 from a digital control circuit 101 in this regard. The output amplitude 199 is controlled as a function of the digital control signal 190.The digital control circuit 101 is configured to determine the digital control signal 190 to reduce a gain error of the analog main signal path 102. The gain error may be introduced due to, for example, varying environmental conditions such as temperature and mechanical stress applied to the device 100, and in particular the sensor 111. The mechanical load can be induced, for example, by moisture or moisture. Over the lifetime of the device 100, different output amplitudes 199 may result depending on these and other environmental conditions. For a fixed set of operating parameters of the analog main signal path 102, a time dependence of the output amplitude 199 may be observed (drift).The apparatus 100 can be used, for example, in a portable device for reading out the sensor 111. In other scenarios, the device 100 may be deployed in automotive applications. In some scenarios, the sensor 111 may be used to measure rotational motion of a magnetic gear that is part of a camshaft sensor.The sensor 111 may be, for example, a magnetic field sensor configured to sense a magnetic field, and may operate according to the spin Hall principle: the sensor 111 may include a four-terminal Hall plate. An excitation or bias current for the Hall plate is impressed into two opposing terminals. At the other two opposite terminals, the Hall voltage is taken off. The Hall plate can be operated according to the spin-Hall principle. According to this principle, the connections of the Hall plate are cyclically exchanged with a clock frequency of the bias current, i.e. the excitation current is impressed during a clock period at a first terminal pair and impressed at a second terminal pair, which is arranged at an angle of approximately 90° with respect to the first terminal pair, in a subsequent clock period. The connections for taking off the Hall voltage are exchanged accordingly. Offset errors in the analog sensor signal output by the Hall plate may be reduced by adding the Hall voltages taken in successive clock periods. However, offset errors may still be present and techniques for reducing such residual offset errors are disclosed herein.Various types and types of sensors 111 may be employed. For magnetic field sensors, for example, operation according to the giant magnetoresistive effect (GMR), tunneling magnetoresistive effect (TMR), anisotropic magnetoresistive effect (AMR) can be used. In the various scenarios disclosed herein, physical quantities other than the magnetic field, such as acceleration, electric field, pressure, etc., may be measured.Some of the sensors 111 employed for the various scenarios disclosed may be differential sensors. An example is the magnetic field sensor operating according to the spin-Hall principle. A transconductance amplifier may be provided (not shown in FIG. 1 ). The transconductance amplifier may convert the differential voltage signal provided by the differential sensor into a current.FIG. 2 illustrates the apparatus 100 of FIG. 1 in more detail. As can be seen from FIG. 2, a current source 130 is provided in the analog main signal path 102. The current source 130 generates a bias current 131 and provides the bias current 131 to the sensor 111. The current source 130 in the example of FIG. 2 is coupled to a supply voltage VDD. In some scenarios, the bias current 131 is modulated at a corresponding clock frequency.While a current source 130 is illustrated in the scenario of FIG. 2, in the various scenarios disclosed herein, it is possible to include a voltage source in the main analog signal path that is configured to generate a bias voltage and provide the bias voltage to the sensor 111. The voltage source may be coupled to the supply voltage VDD. In some scenarios, the bias voltage may be modulated at a corresponding clock frequency.In the scenario of FIG. 2, the amplifier 112 is also operated by the supply voltage VDD. The amplifier 112 includes an input stage and an output stage. In the scenario of FIG. 2, the input stage is formed by a first amplifier 125, such as a transconductance amplifier 125 in the scenario of FIG. 2, and in the scenario of FIG. 2, the output stage is formed by a second amplifier 127, such as implemented in the scenario of FIG. 2 by an operational amplifier 127. In some scenarios, the amplifier 112 may include additional stages or a smaller number of stages.The specific architecture of the amplifier 112 is not relevant to the functioning of the various techniques disclosed herein. In some scenarios, for example, a differential amplifier, such as a programmable gain sense amplifier, may be employed. The measurement amplifier can have a comparably high input impedance, for example. Here, the DC offset caused by the instrumentation amplifier may be fundamentally small, but may nevertheless be further reduced by techniques disclosed here.The amplifier 112 in the scenario of FIG. 2 is a digitally controllable programmable amplifier; i.e., the amplifier 112 may adjust the gain associated with the amplifying depending on the digital control signal 190. Therefore, the gain is digitally controllable. By adjusting the gain, the output amplitude 199 may be adjusted. For example, the amplifier 112 may be integrated into a packet. The packet may include a port or pin to receive the digital control signal 190.In the scenario of FIG. 2, for illustrative purposes, amplifier 112 is configured to adjust contributions to overall gain by both the input stage, i.e., transconductance amplifier 125, and the output stage, i.e., operational amplifier 127. In other scenarios, the amplifier 112 may be configured to adjust either contributions to overall gain by the input stage or by the output stage.In detail, the transconductance amplifier 125 comprises a digitally controllable sense resistor 126. The sense resistor 126 may be for source feedback. The measuring resistor 126 is configured to receive the digital control signal 190 and adjust its specific resistance depending on the digital control signal 190. As a result, the gain contribution by the input stage is adjusted. Therefore, the digitally controllable output amplitude 199 is adjusted.Furthermore, the operational amplifier 127 has a feedback branch which has a digitally controllable feedback resistor 128. The digitally controllable feedback resistor 128 is configured to receive the digital control signal 190 and adjust its resistivity depending on the digital control signal 190. This adjusts the gain contribution by the output stage. Therefore, the digitally controllable output amplitude 199 is adjusted.Another option to adjust the digitally controllable output amplitude 199 - alternatively or additionally to the gain adjustment of the amplifier 112 - is to control the bias current 131 provided by the current source 130. For example, the current source 130 may be configured to receive the digital control signal 190 and adjust the bias current 131 depending on the digital control circuit 190. Usually, a larger (smaller) amplitude of the bias current 131 results in a larger (smaller) input amplitude 198 of the analog sensor signal 195. In some scenarios, it is possible to control the bias voltage provided by a corresponding programmable voltage source.Yet another option to adjust the digitally controllable output amplitude 199 - alternatively or in addition to the gain adjustment of the amplifier 112 and the control of the bias current 131 - is to provide a digitally controllable current divider 129. The digitally controllable current divider 129 may be arranged at different positions along the analog main signal path 102. For illustrative purposes, in the scenario illustrated in FIG. 2, current divider 129 is located before amplifier 127. The current divider 129 may be configured to pass only a portion of the received input current along the main analog signal path 102; the remaining portion may be split off and supplied to ground, for example. To adjust the forward portion of the received input current, the current divider 129 may include one or more digitally controllable switches, such as switches based on a metal oxide field effect transistor (MOSFET), etc. (not shown in FIG. 2 ). Here, the digital control signal 190 may be supplied to the digitally controllable switches.The structure and architecture of the current divider 129 are not relevant for adjusting the digitally controllable output amplitude 199. An exemplary current divider 129 is known, for example, from K. Bult and G. J. G. M. Geleen, An inherently linear and compact MOST-only current division technique, in IEEE J. of Solid-State Circuits 27 (1992) 1730-1735, FIG. 4.By means of the digital control signal 190 it is therefore possible to set the digitally controllable output amplitude 199. In particular, the digitally controllable output amplitude 199 can be adjusted via the digital control signal 190 in a multiplicative manner. Therefore, by appropriately determining the digital control signal 190, it becomes possible to reduce the amplification error of the analog main signal path 102.Various techniques related to reducing the offset error are disclosed below. In order to reduce the offset error of the main analog signal path 102, the chopper switches 121, 122 are provided before and after the input stage of the amplifier 112. In other scenarios, a greater or lesser number of chopper switches 121, 122 may be provided. The chopper switches 121, 122 are optional.FIG. 3 illustrates aspects of the plurality of chopper switches 121, 122. The chopper switch 121 is placed upstream in the main analog signal path 102 of the chopper switch 122. It is possible that at least parts of the amplifier 112 are arranged between the chopper switches 121, 122, e.g. the input stage of the amplifier 112. The sensor 111 may provide the analog sensor signal 195 with a first (residual) DC offset. A second DC offset may be added to the analog sensor signal by amplifier 112. The chopper switches 121, 122 reduce the total DC offset and thereby reduce the offset error.The chopper switches 121, 122 may be driven by a chopper clock signal, for example. The chopper clock signal may be a square waveform. The chopper switch 121 acts as an analog modulator. The chopper switch 121 is configured to chop the received analog sensor signal at a first frequency f 1 to generate a signal having an AC voltage amplitude that potentially varies with a DC voltage offset at the given frequency f 1. For example, f1may be in the range from 100 Hz to 100 kHz, preferably in the range from 0.5 kHz to 50 kHz. f1corresponds to the clock signal of the chopper. The chopper switch 121 acts as an analog demodulator. The chopper switch 122 is configured to chop the received analog sensor signal at the given frequency f 1 to generate a signal having a DC voltage amplitude.f 1 may correspond to the clock frequency of the bias current 131, for example. In particular, by modulating the bias current 131 at the given frequency f 1, a reduction of the first DC offset generated by the sensor 111 may be achieved. Further, since the second DC offset of the amplification can be introduced between the first and second chopper switches 121, 122 after the demodulation of the signal by the second chopper switch 122, the second DC offset can be reduced. Therefore, by reducing the first and second DC offsets, the offset error is reduced.By directly reducing the offset error in the main analog signal path 102, a more reliable and correct reduction can be achieved compared to reference implementations relying on a digital look-up table of offsets versus temperature. A multitemperature measurement for the calibration is not required. Long term drifts resulting in a systematic error are avoided compared to the stored values in the digital look-up table. Thus, according to the techniques disclosed herein, the offset error may be reduced by a factor of approximately up to 100, which is higher than the reduction factor of approximately 3 to 10 for reference implementations that rely on the digital look-up table. For example, the DC offset can be limited to less than 1 microvolt. A comparatively fast offset error reduction can be achieved. Aliasing effects can be low. The amplitude limitation can be continuous in time, so that a correct reduction of the offset can be achieved.However, the signal generated by the chopper switch 122 may have a superimposed chopper ripple error. The chopper ripple error corresponds to residues of the DC offset of the analog sensor signal, which is now transformed and modulated into the AC domain by the second chopper switch 122. Therefore, in some scenarios, it may be desirable to further reduce the offset error of the main analog signal path 102 by reducing the chopper ripple.In some scenarios, a low pass filter may be employed that is disposed after the second chopper switch 122 (not shown in FIG. 3 ). The low pass filter may filter out the chopper ripple in the AC voltage domain.In other scenarios, an analog feedback circuit including an analog low pass filter / integrator may be employed to further reduce the offset error by reducing the chopper ripple.In still other scenarios, the digital control circuit 101 may be employed to further reduce the offset error by reducing the chopper ripple. Here, a low pass filter may be implemented by the digital control circuit 101. By implementing the integration / low pass filter in the digital domain, advantageous electromagnetic compatibility (EMC) features can be achieved. Furthermore, low-pass filtering in the digital domain may be possible with a comparatively high accuracy, in particular compared to reference implementations that implement a low-pass filter in the analog domain. Further, in scenarios where a low pass filter is located in the main analog signal path 102, significant delay may be introduced and thereby the operating bandwidth of the main analog signal path 102 may be limited.For this purpose, the digital control circuit 101 may be configured to determine a further control signal 191 and provide it to the analog main signal path 102 that counteracts the chopper ripple. It is possible that the further control signal is added to the analog main signal path 102 by means of an adder 123. The addition may be between the chopper switches 121, 122, as illustrated in the scenario of FIG. 3 ; in such a scenario, the further control signal 191 corresponds to a DC signal. In further scenarios, as illustrated in the scenario of FIG. 4, the addition may occur after the second chopper switch 122; in such a scenario, the further control signal 191 corresponds to an AC voltage signal. Depending on the particular implementation of the adder 123, the further control signal 191 may be a digital signal or an analog signal.FIG. 5 illustrates aspects of the compensation capacitors 181, 182. The compensation capacitors 181, 182 are sometimes referred to as Miller capacitors. By means of the compensation capacitors 181, 182, a so-called chopped Miller compensation can be achieved. In the scenario of Fig. 5, the compensation capacitors 181, 182 are arranged in parallel with a push-pull amplifier 127 forming the output stage of the amplifier 112. Each of the compensation capacitors 181, 182 is connected to a given chopping polarity of the chopped analog sensor signal 195. Therefore, the compensation capacitors 181, 182 are provided in dual form, so that when a chopped input signal is supplied, the first capacitor 181 is active during a first clock phase and the second capacitor is active during a second clock phase. The activation of the capacitors 181, 182 is achieved via the switches 183.Such a configuration avoids the need for cyclic charge reversal in a single compensation capacitor in which the chopped signal is present. In detail, after a few clock cycles of the chopper clock signal, both the first compensation capacitor 181 and the second compensation capacitor 182 are charged and in further clock cycles only small voltage differences are induced, which have smaller amplitudes and are slower compared to the voltage differences caused by the chopper frequency. The amplifier 112 therefore enables continuous-time signal processing, in contrast to switched capacitor filters operating on the sample-and-hold principle.Such techniques make it possible to achieve high gains by amplifier 112 at a comparably high chopper frequency. A high bandwidth of the main analog signal path 102 can be achieved. The delay for outputting the analog sensor signal 195 may be low. The amplifier 112 may have a comparably small voltage loss and comparably good noise properties. The chip required for the amplifier 112 may be moderate. The total current consumption can be reduced.FIG. 6A illustrates aspects of the digital control circuit 101 according to comparative examples. The digital control circuit 101 as illustrated in the scenario of FIG. 6A includes one analog-to-digital converter (ADC) 311- 314 per input terminal. The input signals 291 to 294 are received via the various input terminals. In the scenario of FIG. 6A, four input signals 291- 294 are received. However, in various other scenarios, a lesser or greater number of input signals may be received. The ADCs 311- 314 are configured to convert the input signals 291- 294 to obtain digital representations of each of the input signals 291- 294. A processor 301 is coupled to a memory 302 and is configured to determine the digital control signal 190 and optionally the further control signal 191 depending on the input signals 291 to 294 corresponding to the digital representations of each of the input signals 291 to 294. The memory 302 may be, for example, a nonvolatile memory such as an electrically erasable and programmable read only memory (EEPROM) or flash memory.In the scenario of FIG. 6A, a first input signal 291 indicates the supply voltage VDD. A second input signal 292 indicates a mechanical load applied to the sensor 111. A third input signal 293 indicates the temperature of the sensor 111. A fourth input signal 294 indicates the chopper ripple of the chopper switches 121, 122. Depending on where the main analog signal path 102 is tapped, the fourth input signal 294 may be a DC or AC signal.The first input signal 291 may be received by, for example, tapping the supply voltage VDD line. The second input signal 292 may be received from, for example, a mechanical load sensor. The third input signal 293 may be received, for example, from a temperature sensor. The fourth input signal 294 may be received, e.g., by tapping the main analog signal path 102 between the chopper switches 121, 122, or after the chopper switches 121, 122, for example.The scenario of FIG. 6B generally corresponds to the scenario of FIG. 6A. Instead of four ADCs 311-314, i.e., a single ADC 311-314 per input signal 291-294, in the scenario of FIG. 6B, a multiplexer 315 is employed in combination with a single ADC 316; i.e., a time division ADC 315, 316 is configured to convert the multiple input signals 291-294 received via the multiple analog inputs to obtain the digital representations of each of the multiple input signals 291-294. Multiplexer 315 may be configured to switch between the various analog inputs at the given sampling rate to receive a corresponding input signal 291- 294 at a time.The time division ADC 315, 316 allows to reduce the space required on-chip for analog-to-digital conversion; further, costs can be reduced. On the other hand, a latency introduced by the analog-to-digital conversion may be comparably larger. Typically, because the characteristics of the input signals 291- 294 vary comparatively slowly over time, a limited sampling rate of the one or more ADCs 311- 316 may be tolerable. For example, the one or more ADCs 311 to 316 may have a sampling rate that is less than 50 kHz, preferably less than 1 kHz, more preferably less than 500 Hz.That is, as can be seen, the sampling rate of the one or more ADCs 311 to 316 may be significantly less than the bandwidth of the main analog signal path 102. The potentially slow sampling rate from the one or more ADCs 311- 316 may not increase the delay with which the analog sensor signal 195 is forwarded, amplified, and output through the main analog signal path 102. This is made possible by the splitting architecture employing the digital control circuit 101 and the main analog signal path 102.Optionally, in the various scenarios disclosed, the digital control circuit 101 may include a digital filter configured to reduce noise (not shown in FIGS. 6A and 6B ) due to analog-to-digital conversion by the at least one ADC 311- 316.The processor 301 may implement different functionality to determine the digital control signal 190 and / or the further control signal 191. The digital control signal 190 may be used to reduce the gain error of the analog main signal path 102; while the further control signal 191 may be used to reduce the offset error of the analog main signal path 102 by reducing the chopper ripple.While a single processor 301 is illustrated in the scenario of FIGS. 6A and 6B, multiple processors may be employed in other scenarios. For example, a separate processor for determining the digital control signal 190 and a further separate processor for determining the further control signal 191 may be possible. In particular, at least two different digital control circuits may be possible, wherein a first of the digital control circuits is configured to determine the digital control signal 190 and a second of the digital control circuits is configured to determine the further control signal 191. Therefore, it may be possible to use different ADCs and / or processors to determine the digital control signal 190 and the further control signal 191, respectively.First, aspects related to the determination of the further control signal 191 will be described. The processor 301 is configured to determine the further control signal 191 depending on the fourth input signal 294 indicative of the chopper ripple. Via the input signal 294 and the further control signal 191, a feedback branch for reducing the offset error and in particular the chopper ripple may be implemented. It is possible that the processor 301 is configured to integrate the fourth input signal 294 indicative of the chopper ripple, i.e. low pass filter the fourth input signal 294. This is done to filter out contributions other than the chopper ripple. Then, the processor 301 may determine the further control signal 191 based on the low pass filter input signal 294. Referring to the scenario of FIG. 3, the processor 301 may convert the filtered fourth input signal 294 to, e.g., DC voltage and invert the sign thereof to obtain the further control signal 191 to be added between the chopper switches 121, 122. Referring to the scenario of FIG. 4, the processor 301 may phase shift the filtered fourth input signal 294 by e.g. 180° to obtain the further control signal 191 to be added after the chopper switches 121, 122.With reference to FIG. 7, aspects related to the determination of the digital control signal 190 will now be described. The processor 301 is configured to determine the digital control signal 190 depending on the control signals 291 to 293 indicating the supply voltage VDD, the mechanical load, and the temperature. In other scenarios, the processor 301 may be configured to determine the digital control signal 190 depending on a single or any combination of the control signals 291- 293, e.g., depending on only the supply voltage VDD, only the temperature, or only the mechanical load.In detail, the processor 301 is configured to determine the digital control signal 190 depending on a predefined polynomial dependency 700 between one or more of the input signals 291- 294 and the digital control signal 190. For example, the predefined polynomial dependency may be of a predefined order, such as first order, second order, third order or fourth order, etc. Corresponding polynomial parameters defining the polynomial dependency may be stored in the memory 302.For example, by means of certain calibration points 299, it may be possible to determine the predefined polynomial dependency 700 during calibration. Simple two-point or three-point calibration may be possible, reducing efforts to prepare the device 100.The predefined polynomial dependency 700 may indicate the gain error caused by certain values of the supply voltage VDD, the mechanical load and / or the temperature. The predefined polynomial dependency 700 may counteract or compensate for the gain error. Generally, the one or more input signals 291- 293 may indicate at least one environmental condition of the device 100, e.g., particularly the sensor 111. Then, the processor 301 may determine the digital control signal 190 based on the digital representation of each of the one or more input signals 291- 293 to reduce the gain error of the analog main signal path 102.In a scenario in which the first input signal 291 indicative of the supply voltage VDD is received from the digital control circuit 101, it is possible to determine the digital control signal 190 such that a ratiometric behaviour of the analog main signal path 102 is achieved. The ratiometric behavior may correspond to a proportional dependence between the amplitude of the supply voltage VDD and the output amplitude 199 of the analog sensor signal 195. Deviations between the ideal proportional dependency of the ratiometric behavior may therefore contribute to the gain error and be reduced in various scenarios disclosed herein.In some scenarios, the predefined polynomial dependency 700 may also take into account cross sensitivities or interdependencies between the various input signals 291- 294. Such dependencies may result from influences between the various environmental conditions indicated by the input signals 291- 294 at the various sensors that provide the input signals 291- 294. Cross sensitivities may usually be relevant in particular for the second input signal 292 indicative of the mechanical load and the third input signal 293 indicative of the temperature. For example, a temperature sensor may be able to exhibit a stress / humidity dependence; in such a scenario where the stress sensor indicates an increased level of stress, the cross-sensitivity may skew the input signal 293 indicative of the temperature; by appropriately interpreting the polynomial dependence 700, it may be possible to reduce such cross-dependencies. Thereby, an accuracy of determining the digital control signal 190 and / or an accuracy of reducing a gain error of the analog main signal path 102 may be increased.By implementing the determination of the digital control signal 190 by means of the polynomial dependency 700, computationally cost-effective determination of the digital control signal 190 is possible. In particular, compared to reference implementations relying on a look-up table having a limited number of discrete values, in combination with interpolation, a more efficient and correct solution can be achieved. Further, it may not be necessary to store large amounts of data in memory 302; data may be limited to a number of parameters defining polynomial dependency 700. Therefore, the size of memory 302 may be comparably limited, particularly as compared to reference implementations that rely on a look-up table. Therefore, the complexity and system cost of the digital control circuit 101 can be reduced. It may be possible to implement the digital control circuit 101 in a highly area-efficient manner. The digital control circuit 101 may be integrated into a small on-chip area. The memory 302 may be designed smaller. Further, it may be easier to cancel cross sensitivities, particularly compared to look-up table based scenarios.FIG. 8 is a flow diagram of a method according to various embodiments. At 1000, the digital control signal is first determined. The digital control signal may be determined, for example, depending on one or more input signals indicative of at least one environmental condition of a device or sensor providing an analog sensor signal. For determining the digital control signal, a predefined polynomial dependency can be used, for example.The digital control signal may be determined to reduce a gain error of the main analog signal path. Alternatively or additionally, the digital control signal may be determined to implement a ratiometric behaviour of the output amplitude of the analog sensor signal. The gain error may include a deviation from ratiometric behavior.At 1001, a digitally controllable output amplitude is then set depending on the digital control signal.At 1002, the sensor signal is then amplified and output at the digitally controllable output amplitude.By adjusting the output amplitude based on the digital control signal that the gain error is reduced, e.g., by implementing ratiometric behavior.Optionally, the method may further comprise determining a further control signal and adjusting the digitally controllable output signal at 1001 further depending on the further control signal (not shown in FIG. 8 ). The further control signal may be determined based on an input signal indicative of a chopper ripple of the chopper switches in the main analog signal path. The further control signal may be determined to reduce an offset error of the analog main signal path.In summary, techniques of implementing a digitally assisted fast-forwarding analog main signal path for outputting and amplifying an analog sensor signal have been illustrated above. These techniques employ a digital control signal to reduce gain error, e.g., by implementing ratiometric behavior. Compared to reference implementations relying on an analog control signal to reduce gain errors, additional circuitry such as DACs may be avoided and the introduction of additional analog errors may be avoided. The use of analog multipliers is avoided. Therefore, higher accuracy can be achieved. A high bandwidth can be achieved.Although the invention has been shown and described with reference to preferred embodiments, equivalents and modifications will occur to others skilled in the art upon reading and understanding the specification. The present invention includes all such equivalents and modifications and is limited only by the scope of the appended claims.For example, although the disclosed digital control circuit and main signal path are described with respect to a sensor, they are not limited to applications associated with a sensor. Rather, the disclosed digital control circuitry and main signal path may be employed in any system in which signals having a low offset error and a low gain error are to be processed.

Claims

An apparatus (100) comprising: - an analog main signal path (102) comprising an amplifier (112) and configured to amplify and output an analog sensor signal (195) of a sensor (111) with an output amplitude (199), wherein the output amplitude (199) is digitally controllable by a digital control signal (190), - a digital control circuit (101) coupled to the analog main signal path (102) and configured to determine the digital control signal (190) and provide the digital control signal (190) to the analog main signal path (102) to reduce an amplification error of the analog main signal path (102), wherein the analog main signal path (102) is configured to adjust the digitally controllable output amplitude (199) depending on the digital control signal (190), wherein the digital control circuit (101) comprises at least one analog-to-digital converter (315, 316), A digital control circuit (101) configured to convert at least one input signal (291-294) to obtain a digital representation of each of the at least one input signal (291-294), the digital control circuit (101) comprising at least one processor (301) to determine the digital control signal (190) based on the digital representation of each of the at least one input signal (291-294), the at least one analog-to-digital converter (315, 316) comprising a time division multiple analog-to-digital converter (315, 316) having multiple analog inputs and configured to convert multiple input signals (291-294) received via the multiple analog inputs to obtain the digital representation of each of the multiple input signals (291-294).The apparatus (100) of claim 1, wherein the amplifier (112) is a digitally controllable programmable amplifier (112) configured to receive the digital control signal (190) and amplify the analog sensor signal (195) with a digitally controllable gain to adjust the digitally controllable output amplitude (199).The apparatus (100) of claim 2, wherein the digitally controllable programmable amplifier (112) comprises a transconductance amplifier (125) having a digitally controllable sense resistor (126), wherein the digitally controllable sense resistor (126) is configured to receive the digital control signal (190) and adjust its resistivity depending on the digital control signal (190) to adjust the digitally controllable output amplitude (199).The apparatus (100) of claims 2 or 3, wherein the digitally controllable programmable amplifier (112) comprises an operational amplifier (127) comprising a digitally controllable feedback resistor (128), wherein the digitally controllable feedback resistor (128) is configured to receive the digital control signal (190) and adjust its resistivity depending on the digital control signal (190) to adjust the digitally controllable output amplitude (199).The apparatus (100) of any preceding claim, wherein the analog main signal path (102) comprises the sensor (111) and an electrical power source (130) of the sensor (111), the electrical power source (130) being configured to provide at least one of a bias current (131) or a bias voltage to the sensor (111), the electrical power source (130) being configured to receive the digital control signal (190) and adjust at least one of the bias current (131) or the bias voltage depending on the digital control signal (190) to adjust the digitally controllable output amplitude (199).The apparatus (100) of claim 1, wherein the at least one processor (301) is configured to determine the digital control signal (190) further depending on a predefined polynomial dependency (700) between the at least one input signal (291-294) and the digital control signal (190).The apparatus (100) of claims 1 or 6, wherein the at least one input signal (291-294) is indicative of at least one environmental condition of the apparatus (100), wherein the at least one processor (301) is configured to determine the digital control signal (190) based on the digital representation of each of the at least one input signal (291-294) to reduce the gain error of the analog main signal path (102).The device (100) according to claim 1, 6 or 7, wherein the analog-to-digital converter (315, 316) has a sampling rate that is less than 50 kHz, preferably less than 1 kHz, more preferably less than 500 Hz.The apparatus (100) according to any of the preceding claims, wherein the digital control circuit (101) is configured to receive an input signal (291) indicative of a supply voltage of the sensor (111), wherein the digital control circuit (101) is configured to determine the digital control signal (190) depending on the input signal (291) indicative of the supply voltage of the sensor (111).The apparatus (100) of claim 9, wherein the at least one processor (301) is configured to determine the digital control signal (190) based on the digital representation of the input signal (291) indicative of the supply voltage such that the main analog signal path (102) outputs the analog sensor signal (195) having a ratiometric characteristic.The apparatus (100) of any preceding claim, wherein the digital control circuit (101) is configured to receive (292, 293) at least one input signal indicative of at least one of a temperature of the sensor (111) and a mechanical load applied to the sensor (111), wherein the digital control circuit (101) is configured to determine (292, 293) the digital control signal (190) depending on the at least one input signal indicative of at least one of the temperature of the sensor (111) and the mechanical load applied to the sensor (111).The apparatus (100) of any preceding claim, wherein the analog main signal path (102) comprises a plurality of chopper switches (121, 122), the plurality of chopper switches (121, 122) being configured to chop the analog sensor signal (195) at a predefined frequency to reduce an offset error of the analog main signal path (102).The apparatus (100) of claim 12, wherein the digital control circuit (101) is configured to receive an input signal (294) indicative of a chopper ripple caused by the plurality of chopper switches (121, 122), wherein the digital control circuit (101) is configured to provide a further control signal to the analog main signal path (102) to reduce the chopper ripple.The apparatus (100) of claims 12 or 13, wherein the analog main signal path (102) comprises an amplifier (112, 125, 127) configured to amplify the analog sensor signal (195), wherein the analog main signal path (102) comprises a plurality of compensation capacitors (181, 182) in parallel with the amplifier (112, 125, 127), each of the plurality of compensation capacitors (181, 182) being connected to a given chopper polarity of the chopped analog sensor signal (195).The device (100) according to any of the preceding claims, further comprising: - the sensor (111), wherein the sensor (111) is a magnetic sensor configured to sense a magnetic field based on a spin Hall principle.The apparatus (100) of any preceding claim, wherein the analog main signal path (102) outputs the analog sensor signal (195) at a bandwidth of more than 1 kHz, preferably more than 100 kHz, more preferably more than 300 kHz.A method comprising: - by means of a time division analog-to-digital converter having a plurality of analog inputs: converting a plurality of input signals received via the plurality of analog inputs to obtain a digital representation of each of the plurality of input signals, - determining a digital control signal (190) based on the digital representations, - amplifying an analog sensor signal (195), and outputting the amplified analog sensor signal (195) having a digitally controllable output amplitude (199) in an analog main signal path (102), - adjusting the digitally controllable output amplitude (199) of an analog sensor signal (195) depending on the digital control signal (190) to reduce a gain error of the analog main signal path (102).The method of claim 17, wherein the method is performed by the apparatus (100) of any one of claims 1 to 16.

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