Semiconductor structure incorporating a magnetic tunnel contact and manufacturing method thereof

Abstract

Semiconductor structure (20) comprising: a carrier layer (100); a transistor region (11) comprising a gate (103) above the carrier layer and a doped region (105a, 105b) at least partially in the carrier layer, the doped region comprising a first doped region (105b) and a second doped region (105a); a first metal interconnect over the transistor region, the first metal interconnect comprising a first via (119) and a second via (119); and a magnetic tunnel contact (201) between the first doped region (105b) of the transistor region and the first via (119) of the first metal interconnect, wherein the second via (119) of the first metal interconnect is formed over a via (119) formed in the same plane as the magnetic tunnel contact (201), wherein the magnetic tunnel contact (201) is a first magnetic tunnel contact (201b) and a first region above the carrier layer (100) contains the first magnetic tunnel contact (201b) between the transistor region and the first metal interconnect; and wherein the semiconductor structure (20) further comprises a second region above the carrier layer, the second region not overlapping the first region, the second region including a second magnetic tunnel contact (201a) between the transistor region (11) and the first metal interconnect, wherein the first magnetic tunnel contact (201b) and the second magnetic tunnel contact (201a) have an identical or different diameter at a respective bottom surface of the first magnetic tunnel contact and the second magnetic tunnel contact from a plan view perspective and different heights from a cross-sectional perspective.

Description

AREA

[0001] The present disclosure relates to a semiconductor structure in which a magnetic tunnel junction is integrated and to manufacturing methods of the semiconductor structure in which a magnetic tunnel junction is integrated. BACKGROUND

[0002] With the increasing use of portable computing devices and wireless communication devices, storage devices may require higher density, lower power, and / or non-volatile properties. Magnetic storage devices may be able to meet the above technical requirements.

[0003] An exemplary data storage mechanism for a magnetic storage device is a tunnel magnetoresistance (TMR) effect of a magnetic tunnel junction (MTJ). For example, a magnetic storage device has been designed with an MTJ, so an MTJ can have a TMR ratio of several hundred to several thousand percent.

[0004] A magnetoresistive random access memory (MRAM) cell is formed by a magnetic tunnel junction (MTJ), which is a structure in which two ferromagnetic layers are separated by a thin insulating barrier. When a potential difference is applied across the two ferromagnetic layers, current flows through the insulating barrier by quantum mechanical tunneling. The resistance of the MTJ depends on the relative orientation of magnetic elements in the two ferromagnetic layers. The resistance is lowest when the magnetizations are aligned parallel and highest when they are antiparallel. One of the relative orientations can be used to represent a "1" and the other to represent a "0."Generally, the magnetic orientation of one of the layers (the fixed layer) is held fixed, while the magnetic orientation of the other layer (the free layer) is adjusted in a write operation. The state of the MRAM cell can be interrogated by measuring the resistance at the contact. For a group of MRAM cells to provide reliable data storage, a sufficiently large difference in resistance between the two possible states must be achieved for each cell in the group.

[0005] Prior art relating to the subject matter of the invention can be found, for example, in the documents US 8 724 377 B2, US 2014 / 0 078 808 A1 and US 2011 / 0 037 108 A1.

[0006] The task is to improve corresponding semiconductor structures.

[0007] The object is achieved by a semiconductor structure according to patent claim 1 and the method according to patent claim 13. Further embodiments emerge from the dependent patent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 is a diagram illustrating a read window of a semiconductor structure incorporating an MTJ, according to some embodiments of the present disclosure; Fig. 2 is a cross-section of a semiconductor structure incorporating an MTJ, according to some embodiments of the present disclosure; Fig. 3 is a cross-section of a semiconductor structure incorporating an MTJ, according to some embodiments of the present disclosure; Fig. 4 is a top view of a layer of a semiconductor structure incorporating an MTJ, according to some embodiments of the present disclosure; Fig. 5 is a schematic diagram showing layers forming an MTJ according to some embodiments of the present disclosure; Fig. 6 is a schematic diagram showing layers forming an MTJ according to some embodiments of the present disclosure; Fig. 7 is a cross-section of a semiconductor structure integrating an MTJ in a first region and a second region, according to some embodiments of the present disclosure; Fig. 8 is a cross-section of a semiconductor structure incorporating an MTJ in a first region, according to some embodiments of the present disclosure; Fig. 9 is a cross-section of a semiconductor structure integrating an MTJ in a first region and a second region, according to some embodiments of the present disclosure; Fig. 10 is a top view of a layer of a semiconductor structure incorporating an MTJ, according to some embodiments of the present disclosure; Fig. 11 to Fig. 26 show partial cross-sectional views of the formation of a semiconductor structure incorporating an MTJ in a first region and a second region, according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] This description of illustrative embodiments should be read in conjunction with the accompanying drawings, which are considered to be a part of the entire disclosure. In the description of embodiments disclosed herein, any reference to a direction or orientation is for convenience of description only and is not intended to limit the scope of the present invention in any way. Relative terms such as "lower," "upper," "horizontal," "vertical," "above," "beneath," "upward," "downward," "top," and "below," as well as derivatives thereof (e.g., "horizontal," "downward," "upward," etc.) should be understood to refer to the orientation as described or as shown in the drawings discussed. These relative terms are for convenience of description only and do not require that the device be constructed or operated in any particular orientation.Terms such as "attached," "fixed," "connected," and "connected" refer to a relationship in which the structures are secured or attached to one another, either directly or indirectly through intervening structures, as well as both movable and rigid attachments or relationships, unless expressly described otherwise. Furthermore, the features and advantages of the invention are presented with reference to the preferred embodiments. Therefore, the invention should expressly not be limited to such preferred embodiments, which show some possible, non-limiting combinations of features that may be present alone or in other combinations of features; the scope of the invention is defined by the appended claims.

[0010] In the drawings, like reference numerals are used to indicate like or similar elements throughout the several views, and illustrative embodiments of the present invention are shown and described. The figures are not necessarily drawn to scale, and in some cases the drawings have been enlarged and / or simplified in places for illustrative purposes only.

[0011] Increasing a read window in an MRAM cell can be achieved by obtaining a narrower full width at half maximum (FWHM) of the device's peak count with respect to the resistance value. Referring to Fig. 1 is Fig. 1 is a schematic diagram illustrating a read window of a semiconductor structure incorporating an MTJ, according to some embodiments of the present disclosure. An upper diagram and lower diagram of Fig. 1 shows an X-axis of resistance and a Y-axis of a number of tested devices. The upper diagram of Fig. Figure 1 shows an ideal case where only one device signal is considered and a narrow FWHM is obtained at both Gaussian peak 1 and Gaussian peak 2. In some embodiments, Gaussian peak 1 refers to a "low" logic level (R low ), while the Gaussian peak 2 is at a “high” logic level (R high ) refers to.

[0012] Likewise, the lower diagram of Fig. 1 shows a real case where not only the device signal but also a signal summation from the routing metal is taken into account and a broadened FWHM is obtained at both Gaussian peak 1' and Gaussian peak 2'. In some embodiments, Gaussian peak 1' refers to a "low" logic level (R low ), while the Gaussian peak 2' is at a “high” logic level (R high ) refers to.

[0013] A read window, as referred to here, lies in a region of specific resistance that can be arbitrarily set between the “low” logic level (R low ) and the “high” logic level (R high ) is selected. When comparing the reading window of the upper diagram and the lower diagram of Fig. 1, the reading window Wr1 of the upper diagram is significantly wider than the reading window Wr2 of the lower diagram. In some embodiments, the lower diagram is Fig. 1 derived from a real semiconductor device, where an MRAM cell is sandwiched between two consecutive metal layers M x and M x+1 In some embodiments, the MRAM cell is positioned after the fourth metal layer M 4 and before the fifth metal layer M 5The metal layer referred to here may be directed to a horizontal metallic interconnect within dielectric materials, as opposed to a vertical metallic interconnect or a so-called "via." Under this condition, the signal of the MRAM cell inevitably contains all the information from preceding metal interconnections M 1 , M 2 , M 3 , including metal lines at different levels and all vias connecting the above-mentioned metal lines.

[0014] The information provided by the above-mentioned preceding metal layers, the MRAM cell, and the underlying transistor can differ from device to device. For example, a process variation may cause the thicknesses or lengths of different metal layers or vias to form a finite distribution. In other words, with identical manufacturing processes, device A and device B may have a different "low" logic level (R low ) and the different “high” logic levels (R high ). Taking into account all manufactured devices, the FWHM of the “low” logic level (R low ) and the “high” logic level (R high ) as shown in the diagram below from Fig. 1, which differs from the narrow counterpart in the ideal case, which is shown in the upper diagram of Fig. 1 is shown.

[0015] Striving for a narrower read window of a memory device is an objective of the present disclosure.

[0016] Process variation can be increased if the manufacturing variation at the bottom metal layer is propagated to the top metal layer. For example, chemical mechanical polishing (CMP) is a process for a damascene metal structure. If a CMP process in the bottom metal layer does not achieve a planarized surface, the small height variation is magnified when the top metal layer is reached, resulting in a serious height variation. It is clear that structural variation of metal layers can directly affect the series resistance of the metal layers. When all manufactured devices are considered, the series resistance of the metal layers can also form a distribution, thereby increasing the FWHM of the "low" logic level peaks (R low ) and that of the “high” logic level (Rhigh ) is widened.

[0017] To narrow the FWHM of the R low and R high Peaks, the present disclosure provides a memory cell formed before any metal layers over a transistor region. For example, an MRAM cell may be formed before the first metal interconnect M 1In other words, the MRAM cell described herein is formed during the middle-end-of-line (MEOL) operation and before the back-end-of-line (BEOL) operation. In some embodiments, the MEOL operation refers to the entire operation after the formation of the gate and source / drain of a transistor and before the formation of metal layers, or the Cu process. In particular, the MEOL operation includes the formation of a conductive plug structure from the gate or source / drain region and the formation of a dielectric layer encapsulating the transistor structure. In particular, the BEOL operation includes all operations after the formation of the metal layer or the Cu process.

[0018] The formation of an MRAM cell before metal layers minimizes the signal from metal routings and thus a narrower FWHM of the R low and R highPeaks can be obtained. Furthermore, the subsequent processing window for CMP operations in BEOL can be broadened due to the fact that the contribution of a process variation in BEOL produces a small impact on the read window as far as a storage device is concerned.

[0019] With reference to Fig. 2 is Fig. 2 is a cross-section of a semiconductor structure 10 in which an MTJ is integrated, according to some embodiments of the present disclosure. In Fig. 2, a transistor region 11, symbolized by the use of a transistor, may be formed on a surface of a carrier layer 100. In alternative embodiments, the carrier layer 100 is a dielectric carrier layer, and no active devices are formed on the dielectric carrier layer, although passive devices such as capacitors, inductors, resistors, and the like may be formed. Contact plugs 113 are formed in an interlayer dielectric (ILD) 115 and may be electrically coupled to the transistor region 11. The semiconductor device 11 and the contact plug 113 may collectively be referred to as a transistor region. The semiconductor device 11 includes a gate 103 and doped regions 105a, 105b at least partially within the carrier layer 100. Fig. Figure 2 shows a planar transistor with a doped region in the support layer 100. However, the present disclosure is not limited thereto. Any non-planar transistor, such as a FinFET structure, may have raised doped regions 105a, 105b.

[0020] An interconnect structure 12, including metal lines 117 and vias 119 and electrically coupled to the transistor region 11, is formed over the ILD 115. Metal lines 117 and vias 119 may be formed from substantially pure copper (e.g., having a copper weight percentage of greater than about 90 percent or greater than about 95 percent) or copper alloys, and may be formed using a single and / or dual damascene process. Metal lines 117 and vias 119 may or may not be substantially free of aluminum. The interconnect structure 12 includes a plurality of metal interconnects, namely M1 , M 2 ,... M top 111, where metal intermediate compound M 1 the metal lines and vias are closest to the ILD 115, while metal interconnect M top 111 are the upper metal lines and vias farthest from ILD 115. Throughout this specification, the term "metal interconnects" refers to the composition of the metal lines and vias in the same layer. Metal Interconnects M 1 to M top111 are formed in inter-metal dielectrics (IMDs) 115', which may be formed from oxides such as undoped silicate glass (USG), fluorinated silicate glass (FSG), low-k dielectric materials, or the like. The low-k dielectric materials may have k values ​​of less than 3.8, although the dielectric materials of IMDs 115' may also be close to 3.8. In some embodiments, the k values ​​of the low-k dielectric materials are less than about 3.0 and may be less than about 2.5.

[0021] In Fig. 2, the semiconductor support layer 100 may be, for example, but not limited to, a silicon support layer. In one embodiment, the support layer 100 is a semiconductor support layer, such as a silicon support layer, although it may include other semiconductor materials, such as silicon germanium, silicon carbide, gallium arsenide, or the like. In the present embodiment, the support layer 100 is a p-type semiconductor support layer (P-type support layer) or an n-type semiconductor support layer (N-type support layer) that includes silicon. Alternatively, the support layer 100 includes another elemental semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.In another alternative, the support layer 100 is a semiconductor on insulator (SOI). In other alternatives, the semiconductor support layer 100 may include a doped epi-layer, a gradient semiconductor layer, and / or a semiconductor layer overlying another semiconductor layer of a different type, such as a silicon layer over a silicon germanium layer. The support layer 100 may include doped regions, such as a p-well, an n-well, or combinations thereof.

[0022] A number of trench isolation (STI) regions 101 are formed in the semiconductor substrate 100. The STI regions 101, which may be formed of suitable dielectric materials, may be used to electrically isolate a transistor from neighboring semiconductor devices, such as other transistors. The STI regions 101 may, for example, be an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (SiO 2), a nitrogen-bearing oxide (e.g. nitrogen-bearing SiO 2 ), a nitrogen-doped oxide (e.g. N 2 -implanted SiO 2 ), silicon oxynitride (Si x O y N z ) and the like. The STI regions may also be formed from any suitable “high dielectric constant” or “high-K” material, where K is greater than or equal to about 8, such as titanium oxide (Ti x O y , e.g. TiO 2 ), tantalum oxide (Ta x O y , e.g. Ta 2 O 5 ), barium strontium titanate (BST, BaTiO 3 / SrTiO 3 ), and the like. Alternatively, the STI regions may be formed from any suitable "low dielectric constant" or "low-K" dielectric material, where K is less than or equal to about 4.

[0023] Still in Fig. 2, the ILD 115 or IMD 115' may be formed by a variety of techniques for forming such layers, e.g., chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering and physical vapor deposition (PVD), thermal growth, and the like. The dielectric layer over the semiconductor support layer 100 may have a thickness ranging, for example, up to about 5.0 nm and may be formed from a variety of dielectric materials and may be, for example, an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (SiO2), a nitrogen-bearing oxide (e.g., nitrogen-bearing SiO2), a nitrogen-doped oxide (e.g., N2-implanted SiO2), silicon oxynitride (Si x Oy Nz), and the like.

[0024] With further reference to Fig. 2, the metal interconnections M 1 , M 2 , and M topconductive material in IMDs 115'. The conductive material may be Ta, Cu, Al, or another suitable metal. The IMD 115' may contain one or more layers of suitable dielectrics. The dielectric may be SiO 2 In some embodiments, the dielectric is a low-k dielectric. A low-k dielectric is a material with a dielectric constant lower than that of silicon dioxide. Examples of low-k dielectrics include organosilicate glasses (OSG) such as carbon-doped silicon dioxide, fluorine-doped silicon dioxide (otherwise referred to as fluorinated fused silica (or FSG)), and organic polymeric low-k dielectrics. Examples of organic polymeric low-k dielectrics include polyarylene ether, polyimide (PI), benzocyclobutene, and amorphous polytetrafluoroethylene (PTFE). A low-k dielectric may be applied by any suitable means, including, for example, spin coating or CVD.

[0025] A memory structure, for example, an MRAM cell, is positioned between the semiconductor device 11 and the interconnect structure 12. In some embodiments, an MTJ layer 201 consisting of a plurality of ferromagnetic and non-ferromagnetic layers, with a bottom electrode 202 and a top electrode 203 parallel to the plurality of layers. For example, the bottom electrode 202 may be brought into contact with the contact plug 113 extending from the semiconductor device 11. The top electrode 203 may be brought into contact with a via 119 of the first metal interconnect M 1 It should be noted that the first metal intermediate M 1 which contains the via 119 and metal lines 117 closest to the ILD 115. The upper electrode 203 is located under the first metal interconnect M 1, in particular, the upper electrode 203 is located under a via 119 of the first metal interconnect M 1. Furthermore, a protection layer 204, which covers at least one sidewall of the MTJ layer 201, is disposed over the dielectric layers 206a, 206b. The protection layer 204 is configured to avoid oxidation or other contamination of the sidewall of the MTJ layer 201 in subsequent processing. The structural integrity of the MTJ layer 201 is critical for the performance of the memory. In some embodiments, the dielectric layers 206a, 206b may be an oxide (e.g., Ge oxide), an oxynitride (e.g., GaP oxynitride), silicon dioxide (SiO2), a nitrogen-bearing oxide (e.g., nitrogen-bearing SiO2), a nitrogen-doped oxide (e.g., N2-implanted SiO2), silicon oxynitride (Si x Oy Nz), and the like. Furthermore, another dielectric layer 205 may be formed over the protective layer 204 and may be coplanar with the top electrode 203 of the MRAM cell.

[0026] With reference to both Fig. 2 as well as Fig. 3 is Fig. 3 is a cross-section of a semiconductor structure incorporating an MTJ, according to some embodiments of the present disclosure. Fig. 2, the bottom electrode 202 of the MRAM cell is electrically coupled to the doped region 105b. In some embodiments, the doped region 105b is a drain or a source. In Fig. 3, the bottom electrode 202 of the MRAM cell is electrically coupled to the gate 103. In some embodiments, the gate 103 of the semiconductor device 11 may be a polysilicon gate or a metal gate. As shown in Fig. 3, a height T of the MTJ layer 201 is in the range of about 15.0 nm to about 25.0 nm. Such a height T is suitable for integrating an MTJ layer 201 into the MEOL process, between the interconnect structure 12 and the transistor region.

[0027] In Fig. 2 and Fig. 3, the MRAM cell is arranged in the semiconductor structure 10 such that the first metal interconnection M 1 , the gate 103, the doped regions 105a, 105b, and the MTJ layer 201 form a conductive loop. In other words, whether the MRAM cell is positioned over the doped regions 105a, 105b or over the gate 103, the "low" logic level (R low ) and the “high” logic level (R high ) can be determined when a current moves through the above-mentioned conductive loop. In this context, a conductive signal can no longer carry information from upper metal layers M x (x>1) and narrow the read window of the MRAM cell.

[0028] With reference to Fig. 4 is Fig. 4 is a plan view of a layer of a semiconductor structure incorporating an MTJ, according to some embodiments of the present disclosure. In some embodiments, Fig. 4 is a plan view taken along AA' of Fig. 2. From a top view perspective, the vias 119 of the first metal interconnect M 1 a footprint of, for example, two circles 40. The footprint of the vias 119 of the first metal interconnect M 1However, it may not be limited thereto. Other geometric shapes are within the contemplated scope of the present disclosure. At the surface of the dielectric layer 206b, the MTJ layer 201 has a footprint, for example, of a circle 41. A bottom of the MTJ layer 201 may have a diameter D1 and a top of the MTJ layer 201 may have a diameter D2, illustrated in dashed lines. In some embodiments, the diameter D1 of the MTJ layer 201 ranges from about 10 nm to about 60 nm. In some embodiments, the diameter D2 of the MTJ layer 201 is 20% to 50% smaller than the diameter D1.

[0029] Fig. 5 is a schematic diagram illustrating multiple ferromagnetic and non-ferromagnetic layers forming an MTJ layer 201, according to some embodiments of the present disclosure. Referring to Fig. 5, the MTJ layer 201 may include ferromagnetic layers 15a1, 15a3, and 15a5, spacers 15a2 and 15a4, and a cap layer 15a6. The spacer 15a2 is formed on the ferromagnetic layer 15a1. The ferromagnetic layer 15a1 is formed on the spacer 15a2. The spacer 15a2 is formed on the ferromagnetic layer 15a3. The ferromagnetic layer 15a3 is formed on the spacer 15a4. The cap layer 15a6 is formed on the ferromagnetic layer 15a1. Each of the ferromagnetic layers 15a1, 15a3, and 15a5 may contain a ferromagnetic material, which may be a metal or a metal alloy, for example, Fe, Co, Ni, CoFeB, FeB, CoFe, FePt, FePd, CoPt, CoPd, CoNi, TbFeCo, CrNi, or the like. The spacer 15a2 may contain a non-ferromagnetic metal, for example, Ag, Au, Cu, Ta, W, Mn, Pt, Pd, V, Cr, Nb, Mo, Tc, Ru, or the like. The spacer 15a4 may contain an insulator, for example, Al.2 O 3 , MgO, TaO, RuO or the like. The cover layer 15a6 may contain non-ferromagnetic material, which may be a metal or an insulator, for example, Ag, Au, Cu, Ta, W, Mn, Pt, Pd, V, Cr, Nb, Mo, Tc, Ru, Ir, Re, Os, Al 2 O 3 , MgO, TaO, RuO, or the like. The capping layer 15a6 may reduce a write current of its associated magnetic random access memory (MRAM) cell. In some embodiments, the spacer 15a4 and the capping layer 15a6 may be any suitable dielectric materials. Dielectric materials that may be suitable for these layers include, for example, SiN, SiOx, and SiON. In some embodiments, the spacer 15a4 is formed from one or more materials selected from the group consisting of SiN, SiOx, and SiON.

[0030] The ferromagnetic layer 15a1 may serve as a free layer 215, whose magnetic polarity or magnetic orientation can be changed during the write operation of its associated MRAM cell. The ferromagnetic layers 15a3, 15a5, and the spacer 15a4 may serve as a fixed or fixed layer 213, whose magnetic orientation cannot be changed during the operation of its associated MRAM cell. It is contemplated that the MTJ layer 201 may be an antiferromagnetic layer (in Fig. 5 not shown) according to other embodiments. In some embodiments, the fixed layer 213 is closer to the bottom electrode 202 and thus to the doped region 105b than the free layer 215. The free layer 215 and fixed layer 213 may be any suitable ferromagnetic or other material that behaves similarly to a ferromagnetic material. Materials that may be suitable include NiFe, CoFe, CoFeB. In some embodiments, the free layer 215 contains CoFeB. In some embodiments, the fixed layer 213 contains either CoFe or COFeB.

[0031] In Fig. 5, an upper surface of the MTJ layer 201 has a diameter D2, while a lower surface of the MTJ layer 201 has a diameter D1. Referring to Fig. 4, the diameter D1 is larger than the diameter D2. The ferromagnetic layer 15a5 is in contact with the lower electrode 202, and the cover layer 15a6 is in contact with the upper electrode 203.

[0032] Fig. 6 is a schematic diagram showing layers forming an MTJ according to some embodiments of the present disclosure. Fig. 6 is a schematic diagram illustrating multiple ferromagnetic and non-ferromagnetic layers forming an MTJ layer 201' according to some embodiments of the present disclosure. Referring to Fig. 6, the MTJ layer 201' may include ferromagnetic layers 15a1, 15a3, and 15a5, spacers 15a2 and 15a4, and a cap layer 15a6. The spacer 15a2 is formed on the ferromagnetic layer 15a1. The ferromagnetic layer 15a3 is formed on the spacer 15a4. The spacer 15a4 is formed on the ferromagnetic layer 15a5. The ferromagnetic layer 15a5 is formed on the spacer 15a2. The ferromagnetic layer 15a1 is formed on the cap layer 15a6. The ferromagnetic layer 15a1 may serve as a free layer 215, the magnetic polarity or magnetic orientation of which may be changed during the write operation of its associated MRAM cell. The ferromagnetic layers 15a3, 15a5 and the spacer 15a4 may serve as a fixed or fixed layer 213 whose magnetic orientation cannot be changed during operation of its associated MRAM cell.It is considered that the MTJ layer 201 is an antiferromagnetic layer (in . Fig. 5 not shown) according to other embodiments.

[0033] In Fig. 6, an upper surface of the MTJ layer 201 has a diameter D2, while a lower surface of the MTJ layer 201 has a diameter D1. Referring to Fig. 4, the diameter D1 is larger than the diameter D2. The cover layer 15a6 is in contact with the lower electrode 202, and the ferromagnetic layer 15a3 is in contact with the upper electrode 203. Fig. 6 is a reversal of the MTJ layers compared to Fig. 5. In Fig. 5, the electric current enters the ferromagnetic layer 15a5 and exits the MTJ layer 201 through the cap layer 15a6. In Fig. 6, the electric current enters the ferromagnetic layer 15a3 and exits the MTJ layer 201' through the cap layer 15a6. Depending on different current input directions, the stacking order of the MTJ layers 201, 201' can be changed accordingly. In some embodiments, the free layer 215 is closer to the bottom electrode 202 and thus to the doped region 105b than the fixed layer 213.

[0034] Since the fabrication of an MTJ layer 201 during a MEOL process increases the probability that the MTJ layer 201 will be exposed under the high-temperature environment, especially during the subsequent metallization processes in BEOL, the MTJ layer 201 presented here can withstand the high-temperature environment without serious diffusion that affects the memory device performance.

[0035] Fig. 7 is a cross-section of a semiconductor structure 20 in which an MTJ is integrated in a first region 700a and / or a second region 700b, according to some embodiments of the present disclosure. Numbering in Fig. 7, which with those in Fig. 2 and Fig. 3 are identical, refer to the same elements or equivalents thereof and are not repeated here for simplicity. A first MTJ layer 201a and a second MTJ layer 201b are positioned in the first region 700a and the second region 700b, respectively. The first region 700a and the second region 700b are two parts of an integrated circuit, each having at least one transistor structure, and the first region 700a does not overlap with the second region 700b. However, the first region 700a or the second region 700b do not have to have an MTJ at the same time. As in Fig. 8, a second region 700b is free of an MTJ or other memory structure. Referring to Fig. 7 and Fig. 9 are the MTJs 201a, 201b in Fig. 7 are both electrically coupled to a doped region 105b, while the first MTJ 201a of the first region 700a in Fig. 9 is coupled to a doped region 105b and the second MTJ 201b of the second region 700b is coupled to a gate 103.

[0036] As in Fig. As shown in Figure 9, a height T1 of the first MTJ layer 201a in the first region 700a is greater than a height T2 of the second MTJ layer 201b in the second region 700b. In some embodiments, the bottom diameter D1 of the first MTJ layer 201a and the bottom diameter D1' of the second MTJ layer 201a are substantially the same, only the heights of the two MTJ layers 201a, 201b are different. It is known that the amount of current sufficient to change the magnetic polarity of an MTJ is related to the total volume of the MTJ. Since the diameters D1, D1' of the first MTJ layer 201a and the second MTJ layer 201b, respectively, are substantially identical, the second MTJ layer 201b with a smaller height T2 tends to change the magnetic polarity under the same current. In some embodiments, the MTJ layer 201b may be an SRAM and the MTJ layer 201a may be a flash.

[0037] With further reference to Fig. 7, a diameter of the first MTJ 201a differs from that of the second MTJ 201b. As in Fig. 10, is Fig. 10 is a plan view taken along line BB' of a semiconductor structure 20 incorporating an MTJ in the first region 700a and the second region 700b, according to some embodiments of the present disclosure.

[0038] In Fig. 10, from a top view perspective, the vias 119 of the first metal interconnection M 1 in the first region 700a a footprint of, for example, two circles 50a. The footprint of the vias 119 of the first metal interconnect M 1However, the diameter of the MTJ layer 201a in the first region 700a may not be limited thereto. Other geometric shapes are within the contemplated scope of the present disclosure. On the surface of the dielectric layer 206b, the MTJ layer 201a in the first region 700a has a footprint of, for example, a circle 51a. A bottom of the MTJ layer 201a may have a diameter D1, and a top of the MTJ layer 201a may have a diameter D2, illustrated in dashed lines. In some embodiments, the diameter D1 of the MTJ layer 201a is in the range of about 10 nm to about 60 nm. In some embodiments, the diameter D2 of the MTJ layer 201a is 20% to 50% smaller than the diameter D1.

[0039] In Fig. 10 have from a top view perspective the vias 119 of the first metal interconnection M 1in the second region 700b a footprint of, for example, two circles 50b. The footprint of the vias 119 of the first metal interconnect M 1 However, in the second region 700b may not be limited thereto. Other geometric shapes are within the contemplated scope of the present disclosure. On the surface of the dielectric layer 206b, the MTJ layer 201b in the second region 700b has a footprint of, for example, a circle 51b. A bottom of the MTJ layer 201b may have a diameter D1' and a top of the MTJ layer 201b may have a diameter D2', which is illustrated in dashed lines. Note that the diameter D1' is smaller than the diameter D1, and likewise, the diameter D2' is smaller than the diameter D2. In some embodiments, the memory in the first region 700a is flash, and the memory in the second region 700b is SRAM.

[0040] In some embodiments, the diameter D1' of the MTJ layer 201b is in the range of about 10 nm to about 60 nm. Note that the diameter D1' is smaller than the diameter D 1 and also the diameter D 2 ' is smaller than the diameter D2. In some embodiments, the diameter D2' of the MTJ layer 201a is 20% to 50% smaller than the diameter D1'.

[0041] Fig. 11 to Fig. 26 show partial cross-sectional views of the formation of a semiconductor structure incorporating an MTJ in a first region 700a and a second region 700b, according to some embodiments of the present disclosure. In Fig. 11, two transistor regions are formed in a form of transistors over the carrier layer 100. As in Fig. As shown in Figure 11, each transistor includes a gate 103 and doped regions 105a, 105b. The transistor in the first region 700a and the second region 700b are separated by an STI 101. In some embodiments, the doped regions 105a, 105b are a raised source and a raised drain, and the gate 103 is a metal gate.

[0042] In Fig. 12, conductive plugs 113 are formed extending from the doped regions 105a, 105b and the gate 103. A patterned ILD 115 is formed prior to filling the contact plug 113. For example, through-holes are formed in the ILD 115 and subsequently filled with electrically conductive material, e.g., copper, gold, or another suitable metal or alloy, to form a series of conductive plugs 113. The conductive plugs 113 may be electrically connected to semiconductor devices, such as transistors, in the semiconductor carrier layer 100. The conductive plugs 113 may be formed by a variety of techniques, e.g.,Electroplating, electroless plating, high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. In . Fig. 12, a planarization operation is performed to expose a top surface of the conductive plugs 113 and the top surface of the ILD 115.

[0043] In Fig. 13, a stack of dielectric layers 206a, 206b, 206c is formed over the planarized surface, which in Fig. 12. In some embodiments, the dielectric layers 206a, 206c may be made of identical materials, while the dielectric layer 206b may be a different material with a different selectivity with respect to an etch or a CMP operation. For example, the dielectric layer 206b may be a silicon oxide layer, while the dielectric layers 206a, 206c may be dielectrics other than silicon oxide. The stack of dielectric layers 206a, 206b, 206c may be formed by a variety of techniques, e.g., chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), sputtering and physical vapor deposition (PVD), thermal growth, and the like.

[0044] In Fig. 14 and Fig. 15, two openings 1401a, 1401b are formed, passing through the stack of dielectric layers 206a, 206b, and 206c. As in Fig. 14, a first opening 1401a is formed over a contact plug 113 that is electrically coupled to the doped region 105b of the first region 700a. A second opening 1401b is formed over a contact plug 113 that is electrically coupled to the doped region 105b of the second region 700b. In some embodiments, a width of the first opening 1401a is greater than a width of the second opening 1401b. Subsequently, a conductive layer 207 is formed over the stack of dielectric layers 206a, 206b, and 206c, as well as filling the first opening 1401a and the second opening 1401b. The conductive layer 207 may be formed by a number of techniques, e.g.High-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. In . Fig. 15, a planarization process is performed to remove the stress on the conductive materials 207 and the dielectric layer 206c. A bottom electrode 202a in the first region 700a and a bottom electrode 202b in the second region 700b may be obtained upon completion of the planarization process. Note that the bottom electrode 202a has a surface area that is different from a surface area of ​​the bottom electrode 202b when viewed from a top-view perspective (not shown). The difference in surface areas between the bottom electrodes 202a and 202b is due to the formation of subsequent MTJ layers with different dimensions.

[0045] In Fig. 16, an MTJ layer 2011 having a thickness of about 15.0 nm to about 25.0 nm and a conductive layer 2031 are formed over the planarized surface, as shown in Fig. 15. The MTJ layer 2011 is formed on the bottom electrodes 202a, 202b and patterned dielectric stacks 206a, 206b. The MTJ layer 2011 can be formed by a variety of techniques, e.g., high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. In some embodiments, the MTJ layer 2011 is a stack of various deposited films. A detailed structure of the MTJ layer 2011 is previously described in Fig. 5 and Fig. 6 and is not repeated here for simplicity. The conductive layer 20312011 can be formed by a variety of techniques, e.g., high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and the like.

[0046] In Fig. 17, a mask layer 1701 is formed on the conductive layer 2031. The mask layer 1701 may have a multi-layer structure, which may include, for example, an oxide layer, an advanced patterning film (APF) layer, and an oxide layer. Each of the oxide layer, the APF layer, and the oxide layer may be formed by a variety of techniques, e.g., high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and the like. In some embodiments, the mask 1701 is configured for patterning the MTJ layers 201a, 201b and top electrodes 203a, 203b, as shown in Fig. 18. For example, a width of the openings 1701a, 1701b of the mask layer 1701 is determined according to the desired MTJ diameter. As previously discussed, the first MTJ layer 201a in the first region 700a has a bottom diameter D1 of about 10 nm to about 60 nm from a top view perspective, and the second MTJ layer 201b in the second region 700b has a bottom diameter D1' smaller than that of D1. In some embodiments, the MTJ layers 201a, 201b and the top electrodes 203a, 203b are formed with a trapezoidal shape when viewed from the cross section.

[0047] In Fig. 19, a dielectric layer 2041 is conformally formed over the MTJ layers 201a, 201b and the top electrodes 203a, 203b. In some embodiments, the dielectric layer 2041 has a thickness of about 5.0 nm to about 30.0 nm. Note that a sidewall of the MTJ layers 201a, 201b and the sidewall of the bottom electrode 202a, 202b are surrounded by the dielectric layer 2041 to avoid oxidation or other contamination. Subsequently, a dielectric layer 2051, such as an oxide layer, is conformally deposited over the dielectric layer 2041. In Fig. 20, a planarization operation is performed on the dielectric layer 2051 such that a top surface of the dielectric layer 2051 is substantially flat. This planarization operation is a preparatory step for the following thinning operation, where starting with a substantially flat surface is critical for the thinning operation. As shown in Fig. 20, a top surface of the MTJ layer 203a, 203b is not exposed from the dielectric layer 2041 after the planarization process.

[0048] With reference to Fig. 21 and Fig. 22, the vias 119 are formed over the conductive plug 113. In some embodiments, a plurality of openings 119' are patterned through the dielectric layers 2051, 2041, 206b, and 206a until the conductive plug is exposed. Conductive material is then filled into the openings 119', followed by a thinning operation that removes the excess conductive material and a portion of the dielectric layers 2051, 2041. It should be noted that in Fig. 22 an upper surface 2031a of the MTJ layer 203a is exposed as a result of the thinning operation.

[0049] With reference to Fig. 23, Fig. 24 and Fig. 25, a first metal intermediate connection M 1 , including vias 119 and metal lines 117 connecting the vias 119, formed over the vias 119 in the same plane as the MRAM cell. In Fig. 23, an etch stop layer (ESL) 208, an IMD 115' and a masking layer 209 are deposited over the entire planarized surface in Fig. 22. The IMD 115', the ESL, and the masking layer 209 can be formed by a variety of techniques for forming such layers, e.g., chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), sputtering and physical vapor deposition (PVD), thermal growth, and the like. Trenches to be filled with conductive materials are patterned over the vias 119 at the same level as the MRAM cell. In Fig. 24, conductive materials are filled into the trenches. After a further planarization step, a dielectric layer 2061 is formed over the filled trenches, and metal lines 117 are formed, for example, using a damascene process.

[0050] In Fig.26 upper metal layers, such as M 3 , M 4 ,... M top over the first metal interconnection M 1 formed and construct the interconnect structure over the MRAM cell.

[0051] The integrated circuit device may undergo further processing by CMOS or MOS technology to form various features known in the art. For example, one or more contact features (not shown), such as silicide regions, may also be formed. The contact features may be coupled to the source and the drain. The contact features include silicide materials such as nickel silicide (NiSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), other suitable conductive materials, and / or combinations thereof. In one example, the contact features are formed by a salicide (self-aligned silicide) process.

[0052] Subsequent processing may further include forming various contacts / vias / lines and multi-layer interconnect features (e.g., metal layers and interlayer dielectrics) over the support layer configured to connect the various features or structures of the integrated circuit device. The additional features may provide electrical interconnection to the device including the formed metal gate structures. For example, a multi-layer interconnect includes vertical interconnects, such as conventional vias or contacts, and horizontal interconnects, such as metal lines. The various interconnect features may implement various conductive materials, including copper, tungsten, and / or silicide.In one example, a damascene and / or dual damascene process is used to form a copper-related multilayer interconnect structure.

[0053] The present disclosure provides a semiconductor structure including a support layer, a transistor region having a gate above the support layer and a doped region at least partially within the support layer, a first metal interconnect above the transistor region, and a magnetic tunnel junction (MTJ) between the transistor region and the first metal interconnect. A first region above the support layer includes a first magnetic tunnel junction (MTJ) between the transistor region and the first metal interconnect, and a second region above the support layer does not overlap with the first region.

[0054] The present disclosure provides a semiconductor structure including a support layer, a transistor region having a gate over the support layer and a doped region at least partially in the support layer, and a first metal interconnect over the transistor region.

[0055] The present disclosure provides a method of fabricating a semiconductor structure, including forming a transistor region over a support layer, the transistor region including a gate and a doped region, forming a magnetic tunnel junction (MTJ) over the transistor region electrically coupled to the transistor region, and forming a first metal interconnect over the MTJ electrically coupled to the MTJ and the transistor region.

[0056] Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above may be implemented in various technologies and replaced by other processes or a combination thereof.

Claims

[1] Semiconductor structure (20) comprising: a carrier layer (100); a transistor region (11) comprising a gate (103) above the carrier layer and a doped region (105a, 105b) at least partially in the carrier layer, the doped region comprising a first doped region (105b) and a second doped region (105a); a first metal interconnect over the transistor region, the first metal interconnect comprising a first via (119) and a second via (119); and a magnetic tunnel contact (201) between the first doped region (105b) of the transistor region and the first via (119) of the first metal interconnect, wherein the second via (119) of the first metal interconnect is formed over a via (119) formed in the same plane as the magnetic tunnel contact (201), wherein the magnetic tunnel contact (201) is a first magnetic tunnel contact (201b) and a first region above the carrier layer (100) contains the first magnetic tunnel contact (201b) between the transistor region and the first metal interconnect; and wherein the semiconductor structure (20) further comprises a second region above the carrier layer, the second region not overlapping the first region, the second region including a second magnetic tunnel contact (201a) between the transistor region (11) and the first metal interconnect, wherein the first magnetic tunnel contact (201b) and the second magnetic tunnel contact (201a) have an identical or different diameter at a respective bottom surface of the first magnetic tunnel contact and the second magnetic tunnel contact from a plan view perspective and different heights from a cross-sectional perspective. [2] The semiconductor structure of claim 1, further comprising an upper electrode (203) and a lower electrode (201) of the magnetic tunnel junction, wherein the upper electrode (203) underlies the first metal interconnection. [3] The semiconductor structure of claim 2, wherein the lower electrode (202) is electrically coupled to the first doped region (105b). [4] The semiconductor structure of claim 3, wherein the first doped region (105b) is a source or a drain. [5] The semiconductor structure of claim 2, wherein the lower electrode (202) is electrically coupled to the gate (103). [6] The semiconductor structure of any preceding claim, wherein the magnetic tunnel contact (201) has a diameter (D1) of about 10 nm to about 60 nm from a plan view perspective at a bottom surface of the magnetic tunnel contact. [7] A semiconductor structure according to any one of the preceding claims, wherein the magnetic tunnel contact (201) has a height of about 15 nm to about 25 nm from a cross-sectional perspective. [8] A semiconductor structure according to any one of the preceding claims, wherein the first magnetic tunnel contact includes a free layer and a fixed layer, the fixed layer being closer to the doped region (105b) than the free layer. [9] Semiconductor structure according to one of the preceding claims, wherein the via is electrically coupled to the upper electrode (203) of the magnetic tunnel contact. [10] A semiconductor structure according to any one of the preceding claims, wherein the transistor is a FinFET structure and the doped region (105a, 105b) is a raised source or a raised drain. [11] The semiconductor structure according to any one of the preceding claims, wherein the first magnetic tunnel contact (201b) and the second magnetic tunnel contact (201a) have different diameters at a bottom surface of the first magnetic tunnel contact and at a bottom surface of the second magnetic tunnel contact from a plan view perspective. [12] A semiconductor structure according to any one of the preceding claims, wherein an area of ​​a first lower electrode of the first magnetic tunnel contact (201b) differs from an area of ​​a second lower electrode of the second magnetic tunnel contact (201a) from a top view perspective. [13] A method for producing a semiconductor structure (20), comprising: Forming a transistor region (11) over a carrier layer (100), the transistor region (11) including a gate (103) and a doped region, and the doped region having a first doped region (105b) and a second doped region (105a); Forming a magnetic tunnel contact (201) over the first doped region (105b) of the transistor region, which is electrically coupled to the transistor region; and Forming a first metal interconnect over the magnetic tunnel contact (201) comprising a first via (119) and a second via (119), wherein the first via is electrically coupled to the magnetic tunnel contact and the transistor region, wherein the second via (119) of the first metal interconnect is formed over a via (119) formed in the same plane as the magnetic tunnel contact (201), wherein the magnetic tunnel contact (201) is a first magnetic tunnel contact (201b) and a first region above the carrier layer (100) contains the first magnetic tunnel contact (201b) between the transistor region and the first metal interconnect; and wherein the semiconductor structure (20) further comprises a second region above the carrier layer which does not overlap with the first region, the second region including a second magnetic tunnel contact (201a) between the transistor region (11) and the first metal interconnect, wherein the first magnetic tunnel contact (201b) and the second magnetic tunnel contact (201a) have an identical diameter at a respective bottom surface of the first magnetic tunnel contact and the second magnetic tunnel contact from a plan view perspective and different heights from a cross-sectional perspective. [14] The method of claim 13, wherein forming the transistor region comprises forming a transistor having the gate and the doped region and forming a conductive plug structure (113) extending from the doped region. [15] The method of claim 14, further comprising forming a lower electrode (202) and an upper electrode (203) of the magnetic tunnel contact, wherein the lower electrode is electrically coupled to the doped region through the conductive plug structure. [16] The method of claim 15, wherein forming the magnetic tunnel contact (201) over the transistor region (11) comprises patterning the magnetic tunnel contact with a diameter of about 10 nm to about 60 nm at a bottom surface of the lower magnetic tunnel contact from a top view perspective. [17] The method of claim 15 or 16, further comprising forming a dielectric (204) conformally covering the top electrode (203) and a sidewall of the magnetic tunnel contact (201).

Images