Semiconductor device with deep diffusion region

Abstract

Method (2) for manufacturing a power semiconductor transistor (1), comprising: - Providing (20) a semiconductor body (10) which has dopants of a first conductivity type; - Forming (21) a trench (11a) extending along a vertical direction (Z) into the semiconductor body (10), wherein the trench (11a) is bounded in a horizontal direction by two trench sidewalls (113a) and vertically by a trench bottom (114a); - Applying (26) a substance (31) to at least one section (111a) of a trench surface formed by one of the trench side walls (113a) and / or the trench floor (114a) of the trench (11a), wherein the application (26) of the substance (31) comprises preventing the substance from being applied to the other of the trench side walls (113a); and - Diffusion (28) of the applied substance (31) from the section (111a) into the semiconductor body (10), thereby generating a semiconductor region (12a) in the semiconductor body (10) which has dopants of a second conductivity type and is located adjacent to the section (111a), wherein the generated semiconductor region (12a) is located adjacent to exactly one of the two trench side walls (113a); - wherein a transition between the trench (11a) and the generated semiconductor region (12a) extends continuously along exactly one of the trench side walls (113a) to the trench floor (114a).

Description

TECHNICAL AREA

[0001] This description relates to embodiments of a method for processing a semiconductor device and embodiments of a power semiconductor transistor. In particular, this description relates to embodiments of a semiconductor device with deeply doped semiconductor regions produced by diffusion. BACKGROUND

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving an electric motor or machine, rely on semiconductor devices. For example, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes, to name a few, have been used for various applications, including, but not limited to, switches in power supplies and power converters.

[0003] Such power semiconductor devices, e.g., a power semiconductor transistor, can have a variety of doped semiconductor regions, such as a doped body region, a doped source region, a doped drift region, a doped contact region, a doped field stop layer, to name a few.

[0004] For example, a doped semiconductor region can be created by diffusion, implantation, and / or epitaxy. Diffusion typically involves carrying out a temperature process over a specific period of time.

[0005] German patent application DE 20 2004 021 424 U1 discloses a semiconductor device with a plurality of trenches, wherein the plurality of active trenches comprises a lower shielding poly, an upper gate poly, a first oxide layer and a second oxide layer, wherein the first oxide layer separates the lower shielding poly from the upper gate poly and the second oxide layer covers the upper gate poly, wherein the lower shielding poly, the upper gate poly, the first oxide layer and the second oxide layer follow the shape of the active trench and extend from the active trench onto a surface of the boundary region.

[0006] German patent application DE 10 2014 100 249 A1 describes a semiconductor device comprising an IGBT cell with a drift zone doped with type II and a desaturation semiconductor structure for desaturating a charge carrier concentration in the IGBT cell. The desaturation structure comprises a type I doped region forming a pn junction with the drift zone and two sections of a trench, or two trenches, located within the type I doped region and laterally adjacent to the IGBT cell. Each of the two trench sections or each of the two trenches has a wide portion beneath a narrow portion. The wide portions delimit a type I doped desaturation channel region of the type I doped region, at least laterally. The narrow portions delimit a type I doped mesa region of the type I doped region, at least laterally.The desaturation channel region has a width that is smaller than the mesa region in the lateral direction and borders the mesa region.

[0007] US Patent 2012 / 0098057 A1 describes a semiconductor device and a method for its fabrication. The method comprises: forming a trench in a semiconductor substrate of a first conductive type; forming a trench-doping layer containing a dopant of a second conductive type on a side wall and bottom surface of the trench; forming a doping region by diffusing the dopant in the trench-doping layer into the semiconductor substrate; and removing the trench-doping layer. SUMMARY

[0008] According to one embodiment, a method for processing a semiconductor device comprises: providing a semiconductor body having dopants of a first conductivity type; forming at least one trench extending along a vertical direction into the semiconductor body, the trench being laterally bounded by two trench sidewalls and vertically bounded by a trench bottom; applying a substance to at least one section of a trench surface formed by one of the trench sidewalls and / or the trench bottom of the at least one trench, the application of the substance comprising preventing the substance from being applied to the other of the trench sidewalls;as well as diffusion of the applied substance from the section into the semiconductor body, thereby creating a semiconductor region in the semiconductor body which contains dopants of a second conductivity type and is located adjacent to the section. The generated semiconductor region is located adjacent to only one of the two trench side walls.

[0009] According to a further embodiment, a power semiconductor transistor comprises a semiconductor body and at least one transistor cell, wherein the at least one transistor cell comprises: a semiconductor drift region enclosed in the semiconductor body and comprising dopants of a first conductivity type; a semiconductor body region enclosed in the semiconductor body and comprising dopants of a second conductivity type; a source region, wherein the semiconductor body region isolates the source region from the semiconductor drift region; a trench extending along a vertical direction into the semiconductor body and comprising a control electrode that is electrically isolated from each of the semiconductor drift region, the semiconductor body region, and the source region;and a semiconductor region comprising dopants of the second conductivity type, which is adjacent to the trench and separated from the semiconductor body region, wherein a transition extends along a trench sidewall of the trench between the trench and the semiconductor region, and wherein a dopant concentration of the semiconductor region adjacent to the trench sidewall at every point along at least 60% of the total extent of the semiconductor region in the vertical direction assumes a value within a range of 50% to 150% of a fixed dopant concentration value.

[0010] According to a further embodiment, a power semiconductor transistor comprises a semiconductor body and at least one transistor cell, wherein the at least one transistor cell comprises: a semiconductor drift region enclosed in the semiconductor body and comprising dopants of a first conductivity type; a semiconductor body region enclosed in the semiconductor body and comprising dopants of a second conductivity type; a source region, wherein the semiconductor body region isolates the source region from the semiconductor drift region; a trench extending along a vertical direction into the semiconductor body and comprising a control electrode, which is isolated from each of the semiconductor drift region, the semiconductor body region, and the source region;and a semiconductor region comprising dopants of the second conductivity type and located adjacent to the trench and separated from the semiconductor body region, wherein a transition extends along a trench sidewall of the trench between the trench and the semiconductor region, and wherein a dopant concentration of the semiconductor region adjacent to the trench sidewall changes by at least 30% of a dopant concentration value in an area comprising at least 80% of the total extent of the semiconductor region in the vertical direction.

[0011] Experts will recognize additional features and advantages when reading the following detailed description and reviewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The components in the figures are not necessarily to scale; instead, the focus is on illustrating the principles of the invention. Furthermore, identical reference numerals in the figures denote corresponding components. The drawings depict: Fig. 1 schematically represents different steps of a method for processing a semiconductor device according to one or more embodiments; Fig. 2 schematically represents a step of a method for processing a semiconductor device according to one or more embodiments; Fig. 3 schematically represents a step of a method for processing a semiconductor device according to one or more embodiments; Fig. 4 schematically represents a step of a method for processing a semiconductor device according to one or more embodiments; Fig. 5 schematically represents a step of a method for processing a semiconductor device according to one or more embodiments; Fig. 6 schematically represents a step of a method for processing a semiconductor device according to one or more embodiments; Fig. 7 schematically represents a step of a method for processing a semiconductor device according to one or more embodiments; Fig. Figure 8 schematically represents a section of a vertical cross-section of a power semiconductor transistor according to one or more embodiments; and Fig. 9 schematically a section of a vertical cross-section of a processed semiconductor device according to one or more embodiments. DETAILED DESCRIPTION

[0013] The following detailed description refers to the accompanying drawings, which form a part of it and illustrate specific embodiments in which the invention can be practiced.

[0014] In this respect, directional terminology such as "top," "bottom," "lower," "front," "back," "rear," "foremost," "rearmost," "below," "above," etc., may be used with reference to the orientation of the described figures. Since parts of embodiments can be positioned in many different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. It is understood that other embodiments may be used and structural or logical modifications may be made without deviating from the scope of protection of the present invention. The following detailed description is therefore not to be understood in a limiting sense, and the scope of protection of the present invention is defined by the accompanying claims.

[0015] Various embodiments are now described in detail, with one or more examples illustrated in the figures. Each example is provided with explanation and is not intended to limit the invention. For instance, features shown or described as part of one embodiment may be used in or in combination with other embodiments to provide yet another embodiment. It is intended that the present invention encompasses such modifications and variants. The examples are used with specific language, which should not be interpreted as limiting the scope of protection of the accompanying claims. The drawings are not to scale and are for illustrative purposes only.For the sake of clarity, unless otherwise stated, the same elements or manufacturing steps have been designated with the same reference symbols in the different drawings.

[0016] The term "horizontal," as used in this description, is intended to describe an orientation that is essentially parallel to a horizontal surface of a semiconductor substrate or region. This could be, for example, the surface of a semiconductor wafer or a bare chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below can be horizontal directions, with the first lateral direction X and the second lateral direction Y being perpendicular to each other.

[0017] The term "vertical," as used in this description, is intended to describe an orientation that is essentially perpendicular to the horizontal surface, i.e., parallel to the normal direction of the semiconductor wafer's surface. For example, the extension direction Z mentioned below can be a vertical direction that is perpendicular to both the first lateral direction X and the second lateral direction Y.

[0018] In this description, n-doped can be referred to as the "first conductivity type," while p-doped can be referred to as the "second conductivity type." Alternatively, opposite doping ratios can be used, so that the first conductivity type can be p-doped and the second conductivity type n-doped. However, as an alternative, the terms "first conductivity type" and "second conductivity type" can both refer to either n-doped or p-doped. Therefore, the second conductivity type can be identical to the first conductivity type in one or more embodiments. In one or more embodiments, the second conductivity type can be complementary to the first conductivity type.

[0019] Furthermore, the term "doping concentration" within this description can refer to an average doping concentration or a mean doping concentration of a specific semiconductor region or zone, such as a semiconductor region within a trench. Therefore, for example, a statement that a specific semiconductor region has a certain doping concentration that is higher or lower compared to the doping concentration of another semiconductor region can indicate that the respective mean doping concentrations of the semiconductor regions differ from one another.

[0020] In the context of this description, the terms "in ohmic contact," "in electrical contact," "in ohmic connection," and "electrically connected" are intended to describe the existence of a low-resistance electrical connection or current path between two regions, zones, areas, or parts of a semiconductor device, or between different terminals of one or more devices, or between a terminal, metallization, or electrode and an area or part of a semiconductor device. Furthermore, in the context of this description, the term "in contact" is intended to describe the existence of a direct physical connection between two elements of the respective semiconductor device, where, for example, a junction between two elements in contact may not include any further intermediate element or the like.

[0021] Specific embodiments described in this description relate, but are not limited to, a power semiconductor device that can be used within a power converter or power supply unit, as well as corresponding processing methods. For example, the power semiconductor device can comprise one or more power semiconductor cells, such as a monolithically integrated diode cell and / or a monolithically integrated transistor cell and / or a monolithically integrated IGBT cell and / or a monolithically integrated MOS-gate diode (MGD) cell and / or a monolithically integrated MOSFET cell and / or derived versions thereof. Such diode cells and transistor cells can be integrated into a power semiconductor module.

[0022] The term "power semiconductor device," as used in this description, refers to a semiconductor device on a single chip with high voltage-blocking and / or high current-carrying capabilities. In other words, such a power semiconductor device is designed to handle high currents, typically in the ampere range, e.g., up to several tens or hundreds of amperes, and / or high voltages, typically above 50 V, more commonly 500 V or higher.

[0023] Fig. 1 represents different steps of a method 2 for processing a semiconductor device according to one or more embodiments.

[0024] In a first step 20, a semiconductor body 10 is provided. The semiconductor body 10 can have dopants of a first conductivity type. For example, the semiconductor body 10 is n-doped. The semiconductor body 10 can be provided as part of a semiconductor wafer. For example, the semiconductor wafer can have a diameter of at least 200 mm, such as a diameter of 300 mm or a diameter even greater than 300 mm. For example, the semiconductor body 10 is a semiconductor wafer.

[0025] The semiconductor body 10 has an area 10⁻¹ that can extend along both the first lateral direction X and the second lateral direction Y, where each of these lateral extensions X and Y can be horizontal directions. Furthermore, the semiconductor body 10 can extend along a vertical direction Z that is perpendicular to the lateral extensions X and Y, for example, at least 10 µm, at least 40 µm, at least 60 µm, at least 110 µm, or even more than 180 µm.

[0026] In the next step 21, a trench is created that extends along the vertical direction Z into the semiconductor body 10. Fig. Figures 1-7 show two such trenches, 11a and 11b, schematically represented, while Fig. 8 and Fig. 9 merely show one such trench 11a. It is understood that according to other embodiments, more than one trench or more than two trenches can be created in step 21. For example, each trench created in step 21 forms part of a (not shown in Fig. 1 (shown) transistor cell, e.g., of a MOS control head, e.g., a trench-gate MOS control head. This optional aspect is explained in more detail below. Step 21 of forming at least one trench 11a, 11b (step 21) may include an etching processing step.

[0027] For example, the generated trenches 11a, 11b extend at least 1 µm, at least 2 µm, or even more than 4 µm along the vertical direction Z. The trenches 11a and 11b are laterally bounded by two trench sidewalls 113a, 113b along the first lateral direction X. Furthermore, the trenches 11a and 11b are vertically bounded by a trench bottom 114a, 114b along the vertical direction Z. For example, the trench sidewalls 113a and 113b extend in a direction parallel to the vertical direction Z, and the trench bottoms 114a and 114b extend in a direction that is essentially parallel to the first lateral direction X, and at a transition from the trench bottoms 114a, 114b to the trench sidewalls 113a, 113b also in the vertical direction Z; in other words, a transition between the trench sidewalls 113a, 113b and the trench bottoms 114a and 114b can be curved, as shown schematically in Fig. Figure 1 illustrates this. In the context of the present description, for example, the trench sidewalls 113a, 113b can be those parts of the trench surface that extend essentially only along the vertical direction Z. Furthermore, the widths of the trenches 11a, 11b along the first lateral direction X can each be less than 2 µm or even less than 1 µm. For example, the width of each trench 11a, 11b along the first lateral direction X is less than 40% or even less than 20% of the total extent of the respective trench 11a, 11b along the vertical direction Z. Furthermore, the trenches 11a and 11b can extend at least 1 µm or at least 2 µm along the second lateral direction Y.

[0028] In a further step 26, a substance 31 is applied to at least one section 111a, 111b of a trench surface formed by one of the trench side walls 113a, 113b and / or the trench floor 114a, 114b of the respective trench 11a, 11b. At the same time, it can be prevented that the substance 31 is also applied to the other of the two trench side walls 113a, 113b. Therefore, according to the Fig. In the embodiment shown in Figure 1, section 111a of the trench surface of trench 11a is formed only by the right of the trench side walls 113a and parts of the trench floor 114a, and not by the left of the trench side walls 113a. Furthermore, according to this embodiment, section 111b of the trench surface of trench 11b is formed only by the left of the two trench side walls 113b and parts of the trench floor 114b, and not by the right of the two trench side walls 113b. Exemplary procedures to prevent the remaining part of the trench surface from being exposed to the step of applying substance 31 are described in more detail below.

[0029] In one embodiment, only a portion of the trench floor 114a, 114b contributes to the section 111a, 111b that is subjected to the application of the substance 31. For example, this portion comprises no more than 80% of the total extent of the trench floor 114a, 114b along the first lateral direction X, up to no more than 65%, or up to no more than 60% of the total extent. Furthermore, the portion of the trench floor 114a, 114b can comprise more than 5% up to more than 10%, or even up to more than 20% of the total extent of the trench floor 114a, 114b along the first lateral direction X. For example, as schematically shown in each of the Fig. 1 and Fig. 5 to 7 and Fig. Figure 9 shows that the portion of the trench bottom 114a, 114b contributing to section 111a, 111b comprises approximately 40 to 60% of its total extent, with the remaining portion of the trench bottom 114a, 114b not being subjected to the application of substance 31 according to one or more embodiments. This aspect is discussed in more detail with reference to Fig. 5-6 are explained using examples.

[0030] The application of substance 31 in step 26 can comprise at least one of three methods: plasma deposition (PLAD), tilted implantation, or implantation along essentially only the vertical direction Z. For example, during tilted implantation, it can be ensured that the angle between an ion implantation beam and the vertical direction Z is kept below 10°, below 8°, below 6°, or even below 4°. Furthermore, this angle can even be essentially 0°, so that the implantation occurs essentially only along the vertical direction Z. Other variations of such implantation are explained in more detail below.

[0031] In a further step 28, diffusion takes place. Accordingly, the applied substance 31 can diffuse from sections 111a, 111b of the trench surfaces into the semiconductor body 10. This creates semiconductor regions 12a, 13a, which have dopants of a second conductivity type. The second conductivity type can be identical to or complementary to the first conductivity type. For example, the generated semiconductor regions 12a, 12b can be p-doped regions. The semiconductor regions 12a, 12b can be arranged adjacent to the respective sections 111a, 111b. For example, as in Fig. As specified in Figure 1, the semiconductor region 12a is located adjacent to section 111a, which has been exposed to the step of applying substance 31 (step 26), and the semiconductor region 12b may be located adjacent to section 111b of the trench surface of trench 11b, which has been exposed to the step of applying substance 31. Furthermore, sections 111a and 111b may comprise at least a portion of the respective trench bottom 114a, 144b, as exemplified in Figure 1. Fig. 1 shown.

[0032] Therefore, according to one or more embodiments, the generated semiconductor region 12a can be arranged adjacent to only one of the two trench side walls 113a. For example, the generated semiconductor region 12a is not arranged adjacent to the remaining parts of the trench surface of trench 11a that have not been subjected to the application of the substance 31. Similarly, the generated semiconductor region 12b is, for example, not arranged adjacent to the remaining parts of the trench surface of trench 11b that have not been subjected to the application of the substance 31.

[0033] Furthermore, according to one or more embodiments, the generated semiconductor region 12a, 12b can extend deeper into the semiconductor body 10 along the vertical direction Z compared to the respective trench 11a, 11b. For example, the semiconductor region 12a extends more than 10%, more than 30%, more than 60%, or even more than 100% of the total extent of the trench 11a, which may be, for example, a distance along the vertical direction Z between the trench surface 10-1 and the lowest point of the trench bottom 114a, into the semiconductor body 10. In other words, the lowest point of the semiconductor region 12a can be positioned deeper in the semiconductor body 10 than the lowest point of the trench bottom 114a. For example, the distance between these two lowest points along the vertical direction Z is at least 1 µm or at least 3 µm.A dopant concentration of the dopants of the second conductivity type at the lowest point of the generated semiconductor region 12a can be at least 10. 15 cm -3 , at least 10 16 cm -3 or even more than 10 17 cm- 3 The same can also apply to the generated semiconductor region 12b. Furthermore, it is understood that – in contrast to the schematic representation in Fig. 1 - the generated semiconductor regions 12a, 12b do not necessarily have to extend along the vertical direction Z, which begins at the surface 10-1 of the semiconductor body 10. Rather, it is also possible to prevent at least an upper part of the section (111a, 111b) forming the trench sidewall 113a, 113b from being exposed to the application of substance 31. For example, only the trench bottom 114a, 114b, or a part thereof, is exposed to the application of substance 31.

[0034] Therefore, with respect to the surface 10-1 of the semiconductor body 10, comparatively deep semiconductor regions 12a, 12b can be generated by carrying out a diffusion process, whereby this diffusion process can be implemented at a comparatively low temperature and / or within a comparatively short period of time, because the distance which the applied substance 31 has to diffuse into the semiconductor body 10 is comparatively small.

[0035] According to the schematic in Fig. In the embodiments shown in Figure 1, a transition between the trench 11a, 11b and the generated semiconductor region 12a, 12b arranged adjacent to it can extend continuously along only one of the trench side walls 113a, 113b to the trench floor 114a, 114b. For example, the transition can begin at the surface 10-1 of the semiconductor body 10 and can extend continuously along the vertical direction to the beginning of the trench floor 114a, 114b and along the first lateral direction X (or in the opposite direction) along parts of the trench floor 114a, 114b. Furthermore, the generated semiconductor region 12a, 12b can, depending on the B. at least one of a duration of diffusion and a percentage of the trench floor 114a, 114b that can contribute to section 111a, 111b, extends laterally further along the trench floor 114a, 114b, e.g.even so that it reaches the transition from the trench floor 114a, 114b to the respective other of the trench side walls 113a, 113b.

[0036] It is understood, however, that according to further embodiments, the step of applying the substance 31 (step 26) can be carried out in such a way as to ensure that the substance 31 is not applied to any of the trench sidewalls 113a, 113b. For example, to this end, step 26 of applying the substance 31 can be carried out with substantially vertical ion beam implantation in a direction substantially parallel to the extension direction of the trenches 11a, 11b; e.g., substantially only in the vertical direction Z, where the latter formulation in this description is intended to express a beam direction in the vertical direction Z or within a deviation of, e.g., less than 15° from the vertical direction Z. To this end, the sidewalls 113a, 113b of the trenches 11a, 11b can be protected so that they are not exposed to the implantation, as will be explained in more detail below.Furthermore, as described above, in one embodiment only a portion of the trench floor 114a, 114b contributes to the section 111a, 111b that is subjected to the application of the substance 31. For example, this portion comprises no more than 80%, no more than 65%, or no more than 60% of the total extent of the trench floor 114a, 114b along the first lateral direction X. Furthermore, the portion of the trench floor 114a, 114b can comprise more than 5%, more than 10%, or more than 20% of the total extent of the trench floor 114a, 114b along the first lateral direction X.

[0037] Referring more specifically to the step of applying substance 31 (step 26), it is understood that substance 31 can be gaseous and that the application of substance 31 can involve a diffusion process through a mask, e.g., instead of the implantation process mentioned above. For this purpose, the surface 10-1 of the semiconductor body 10 can be masked with a mask (not shown), and subsequently, mask diffusion can be carried out such that, for example, only section 111a, 111b of the surface of the trench 11a, 11b is exposed to the application of substance 31.

[0038] For example, substance 31 can comprise at least one of boron, aluminum, and gallium. For example, such a substance is used to create p-doped semiconductor regions 12a, 12b, e.g., in the case of an n-doped semiconductor body 10. In another embodiment, the substance can comprise at least one of phosphorus, antimony, and arsenic. For example, such a substance is used to create an n-doped semiconductor region 12a, 12b, e.g., in the case of a p-doped semiconductor body 10.

[0039] Furthermore, according to one embodiment, a sputtering process can be carried out before the substance 31 is applied in step 26. Such a sputtering process can be carried out to remove an oxide layer (not shown) present on section 111a, 111b, which formed after the formation of the trench 11a, 11b, or after a (in Fig. 1. A masking layer (not shown) has been formed. For example, the thickness of such an oxide layer can be less than 3 nm. Therefore, according to one embodiment, such a sputtering process can ensure that the substance 31 is applied directly to the surface of the trench 11a, 11b and can therefore support the subsequent diffusion step because the applied substance 31 does not have to pass through an oxide layer. Furthermore, if the sputtering process is carried out after the masking layer has been formed, the sputtering process can be carried out in such a way that the masking layer remains present on the semiconductor body 10 in a sufficient thickness, e.g., in regions that are not to be subjected to the application of the substance 31.

[0040] The following will explain in more detail exemplary procedures to prevent a remaining section of the trench surface from being subjected to the application of substance 31.

[0041] For example, one can, on the in Fig. Referring to the schematically illustrated process step 22, a masking layer 13 is formed on or at the trench surfaces formed by the side walls 113a, 113b and the trench bottoms 114a, 114b of the trenches 11a, 11b after the trenches 11a, 11b have been created (step 21). As in Fig. As shown in Figure 2, the surface 10-1 of the semiconductor body 10 can also be covered by the masking layer 13. The creation of the masking layer 13 (step 22) can include performing an oxidation processing step. Therefore, the masking layer 13 can be formed from an oxide such as silicon oxide.

[0042] Now on to the in Fig. Referring to the schematically illustrated process step 23, the trenches 11a, 11b can be filled with a trench fill material 32 after the masking layer 13 has been formed on the trench surfaces. Such a trench fill material 32 can comprise at least one made of carbon, an oxide, or another material that can be easily etched.

[0043] Furthermore, on the in Fig. 4 and Fig. Referring to the schematically illustrated process steps 24 and 25, a mask 4 can be formed which only partially covers the openings 115a, 115b of the trenches 11a, 11b. Step 24 of forming the mask 4 can include performing a trench lithography processing step, e.g., so that the trenches 11a, 11b are only partially opened. For example, the mask 4 covers at least 30% of the trench opening 115a. In another embodiment, the mask 4 can cover at least 50%, at least 70%, or at least 90% of the trench opening 115a. For example, the part of the mask 4 that partially covers the opening 115a of the trench 11a is supported by the trench fill material 32, which was filled into the trench 11a before the mask 4 was formed. Therefore, according to one embodiment, at least 10%, at least 20%, at least 30%, or at least 50% of the trench opening 115a is covered by the mask 4. The same can apply to trench 11b.

[0044] In a next step, 25 can be shown schematically in Fig. Figure 5 shows that both a portion of the trench fill material 32 not covered by the mask 4 and an adjacent portion of the masking layer 13 are removed. Such removal can include performing an etching process step, which may, for example, be an anisotropic etching process. This exposes sections 111a and 111b so that they can subsequently be subjected to the application (step 26) of the substance 31. As previously explained, a sputtering process can be performed before the application of the substance 31 to remove any remaining masking layer or oxidation layer. Furthermore, in one embodiment, only a portion of the trench bottom 114a and 114b is exposed during the removal step 25, so that ultimately only the exposed portion contributes to section 111a and 111b, which can be subjected to the application of the substance 31.For example, the exposed portion may not exceed 80%, 65%, or 60% of the total extent of the trench floor 114a, 114b along the first lateral direction X. Furthermore, the portion of the trench floor 114a, 114b may exceed 5%, 10%, or even 20% of the total extent of the trench floor 114a, 114b along the first lateral direction X.

[0045] As schematically in Fig. As shown in Figure 6, during the application (step 26) of substance 31, the remaining portion of the trench fill material 32 and / or the remaining portion of the masking layer 13 can cover the remaining section of the trench surface, e.g., at least one of the two trench side walls 113a, 113b. This causes the covered trench side wall (the left trench side wall 113a of trench 11a and the right trench side wall 113b of trench 11b) to be Fig. 6) not subjected to the application of substance 31.

[0046] For example, after the application (step 26) of the substance 31, both the remaining portion of the trench fill material 32 and the remaining masking layer 13 within the trenches 11a, 11b can be removed. Diffusion step 28 can then be carried out to generate the semiconductor regions 12a, 12b. In one embodiment, diffusion step 28 can be performed in an oxidizing atmosphere, e.g., to prevent the substance 31 from diffusing through the trench sidewalls 113a, 113b. Alternatively or additionally, an oxide can be deposited along the trench sidewalls 113a, 113b, e.g., at relatively low temperatures.

[0047] After the diffusion process, e.g., after the creation of the semiconductor regions 12a, 12b, the semiconductor device 1 can be further processed, such further processing being the formation of a control electrode (see control electrode 116a in Fig. 8) within the trench 11a, 11b. For example, such a control electrode can be a gate electrode separated from the semiconductor body 10 by a (in Fig. 1-7 (not shown) trench insulation material is insulated. Furthermore, further processing can include the creation of a semiconductor source region and a semiconductor body region adjacent to trench 11a, 11b, e.g., to form a MOS control head of a transistor cell. These aspects are discussed with reference to Fig. 8 explained in more detail.

[0048] Regarding all embodiments, the application (step 26) of substance 31, as described above, may include a plasma deposition processing step. For example, this plasma deposition processing step is implemented after a portion of the trench fill material 32 has been removed and section 111a, 111b of trench 11a, 11b has been exposed. Alternatively or additionally to the plasma deposition processing step, implantation, such as vertical implantation along the vertical direction Z and / or implantation at an angle, where the angle of an ion beam for the implantation at an angle may be less than 10°, may be carried out as described above.Vertical implantation can increase the dopant concentration in deeper parts of the semiconductor regions 12a, 12b, while tilt implantation can increase the dopant concentration in a region adjacent to a trench sidewall, e.g., in upper parts of the semiconductor regions 12a, 12b. A combination of tilt implantation, vertical implantation, and / or plasma deposition can enable the creation of different dopant concentration profiles along the vertical direction Z within the generated semiconductor region 12a, 12b. Examples of such dopant concentration profiles are described in more detail with reference to [reference missing]. Fig. 9 explained.

[0049] As in Fig. As shown in Figures 1 to 7, more than one trench can be created within the semiconductor body 10; for example, at least two trenches 11a, 11b are created, and of course, in step 21, many more than two trenches can be created within the semiconductor body 10. According to a Fig. In the schematically illustrated embodiment 4-7, the semiconductor regions 12a and 12b are generated within a mesa section 10-2 of the semiconductor body 10, which is laterally bounded by one of the two side walls 113a and one of the two side walls 113b. For example, the distance between the two side walls of the different grooves 11a, 11b, which face each other along the first lateral direction X, can be less than 10 µm, less than 5 µm, less than 2 µm, or even less than 1 µm. For this purpose, the mask 4 can be configured such that a section of the surface 10-1 above the mesa section 10-2 of the semiconductor body 10 also remains exposed, i.e., not covered by the mask 4. The step of removing the masking layer 13 can also include the removal - at least partially - of the masking layer 13 that was formed on the surface 10-1 above the mesa section 10-2.Subsequently, during the application (step 26) of substance 31, at least a corresponding portion of the surface 10-1 above the mesa section 10-2 can also be subjected to the application of substance 31, e.g., by plasma deposition, vertical implantation, or implantation at an angle and / or diffusion through a mask. Accordingly, during the diffusion step (step 28), substance 31 can also diffuse from the surface 10-1 above the mesa section 10-2 along the vertical direction Z into the semiconductor body 10, thereby creating a further, in . Fig. The semiconductor region 19 shown in Figure 7 is generated, wherein the further semiconductor region 19 and the generated semiconductor regions 12a and 12b can form a contiguous semiconductor region containing dopants of the second conductivity type. After the diffusion process, the dopant concentration in the contiguous semiconductor region 19, 12a, 12b can be further adjusted by surface implantation. For example, the semiconductor device 1 can be further processed after such a contiguous semiconductor region 19, 12a, 12b has been formed, with such further processing potentially including the formation of a MOS control head adjacent to the other trench sidewalls 113a and 113b, which are not adjacent to the contiguous semiconductor region 12a, 19, 12b. This aspect will now be explained in more detail.

[0050] Fig. Figure 8 represents a section of a vertical cross-section of a power semiconductor transistor 5 (hereinafter also referred to as "transistor"), which comprises a semiconductor body 10 and at least one transistor cell 50. For example, the transistor 5 has an IGBT or MOSFET structure. The transistor cell 50 comprises a semiconductor drift region 501, which contains dopants of a first conductivity type. For example, the semiconductor drift region is an n-doped semiconductor region. Furthermore, the transistor cell 50 comprises a semiconductor body region 502, which is enclosed in the semiconductor body 10 and contains dopants of a second conductivity type. For example, the semiconductor body region 502 is a p-type region. Furthermore, the transistor 50 comprises a source region 503, which can be a semiconductor source region 503, wherein the semiconductor body region 502 isolates the source region 503 from the semiconductor drift region 501.

[0051] The transistor cell 50 further comprises a trench 11a extending along the vertical direction Z into the semiconductor body 10 and containing a control electrode 116a that is electrically isolated from each of the semiconductor drift region 501, the semiconductor body region 502, and the source region 503. For this purpose, an insulator 117a can be included in the trench 11a to ensure this isolation. The control electrode 116a can be a gate electrode. Therefore, the transistor cell 50 can include a MOS control head having a gate-trough structure.

[0052] The power semiconductor transistor 5 can further comprise a first load terminal 51 and a second load terminal 52 coupled to the semiconductor body 10. For example, the transistor is configured to carry a load current between the first load terminal 51 and the second load terminal 52, the transistor 5 being controllable by a control signal provided to the control electrode 116a. For this purpose, the control electrode 116a can be electrically coupled to the control terminal 53. The control terminal 53 can be a gate terminal, the first load terminal 51 can be a source terminal, and the second load terminal 52 can be a drain terminal. Each of the source region 503 and the semiconductor body region 502 can be electrically connected to the first load terminal 51 by means of a first metallization 511.The second load terminal 52 can be electrically connected to the semiconductor body 10 by means of a second metallization 521. For example, the first metallization 511 is a front-side metallization of the transistor 5, and the second metallization 521 is a back-side metallization of the transistor 5. The transistor 5 can comprise a plurality of transistor cells 50.

[0053] The source region 503 and the semiconductor body region 502 can each be in physical contact with one of the two side walls 113a of the trench 11a, i.e., in physical contact with the insulator 117a, as shown schematically in Fig. 8 shown.

[0054] Adjacent to the other of the two trench side walls 113a, a semiconductor region 12a may be included, which contains dopants of the second conductivity type. For example, the semiconductor region 12a is a p-doped semiconductor region.

[0055] For example, the semiconductor region 12a of the power semiconductor transistor 5 was designed according to one or more embodiments of the above with reference to Fig. The procedure described in 1-7 produces 2.

[0056] For example, semiconductor region 12a is located adjacent to trench 11a, i.e., in physical contact with one of the trench sidewalls 113a and the trench floor 114a. Furthermore, semiconductor region 12a can be located separately from semiconductor body region 502. For example, semiconductor body region 502 and semiconductor region 12a are spatially isolated from each other by means of trench 11a and drift region 501. Likewise, as explained above, another semiconductor region 19 (not in Fig. 8 shown, cf. Fig. 7) be arranged laterally adjacent to semiconductor region 12a. What has been said above regarding the further semiconductor region 19 applies equally to the power semiconductor transistor 5.

[0057] Furthermore, the semiconductor region 12a can be a region without an electrical reference potential. For example, the semiconductor region 12a is not connected to any of the first load terminal 51, the second load terminal 52, the control terminal 53, or any other defined electrical potential.

[0058] According to one embodiment, the dopant concentration of the semiconductor region 12a adjacent to the trench side wall 113a assumes a value that, at any point along at least 60% of the total extent of the semiconductor region 12a in the vertical direction Z, is in a range of 50% to 150%, in a range of 70% to 130%, or even in a range of 90% to 110% of a fixed dopant concentration value. Such a substantially homogeneous dopant concentration distribution can even be present for more than 60% of the total extent in the vertical direction Z, for example, for more than 70%, 80%, 90%, or even more than 95%, such as more than 98% of the total extent of the semiconductor region 12a in the vertical direction Z. This type of homogeneous dopant concentration along the vertical direction Z is described in Fig. Figure 9, variant (A), schematically depicts the dopant concentration CC along the vertical direction Z. Therefore, the dopant concentration CC according to variant (A) does not deviate significantly from the fixed dopant concentration value CC1. Rather, it can be in the range of 90% to 110% of the fixed dopant concentration value CC1, and this range can even be smaller, such as 95% to 105% of the fixed dopant concentration value CC1, or even smaller, such as between 98% and 102% of the fixed dopant concentration value CC1. According to one embodiment, such a substantially homogeneous dopant concentration along the vertical direction Z can be achieved by means of an implantation with an inclination angle or by means of a plasma deposition step, as explained above with reference to process step 26.

[0059] According to a further embodiment, the dopant concentration CC of the semiconductor region 12a adjacent to the trench side wall 113a changes by at least 30% of a dopant concentration value present in an area that comprises at least 80% of the total extent of the semiconductor region 12a in the vertical direction Z. For example, dopant profiles exhibiting significant size changes along the vertical direction Z can be generated within the semiconductor region 12a by applying (step 26) the substance 31 by means of a combination of plasma deposition, tilted implantation and / or vertical implantation in the vertical direction Z and / or diffusion through a mask.

[0060] For example, the area which comprises at least 80% of the total extent of the semiconductor region 12a along the vertical direction Z can be divided into a first part 12a-1 and a second part 12a-2, as schematically shown in Fig. Figure 9 is shown. It is understood that the area can also be more than 85% of the total extent of the semiconductor region 12a along the vertical direction Z, more than 90%, more than 95% or even more than 99% of the total extent of the semiconductor region 12a along the vertical direction Z.

[0061] According to the in Fig. In the schematically represented variant 9(B), the change in dopant concentration in the region consists of an increase along the vertical direction Z. Therefore, the dopant concentration of the semiconductor region 12a within the first part 12a-1 and the second part 12a-2 can increase along the vertical direction Z, with the increase being at least 30% of the fixed dopant concentration value CC1. In other words, the dopant concentration CC in an upper section of the semiconductor region 12a can be CC1, and in a lower section of the semiconductor region 12a, the dopant concentration CC can be at least 1.3*CC1.

[0062] According to another embodiment, which in Fig. As schematically represented in Figure 9(C), the change in dopant concentration in the region can consist of a decrease along the vertical direction Z. Accordingly, the dopant concentration in an upper section of semiconductor region 12a can assume the value CC1, and in the lower section, the dopant concentration CC of semiconductor region 12a can be a maximum of 0.7*CC1.

[0063] According to yet another embodiment, the dopant concentration in the first part 12a-1 decreases along the vertical direction Z, and in the second part 12a-2, the dopant concentration increases along the vertical direction Z. This embodiment is shown schematically in Fig. 9 (D) is shown. For example, such a dopant profile can be obtained by both performing vertical implantation to apply the substance 31 essentially only to at least a section of the trench bottom 114a, and by subjecting the surface 10-1 of the semiconductor body 10 to surface implantation. Diffusion can then take place, resulting in a dopant concentration profile such as that shown in Fig. 9(D) schematically represented can provide.

[0064] As shown, the first part 12a-1 can be an upper part of the semiconductor region 12a, and the second part 12a-2 can be a lower part of the semiconductor region 12a. The decrease along the vertical direction Z in the first part 12a-1 can be at least 30% of an initial dopant concentration value present adjacent to the surface 10-1 of the semiconductor body 10. Furthermore, the increase along the vertical direction Z within the second part 12a-2 can also be at least 30% of a dopant concentration value present at a transition between the first part 12a-1 and the second part 12a-2.

[0065] According to all embodiments, the total extent of the semiconductor region 12a, 12b along the vertical direction Z can be in the range of 2 to 50 µm, 3 to 15 µm, or 4 to 10 µm. Instead of forming a region without an electrical reference potential, the semiconductor region 12a, 12b can also be connected to a fixed electrical potential, such as the electrical potential of the first load terminal 51 or the electrical potential of the gate terminal 53, to name a few. This allows a low voltage to be achieved between the semiconductor region 12a and the control electrode 116a, thereby reducing the electric field within the trench insulator 116a.

[0066] Features of further embodiments are defined in the dependent claims. The features of further embodiments and the features of the embodiments described above can be combined to form additional embodiments, provided that the features are not explicitly described as alternatives to each other.

[0067] The preceding section described embodiments relating to semiconductor wafers as well as methods and systems for processing a semiconductor wafer. For example, these semiconductor wafers are based on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g., semiconductor regions 10 and 12a to 12b, 503, 502 of exemplary embodiments, can be a monocrystalline Si region or Si layer. In other embodiments, polycrystalline or amorphous silicon can be used.

[0068] It is understood, however, that semiconductor regions 10 and 12a to 12b, 503, 502 can consist of any semiconductor material suitable for fabricating a semiconductor device. Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary, or quaternary III-V semiconductor materials such as... Examples include gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AllnN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGalnN) or indium gallium arsenide phosphide (InGaAsP), as well as binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few.The semiconductor materials mentioned above are also referred to as "homo-junction semiconductor materials." When two different semiconductor materials are combined, a hetero-junction semiconductor material is formed. Examples of hetero-junction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN) - aluminum gallium indium nitride (AlGalnN), indium gallium nitride (InGaN) - aluminum gallium indium nitride (AlGalnN), indium gallium nitride (InGaN) - gallium nitride (GaN), aluminum gallium nitride (AlGaN) - gallium nitride (GaN), indium gallium nitride (InGaN) - aluminum gallium nitride (AlGaN), silicon-silicon carbide (SixC1-x), and silicon-SiGe hetero-junction semiconductor materials. For power semiconductor device applications, Si, SiC, GaAs, and GaN materials are currently the most commonly used.

[0069] Spatial reference terms such as "under," "below," "lower," "above," "above," "upper," and similar terms are used for the sake of clarity to explain the positioning of one element relative to another. These terms are intended to encompass different orientations of the respective device in addition to the different orientations depicted in the figures. Furthermore, terms such as "first," "second," and similar terms are also used to describe different elements, regions, sections, etc., and are not intended to be restrictive. Throughout the description, identical terms refer to identical elements.

[0070] As used here, the terms "possessing," "containing," "encompassing," "having," and similar expressions, which indicate the presence of mentioned elements or characteristics, are open terms that do not exclude additional elements or characteristics. The articles "a / an" and "the" are intended to include both the plural and the singular unless the context clearly indicates otherwise.

Claims

[1] Method (2) for manufacturing a power semiconductor transistor (1), comprising: - Providing (20) a semiconductor body (10) which has dopants of a first conductivity type; - Forming (21) a trench (11a) extending along a vertical direction (Z) into the semiconductor body (10), wherein the trench (11a) is bounded in a horizontal direction by two trench sidewalls (113a) and vertically by a trench bottom (114a); - Applying (26) a substance (31) to at least one section (111a) of a trench surface formed by one of the trench side walls (113a) and / or the trench floor (114a) of the trench (11a), wherein the application (26) of the substance (31) comprises preventing the substance from being applied to the other of the trench side walls (113a); and - Diffusion (28) of the applied substance (31) from the section (111a) into the semiconductor body (10), thereby generating a semiconductor region (12a) in the semiconductor body (10) which has dopants of a second conductivity type and is located adjacent to the section (111a), wherein the generated semiconductor region (12a) is located adjacent to exactly one of the two trench side walls (113a); - wherein a transition between the trench (11a) and the generated semiconductor region (12a) extends continuously along exactly one of the trench side walls (113a) to the trench floor (114a). [2] Method (2) according to claim 1, wherein the application (26) of the substance (31) comprises at least one of a plasma deposition, an implantation with an angle of inclination and an implantation along substantially only the vertical direction (Z). [3] Method (2) according to claim 1, wherein the substance (31) is gaseous and the application (26) of the substance (31) comprises diffusion through a mask. [4] Method (2) according to any of the preceding claims, which further comprises carrying out a sputtering process prior to the application (26) of the substance (31) in order to remove an oxide layer present on the section (111a) which has formed after the formation (21) of the trench (11a). [5] Method (2) according to any one of the preceding claims, wherein the substance (31) comprises at least one of boron, aluminium and gallium. [6] Method (2) according to any one of the preceding claims 1 to 5, wherein the substance (31) comprises at least one of phosphorus, antimony and arsenic. [7] Method (2) according to any of the preceding claims, wherein the semiconductor body (10) is provided as part of a semiconductor wafer which has a diameter of at least 200 mm. [8] Method (2) according to any of the preceding claims, further comprising: - Implanting dopants of the second conductivity type into the semiconductor body (10) by performing surface implantation. [9] Method (2) according to any of the preceding claims, which further comprises the following before the application (26) of the substance (31): - Creating (22) a masking layer (13) on the trench surface (113a, 114a); - Filling (23) the trench (11a) with a trench fill material (32); - Forming (24) a mask (4) which only partially covers an opening (115a) of the trench (11a); - Removing (25) both a portion of the trench fill material (32) that is not covered by the mask (4) and a portion of the masking layer (13) adjacent to that portion, in order to expose only the section (111a) of the trench surface (113a, 114a) that will be subjected to the subsequent application (26) of the substance (31). [10] Method (2) according to claim 9, which, after the application (26) of the substance (31), further comprises: - Removal (27) of both the remaining portion of the trench fill material (32) and the remaining masking layer (13) within the trench (11a), wherein the diffusion step (28) is carried out after the removal step (27). [11] Method (2) according to any of the preceding claims, further comprising: - Forming a control electrode (116a) inside the trench (11a). [12] Method (2) according to any of the preceding claims, wherein the step (26) of applying the substance (31) and the step of diffusing (28) the applied substance (31) are carried out such that a dopant concentration (CC) of the generated semiconductor region (12a) adjacent to the trench side wall (113a) assumes a value which at every point along is at least 60% of the total extent of the semiconductor region (12a) in the vertical direction (Z) within a range of 50% to 150% of a fixed dopant concentration value (CC1). [13] Method (2) according to any one of the preceding claims 1 to 11, wherein the step (26) of applying the substance (31) and the step of diffusing (28) the applied substance (31) are carried out such that a dopant concentration (CC) of the semiconductor region (12a) adjacent to the trench side wall (113a) in an area (12a-1, 12a-2) which is at least 80% of the total extent of the semiconductor region (12a) in the vertical direction (Z) changes by at least 30% of a dopant concentration value (CC1) that is present in the area (12a-1, 12a-2). [14] Power semiconductor transistor (5) comprising a semiconductor body (10) and at least one transistor cell (50), wherein the at least one transistor cell (50) has the following: - a semiconductor drift region (501) which is enclosed in the semiconductor body (10) and contains dopants of a first conductivity type; - a semiconductor body region (502) which is enclosed in the semiconductor body (10) and has dopants of a second conductivity type; - a source region (503), wherein the semiconductor body region (502) isolates the source region (503) from the semiconductor drift region (501); - a trench (11a) extending along a vertical direction (Z) into the semiconductor body (10) and comprising a control electrode (116a) which is electrically isolated from each of the semiconductor drift region (501), the semiconductor body region (502) and the source region (503); and - a semiconductor region (12a) which contains dopants of the second conductivity type and is adjacent to the trench (11a) and separated from the semiconductor body region (502), wherein a transition between the trench (11a) and the semiconductor region (12a) extends continuously along exactly one trench side wall (113a) of the trench (11a) to the trench bottom (114a) of the trench (11a), and wherein a dopant concentration (CC) of the semiconductor region (12a) adjacent to the trench side wall (113a) assumes a value which at every point along is at least 60% of the total extent of the semiconductor region (12a) in the vertical direction (Z) within a range of 50% to 150% of a fixed dopant concentration value (CC1).

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