Output drivers with a multitude of drivers and corresponding procedures

Abstract

A method comprising: in response to the voltage level of an input signal meeting an input voltage threshold, activating a first driver of a plurality of drivers configured to jointly generate an output signal; and in response to the voltage level of the input signal meeting the input voltage threshold and a voltage level of the output signal meeting an output voltage threshold, switching the activation of a second driver of the plurality of drivers, the second driver being configured to switch more current than the first driver when activated, and the first driver having a faster slew rate than the second driver; further comprising: determining that the voltage level of the output signal meets the output voltage threshold when the voltage level of the output signal is greater than the output voltage threshold.and wherein switching the activation of the second driver of the plurality of drivers comprises activating the second driver, wherein the output voltage threshold is a first output voltage threshold, wherein the method further comprises: activating the second driver in response to the input signal voltage level meeting the input voltage threshold and the output signal voltage level being less than a second output voltage threshold; and deactivating the second driver in response to the output signal voltage level being between the first output voltage threshold and the second output voltage threshold.

Description

TECHNICAL FIELDThe present application relates to output drivers that can be used for data communication on a CAN bus (CAN=controller area network) or other applications.BACKGROUNDOutput drivers can be used in a wide variety of systems. As an example, electrical drivers may be used to communicate data over wired interfaces. When transmitting data over a wired interface, signal integrity may be a problem. For example, the electrical characteristics of the interconnects and / or packaging may interfere with the signaling voltages and currents and affect the output driver performance. In some examples, slew rate control of the output driver may be used to address such signal integrity issues.For example, with reasonable slew rate control of the output signal generated by an output driver, signal integrity problems resulting from switching noise (dI / dt), transmission line effects, and electromagnetic interference (EMI) (dV / dt) may be reduced.US 6 031 389 A discloses an output driver comprising a plurality of drivers, first a first driver and then a second driver being activated.It is therefore an object to provide possibilities for being able to achieve a fast rise speed even if higher currents are required overall.BRIEF DESCRIPTIONThere is provided a method according to claim 1, an output driver according to claim 5 and an output driver according to claim 9.In general, the present application is directed to methods for combining multiple drivers having different characteristics into an output driver. For example, a first driver having a desired slew rate may be combined with a second driver having desired DC characteristics to form an output driver having both a desirable slew rate and desirable DC characteristics.In one example, a method comprises, in response to a voltage level of an input signal satisfying an input voltage threshold, activating a first driver of a plurality of drivers configured to jointly generate an output signal. In this example, the method also includes, responsive to the voltage level of the input signal satisfying the input voltage threshold and a voltage level of the output signal satisfying an output voltage threshold, switching activation (e.g., switching from a deactivated state to an activated state or switching from an activated state to a deactivated state) of a second driver of the plurality of drivers, wherein the second driver is configured to switch more current (e.g., drive or output more current) than the first driver when activated, and wherein the first driver has a faster slew rate ("slew rate") than the second driver.The method further comprises:Determining that the voltage level of the output signal satisfies the output voltage threshold when the voltage level of the output signal is greater than the output voltage threshold, and wherein switching activation of the second driver of the plurality of drivers comprises activating the second driver, wherein the output voltage threshold is a first output voltage threshold, the method further comprising:responsive to the voltage level of the input signal satisfying the input voltage threshold and the voltage level of the output signal being less than a second output voltage threshold, activating the second driver; andresponsive to the voltage level of the output signal being between the first output voltage threshold and the second output voltage threshold, disabling the second driver.A signal satisfying a threshold may mean that the signal has a predetermined relationship (e.g., greater than, greater than or equal to, less than, less than, or equal to, equal to) to the threshold. If the signal has the respectively predefined relation, a specific event, e.g. activation or deactivation of a driver, can then occur.In another example, an output driver includes a plurality of drivers configured to collectively generate an output signal. In this example, a first driver of the plurality of drivers is configured to be activated in response to a voltage level of an input signal satisfying an input voltage threshold, and a second driver of the plurality of drivers is configured to switch its activation in response to the voltage level of the input signal satisfying the input voltage threshold and a voltage level of the output signal satisfying an output voltage threshold. In this example, the second driver is configured to switch more current when driven than the first driver, and the first driver has a faster slew rate than the second driver.In another example, an output driver comprises a plurality of means for generating an output signal together and control means for controlling the means for generating the output signal together. In this example, the control means may be arranged to: activate a first means of the plurality of means for generating the output signal jointly in response to a voltage level of an input signal satisfying an input voltage threshold value; and switch the activation of a second means of the plurality of means for generating the output signal jointly in response to the voltage level of the input signal satisfying the input voltage threshold value and a voltage level of the output signal satisfying an output voltage threshold value. In this example, the second means is arranged to switch more current than the first means when activated and the first means has a faster slew rate than the second means.Details of these and other examples are set forth in the accompanying drawings and the description below. Other features, objects and advantages will be apparent from the description and drawings, and from the claims.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a conceptual diagram of an example output driver according to some or more methods of the present application. FIG. 2 is a schematic and conceptual diagram of further details of drivers included in the output driver of FIG. 1, according to one or more examples of the present application. FIG. 3 is a schematic and conceptual diagram of further details of feedback logic included in the output driver of FIG. 1, in accordance with one or more examples of the present application. FIG. 4 is a graphical representation of exemplary signals that may correspond to signals in an output driver, in accordance with one or more techniques of the present application. FIG. 5 is a flowchart illustration of example operations of an example battery powered engine system according to one or more techniques of the present application.DETAILED DESCRIPTIONAs discussed above, slew rate control may be used to reduce signal integrity issues of the output signal generated by an output driver. However, in some examples, it may not be desirable to implement an output driver with a decreased slew rate, e.g., due to the resulting impact on the other electrical characteristics of the output signal. As an example, an increase in the propagation delay of the output driver may occur when an output driver is slowly turned on. This is because the propagation delay is an accumulated delay of the internal signal delay from the input to the gate of the driver and the rate at which the output signal rises / falls as driven by the driver.Propagation delay may be defined as the elapsed time between a time when the input level of the driver crosses an input threshold (e.g., 50%) to a time when the output level of the driver crosses an output threshold (e.g., 50%). The input threshold and the output threshold may be selected based on, e.g., a communication standard and / or application of the driver. In this regard, it is desirable that an output driver meet one or more EMI requirements (e.g., by very slow slew rates of the output signal) without significantly increasing the propagation delay (e.g., minimizing the effect of the slow slew rates on the delay contribution of the output signal slew / droop).As an example, the slew rate of an output driver may be controlled by adding a (multiple) series resistor to the driver. For example, where an output driver comprises one or more metal oxide semiconductor (MOS) transistors, which may have enormous variation over process, voltage, and temperature (PVT), a resistor may be added to the path of the output driver. Because the resistor has less variation over PVT states, inserting the resistor into the path may help control the slew rate of the output signal (e.g., as adding a series resistor to a MOS transistor shifts the MOS transistor into a linear operating region, thereby reducing overall slew rate propagation).However, in some examples, it may not be desirable to add a resistor to the driver. For example, while adding a resistor to a driver may provide desirable slew rate control, this technique may not help meet the delay requirements because the behavior of the driver is linearized. In addition, it may not be desirable to add a resistor, as the resulting size of the MOS transistor required to meet the DC requirements of the pad may be large, resulting in undesirable area utilization.As another example, the slew rate of an output driver may be controlled by utilizing a staggered driver. For example, the output driver transistor may be finger-shaped and separately controlled. In operation, the gates of the finger-type driver may be slowly activated to reduce the dv / dt of the output signal.However, in some examples, it may not be desirable to use a staggered driver. For example, when the output driver gate is slowly turned on, the contribution of propagation delay from the driver increases in the same ratio, increasing the difficulty in meeting the delay requirement while maintaining the slow slew rate. While it may be possible to optimize the delay achieved by controlling the ratio of the driver fingers that can be turned on, this method still has some limitations on what results can be achieved. In addition, by using such a staggered driver, the amount and area of pre-driver logic required to perform gate control for driver fingers is increased.As another example, the slew rate of an output driver may be controlled by adding a Miller capacitance (e.g., a capacitance between the gate and the drain of the output driver). The gate of the output driver may be controlled such that the slew rate is based on the rate of change of voltage across the load capacitance.However, in some examples, it may not be desirable to use Miller capacitance. For example, using a Miller capacitance could not be very effective for addressing PVT deviations. In addition, Miller capacitance could also slow the output driver down so that satisfying delay requirements could be more difficult. Furthermore, there could also be an area penalty because the amount of Miller capacitance required to control slew rate could be large.As another example, the slew rate of an output driver may be controlled by controlling the gate of the output driver (similar to the Miller capacitance approach). In some examples, the gate of the output driver may be controlled based on feedback from the pad to which the driver outputs the output signal. For example, the output signal may be detected and used to control the gates of the output driver. The feedback from the pad could be used to turn on some gate fingers or could be used to control the pre-driver. While using feedback from the pad may address the slew rate problem, it may also cause difficulties to meet the delay requirement.In some examples, the gate of the output driver may be controlled by using a current controlled pre-driver. For example, the pre-driver may be controlled with a band gap supplied current or by any other current source circuit such that the current is substantially constant across different PVT states. Since the current would be a constant current across PVT states, the speed at which the gate of the output driver is charged may also be constant, which may help the driver achieve a regulated slew rate across PVT. However, in some examples, it may not be desirable to use a current controlled pre-driver to control the gate of the output driver (e.g., when the load is variable). In addition, when the gate of the output driver is loaded at constant speed, the delay problem is not addressed by using a current controlled pre-driver. Furthermore, this technique could provide static power consumption that may be undesirable.According to one or more techniques of the present application, a variety of the above techniques may be combined to produce an output driver with desirable slew rate control for various PVT states, desirable propagation delay, and desirable DC characteristics. For example, a first driver that uses additional resistance may be combined with a second driver that uses feedback from the pad to form an output driver that has desirable slew rate, delay, and DC characteristics.FIG. 1 is a conceptual diagram illustration of an example output driver 2 in accordance with one or more techniques of the present application. Output driver 2 may be configured to generate an output signal in response to receiving an input signal. For example, in response to receiving an input signal at input 12, output driver 2 may generate an output signal at output 14. In some examples, output driver 2 may be included in an integrated circuit, such as an integrated circuit used to communicate data over a wired interface. As shown in the example of FIG. 1, output driver 2 may include driver 6, feedback logic 8, and driver 10.In some examples, the output driver 2 may include driver 6, which may be configured to generate an output signal based on a control signal. For example, driver 6 may use the input signal received at input 12 as a control signal and generate an output signal for output at output 14 in response to determining that a voltage level of the input signal corresponds to an input voltage threshold.In some examples, output driver 2 may include feedback logic 8, which may be configured to generate a control signal based on one or more signals such as the input signal and output signal of output driver 2. For example, feedback logic 8 may be configured to activate driver 10 in response to determining that both the voltage level of the input signal corresponds to the input voltage threshold and that a voltage level of the output signal corresponds to an output voltage level.In some examples, output driver 2 may include driver 10, which may be configured to generate an output signal based on a control signal. For example, driver 10 may generate an output signal for output at output 14 in response to receiving a control signal from feedback logic 8.In some examples, driver 10 may have different characteristics than driver 6. As one example, driver 10 may be configured to switch a larger amount of current than driver 6. As another example, driver 10 may be sized differently than driver 6.As discussed above, in response to receiving an input signal at input 12, output driver 2 may generate an output signal at output 14. In some examples, output driver 2 may be configured to generate an output signal in compliance with one or more requirements such as one or more of a slew rate requirement, a time delay requirement, and one or more DC requirements.According to one or more techniques of the present application, driver 6 and driver 10 may collectively generate the output signal at output 14 in compliance with one or more of the requirements. For example, driver 6 may be used to meet a slew rate requirement and may be controlled based on the input signal and driver 10 may be used to meet one or more DC requirements and may be controlled based on both the input signal and the output signal.In operation, driver 6 and feedback logic 8 may receive the input signal via input 12. In response to determining that a voltage level of the input signal corresponds to an input voltage threshold, driver 6 may operate and begin generating the output signal. In some examples, the input signal may be a binary signal and driver 6 may determine that the voltage level of the input signal corresponds to the threshold when the binary signal switches (i.e., switches from "0" to "1" and vice versa).In either case, feedback logic 8 may selectively activate driver 10 based on both the output signal and the input signal. For example, feedback logic 8 may switch activation of driver 10 in response to determining that both the voltage level of the input signal satisfies the input voltage threshold and a voltage level of the output signal satisfies one or more output voltage thresholds.As an example, the feedback logic 8 may activate the driver 10 where the voltage level of the output signal is greater than a first output voltage threshold (e.g., 80% of the desired level). In other words, driver 6 may generate the output signal until the voltage level of the output signal crosses the first output voltage threshold, at which point driver 6 and driver 10 may together generate the output signal until the input signal no longer meets the input voltage threshold. In this manner, driver 6 may be used to meet a slew rate requirement, driver 10 may be used to meet one or more DC requirements, while the combination of driver 6 and driver 8 may be used to meet a time delay requirement.As another example, feedback logic 8 may activate driver 10 where the voltage level of the output signal is less than a second output voltage threshold (e.g., 20% of the desired level). In other words, driver 6 and driver 10 may together generate the output signal until the voltage level of the output signal crosses the second output voltage threshold, at which point driver 10 may disable and driver 6 may generate the output signal until the input signal no longer meets the input voltage threshold. In this manner, driver 6 may be used to meet a slew rate requirement, driver 10 may be used to meet one or more DC requirements, while the combination of driver 6 and driver 8 may be used to meet a time delay requirement.As yet another example, the feedback logic 8 may activate the driver 10 where the voltage level of the output signal is greater than the first output voltage threshold and where the voltage level of the output signal is less than a second output voltage threshold. In other words, driver 6 and driver 10 may collectively generate the output signal until the voltage level of the output signal crosses the second output voltage threshold, at which point driver 10 may deactivate and driver 6 may generate the output signal until the voltage level of the output signal crosses the first output voltage threshold, where driver 6 and driver 10 may again collectively generate the output signal until the input signal no longer meets the input voltage threshold. In this manner, driver 6 may be used to meet a slew rate requirement, driver 10 may be used to meet one or more DC requirements, while the combination of driver 6 and driver 10 may be used to meet a propagation delay requirement.FIG. 2 is a schematic and conceptual diagram representation of further details of drivers included in the output driver of FIG. 1, in accordance with one or more examples of the present application. As shown in FIG. 2, output driver 2A may include pre-driver 4, driver 6, feedback logics 8A / 8B, and driver 10.In some examples, output driver 2A may include pre-driver 4 that may be configured to receive an input signal, perform one or more operations to manipulate the input signal, and output the manipulated signal to one or more components of output driver 2A. For example, pre-driver 4 may perform level shifting to convert a voltage range of the input signal to a voltage range of one or more transistors of driver 6 and / or driver 10. In addition to processing the input signal, pre-driver 4 may be configured to generate one or more control signals 32A- 32B (collectively "control signals 32") based on the input signal. For example, in response to determining that the voltage level of the input signal transitions from low to high, pre-driver 4 may output one or more of control signals 32 to cause one or more drivers to activate (one or more pull-down drivers where output driver 2A inverts or one or more pull-up drivers where output driver 2A does not invert). Similarly, in response to determining that the voltage level of the input signal transitions from high to low, pre-driver 4 may output one or more of control signals 32 to cause one or more drivers to activate (one or more pull-down drivers where driver 2A does not invert or one or more pull-up drivers where output driver 2A inverts).In some examples, output driver 2A may include driver 6A, which may be configured to perform operations similar to driver 6 of FIG. 1. For example, driver 6A may be configured to generate an output signal based on a control signal. In some examples, driver 6A may generate the output signal using a push configuration, a pull configuration, and / or a push-pull configuration. As shown in FIG. 2, driver 6A is a push-pull configuration that includes driver 20 and resistor 22 configured to pull up the voltage level of the output signal at output 14 (e.g., to VDD) along with resistor 24 and driver 26 configured to pull down the voltage level of the output signal at output 14 (e.g., to ground). As discussed above, including resistor 22 and resistor 24 in the paths of driver 20 and driver 26, respectively, may control the slew rates of driver 22 and driver 26 such that driver 20 and driver 26 operate in a linear region.While shown in FIG. 2 as a PMOS transistor and an NMOS transistor, drivers 20 and driver 26, respectively, may be any device capable of switching electric current. For example, driver 20 and / or 26 may include one or more PMOS transistors, one or more NMOS transistors, one or more junction bipolar transistors, and the like. Pre-driver 4 may be configured such that output driver 2A performs the same operation regardless of the type of switching devices included in driver 20 and driver 26.In some examples, output driver 2A may include driver 10A, which may be configured to perform operations similar to driver 10 of FIG. 1. For example, driver 10A may be configured to generate an output signal based on a control signal. In some examples, driver 10A may generate the output signal using a push configuration, a pull configuration, and / or a push-pull configuration. As shown in FIG. 2, driver 10A has a push-pull configuration that includes PMOS drivers 28 configured to pull up the voltage level of the output signal at output 14 (e.g., to VDD) along with NMOS driver 30 configured to pull down the voltage level of the output signal at output 14 (e.g., to ground).While shown as a PMOS transistor and an NMOS transistor, respectively, in FIG. 2, driver 28 and driver 28 may be any device capable of switching electric current. For example, driver 28 and / or 28 may include one or more PMOS transistors, one or more NMOS transistors, one or more junction bipolar transistors, and the like. Feedback logics 8A- 8B may be configured such that output driver 2A performs the same operation regardless of the type of switching devices included in driver 28 and driver 26.In some examples, output driver 2A may include feedback logics 8A- 8B that may be configured to perform operations similar to feedback logic 8 of FIG. 1. For example, each of the feedback logics 8A- 8B may be configured to generate a control signal based on one or more signals such as the output signal at the output 14 and one or more of control signals 32. As an example, feedback logic 8A may generate control signal 34A based on control signal 32A and the output signal. As another example, feedback logic 8B may generate control signal 34B based on control signal 32B and the output signal.According to one or more techniques of the present application, driver 6A and driver 10A may collectively generate the output signal at output 14 according to one or more design requirements. In the following example, output driver 2A is described as a noninverting driver where the voltage level of the output signal at output 14 may be pulled high when the input signal corresponds to a logic high (e.g., "1") level and pulled low when the input signal corresponds to a logic low (e.g., "0") level. However, the methods of the present application are equally applicable when the output driver 2A is in an inverting configuration where the voltage level of the output signal at the output 14 may be pulled high when the input signal is at a logic low (e.g., "0") level and pulled low when the input signal is at a logic high (e.g., "1") level.In operation, the voltage level of the input signal at input 12 may initially be high and output driver 2A may pull up the voltage level of the output signal at output 14. For example, one or both of the drivers 20 and driver 28 may pull pre-drivers 4, may pull the voltage level of the output signal at output 14 up to VDD (i.e., in response to control signal 32A and / or control signal 34A).In any event, when the voltage level of the input signal transitions from high to low, output driver 2A may pull down the voltage level of the output signal at output 14. For example, in response to determining that the voltage level of the input signal is less than an input voltage threshold, pre-driver 4 may output control signal 32B to driver 26 and feedback logic 8B. In response to receiving the control signal 32B, driver 26 may activate and begin to pull down the voltage level of the output signal and feedback logic 8B may determine whether to activate driver 30 (e.g., whether it should output the output control signal 34B). For example, feedback logic 8B may activate driver 30 in response to determining that a voltage level of the output signal is greater than a first output voltage threshold. In other words, in response to receiving the control signal 32B (i.e., determining that both voltage levels of the input signal meet the input voltage threshold) and determining that the voltage level of the output signal meet an output voltage threshold, feedback logic 8B may output control signal 34B such that driver 30 activates and reduces the voltage level of the output signal.As the voltage level of the output signal is pulled down, feedback logic 8B may further determine whether the voltage level of the output signal corresponds to the first output voltage threshold. In response to determining that the voltage level of the output signal no longer corresponds to (i.e., is less than) the first output voltage threshold, the feedback logic 8B may disable the driver 30, such as ceasing to output the control signal 34B, such that the driver 30 stops pulling down the voltage level of the output signal. However, since the driver 26 remains driven, the voltage level of the output signal can still be pulled down.As the voltage level of the output signal continues to decrease, feedback logic 8B may determine whether the voltage level of the output signal satisfies (i.e., is less than) a second output voltage threshold. In response to determining that the voltage level of the output signal is less than the second output voltage threshold, feedback logic 8B may activate drivers 30, such as output control signal 34B, such that driver 30 begins to pull down the voltage level of the output signal. However, while the driver 26 remains driven, the voltage level of the output signal may continue to be pulled down. In other words, driver 26 may be driven during a period of time during which the voltage level of the input signal is less than the input signal threshold and driver 30 may be driven during one or both of (1) a period of time during which the voltage level of the input signal is less than the input signal threshold and the voltage level of the output signal is greater than a first output voltage threshold and (2) a period of time during which the voltage level of the input signal is less than the input signal threshold and the voltage level of the output signal is less than a second output voltage threshold. In this manner, driver 26 and driver 30 may collectively generate the output signal according to the one or more design requirements.In some examples, driver 20 and driver 28 may perform operations similar to driver 26 and driver 30 when the voltage level of the input signal transitions from low to high. For example, driver 20 may be driven during a period of time during which the voltage level of the input signal is greater than the input signal threshold and driver 28 may be driven during one or both of (1) a period of time during which the voltage level of the input signal is greater than the input signal threshold and the voltage level of the output signal is less than a third output voltage threshold and (2) a period of time during which the voltage level of the input signal is greater than the input signal threshold and the voltage level of the output signal is greater than a fourth output voltage threshold. In some examples, the third output voltage threshold and the fourth output voltage threshold may mirror the first output voltage threshold and the second output voltage threshold, respectively. For example, where the first output voltage threshold is 20% of the steady-state pulled-down voltage of the output signal, the third output voltage threshold may be 20% of the steady-state pulled-up voltage of the output signal. In this manner, driver 20 and driver 28 may collectively generate the output signal according to the one or more design requirements.FIG. 3 is a schematic and conceptual diagram representation of further details of feedback logic included in the output driver of FIG. 1, in accordance with one or more examples of the present application. As shown in FIG. 3, output driver 2B may include driver 6, feedback logic 8, and driver 10.In some examples, output driver 2B may include driver 6B, which may be configured to perform operations similar to driver 6 of FIG. 1 and / or driver 6A of FIG. 2. For example, driver 6B may be configured to generate an output signal based on a control signal. As shown in FIG. 3, driver 6B may generate the output signal based on the input signal received at input 12.In some examples, output driver 2B may include driver 10B, which may be configured to perform operations similar to driver 6 of FIG. 1 and / or driver 10A of FIG. 2. For example, driver 10B may be configured to generate an output signal based on a control signal. As shown in FIG. 3, driver 10B may generate the output signal based on a control signal generated by feedback logic 9.In some examples, output driver 2B may include feedback logic 9, which may be configured to perform operations similar to feedback logic 8 of FIG. 1 and / or feedback logic 8A- 8B of FIG. 2. For example, feedback logic 9 may be configured to generate a control signal based on one or more signals such as the output signal at output 14 and one or more of control signals 32. As an example, feedback logic 9 may generate control signal 35 based on the input signal and the output signal. As shown in FIG. 3, feedback logic 9 may include comparators 38A-38B (collectively "comparator 38"), OR gate 40, and AND gate 42.In some examples, feedback logic 9 may include one or more comparators 38 that may generate a control signal indicating whether or not a voltage level of an input signal meets a voltage threshold. As an example, comparator 38A may output control signal 39A indicating whether the voltage level of the output signal corresponds to a first voltage threshold. As another example, comparator 38B may output control signal 39B indicating whether the voltage level of the output signal corresponds to a second voltage threshold.In some examples, one or both of comparators 39 may be an inverter with a shifted switching threshold voltage. For example, unlike having a 50% switching threshold, one or both of comparators 39 may be an inverter having a switching threshold that is either >50% or <50%. As an example, comparator 38A may have a very low / very high signal rise / fall switching threshold. As another example, comparator 38B may have a very high / very low signal rise / fall switching threshold.Therefore, where the voltage level of the output signal begins to rise / fall, comparator 38A (i.e., with a very low switching threshold (<50%%)) may detect the signal state and switch the logic level of control signal 39A when the voltage level of the output signal reaches the first threshold voltage (e.g., 20% of its final signal level). This switching of the logic level of the control signal 39A may cause the driver 10B to be disabled.Thus, after the first threshold of signal rise / fall, driver 6B may be driven while driver 10B is inactive. Meanwhile, comparator 38B (i.e., with very high / low signal rise / fall switching threshold) cannot toggle the logic level of control signal 39B because the voltage level of the output signal has not yet matched a second threshold (e.g., 80% of its final signal level).Therefore, from the first threshold to the second threshold, the output signal inclination is determined mainly by driver 6B. As discussed above, driver 6B may be configured with linear behavior. Since the behavior is linear, the slew rate can be controlled over this entire range of the output signal for various process, voltage, and temperature (PVT) conditions.Once the output signal reaches the second threshold of its level, comparator 38B may detect the change of state and toggle the logic level of control signal 39B when the voltage level of the output signal reaches the second threshold voltage (e.g., 80% of its final signal level). By switching the control signal 39B, the comparator 38B may cause re-driving of the driver 10B after the second signal rise / fall threshold. In this manner, output driver 2B may meet one or more of the DC output / pad requirements.Thus, initially, because driver 10B is enabled (e.g., instantaneous and complete), this may assist in charging the load capacitance and thus meet one or more initial delay requirements. Thereafter, when driver 10B is disabled, the slew rate of the output signal is controlled by driver 6B. Finally, driver 10B is reactivated towards the end of the signal rise / fall (after reaching 80% of the signaling level) to meet one or more DC output / pad requirements.In some examples, the switching thresholds used by comparator 38 may be selected and / or set based on one or more delay requirements. The size of driver 6B and the value of a resistance included in driver 6B (i.e., as discussed above) may also be designed based on the increase requirement, e.g., without any effect on either the delay or the DC strength of the output driver. In this manner, driver 6B and driver 10B can collectively achieve both the slew rate and delay requirements of the output driver in parallel and not at the expense of each other.Additional advantages of an output driver that includes two drivers with different characteristics (i.e., driver 6 and driver 10) are not limited to the lack of area increase because the current strength of the output driver is used as determined from the DC requirement. Similarly, since there is no static power consumption, the cost and area of any slew rate control logic can be reduced.FIG. 4 is a graphical representation of example signals that may correspond to signals in an output driver, in accordance with one or more techniques of the present application. As shown in FIG. 4, graph 400 may include a time-representative horizontal axis, a voltage-representative vertical axis, and a plurality of signals 402- 412. For purposes of illustration, signals 402-412 are described in connection with output driver 2B of FIG. 3, although output drivers of configurations other than output driver 2B may generate the signals of FIG. 4.In some examples, input signal 402 may be an example of the input signal received by output driver 2B at input 12, output signal 404 may be an example of the output signal generated by output driver 2B at output 14, VLS 406 may be an example of a control signal 39B generated by comparator 38B, VHS 408 may be an example of a control signal 39A generated by comparator 38A, VS 410 may be an example of a control signal 41 generated by OR gate 40, and VG 412 may be an example of a control signal 35 generated by AND gate 42. As such, VS 410 may be an "OR" of VLS 406 and VHS 408 and VG may be an "AND" of VS 410 and input signal 402.According to one or more techniques of the present application, output driver 2B may receive input signal 402 at input 12 and generate output signal 404 at output 14. As illustrated by graph 400, output driver 2B may be non-inverting such that while the voltage level of input signal 402 is low, the voltage level of output signal 404 is low, and vice versa. As discussed above, driver 6B may be directly controlled by input signal 402, such that when input signal 402 is a logic high (e.g., "1"), driver 6B may begin to pull up the voltage level using output signal 404, and vice versa.As discussed above, OR gate 40 may output VS 410 as a logic high where one or both of VLS 408 or VHS 410 are logic high. As illustrated by graph 400, comparator 38B may output VLS 406 as a logic high where the voltage level of output signal 404 is less than first output threshold 414 and comparator 38A may output VHS 408 as a logic high where the voltage level of output signal 404 is greater than second output threshold 416. As such, VS 410 may be a logic high when the voltage level of output signal 404 is less than first output threshold 414 and when the voltage level of output signal 404 is greater than second output threshold 416. Because driver 10B is controlled by VG 412, driver 10B may be driven when VG 412 is a logic high.FIG. 5 is a flowchart illustration of example operations of an example battery powered engine system according to one or more techniques of the present application. The exemplary operations are described below for illustrative purposes only in connection with output driver 2B of FIG. 3, although output drivers having configurations other than output driver 2B may generate the signals of FIG. 4.According to one or more techniques of the present application, output driver 2B may determine whether the voltage level of an input signal corresponded to an input voltage threshold (502). For example, output driver 2B may determine whether the voltage level of the input signal received at input 14 is greater than 50% of its logic high level. In response to determining that the voltage level of the input signal does not meet the input voltage threshold (at branch "no" of 502), output driver 2B may continue to monitor the voltage level of the input signal to determine whether the voltage level of the input signal meets the input voltage threshold (502).In response to determining that the voltage level of the input signal satisfies the input voltage threshold (branch "Yes" of 502), output driver 2B may activate a first driver of a plurality of drivers configured to jointly generate an output signal ( 504). For example, output driver 2B may enable driver 6B that may pull up / pull down the voltage level of the output signal depending on whether output driver 2B may be inverted or not inverted. In addition to enabling the first driver, output driver 2B may determine whether the voltage level of the output signal corresponds to a first output voltage threshold ( 506). For example, feedback logic 9 may determine whether the voltage level of the output signal is less than, e.g., 20% of the level of its logic high.In response to determining that the voltage level of the output signal corresponds to the first output voltage threshold (branch "Yes" of 506), output driver 2B may activate a second driver of the plurality of drivers. For example, output driver 2B may enable driver 10B, which together with driver 6B may boost / buck the voltage level of the output signal depending on whether output driver 2B may boost / buck in an inverted manner or not. As the voltage level of the output signal increases / decreases, output driver 2B may continue to monitor the voltage level of the output signal to determine whether the voltage level of the output signal still corresponds to the first output voltage threshold ( 506). In response to determining that the voltage level of the output signal does not meet the first output voltage threshold (branch "no" of 506), output driver 2B may disable (510) the second driver. For example, as the voltage level of the output signal increases / decreases above the first output voltage threshold, output driver 2B may disable driver 10B such that the output signal is generated by driver 6B, e.g., without support of driver 10B.Output driver 2B may further monitor the voltage level of the output signal to determine whether the voltage level of the output signal satisfies a second output voltage threshold ( 512). For example, feedback logic 9 may determine whether the voltage level of the output signal is greater than, e.g., 80% of the level of its logic high. In response to determining that the voltage level of the output signal corresponds to the second output voltage threshold (branch "Yes" of 512), output driver 2B may activate the second driver ( 514).As discussed above, the first driver (e.g., driver 6B) may be configured to meet one or more slew rate requirements and the second driver (e.g., driver 10B) may be configured to meet one or more delay and / or DC requirements. As such, in this manner, the first driver and the second driver may collectively generate the output signal to meet the slew rate requirements, the delay requirements, and the DC requirements.Additionally, as discussed above, in some examples, output driver 2B may activate the second driver based on one or more thresholds. As an example, output driver 2B may enable the second driver during two time periods (when the output signal transitions from low to high, similar to conditions when the output signal transitions from high to low), (1) when the voltage level of the output signal is less than a first threshold, and (2) when the voltage level of the output signal is greater than a second threshold. As another example, the output driver 2B may activate the second driver only when the voltage level of the output signal is less than the first threshold. As another example, the output driver 2B may activate the second driver only when the voltage level of the output signal is greater than the second threshold.An exemplary application for the techniques of the present application is an output driver operating on a controller area network (CAN) bus. In some examples, the CAN bus specification may describe a slew rate requirement of 60 mv / ns for 20%-80% and 80%-20% signal slew / droop, respectively, and a 10 ns delay requirement of 50% of the input signal to achieve 20% of the output signal. However, with 60 mV / ns of slew rate, the time required to achieve 20% would be 10 ns in 3 V / configurations and 16.67 ns in 5 V configurations. As such, it could be a requirement for a driver to meet the 10 ns delay requirement (including the input signal to output driver propagation delay). Additionally, with reference to all variations on process, voltage and temperature, satisfying the delay requirement becomes a further challenge.According to one or more techniques of the present application, an output driver, such as output driver 2, may include a first driver having a slew rate that satisfies the CAN requirement of 60 mV / ns, such as driver 6, and a second driver that satisfies the 10 ns propagation delay requirement, such as driver 10. Additionally, the second driver may be activated during one or periods. As an example, the second driver may be activated when both the input signal is high and the voltage level of the output signal is below a first output threshold. As another example, the second driver may be activated when both the input signal is high and the voltage level of the output signal is greater than a second output threshold. As another example, the second driver may operate when both the input signal is high and the voltage level of the output signal is below a first output threshold, disable when the voltage level of the output signal is between the first output threshold and the second output threshold, and drive again when the voltage level of the output signal is greater than the second output threshold. In these ways, output driver 2 can meet the slew rate, time delay, and DC requirements of the CAN specification.The following examples may represent one or more aspects of the application.Example 1. a method comprising: responsive to a voltage level of an input signal corresponding to an input voltage threshold, activating a first driver of a plurality of drivers configured to jointly generate an output signal; and responsive to the voltage level of the input signal corresponding to the input voltage threshold and a voltage level of the output signal corresponding to an output voltage threshold, switching activation of a second driver of the plurality of drivers, wherein the second driver is configured to switch more current than the first driver when activated, and wherein the first driver has a faster slew rate than the second driver.Example 2. the method of example 1, further comprising: determining that the voltage level of the output signal corresponds to the output voltage threshold where the voltage level of the output signal is greater than the output voltage threshold, and wherein switching activation of the second driver of the plurality of drivers comprises activating the second driver.Example 3. The method in any combination of Examples 1-2, wherein the output voltage threshold is a first output voltage threshold, the method further comprising: responsive to the voltage level of the input signal corresponding to the input voltage threshold and the voltage level of the output signal being less than a second output voltage threshold, enabling the second driver; and responsive to the voltage level of the output signal being between the first output voltage threshold and the second output voltage threshold, disabling the second driver.Example 4. the method of any combination of Examples 1-3, wherein the first driver comprises a resistor configured to modify the slew rate of the first driver.Example 5. the method of any combination of Examples 1-4, wherein: driving the first driver comprises activating a first push driver of the plurality of drivers, and switching the activation of the second driver comprises switching the activation of a second push driver of the plurality of drivers, or activating the first driver comprises activating a first pull driver of the plurality of drivers, and switching the activation of the second driver comprises switching the activation of a second pull driver of the plurality of drivers.Example 6. the method of any combination of examples 1-5, wherein the output signal is a controller area network (CAN) bus communication signal.Example 7. output driver comprising: a plurality of drivers configured to jointly generate an output signal, wherein: a first driver of the plurality of drivers is configured to activate, in response to a voltage level of an input signal corresponding to an input voltage threshold, a second driver of the plurality of drivers is configured to switch activation in response to the voltage level of the input signal corresponding to the input voltage threshold and a voltage level of the output signal corresponding to an output voltage threshold, wherein the second driver is configured to switch more current than the first driver when activated, and wherein the first driver has a faster slew rate than the second driver.Example 8. The output driver of claim 7, wherein: the voltage level of the output signal corresponds to the output voltage threshold where the voltage level of the output signal is greater than the output voltage threshold, and the second driver is configured to be activated by at least activation.Example 9. the output driver of any combination of examples 7-8, wherein: the output voltage threshold is a first output voltage threshold, the second driver is configured to be activated in response to the voltage level of the input signal corresponding to the input voltage threshold and the voltage level of the output signal being less than a second output voltage threshold, and the second driver is configured to be deactivated in response to the voltage level of the output signal being between the first output voltage threshold and the second output voltage threshold.Example 10. output driver according to any combination of examples 7-9, further comprising: a resistor configured to modify the slew rate of the first driver.Example 11. the output driver of any combination of examples 7-10, wherein: the first driver is configured to be activated by at least activating a first push driver of the plurality of drivers, and the second driver is configured to switch activation by at least switching activation of a second push driver of the plurality of drivers, or the first driver is configured to be activated by at least activating a first pull driver of the plurality of drivers, and the second driver is configured to switch activation by at least switching activation of a second pull driver of the plurality of drivers.Example 12. output drivers of any combination of examples 7-11, wherein the output signal is a controller area network (CAN) bus communication signal.Example 13. output driver comprising: a plurality of means for generating an output signal together; and means for controlling the means for generating the output signal together, configured to: activate a first means of the plurality of means for generating the output signal together in response to a voltage level of an input signal corresponding to an input voltage threshold, switch activation of a second means of the plurality of means for generating the output signal together in response to the voltage level of the input signal corresponding to the input voltage threshold, and a voltage level of the output signal corresponding to an output voltage threshold, wherein the second means is configured to switch more current than the first means when activated, and wherein the first means has a faster slew rate than the second means.Example 14. The output driver of example 13, wherein the means for controlling is configured to: determine that the voltage level of the output signal corresponds to the output voltage threshold when the voltage level of the output signal is greater than the output voltage threshold, and switch activation of the second means of the plurality of drivers by at least activating the second means.Example 15. The output driver of any combination of Examples 13-14, wherein the output voltage threshold is a first output voltage threshold, and wherein the means for controlling is configured to: activate the second means in response to the voltage level of the input signal corresponding to the input voltage threshold and the voltage level of the output signal being less than a second output voltage threshold, and deactivate the second means in response to the voltage level of the output signal being between the first output voltage threshold and the second output voltage threshold.Example 16. The output driver of any combination of Examples 13-15, further comprising: means for altering the slew rate of the first driver.Example 17. output driver according to any combination of examples 13-16, wherein the means for controlling is configured to: activate the first means by at least activating a first push means of the plurality of means, and switch the activation of the second means by at least switching the activation of the second push means of the plurality of means, or activate the first means by at least activating a first push means of the plurality of means, and switch the activation of the second means by at least switching the activation of a second pull means of the plurality of means.Example 18. Output Driver of any combination of Examples 13-17, wherein the output signal is a communication signal of a controller area network (CAN) bus.The techniques described in the present application may be embodied, at least in part, in hardware, software, firmware, or any combination thereof. For example, various aspects of the described methods may be performed in one or more processors, including one or more microprocessors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or any other equivalent integrated or discrete logic circuitry, as well as any combination of such components. The term "processor" or "processing circuitry" may generally refer to any of the foregoing logic circuitry, alone or in combination with other logic circuitry, or any other equivalent circuitry. A controller including hardware may also perform one or more of the techniques of the present application.Such hardware, software, and firmware may be embodied in the same device or separate devices to support the various techniques described in the present application. In addition, any of the described units, modules, or components may be embodied together or separately as discrete, but commonly operable logic devices. Representations of the various features as modules or units are intended to emphasize different functional aspects and not necessarily mean that such modules or units must be executed by separate hardware, firmware, or software components. Rather, functionality associated with one or more modules or units may be performed by separate hardware, firmware, or software components, or integrated into common or separate hardware, firmware, or software components.The techniques described in the present application may also be embodied or encoded in an article of manufacture including a computer readable storage medium encoded with instructions. Instructions embedded or encoded in an article of manufacture including a computer readable storage medium may cause one or more programmable processors or other processors to perform one or more of the techniques described herein, such as when instructions included or encoded in the computer readable storage medium are executed by one or more processors. Computer readable storage media may include random access memory (RAM), read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electronically erasable programmable read only memory (EEPROM), flash memory, a hard disk, a compact disk ROM (CD-ROM), a floppy disk, a cassette, magnetic medium, optical medium, or other computer readable medium. In some examples, an article of manufacture may include one or more computer readable storage media.In some examples, a computer readable storage medium may comprise a non-transitory medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or a propagated signal. In certain examples, a non-transitory storage medium may store data that may change over time (e.g., in RAM or cache).Various aspects have been described in the present application. These and other aspects are within the scope of the following claims.

Claims

A method comprising: in response to a voltage level of an input signal satisfying an input voltage threshold, activating a first driver of a plurality of drivers configured to jointly generate an output signal; and in response to the voltage level of the input signal satisfying the input voltage threshold and a voltage level of the output signal satisfying an output voltage threshold, switching activation of a second driver of the plurality of drivers, wherein the second driver is configured to switch more current than the first driver when activated, and wherein the first driver has a faster slew rate than the second driver, further comprising: determining that the voltage level of the output signal satisfies the output voltage threshold when the voltage level of the output signal is greater than the output voltage threshold, and wherein switching activation of the second driver of the plurality of drivers comprises activating the second driver, wherein the output voltage threshold is a first output voltage threshold, the method further comprising: in response to the voltage level of the input signal satisfying the input voltage threshold and the voltage level of the output signal being less than a second output voltage threshold, activating the second driver; and in response to the voltage level of the output signal being between the first output voltage threshold and the second output voltage threshold, deactivating the second driver.The method of claim 1, wherein the first driver comprises a resistor configured to modify the slew rate of the first driver.The method of claim 1 or 2, wherein: activating the first driver comprises activating a first push driver of the plurality of drivers, and switching activation of the second driver comprises switching activation of a second push driver of the plurality of drivers, or activating the first driver comprises activating a first pull driver of the plurality of drivers, and switching activation of the second driver comprises switching activation of a second pull driver of the plurality of drivers.The method of any of claims 1-3, wherein the output signal is a controller area network (CAN) bus communication signal.An output driver comprising: a plurality of drivers configured to jointly generate an output signal, wherein: a first driver of the plurality of drivers is configured to be activated in response to a voltage level of an input signal satisfying an input voltage threshold, a second driver of the plurality of drivers is configured to switch its activation in response to the voltage level of the input signal satisfying the input voltage threshold and a voltage level of the output signal satisfying an output voltage threshold, wherein the second driver is configured to switch more current than the first driver when activated, and wherein the first driver has a faster slew rate than the second driver, wherein: the voltage level of the output signal satisfies the output voltage threshold when the voltage level of the output signal is greater than the output voltage threshold, and the second driver is configured to, activating by switching activation when the voltage level of the output signal is greater than the output voltage threshold, wherein: the output voltage threshold is a first output voltage threshold, the second driver is configured to be activated in response to the voltage level of the input signal satisfying the input voltage threshold and the voltage level of the output signal being less than a second output voltage threshold, and the second driver is configured to be deactivated in response to the voltage level of the output signal being between the first output voltage threshold and the second output voltage threshold.The output driver of claim 5, further comprising: a resistor configured to modify the slew rate of the first driver.The output driver according to claim 5 or 6, wherein: the first driver is configured to be activated at least by activating a first push driver of the plurality of drivers, and the second driver is configured to switch its activation at least by switching the activation of a second push driver of the plurality of drivers, or the first driver is configured to be activated at least by activating a first pull driver of the plurality of drivers, and the second driver is configured to switch its activation at least by switching the activation of a second pull driver of the plurality of drivers.The output driver of any of claims 5-7, wherein the output signal is a controller area network (CAN) bus communication signal.An output driver comprising: a plurality of means for generating an output signal together; and control means for controlling the means for generating the output signal together, wherein the control means is arranged to: activate a first means of the plurality of means for generating the output signal together in response to a voltage level of an input signal satisfying an input voltage threshold, switch activation of a second means of the plurality of means for generating the output signal together in response to the voltage level of the input signal satisfying the input voltage threshold and a voltage level of the output signal satisfying an output voltage threshold, wherein the second means is arranged to switch more current than the first means when activated, and wherein the first means has a faster slew rate than the second means, wherein the control means is arranged to: determine, wherein the voltage level of the output signal satisfies the output voltage threshold when the voltage level of the output signal is greater than the output voltage threshold, and switching the activation of the second means of the plurality of drivers at least by activating the second means, wherein the output voltage threshold is a first output voltage threshold, and wherein the control means is configured to: activate the second means in response to the voltage level of the input signal satisfying the input voltage threshold and the voltage level of the output signal being less than a second output voltage threshold, and deactivate the second means in response to the voltage level of the output signal being between the first output voltage threshold and the second output voltage threshold.The output driver of claim 9, further comprising: means for altering the slew rate of the first driver.The output driver according to claim 9 or 10, wherein the control means is configured to: activate the first means at least by activating a first push means of the plurality of means, and switch the activation of the second means at least by switching the activation of a second push means of the plurality of means, or activate the first means at least by activating a first pull means of the plurality of means, and switch the activation of the second means at least by switching the activation of a second pull means of the plurality of means.The output driver of any of claims 9-11, wherein the output signal is a controller area network (CAN) bus communication signal.

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