Current-controlled crystal oscillator

Abstract

Oscillator circuit with an oscillator stage (OSC) and a first current source (I ddx ) which is designed to drive the oscillator stage (OSC), wherein the oscillator stage (OSC) comprises an oscillator stage input terminal, an oscillator stage output terminal, a crystal oscillator (X1) which is designed to supply an oscillation signal between the oscillator stage input terminal and the oscillator stage output terminal, wherein the crystal oscillator (X1) has a first oscillator terminal (x 11 ) and a second oscillator connection (x 12), wherein the oscillator circuit comprises an operational amplifier having an inverting input, a non-inverting input and an operational amplifier output, wherein the oscillator stage input terminal is coupled to the inverting input and the oscillator stage output terminal is coupled to the non-inverting input, and the operational amplifier output is coupled to the oscillator stage input terminal such that the oscillator stage input terminal and the oscillator stage output terminal are controlled to have an equal DC voltage level.

Description

FIELD OF THE INVENTION

[0001] The invention relates to oscillator circuits and in particular to crystal oscillator circuits. BACKGROUND OF THE INVENTION

[0002] A crystal oscillator is an electronic oscillator circuit that uses the mechanical resonance of a vibrating crystal made of piezoelectric material to generate a signal at a very precise frequency.

[0003] This frequency is commonly used to track time, to provide a stable clock signal required for a digital system, and / or to stabilize frequencies for radio transmitters and receivers.

[0004] The most common type of piezoelectric material used in crystal oscillators is quartz crystal, but other materials such as polycrystalline ceramics are also used.

[0005] Typically, quartz crystals are cut and mounted to vibrate best at a desired resonant frequency or at a multiple of the desired resonant frequency. When the crystal vibrates, it can be modeled as an RLC circuit, producing a rapidly changing reactance with frequency. The RLC circuit creates positive feedback and amplification at the resonant frequency, thus producing sustained oscillations.

[0006] Fig. Figure 1 represents a current-controlled CMOS inverter oscillator circuit as described in E. Vittoz, “Low-Power Crystal and MEMS Oscillators: The Experience of Watch Developments,” Integrated Circuits and Systems, Fig. 5.25, page 129, DOI 10.1007 / 978-90-481-9394-3. The circuit of Fig. 1 comprises a transistor T1 with a gate G1, a source S1, and a drain D1, a transistor T2 with a gate G2, a source S2, and a drain D2, a transistor T3 with a gate G3, a source S3, and a drain D3, a capacitor C1 with a first end 10 and a second end 11, a capacitor C2 with a first end 12 and a second end 13, a capacitor C3 with a first end 14 and a second end 15, a resistor R1 with a first end 16 and a second end 17 and a crystal oscillator 18 with a first end 19 and a second end 20. The source S1 is connected to the source S2 and to the second end 15 of the capacitor C3. The drain D2 is connected to the second end 17 of the resistor R1, to the second end 20 of the crystal oscillator 18, to the drain D3 and to the second end 13 of the capacitor C2.Gate G2 is connected to the first end 16 of resistor R1, to the first end 19 of crystal oscillator 18, to gate G3, and to the second end 11 of capacitor C1. The first end 10 of capacitor C1 is connected to source S3, to the first end 12 of capacitor C2, and to the first end 14 of capacitor C3.

[0007] In the known circuit according to Fig. 1, resistor R1 is a feedback resistor from the drains D2 and D3 of transistors T2 and T3, respectively, to the gates G2 and G3 of transistors T2 and T3, respectively, to ensure that the DC voltage levels of these drains D2 and D3 and these gates G2 and G3 of transistors T2 and T3 are equal. Therefore, the DC voltage level at both terminals 19 and 20 of the oscillator crystal 18 is equal. The feedback resistor R1 should have a very high resistance value in the case of low power requirements, since it consumes electrical power all the time.

[0008] US 2014 / 0 091 869 A1 describes methods and devices for a crystal oscillator with a low-noise, amplitude-based start-up control loop. A large gain factor is used to quickly start the crystal's oscillation.

[0009] US 4 959 557 A relates to digital logic systems and, in particular, to a circuit for controlling the duty cycle of a clock generated by a crystal oscillator. SUMMARY OF THE INVENTION

[0010] In a first aspect, the invention provides an oscillator circuit comprising an oscillator stage (OSC) and a first current source (I ddx) which is designed to drive the oscillator stage (OSC), wherein the oscillator stage (OSC) comprises an oscillator stage input terminal, an oscillator stage output terminal, a crystal oscillator (X1) which is designed to supply an oscillation signal between the oscillator stage input terminal and the oscillator stage output terminal, wherein the crystal oscillator (X1) has a first oscillator terminal (x 11 ) and a second oscillator connection (x 12), wherein the oscillator circuit comprises an operational amplifier having an inverting input, a non-inverting input and an operational amplifier output, wherein the oscillator stage input terminal is coupled to the inverting input and the oscillator stage output terminal is coupled to the non-inverting input, and the operational amplifier output is coupled to the oscillator stage input terminal such that the oscillator stage input terminal and the oscillator stage output terminal are controlled to have an equal DC voltage level.

[0011] As a result, all elements in the oscillator circuit are current-controlled. This provides several features for the oscillator circuit, including much less dispersion across the processing corners, the oscillator circuit being self-adjusting to a suitable supply voltage that is as low as possible, but not lower than a minimum value required for the oscillator circuit to operate correctly, and the individual components can be easily designed, especially scaling.

[0012] The dependent claims focus on advantageous embodiments.

[0013] Those skilled in the art will understand that the features described above may be combined in any manner deemed useful. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Aspects of the invention are explained below by way of example with reference to the drawings. The drawings are schematic and may not be drawn to scale.

[0015] The features and effects of the present invention will be explained in more detail below with reference to the drawings, in which preferred and illustrative embodiments of the invention are shown. Those skilled in the art will recognize that other alternative and equivalent embodiments of the invention may be devised and practiced without departing from the scope of the present invention. Fig. 1 represents a current-controlled CMOS inverter oscillator circuit. Fig. Figure 2 illustrates a current-controlled crystal oscillator circuit according to an embodiment of the invention. Fig. 3 shows a higher level block diagram of the circuit according to Fig. 2. Fig. 4 shows an alternative bias circuit BC' to that shown in Fig. 2 and an example of the operational amplifier OA1 of the oscillator circuit. Fig. 5, Fig. 6, Fig. 7, Fig. 8 and Fig. 9 show simulation results of the current-controlled crystal oscillator circuit of Fig. 2, which operates in a transmitter / receiver mode. Fig. 10, Fig. 11, Fig. 12 and Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18 and Fig. 19 show simulation results of the current-controlled crystal oscillator circuit of Fig. 2, which operates in a timer mode. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0016] The examples and embodiments described herein are intended to illustrate rather than limit the invention. Those skilled in the art may construct alternative embodiments without departing from the scope of the claims. Reference numerals placed in parentheses in the claims should not be interpreted as limiting the scope of the claims. Elements described as separate entities in the claims or in the description may be implemented as single or multiple hardware elements that combine the features of the described elements.

[0017] Fig. Figure 2 illustrates a current-controlled crystal oscillator circuit according to an embodiment of the invention.

[0018] The current-controlled crystal oscillator circuit of Fig. 2 comprises, from left to right, a series connection of the following subcircuits: a bias circuit BC, a regulator OA1 and a low-pass filter circuit R / LPF, an oscillator stage OSC, a current mode comparator CMC, and an output circuit OS. A level shifter L receives an output voltage V out the output circuit OS.

[0019] The current-controlled crystal oscillator circuit of Fig. 2 comprises several transistors T i (i = 4, 5, ..., 12). Each of these transistors T i has a respective gate G i , a Source S i and a drain D i For simplicity, a transistor T i hereinafter referred to as the i-th transistor in the patent description. It should be noted that the relevant reference numeral may be different in the claims, as they may appear in a different order in the claims.

[0020] The current-controlled crystal oscillator circuit of Fig. 2 comprises a resonance crystal X1 and a current source I1.

[0021] Fig. Figure 2 also shows the currents received by each of the subcircuits: the bias circuit BC receives a current I bias , the regulator and low-pass filter circuit R / LPF receives a current I reg , the oscillator stage OSC receives a current I osc , the current mode comparator CMC receives a current I cp1 , and the output circuit OS receives a current I cp2 .

[0022] The bias circuit BC of the current-controlled crystal oscillator circuit includes a fourth P-type transistor T4 and a fifth N-type transistor T5, whose respective drain terminals D4 and D5 are connected to each other, and whose gate terminals G4 and G5 are connected to their respective drain terminals D4 and D5. The source terminal S5 of the N-type transistor T5 is connected to ground, and the source terminal S4 of the P-type transistor T4 is connected to the current source I1.

[0023] The R / LPF circuit of the current-controlled crystal oscillator circuit of Fig. 2 comprises an operational amplifier OA1, a capacitor C4 with a first end c 41 and a second end c 42 , a capacitor C5 having a first end c 51 and a second end c 52 , a resistor R2 with a first end r 21 and a second end r 22 , a resistor R3 with a first end r31 and a second end r 32 , a resistor R4 with a first end r 41 and a second end r 42 , and a sixth N-type transistor T6 with a source S6, a drain D6, and a gate G6. The second end c 42 of the capacitor C4 is connected to the inverting input of the operational amplifier OA1, the second end c 52 of the capacitor C5 is connected to the non-inverting input of the operational amplifier OA1 and the first end c 41 of the capacitor C4 is connected to the first end c 51 of capacitor C5 and connected to ground. The gate G6 of transistor T6 is connected to the gate G5 of transistor T5, the drain D6 of transistor T6 is connected to the negative power supply of operational amplifier OA1, and the source S6 of transistor T6 is connected to ground. The output of operational amplifier OA1 is connected to the first end r 31of the resistor R3, the second end r 32 of the resistor R3 is connected to the second end r 22 of the resistor R2 and with the second end r 42 of the resistor R4, the first end r 21 of the resistor R2 is connected to the inverting input of the operational amplifier OA1 and the first end r 41 of the resistor R4 is connected to the non-inverting input of the operational amplifier OA1.

[0024] Furthermore, the oscillator stage OSC of the current-controlled crystal oscillator circuit of Fig. 2 an eighth N-type transistor T8 having a source S8, a drain D8 and a gate G8, a seventh P-type transistor T7 having a source S7, a drain D7 and a gate G7, a capacitor C7 having a first end c 71 and a second end c 72 , a resistor R5 with a first end r 51 and a second end r 52, a resistor R6 with a first end r 61 and a second end r 62 . The first end r 51 of the resistor R5 is connected to the first end c 71 of the capacitor C7 and connected to the current source I1. The second end c 72 of the capacitor C7 is connected to ground and the second end r 52 of the resistor R5 is connected to the source S7 of the transistor T7. The gate G7 of the transistor T7 is connected to the second end r 22 of the resistor R2 and the drain D7 of the transistor T7 is connected to the drain D8 of the transistor T8. The gate G8 of the transistor Ts is connected to the second end r 22 of the resistor R2 and the source S8 of the transistor T8 is connected to the first end r 61 of the resistor R6. Furthermore, the oscillator stage OSC of the current-controlled crystal oscillator circuit of Fig. 2 a resistor R7 with a first end r 71and a second end r 72 and a switch S2, the first end r 71 of the resistor R7 with the second end c 62 of the capacitor C6, the second end r 72 of the resistor R7 is connected to one end of the switch S2 and the other end of the switch S2 is connected to the first end c 81 of the capacitor C8.

[0025] The current mode comparator CMC of the current controlled crystal oscillator circuit of Fig. 2 includes a tenth transistor T 10 N-type with a source S 10 , a drain D 10 and a Gate G 10 and a ninth P-type transistor T9 having a source S9, a drain D9, and a gate G9. The gate G9 of the ninth transistor T9 is connected to the gate G 10 of the tenth transistor T 10 and with the second end r 22 of the resistor R2. The drain D9 of the ninth transistor T9 is connected to the drain D10 of the tenth transistor T 10 connected. The Source S 10 of the tenth transistor T 10 is connected to ground and the source S9 of the ninth transistor T9 is connected to the current source I1.

[0026] The output circuit OS of the current-controlled crystal oscillator circuit of Fig. 2 includes a twelfth transistor T 12 N-type with a source S 12 , a drain D 12 and a Gate G 12 and an eleventh transistor T 11 P-type with a source S 11 , a drain D 11 and a Gate G 11 . Gate G 11 of the eleventh transistor T 11 is connected to Gate G 12 of the twelfth transistor T 12 which together with the drains D9, D 10 of the ninth or tenth transistor T9, T 10 are connected. The drain D 11 of the eleventh transistor T 11 is connected to the drain D12 of the twelfth transistor T 12 connected. The Source S 12 of the twelfth transistor T 12 is connected to ground and the source S 11 of the eleventh transistor T 11 is connected to the current source I1.

[0027] Furthermore, the current-controlled crystal oscillator circuit of Fig. 2 a capacitor C6 having a first end c 61 and a second end c 62 , a capacitor C8 having a first end c 81 and a second end c 82 , a resistor R7 with a first end r 71 and a second end r 72 and a crystal oscillator X1 having a first end x 11 and a second end x 12 . The first end c 61 of the capacitor C6 is connected to ground, the second end c 82 of the capacitor C8 is connected to ground, the second end c 62of the capacitor C6 is connected to the first end r 71 of the resistor R7, with the first end x 11 of the crystal oscillator X1 and with the second end r 22 of the resistor R2. The second end r 72 of the resistor R7 is connected via a switch SW2 to the first end c 81 of the capacitor C8, with the second end x 12 of the crystal oscillator X1, and with the second end r 42 of the resistor R4.

[0028] Finally, the circuit of Fig. 2 another power source I s with an output connected to an output of the current source I1 via a switch SW1. Thus, all elements in the Fig. 2. This creates several features for the oscillator circuit, including: • much less scatter across processing corner points • the oscillator circuit is now self-adjusting to a suitable supply voltage that is as low as possible, but not lower than a minimum value required for the oscillator circuit to operate correctly • the individual components can be easily designed, especially scaling is easy.

[0029] The basic operation of the circuit of Fig. 2 will now be described.

[0030] The person skilled in the art will recognize that the oscillator stage OSC has a similar construction to that shown in Fig. 1. The main differences between the oscillator stage OSC and the oscillator of Fig. 1 consist in that the feedback resistor R1 is replaced by the regulator OA1, that the source S8 of the eighth transistor T8 is connected to ground via the resistor R6, that the source S7 of the seventh transistor T7 is connected to the resistor R5 and that the resistor R7 (which is connected to the resistor R1 in Fig. 1) is arranged in series with the switch SW2. Furthermore, all peripheral circuits of the oscillator are powered by the current source I ddx supplied.

[0031] Fig. 3 shows a higher level block diagram of the circuit according to Fig. 3, which only the current source I ddx , the bias circuit BC, the regulator / low-pass filter circuit R / LPF, the oscillator stage OSC, the current mode comparator CMC and the output stage OS and their mutual connections.

[0032] The bias circuit BC provides an output voltage V BC , out.

[0033] The regulator / low-pass filter circuit R / LPF receives the output voltage V BC,out of the bias circuit BC as its input voltage V R / LPF,in . In addition, the regulator / low-pass filter circuit R / LPF provides an output voltage V R / LPF,out to the input of the oscillator stage OSC. Furthermore, the operational amplifier OA1 in the regulator / low-pass filter circuit R / LPF receives a feedback signal derived from the voltage difference between the input and output of the oscillator stage OSC, which in the embodiment shown is equal to the voltage across the crystal oscillator X1.

[0034] The regulator / low-pass filter circuit R / LPF is arranged such that the DC input voltage of the oscillator stage OSC is equal to the DC output voltage of the oscillator stage OSC. In the embodiment shown, this is achieved by the operational amplifier OA1 in the regulator R / LPF, which charges / discharges the capacitor C6 so that the average input voltage of the oscillator stage OSC is equal to the average output voltage of the oscillator stage OSC. Note that feedback of the voltage difference between the input and output of the oscillator stage OSC to any type of operational amplifier whose output is coupled to the input of the oscillator stage OSC can be used for this purpose.

[0035] Unlike most other oscillators, the comparator in the preferred embodiment is not a "voltage mode" comparator. In such a "voltage mode" comparator, its input would be coupled to the output of the oscillator stage OSC. Here, the input of the current mode comparator CMC is coupled to the input of the oscillator stage OSC. The current mode comparator CMC indicates when the absolute current through transistor T7 is greater or less than the absolute current through transistor T6. A voltage mode comparator could also be used, although this would introduce more phase noise.

[0036] The oscillator and all its peripheral circuits run at the self-biasing voltage V ddx . V ddx is lower than the supply voltage V ddanother circuit arrangement to save power in the oscillator. Within the oscillator, apart from the level shifter, the logic level is the internal supply voltage V ddx . The output stage of the oscillator is a level shifter L, which converts the logic level of the signal, as received by the output circuit OS, to the supply voltage V dd the circuit arrangement to which the resulting oscillation signal is to be supplied.

[0037] The bias circuit BC of Fig. 3 receives a current from the current source I ddx at the source S4 of transistor T4. See also Fig. 2. This current generates a voltage V gs4 between the gate G4 / drain D4 and the source S4 of the transistor T4, so that T4 is in saturation mode. The transistor T4, operating in saturation, supplies a current I bias to the transistor T5. Consequently, a voltage V Pbetween the source S4 and the gate G4 / drain D4 of the transistor T4 and a voltage V N is present between the drain D5 / gate G5 and the source S5 of the transistor T5. By defining the output voltage of the current source I ddx as V ddx the following equation applies: Vddx−VP=VN

[0038] Transistor T5 is connected to transistor T6 in a current mirror arrangement. This means that the voltage across the gate-source of transistor T6 is equal to the voltage across the gate-source of transistor T5. Since all transistors were fabricated in the same manufacturing step on the same chip, the current flowing through transistor T6 has a fixed ratio to that flowing through transistor T5, as determined by their relative surface areas. The drain current through T6 is the bias current of the operational amplifier OA1 in the regulator R / LPF (see, for example, the embodiment of Fig. 4). The reference voltage at the non-inverting input of the operational amplifier OA1 is the low-pass filtered output voltage of the oscillator stage OSC (high-frequency components in the output voltage of the oscillator stage OSC are shorted to ground via capacitor C5). The feedback voltage of the regulator R / LPF at the inverting input of the operational amplifier OA1 is the low-pass filtered input voltage of the oscillator stage OSC (high-frequency components in the output voltage of the oscillator stage OSC are shorted to ground via capacitor C4). The output of the regulator R / LPF is connected to the input of the oscillator stage OSC and charges / discharges capacitor C6 until the voltage at both inputs of the operational amplifier OA1 in the regulator R / LPF is equal. Since the Wi / Li ratios of T7 and Ts are similar to those of T4 and T5 (where W i the channel width of the transistor T i represents and L ithe channel length of the transistor T i represents), the average value of the input and output voltage of the oscillator stage OSC is V N . The same applies to the W i / L i ratios of the transistors of the CMC and OS stages and therefore their turning point is close to a voltage level equal to V N .

[0039] Due to the configuration of the circuit of Fig. 2 is therefore the same voltage difference V P between the output voltage V ddx the current source I ddx and the gate G7 of the transistor T7, between the output voltage V ddx the current source I ddx and the gate G9 of the transistor T9 and between the output voltage V ddx the current source I ddx and Gate G 11 of the transistor T 11 For the same reason, the same voltage difference V N between the gate G8 of the transistor T8 and ground, between the gate G10 of the transistor T 10 and ground and between the gate G 12 of the transistor T 12 and mass present.

[0040] As in the circuit of Fig. 2, the voltage between the output of the current source I ddx and mass V N +V P .

[0041] In this way, all stages of the circuit are Fig. 3, namely the bias circuit BC, the regulator / LPF circuit R / LPF, the oscillator stage OSC, the current mode comparator CMC and the output stage OS, are well balanced regardless of the processing corner point of the whole circuit, the current temperature when using and the injected current when using.

[0042] The DC voltage at the output of the operational amplifier OA1 follows the DC voltage present at the inverting and non-inverting input of the operational amplifier OA1, which are controlled to be equal.

[0043] The resistor R3 at the output of the operational amplifier OA1 prevents a rail-to-rail swing of the voltage V x1 Linearity errors in the regulator and LPF circuit R / LPF are caused.

[0044] The operational amplifier OA1 is connected in a closed loop, with the output of the operational amplifier OA1, which is connected to the input of the oscillator stage OSC, being fed back to the inverting input of the operational amplifier OA1 via resistor R2. The non-inverting input of the operational amplifier OA1 is connected to the output of the oscillator stage OSC via resistor R4. In other words, the input and output of the oscillator stage OSC are fed back to the inverting and non-inverting inputs of the operational amplifier OA1. During use, these inverting and non-inverting inputs have the same DC voltage level. In this way, the operational amplifier OA1 controls the regulator and LPF circuit R / LPF so that the DC voltage level at the input of the oscillator stage OSC is the same as the DC voltage level at the output of the oscillator stage OSC.Thus, the operational amplifier OA1 replaces the resistor R1 in the state-of-the-art design of . Fig. 1, the advantage being that such an operational amplifier OA1 consumes less electrical energy during use.

[0045] However, providing only this feedback circuit with the operational amplifier OA1 would cause a relatively slow start of the entire circuit.

[0046] Therefore, the series connection of the resistor R7 and the switch SW2 was provided, which has the same function as the resistor R1 in the circuit according to the prior art ( Fig. 1), but only at the time of circuit start-up. This means that at the time of start-up, switches SW1 and SW2 are both closed to allow current to flow. The crystal oscillator X1 oscillates and delivers an oscillation signal at its output terminals x 11 and x 12An oscillation voltage is established across resistor R7. This oscillation signal across crystal oscillator X1 is output to the inverting and non-inverting input terminals of operational amplifier OA1 in the R / LPF circuit, so that its output also generates an oscillation signal, which is then supplied to the rest of the circuit, as explained above. In the circuit of Fig. 3 After initialization, i.e., when operational amplifier OA1 delivers a stable oscillation signal at its output, switches SW1 and SW2 are opened, so that no more current flows through them. Then, no more current flows through resistor R7, thus saving energy. Even if resistor R7 is disconnected from the circuit after initialization, operational amplifier OA1 in the R / LPF circuit causes the DC voltage difference across crystal oscillator X1 to be 0 (zero). This means that both terminals x 11and x 12 are controlled to operate at the same DC voltage V N One method for controlling the opening of switches SW1 and SW2 is to count a predetermined number of generated pulses by the oscillator after startup. To this end, the oscillator output signal can be fed to a counting circuit that counts the number of pulses of the generated signal and is arranged to control the opening / closing of switches SW1b and SW2. For example, SW1 and SW2 are opened by such a counting circuit when 1024 pulses are counted.

[0047] On average, in the preferred embodiment, the DC voltages V x1 , V x2 , V N , and V P in the circuit of Fig. 3 are essentially the same. Here, "essentially" means that these DC voltages should have the same values, but they may differ slightly in practice due to tolerances in the design of the various transistors used.

[0048] In the oscillator stage OSC of the circuit of Fig. 2, no amplitude control is required because the current source I ddx the voltage V ddx The oscillator stage OSC is a push-pull stage with twice the gm compared to a single transistor "grounded source" configuration at the same current. Apart from a small voltage drop across the respective resistors R5 and R6, the voltage at the interconnected drains D7 and D8 fluctuates between ground and the voltage V ddx . Resistors R5 and R6 dampen the limitation of V x2 .

[0049] Apart from the resistors R5 and R6, the current mode comparator CMC is a copy of the oscillator stage OSC, but the oscillator stage OSC drives a heavy load, i.e. the load capacitors C6 and C8, which requires a relatively high current, while the current mode comparator CMC itself drives a tiny load, i.e. the output circuit OS, which allows the output of the output circuit OS to jump from “rail to rail”, i.e. between the voltage V ddx and ground. The voltage drop at peak currents across resistors R5 and R6 increases the current gain of the current mode comparator CMC.

[0050] The output stage OS is a copy of the current mode comparator CMC. The respective sizes of the transistors T 11 and T 12 However, they differ from the respective sizes of the transistors T9 and T 10, so that the power consumption is very low, the output stage OS forms a relatively small load for the current mode comparator CMC and can drive a relatively heavy load itself.

[0051] In summary, the basic functionalities of the respective function blocks of Fig. 2 and 3 as follows: • Power source I ddx : designed to supply a constant current to the entire current-controlled oscillator circuit; finally, I ddx have a temperature coefficient to fine-tune the performance of the oscillator's temperature coefficient TC. • Bias circuit BC: designed to provide a well-defined first DC output voltage VBC.out; • Regulator and LPF circuit R / LPF: designed to provide an equal second DC output voltage VR / LPC at two different output terminals while allowing an oscillating voltage signal to be present between these two output terminals; • Oscillator stage OSC: designed to provide a first oscillation signal VOSC,out; • Current mode comparator CMC: designed to receive the oscillation signal VOSC and provide an amplified oscillation signal. This amplified oscillation signal is clamped between ground and Vddx. • Output stage OS: designed to form a small load for the output of the current mode comparator CMC and to enable the control of the level shifter L. • Level converter L: designed to convert the logic level of the output signal VCMC,out of the current mode comparator CMC to a required logic level of the circuits that receive the oscillation signal of the oscillator, as shown in Fig. 2 and Fig. 3 shown.

[0052] Fig. 4 shows an alternative bias circuit BC' to that shown in Fig. 2 and an example of the operational amplifier OA1 of the oscillator circuit, in which the same reference numeral refers to the same components as in Fig. 2 and Fig. 3 refers.

[0053] The alternative bias circuit BC' of Fig. 4 includes the regulator OA1 and includes several transistors T j (j = 13, 14, ..., 17). Each of these transistors T i has a respective gate G j , a Source S j , and a drain D j on.

[0054] The alternative bias circuit BC' of Fig. 4 comprises a thirteenth transistor T 13 N-type, whose source terminal S 13 is connected to the drain terminal D5 of the transistor T5, whose drain terminal D 13 with the drain terminal D4 of the transistor T4, with its gate G 13 and is connected to the gate G5 of the transistor T5, a fourteenth transistor T 14 N-type with a source S 14 , which is connected to the drain D6 of the transistor T6, and a gate G 14 , which ends with the first r 21 of the resistor R2 (in Fig. 4 not shown), a fifteenth transistor T 15 N-type with a source S 15 , which is connected to the drain D6 of the transistor T6, and a gate G 15 , which ends with the first r 41 of the resistor R4 (in Fig. 4 not shown), a sixteenth transistor T 16 P-type with a drain D 16, which is connected to the drain D 14 of the transistor T 14 connected to a gate G 16 , which is connected to the drain D 14 of the transistor T 14 connected, and a source S 16 , which is connected to the power source I ddx and a seventeenth transistor T 17 P-type with a drain D 17 , which is connected to the drain D 15 of the transistor T 15 and with the first end r 31 of the resistor R3 (in Fig. 4 not shown) is connected to a gate G 16 , which is connected to the drain D 14 of the transistor T 14 connected, and a source S 17 , which is connected to the power source I ddx This makes the gate G 15 the inverting input and the gate G 14 is the non-inverting input, whereas the drain node D 15 / Drains D 17 the output of the regulator.

[0055] In the construction of Fig. 4 is the additional cascode transistor T 13 characterized in that it W 13 / L 13 >> β, where β = W / L of the transistor T5, which leads to a lower gate-source voltage Vgs13, and the drain-source voltage Vds5 across the drain D5 and the source S5 satisfies the condition: Vds5 > Vd sat5 , where Vd sat5 is the saturation voltage of transistor T5. Thus, transistor T5 is in saturation.

[0056] In one example, the transistor T6 satisfies the condition 2*W / L and the condition Vds6 > Vd sat6 . Thus, transistor T6 is also in saturation.

[0057] Both transistors T 14 and T 15 are characterized by the fact that they W 14 / L 14 >> β and W 15 / L 15 >> β.

[0058] Since these conditions are met, the regulator stage R / LPF (here with the transistors T6, T 14 , T 15, T 16 , T 17 ) all transistors are in saturation if: Vin+≈Vin−≈VN≈Vddx−VP,

[0059] The Fig. The current-controlled crystal oscillator circuit shown in Figure 2 can operate in a transmitter / receiver mode, in which stabilized frequencies for radio transmitters and / or radio receivers can be generated. In this mode, the rising / falling edges of the generated oscillation signal, as ultimately generated, should be as precise as possible, so that they define temporal moments at which certain actions can start / end as precisely as possible. This is achieved by feeding relatively more current into the oscillator circuit through the current source I ddx achieved, so that lower phase noise is obtained.

[0060] The circuit dimensions are, to a large extent, linearly proportional to the crystal frequency. The following main parameters can be used for the circuit of Fig. 2 apply: f XTAL Frequency of the crystal oscillator X1 (e.g. 16 MHz). I ddx Supply current fed into the oscillator. I S Starting current. f LPF Crossover frequency of the low-pass filters C4, R2 and C5, R4 C DDX V DDX -Smoothing capacitor (e.g. 50 pF; C7 in Fig. 2). R SPN Equivalent series resistance value of resistors R5 and R6 in the oscillator stage OSC. R START Resistance value of the feedback resistor in start mode (R7 in Fig. 2). R S Equivalent series resistance value of the resistor (R3 in Fig. 2) and the regulator OA1 in the OA / LPF. β BIAS Channel width divided by the channel length of the channel of the NMOS transistor of the bias circuit BS (T5 in Fig. 2). β OSCChannel width divided by the channel length of the NMOS transistor channel in the oscillator stage OSC (T8) β CP1 Channel width divided by the channel length of the NMOS transistor channel of the current mode comparator CMC (T 10 in Fig. 2). β CP2 Channel width divided by the channel length of the channel of the NMOS transistor of the output circuit OS (T 12 in Fig. 2). α PN Channel width divided by the channel length of the PMOS transistor channel divided by the channel width divided by the channel length of the NMOS transistor channel in the bias circuit BC, oscillator stage OS current mode comparator CMC and output circuit OS. C L Load capacitors (specified by the crystal manufacturer; C6, C8 in Fig. 2).

[0061] In one embodiment of the current controlled crystal oscillator circuit of Fig. 2, which operates in a transmitter / receiver mode, the multiple circuit dimensions of Fig. 2 have the following values: Iddx≈fXTAL*2 pA / Hz(≈32 μA at fXTAL=16 MHz; ≈64 nA at fXTAL=32 kHz) fLPF≈fXTAL / 40 (≈400 kHz at fXTAL=16 MHz; e.g. C=2 pF and R=200 kΩ) RSPN≈60 mV / Iddx (≈1800 Ω at fXTAL=16 MHz) βBIAS≈250 μA / Iddx (≈8≈0.2*2.4 μm / 60 nm at t fXTAL=16 MHz; thus, if L=60 nm, then W=0.2*2.4μ=0.48 μm) βOSC≈62.5 mA / Iddx(≈2000 ≈ 50*2.4 μm / 60 nm at fXTAL=16MHz) βCP1≈12.5 mA / Iddx(≈400≈10*2.4 μm at fXTAL =16MHz) βCP2≈1.25 mA / Iddx(≈40≈1*2.4 μm / 60 nm at fXTAL=16 MHz) αPN≈2.5 and the channel width divided by the channel length of the channel of T6 is 2* βBIAS.

[0062] These parameters may have a value in a range of 50% to 150% of the above nominal values. Preferably, these parameters may have a value in a range of 75% to 125% of the above nominal values, and even more preferably, these parameters may have a value in a range of 90% to 110% of the above nominal values.

[0063] In this way, the current flowing through the current source I ddx the current-controlled crystal oscillator circuit of Fig. 2, which operates in a transmitter / receiver mode, is distributed between the different blocks in the following way: the current I bias the bias circuit is ≈2.5% of the current I ddx , the current I osc the oscillator stage OSC is ≈78 % of the current I ddx , the current I cp1 of the current mode comparator CMC is ≈14 % of the current I ddx and the current I cp2 of the output circuit OS is ≈0.5% of the current Iddx . The remaining 5% of the current I ddx are consumed by the regulator (OA1).

[0064] Fig. 5, Fig. 6, Fig. 7, Fig. 8 and Fig. 9 show simulation results of the current-controlled crystal oscillator circuit of Fig. 2, which operates in a transmitter / receiver mode. In Fig. 5, Fig. 6, Fig. 7 and Fig. 8 the horizontal axes represent the current I ddx the current-controlled crystal oscillator circuit of Fig. 2, operating in a transmitter / receiver mode, in microamperes. The vertical axes represent: in Fig. 5, V x1 , V x2 , and avg_vddx, represented in volts, in Fig. 6 the ratio of the stroke voltage, which is shown in volts, to V ddx which is expressed in volts, in Fig. 7 the efficiency factor, which is determined by the ratio of the stroke voltage, expressed in volts, to the current I, expressed in amperes ddx is defined, and in Fig. 8 the duty cycle of the output signal as provided by the level shifter L. In Fig. 9 the horizontal axis also represents the current I ddx in microamperes, which represents the total current of the entire current-controlled crystal oscillator circuit of Fig. 2 operating in a transmitter / receiver mode, and along the vertical axis five curves are shown, each representing the percentage % of the current I ddx , which belongs to I CP2 the percentage % of the current I ddx , which leads to stream I bias the percentage % of the current I ddx , which leads to stream I reg the percentage % of the current I ddx , which leads to stream I CP1 and the percentage % of the current I ddx , which leads to stream I OSC goes, represent.

[0065] As shown in the simulations conducted in Fig. 5, Fig. 6, Fig. 7, Fig. 8 and Fig. 9, the current I ddx from 10 microamperes to 300 microamperes, the capacitors C6 and C8 have a capacity of 18 picofarads and the circuit operates at a temperature of 25 degrees Celsius.

[0066] To accelerate the start of the crystal oscillator, a relatively high current (I S in Fig. 2) is fed into the transmitter / receiver mode configuration, while the resistors R5 and R6 are short-circuited by switches and the switch SW2 (in Fig. 2) is closed. More than 90 % of the fed-in current (sum of I ddx and I S ) flows in the oscillator stage (T7 and Ts), which maximizes its transconductance. The starting resistance R START (R7 in Fig. 2) ensures that the input and output voltage of the oscillator stage are approximately equal at start-up, independent of the regulator (OA1 in Fig. 2). A 12-bit clock counter (2 12 =4096 clock pulses), which is reset by a POR signal (power-on reset signal), can be used to switch from start-up mode to transmitter / receiver mode after starting the oscillator. The resistor R START (R7 in Fig. 2) can be 100 kΩ and I S can be 1 mA for a 16 MHz crystal. For a lower crystal frequency, a higher value for R START in combination with a lower starting current (I S ) be used.

[0067] The current-controlled crystal oscillator circuit used in Fig. 2, can also operate in a timer mode to provide a stable clock signal. In this embodiment, the phase noise requirements are less stringent, since the timer counts an average number of oscillation cycles only by counting the number of rising / falling edges. Thus, the current, as fed into the oscillator circuit by the current source I ddx fed in, be much lower than in transmitter / receiver mode.

[0068] In one embodiment of the current controlled crystal oscillator circuit of Fig. 2, which operates in a timer mode, the multiple circuit dimensions of Fig. 2 have the following values: Iddx≈fXTAL*125 fA / Hz(≈2 μA at fXTAL=16 MHz; ≈4 nA at fXTAL=32kHz) fLPF≈fXTAL / 40 (≈400 kHz at fXTAL=16 MHz) RSPN≈0 mV / Iddx (≈0Ω at fXTAL=16 MHz→closed switch via R5 and R6 in Fig. 2) βBIAS≈16 μA / Iddx(≈8≈0.2*2.4 μm / 60 nm at fXTAL=16 MHz; therefore, if L=60 nm, then W=0.2*2.4 μ=0.48 μm) βOSC≈1.25 mA / Iddx(≈640≈16*2.4 μm / 60nm at fXTAL=16MHz) βCP1≈16 μA / Iddx(≈8≈0.2*2.4 μm / 60 nm at fXTAL=16 MHz) βCP2≈8 μA / Iddx (≈4≈0.1*2.4 μm / 60 nm at fXTAL=16 MHz) αPN≈2.5 and the channel width divided by the channel length of the channel of T6 is 2*βBIAS.

[0069] These parameters may have a value in a range of 50% to 150% of the above nominal values. Preferably, these parameters may have a value in a range of 75% to 125% of the above nominal values, and even more preferably, these parameters may have a value in a range of 90% to 110% of the above nominal values.

[0070] In this way, the current source I1 of the current-controlled crystal oscillator circuit is Fig. 2, which operates in a timer mode, distributed the supplied current between the different blocks in the following way: the current I bias of the bias circuit is ≈0.5% of the current I1, the current I osc of the oscillator stage OSC is ≈97 % of the current I1, the current I cp1 of the current mode comparator CMC is ≈1 % of the current I1 and the current I cp2 of the output circuit OS is ≈0.1% of the current I1. The remaining 1% of the current I1 is consumed by the regulator (OA1).

[0071] Fig. 10, Fig. 11, Fig. 12 and Fig. 13 and Fig. 14 show simulation results of the current-controlled crystal oscillator circuit of Fig. 2, which operates in a timer mode. In Fig. 10, Fig. 11, Fig. 12 and Fig. 13 and Fig. 14 are the same results as in Fig. 5, Fig. 6, Fig. 7, Fig. 8 and Fig. 9, but each shown for the timer mode. In the simulations to obtain the results shown in Fig. 10, Fig. 11, Fig. 12 and Fig. 13 and Fig. 14, the current I varies ddx between 0.7 microamperes and 3 microamperes, the capacitors C6 and C8 have a capacitance of 8 picofarads and the circuit temperature operates at 25 degrees Celsius.

[0072] Fig. 15, Fig. 16, Fig. 17 and Fig. 18 also present simulation results of the current-controlled crystal oscillator circuit of Fig. 2, which operates in a timer mode. In Fig. 15, Fig. 16, Fig. 17 and Fig. 18 the horizontal axes represent the temperature in degrees Celsius. The vertical axes represent: in Fig. 15 V x1 and V x2 , represented in volts, in Fig. 16 the ratio of the stroke voltage, which is shown in volts, to Vddx, which is expressed in volts, in Fig. 17 the efficiency factor, which is determined by the ratio of the stroke voltage, expressed in volts, to the current I ddx , which is expressed in amperes, and in Fig. 18 shows the duty cycle of the output signal as provided by the level shifter L. For each of the four figures, three curves are shown for each parameter, representing simulation results for the nominal process corner and for the extreme values ​​of the processing corners: the so-called "fast" corner and the "slow" corner. At the slow corner, all process parameters are set to the processing limits, resulting in the slowest possible circuits.

[0073] Fig. 19 presents simulation results of the current-controlled crystal oscillator circuit of Fig. 2, which operates in a timer mode. In Fig. 19 the horizontal axis represents the temperature in degrees Celsius and the vertical axis represents the percentage of current I ddx which leads to current I OSC Three curves are also shown here.

[0074] During the simulations to obtain the results shown in Fig. 10-19, the current I ddx set to 1.5 microamperes, the capacitors C6 and C8 had a capacity of 8 picofarads and the circuit temperature exceeded the processing limits.

[0075] In summary, the design of the oscillator circuit shown can be optimized for three embodiments: Timer mode: the examples of the figures are: i osc = 2 µA; C6=C8≈8 pF; Vddx≈450 mV; Vx_pp[=peak-to-peak voltage across the crystal oscillator X1]≈0.7*Vddx; Phase noise (phase_noise)(10 kHz)≈−116 dBc / Hz; (iosc cannot be higher than 1 μA if C6 = C8≈3 pF (only parasitic interference effects); Transmitter / receiver (transceiver) mode: the examples in the figures are: Iosc=32 μA; 5 pF < C6=C8 <18 pF ; Vddx ≈750 mV; Vx_pp≈1.1*Vddx; Phase noise (phase_noise)(10 kHz)<−146 dBc / HzStart mode: Iosc=1 mA; C6=C8=18 pF; Vddx<1.4V; Vx_pp→accelerated start

[0076] The three embodiments described above, in which the Fig.2, which can operate in a transmitter / receiver mode, a timer mode, or an accelerated start mode, can be combined in a single circuit, wherein the circuit can comprise separate, different (transistor) elements in the oscillator circuit for each mode and suitably arranged switches arranged to connect or disconnect them from the rest of the oscillator circuit depending on the mode in which the circuit should operate. The circuit according to this embodiment can, for example, comprise two versions of the transistor T 10 , one with an area value of 10x and another with an area value of 0.15x, where 1x=2.4 µm / 60 nm. When the circuit operates in a transmitter / receiver mode, the transistor is independent of the two versions of T 10with an area value of 10x is the one that is connected to the circuit by means of these switches, while when the circuit operates in a timer mode, the transistor with an area of ​​0.15x is the one that is connected to the circuit by means of these switches.

[0077] It will be apparent to one skilled in the art that the scope of the invention is not limited to the examples discussed above, but that various changes and modifications thereof are possible without departing from the scope of the invention as defined in the appended claims. Although the invention has been shown and described in detail in the figures and description, such illustration and description are to be considered as illustrative or exemplary only and not restrictive. The present invention is not limited to the disclosed embodiments, but includes any combination of the disclosed embodiments which may obtain an advantage. The invention is limited only by the appended claims and their technical equivalents.

[0078] Variations to the disclosed embodiments may be understood and made by one skilled in the art in practicing the claimed invention, from a study of the figures, the description, and the appended claims. In the description and claims, the word "comprising" does not exclude other elements, and the indefinite article "a" or "an" does not exclude several. Indeed, it is to be construed as meaning "at least one." The mere fact that certain features are recited in mutually different dependent claims does not indicate that a combination of those features cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope of the invention.

Claims

[1] Oscillator circuit with an oscillator stage (OSC) and a first current source (I ddx ) which is designed to drive the oscillator stage (OSC), wherein the oscillator stage (OSC) comprises an oscillator stage input terminal, an oscillator stage output terminal, a crystal oscillator (X1) which is designed to supply an oscillation signal between the oscillator stage input terminal and the oscillator stage output terminal, wherein the crystal oscillator (X1) has a first oscillator terminal (x 11 ) and a second oscillator connection (x 12), wherein the oscillator circuit comprises an operational amplifier having an inverting input, a non-inverting input and an operational amplifier output, wherein the oscillator stage input terminal is coupled to the inverting input and the oscillator stage output terminal is coupled to the non-inverting input, and the operational amplifier output is coupled to the oscillator stage input terminal such that the oscillator stage input terminal and the oscillator stage output terminal are controlled to have an equal DC voltage level. [2] An oscillator circuit according to claim 1, further comprising a first capacitor (C6) connected to the oscillator stage input terminal and a second capacitor (Cs) connected to the oscillator stage output terminal. [3] An oscillator circuit according to claim 1 or 2, further comprising a third capacitor (C4) connected to the inverting input of the operational amplifier and a fourth capacitor (C5) connected to the non-inverting input of the operational amplifier. [4] Oscillator circuit according to one of claims 1-3, wherein the operational amplifier output is connected to the oscillator stage input terminal via a first resistor (R3). [5] Oscillator circuit according to one of claims 1-4, wherein the oscillator stage (OSC) comprises a series circuit of a first transistor (T7) and a second transistor (T8) connected at a first node, wherein the first transistor (T7) has a first gate (G7) and the second transistor (T8) has a second gate (G8), wherein the first gate (G7) and the second gate (G8) are connected to each other at a second node, wherein the second node is connected to the first oscillator terminal (x 11 ) of the crystal oscillator (X1) and the first node is connected to the second oscillator terminal (x 12 ) of the crystal oscillator (X1). [6] Oscillator circuit according to claim 5, wherein the series connection of the first transistor (T7) and the second transistor (T8) is designed such that an oscillator stage current (I osc ) from the first power source (I ddx ) is received. [7] Oscillator circuit according to claim 6, wherein one side of the series circuit of the first transistor (T7) and the second transistor (T8) is connected to the first current source (I ddx ) via a second resistor (R5), and another side of the series circuit of the first transistor (T7) and the second transistor (T8) is connected to ground via a third resistor (R6). [8] An oscillator circuit according to any one of the preceding claims, wherein the operational amplifier is arranged to receive electrical power from a third transistor (T6) arranged in a current mirror arrangement with a fourth transistor (T5) arranged in a bias circuit, such fourth transistor (T5) being arranged to conduct a predetermined DC bias current. [9] Oscillator circuit according to claim 8, wherein the bias circuit comprises a fifth transistor (T4) arranged in a diode arrangement in series with the fourth transistor (T5) and configured to receive current from the first current source (I ddx ) to receive. [10] Oscillator circuit according to one of the preceding claims, wherein the oscillator stage input terminal is connected either directly or indirectly to a current mode comparator (CMC), the current mode comparator (CMC) comprising a series circuit of a sixth transistor (T9) and a seventh transistor (T 10 ) connected at a third node, wherein the sixth transistor (T9) has a sixth transistor gate (G9) and the seventh transistor (T 10 ) a seventh transistor gate (G 10 ), wherein the sixth transistor gate (G9) and the seventh transistor (T 10) are connected to each other at a fourth node, wherein the fourth node is designed to receive an oscillation signal from the oscillator stage input terminal, and the series connection of the sixth transistor (T9) and the seventh transistor (T 10 ) is designed to receive current from the first current source (I ddx ) to receive. [11] Oscillator circuit according to claim 10, wherein the current mode comparator (CMC) has a current mode comparator output connected to an output circuit (OS), the output circuit (OS) comprising a series circuit of an eighth transistor (T 11 ) and a ninth transistor (T 12 ) connected at a fifth node, wherein the eighth transistor (T 11 ) an eighth transistor gate (G 11 ) and the ninth transistor (T 12 ) a ninth transistor gate (G 12 ), wherein the eighth transistor gate (G 11) and the ninth transistor (T 12 ) are connected to each other at a sixth node, wherein the sixth node is configured to receive a signal from the current mode comparator output, and the series connection of the eighth transistor (T 11 ) and the ninth transistor (T 12 ) is designed to receive current from the first current source (I ddx ) to receive. [12] Oscillator circuit according to claim 11, wherein the output circuit (OS) has an output circuit output connected to an input of a level converter (L) configured to convert a logic level of an output circuit output signal. [13] Oscillator circuit according to one of the preceding claims, wherein the oscillator circuit comprises a second resistor (R7) arranged in a series circuit with a first switch (SW2), wherein the series circuit of the second resistor (R7) and the first switch (SW2) is connected between the first oscillator terminal (x 11 ) and the second oscillator connection (x 12 ), wherein the oscillator circuit is designed to switch on the first switch (SW2) when the oscillator circuit starts up and to switch off the first switch (SW2) after a start-up phase. [14] Oscillator circuit according to claim 13, wherein the oscillator circuit comprises a series circuit of a second current source (I S ) and a power source switch (SW1), wherein the series connection of a second power source (I S ) and a current source switch (SW1) parallel to the first current source (I ddx ) is arranged.

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