Semiconductor device structure and methods for its fabrication

Abstract

Semiconductor device structure (1800, 2000) comprising: a first semiconductor substrate (110) having a surface (114) and a depression (116), wherein the depression (116) extends through the first semiconductor substrate (110); a first wiring layer (132) below the surface (114); a nickel layer (230) in the depression (116) extending to the first wiring layer (132) so that it is electrically connected to the first wiring layer (132); a gold layer (240) over the nickel layer (230); and a conductive ring structure (R1) between the first wiring layer (132) and the first semiconductor substrate (110), wherein the conductive ring structure (R1) surrounds the nickel layer (230) and is connected to the first wiring layer (132).

Description

BACKGROUND OF THE INVENTIONThe semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and fabricating ICs.In the course of IC evolution, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometric size (i.e., the smallest component or line that can be created with a fabrication process) has decreased. This downsizing process generally offers advantages of increasing productivity and decreasing corresponding costs.However, as the feature sizes continue to decrease, the fabrication processes become more and more difficult to perform. It is therefore a challenge to produce reliable semiconductor devices of ever smaller sizes.US 2013 / 0009270 A1 discloses a method for producing a bond pad on a semiconductor device. The method includes forming a recess in a semiconductor substrate and depositing the bond pad in the recess such that the bond pad is in direct contact with a metallic interconnect structure. A buffer layer and a passivation layer are deposited over the semiconductor device, which are then partially removed again to expose a portion of the bond pad.US 2011 / 0147933 A1 describes a method for producing a semiconductor package which has two regions with different types of contact pads, which are each part of a conductive via. A nickel-gold coating is applied to contact pads in the first region by means of an electrolytic coating method, while a nickel-palladium-gold coating is applied to contact pads in the second region by means of an electroless coating method.US 2005 / 0127529 A1 discloses a structure for reinforcing a bond pad on a via structure in a semiconductor device. The reinforcing structure has the same layer structure as the via structure, wherein conductive layers in the reinforcing structure and in the via structure are electrically connected to one another. The reinforcing structure may annularly surround the via structure.US 2005 / 0 003 677 A1 discloses methods for plating bond pads with nickel and gold layers.Brief Description of the DrawingsAspects of the present invention can best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with common practice in the industry, various elements are not drawn to scale. Rather, for clarity of discussion, the dimensions of the various elements may be arbitrarily increased or decreased.FIGS. 1A to 1L are sectional views of various stages of a process for manufacturing a semiconductor device structure, in accordance with some example embodiments. FIG. 1L- 1 is a top view of the bond pad, nickel layer, and gold layer of FIG. 1L, in accordance with some example embodiments. FIG. 1L- 2 is a top view of the bond pad, nickel layer, and gold layer of FIG. 1L, in accordance with some example embodiments. FIG. 1L- 3 is a top view of the bond pad, nickel layer, and gold layer of FIG. 1L, in accordance with some example embodiments. FIG. 2 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 3 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 4 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments.FIGS. 5A and 5B are cross-sectional views of various stages of a process for manufacturing a semiconductor device structure, in accordance with some example embodiments. FIG. 6 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 7 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 8 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 9 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 10 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 11 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 12 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 13 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 14 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 15 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 16 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 17 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 18A is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. FIG. 18B is a top view of a nickel layer, a conductive ring structure, and a portion of a wiring layer of the semiconductor device structure of FIG. 18A, in accordance with some embodiments. FIG. 19 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. FIG. 20 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.Detailed DescriptionThe present invention provides a semiconductor device structure having the features of claim 1 and a method of manufacturing a semiconductor device structure having the features of claim 13. Exemplary embodiments are given in the dependent claims.The following description provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, in the description below, the formation of a first element over or on a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, in the present invention, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Moreover, spatially relative terms such as "underlying", "under", "lower(r)" / "lower", "overlying", "upper(r)" / "upper" and the like may be used herein to easily describe the relationship of an element or feature to one or more other elements or features depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative descriptors used herein may also be interpreted accordingly. It should be appreciated that additional steps may be performed before, during, and after the method, and some of the described steps may be replaced with other embodiments of the method or may be omitted.FIGS. 1A to 1L are sectional views of various stages of a process for manufacturing a semiconductor device structure, in accordance with some example embodiments.As shown in FIG. 1A, in some embodiments, a semiconductor substrate 110 is provided. The semiconductor substrate 110 has surfaces 112 and 114 that are opposite to each other in some embodiments. The semiconductor substrate 110 is a semiconductor wafer (such as a silicon wafer) or a portion of a semiconductor wafer in some embodiments.In some embodiments, the semiconductor substrate 110 is made of an elemental semiconductor material comprising silicon or germanium in a single crystal, polycrystal, or amorphous structure. In some other embodiments, the semiconductor substrate 110 is made of a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor such as SiGe or GaAsP, or a combination thereof. The semiconductor substrate 110 may also include multilayer semiconductors, semiconductors on insulator (SOI) (such as silicon on insulator or germanium on insulator), or a combination thereof.As shown in FIG. 1A, in some embodiments, the surface 114 has a recess 114 a. As shown in FIG. 1A, in some embodiments, an insulating layer 10 is formed in the recess 114 a. The insulating layer 10 is filled in the recess 114 ain some embodiments.In some embodiments, the insulating layer 10 is made of a suitable insulating material, such as hydrogenated silicon oxide carbide (SiCO:H), silicon oxynitride, silicon oxide, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphorosilicate glass (BPSG), fluorosilicate glass (FSG), a low-k material, a porous dielectric material, or a combination thereof.As shown in FIG. 1A, in some embodiments, a dielectric layer 120 is deposited on the surface 114 and the insulating layer 10. The dielectric layer 120 includes dielectric layers stacked on top of each other (not shown) in some embodiments.The dielectric layer 120 is made of a suitable dielectric material, such as hydrogenated silicon oxide carbide (SiCO:H), silicon oxynitride, silicon oxide, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), a low-k material, a porous dielectric material, or a combination thereof, in some embodiments. The dielectric layer 120 is deposited by a suitable method, such as CVD, HDPCVD, spin-on, sputtering, or a combination thereof, in some embodiments.As shown in FIG. 1A, in some embodiments, wiring layers 132 and 134 are formed in the dielectric layer 120. In some embodiments, a wiring layer 136 is embedded in the dielectric layer 120. The wiring layer 136 is exposed from the dielectric layer 120 in some embodiments. The wiring layers 132, 134, and 136 are made of a suitable conductive material, such as copper, a copper alloy, silver, gold, aluminum, or a combination thereof.As shown in FIG. 1A, conductive via structures (via structure) 142 and 144 are formed in dielectric layer 120 in some embodiments. The conductive via structures 142 electrically connect the wiring layer 132 to the wiring layer 134, in some embodiments. In some embodiments, the via structures 144 electrically connect the wiring layer 134 to the wiring layer 136.As shown in FIG. 1B, in some embodiments, the semiconductor substrate 110 is inverted. As shown in FIG. 1B, a semiconductor substrate 250 is provided in some embodiments. The semiconductor substrate 250 is a semiconductor wafer (such as a silicon wafer) or a portion of a semiconductor wafer in some embodiments. In some embodiments, the semiconductor substrate 250 is made of an elemental semiconductor material comprising silicon or germanium in a single crystal, polycrystal, or amorphous structure.In some other embodiments, the semiconductor substrate 250 is made of a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor such as SiGe or GaAsP, or a combination thereof. The semiconductor substrate 250 may also include multilayer semiconductors, semiconductors on insulator (SOI) (such as silicon on insulator or germanium on insulator), or a combination thereof.As shown in FIG. 1B, in some embodiments, a dielectric layer 260 is deposited over the semiconductor substrate 250. The dielectric layer 260 is a multilayer structure in some embodiments. The dielectric layer 260 includes dielectric layers stacked on top of each other (not shown) in some embodiments.The dielectric layer 260 is made of a suitable dielectric material, such as hydrogenated silicon oxide carbide (SiCO:H), silicon oxynitride, silicon oxide, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), a low-k material, a porous dielectric material, or a combination thereof, in some embodiments. The dielectric layer 260 is deposited by a suitable method, such as CVD, HDPCVD, spin-on, sputtering, or a combination thereof, in some embodiments.As shown in FIG. 1B, in some embodiments, wiring layers 272, 274, and 276 are formed in the dielectric layer 260. In some embodiments, a wiring layer 278 is embedded in the dielectric layer 260. The wiring layer 278 is exposed by the dielectric layer 260 in some embodiments. The wiring layers 272, 274, 276, and 278 are made of a suitable conductive material, such as copper, a copper alloy, silver, gold, aluminum, or a combination thereof.As shown in FIG. 1B, conductive via structures 282, 284, and 286 are formed in dielectric layer 260, in some embodiments. The conductive via structures 282 electrically connect the wiring layer 272 to the wiring layer 274 in some embodiments. In some embodiments, the via structures 284 electrically connect the wiring layer 274 to the wiring layer 276.The conductive via structures 286 electrically connect the wiring layer 276 to the wiring layer 278 in some embodiments. The semiconductor substrate 250, the dielectric layer 260, the wiring layers 272, 274, 276, and 278, and the conductive via structures 282, 284, and 286 collectively form a wiring substrate S in some embodiments.As shown in FIG. 1B, in some embodiments, the dielectric layers 260 and 120 are connected to each other. In some embodiments, the wiring layers 278 and 136 are connected to each other. In some embodiments, the wiring layers 278 and 136 are electrically connected to each other.As shown in FIG. 1B, in some embodiments, a dielectric layer 150 is formed on the surface 112. The dielectric layer 150 is a transparent layer in some embodiments. The dielectric layer 150 includes a high-k material in some embodiments. The dielectric layer 150 includes an oxide and / or a nitride in some embodiments.The dielectric layer 150 includes silicon oxide, silicon nitride, and / or silicon oxynitride in some embodiments. The dielectric layer 150 is deposited by a suitable method, such as CVD, HDPCVD, spin-on, sputtering, or a combination thereof, in some embodiments.As shown in FIG. 1C, in some embodiments, portions of the dielectric layer 150 and the semiconductor substrate 110 are removed. In some embodiments, an opening 152 and a recess 116 are formed after removal. The opening 152 passes through the dielectric layer 150 in some embodiments.In some embodiments, the recess 116 is formed in the semiconductor substrate 110 from the surface 112. The recess 116 extends through the semiconductor substrate 110, in some embodiments. The recess 116 exposes a portion of the insulating layer 10 in some embodiments. In some embodiments, the removal process includes a photolithography process and an etching process.As shown in FIG. 1C, in some embodiments, an insulating layer 160 is formed over the dielectric layer 150 to cover the sidewalls 152 aof the opening 152 as well as the sidewalls 116 aand the bottom surface 116 bof the recess 116. The insulating layer 160 is in direct contact with the insulating layer 10 in some embodiments. the insulating layer 160 includes an oxide, such as silicon oxide.As shown in FIG. 1D, in some embodiments, portions of the insulating layer 160, the insulating layer 10, and the dielectric layer 120 are removed. After removal, openings 162 and vias 10a are formed in some embodiments. The openings 162 pass through the insulating layer 160 in some embodiments. The contact holes 10 apass through the insulating layer 10 and penetrate into the dielectric layer 120 to expose the wiring layer 132, in some embodiments. The removal process includes a photolithography process and an etching process.As shown in FIG. 1E, in some embodiments, a bond pad 180 is formed on the bottom surface 116 bof the recess 116 to extend into the contact holes 10 ato electrically connect them to the wiring layer 132. The bond pad 180 comprises a conductive material in some embodiments. The bond pad 180 comprises aluminum or copper in some embodiments. The bond pad 180 is formed using a physical vapor deposition process, a photolithography process, and an etching process, in some embodiments.As shown in FIG. 1F, in some embodiments, the insulating layer 160 on the top surface 154 of the dielectric layer 150 is removed. The insulating layer 160 in the recess 116 and the opening 152 exposed by the bond pad 180 is thinned in some embodiments. The removal and thinning of the insulating layer 160 includes an anisotropic etching process in some embodiments. In some embodiments, the anisotropic etching process includes a dry etching process.As shown in FIG. 1G, in some embodiments, a dielectric fill layer 190 is formed in the recess 116. The dielectric fill layer 190 is filled in the recess 116, the opening 152, and the contact holes 10 ain some embodiments. The formation of the dielectric fill layer 190 includes a deposition process and a chemical mechanical polishing process, in some embodiments. The dielectric fill layer 190 comprises an oxide (e.g., silicon oxide) or other suitable dielectric material.As shown in FIG. 1H, in some embodiments, an opaque layer 210 is formed on the top surface 154 of the dielectric layer 150. The opaque layer 154 includes light blocking portions 212 and mesh portions 214 in some embodiments. The light blocking portions 212 are configured to block the light from reaching light sensitive elements (e.g., photodiodes) over or in the semiconductor substrate 110, in some embodiments. The grating portions 214 are configured to direct the light to the light-sensitive elements (e.g., photodiodes) over or within the semiconductor substrate 110, in some embodiments.As shown in FIG. 11, in some embodiments, portions of the dielectric layer 150 between the grid portions 214 or between the grid portion 214 and the light blocking portion 212 are removed. The removal, in some embodiments, creates depressions 156 in the dielectric layer 150 and between the grid parts 214 or between the grid part 214 and the light-blocking part 212.In some embodiments, a passivation layer (not shown) is formed over the opaque layer 210, the dielectric layer 150, the insulating layer 160, and the dielectric fill layer 190. The passivation layer includes an insulating material in some embodiments.As shown in FIG. 1J, in some embodiments, a portion of the dielectric fill layer 190 is removed. The removal, in some embodiments, creates an opening 192 in the dielectric fill layer 190. In some embodiments, the opening 192 exposes the bond pad 180 over the bottom surface 116 b(or the insulating layer 10).As shown in FIG. 1K, in some embodiments, a nickel layer 230 is formed over the bond pad 180. The nickel layer 230 contains nickel as a main component in some embodiments. The nickel layer 230 contains at least 60% by mass nickel in some embodiments. The nickel layer 230 contains at least 80 mass % nickel in some embodiments.In some embodiments, the nickel layer 230 is in the opening 192. In some embodiments, the entire nickel layer 230 is in the opening 192. In some embodiments, the nickel layer 230 does not extend beyond the opening 192. In some embodiments, the nickel layer 230 is substantially planar.The nickel layer 230 is formed using an electroless plating process in some embodiments. In electroless plating, in some embodiments, the nickel layer 230 may be selectively deposited on the metal layer (i.e., the bond pad 180). Therefore, in some embodiments, the nickel layer 230 is formed without using a photolithography process and an etching process.As shown in FIG. 1L, in some embodiments, a gold layer 240 is formed over the nickel layer 230. The gold layer 240 contains gold as a main constituent in some embodiments. The gold layer 240 contains at least 60% by mass gold in some embodiments. The gold layer 240 contains at least 80 mass % gold in some embodiments.The gold layer 240 is formed using an immersion plating process in some embodiments. In some embodiments, the gold layer 240 and the nickel layer 230 do not extend to the surface 112. In some embodiments, the gold layer 240 and the entire nickel layer 230 are in the opening 192. In some embodiments, the thickness T 1 of the nickel layer 230 is greater than the thickness T 2 of the gold layer 240.In some embodiments, the material of the bond pad 180 is different from the material of the nickel layer 230 and the gold layer 240. Since the modulus of elasticity of nickel is greater than that of the material of the bond pad 180 (e.g., copper or aluminum), at the same normal stress, the normal stress on nickel is less than that of the material of the bond pad 180 (e.g., copper or aluminum).Thus, the formation of the nickel layer 230 prevents the bond pad 180 from being peeled off during a subsequent wire draw test or ball shear test. Since the hardness of gold is lower than that of nickel, the gold layer 240 compensates for the bonding voltage generated by a wire bonding process or a nail head bonding process performed subsequently. In some embodiments, in this step, the semiconductor device structure 100 is formed in substantial portions.In plan view, the bond pad 180 may have other shapes, and the nickel layer 230 and the gold layer 240 are formed only over the bond pad 180 exposed by the opening 192. Examples of a bond pad 180 having other shapes are shown in FIGS. 1L-1, 1L-2, and 1L-3.FIG. 1L- 1 is a top view of the bond pad 180, the nickel layer 230, and the gold layer 240 of FIG. 1L, in accordance with some embodiments. FIG. 1L is a cross-sectional view illustrating the bond pad 180, the nickel layer 230, and the gold layer 240 along a line of intersection I-I of FIG. 1L-1, in accordance with some embodiments. As shown in FIGS. 1L and 1L-1, the bond pad 180 has an island-like shape, and the nickel layer 230 and the gold layer 240 are formed over the bond pad 180.FIG. 1L- 2 is a top view of the bond pad 180, the nickel layer 230, and the gold layer 240 of FIG. 1L, in accordance with other embodiments. FIG. 1L is a cross-sectional view illustrating the bond pad 180, the nickel layer 230, and the gold layer 240 along a line of intersection I-I of FIGS. 1L-2, in accordance with some embodiments. As shown in FIGS. 1L and 1L- 2, in some embodiments, the bond pad 180 has strip-shaped portions 182 spaced apart from each other. In some embodiments, the nickel layer 230 and the gold layer 240 are formed over the strip-shaped portions 182.FIG. 1L- 3 is a top view of the bond pad 180, the nickel layer 230, and the gold layer 240 of FIG. 1L, in accordance with still further embodiments. FIG. 1L is a cross-sectional view illustrating the bond pad 180, the nickel layer 230, and the gold layer 240 along a line of intersection I-I of FIGS. 1L-3, in accordance with some embodiments. As shown in FIGS. 1L and 1L- 3, in some embodiments, the bond pad 180 has a ring shape. In some embodiments, the nickel layer 230 and the gold layer 240 are formed over the bond pad 180.FIG. 2 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 2, in some embodiments, the semiconductor device structure 100 further includes a palladium layer 290. The palladium layer 290 is formed between the nickel layer 230 and the gold layer 240 in some embodiments. The palladium layer 290 is formed using an electroless plating process in some embodiments.In some embodiments, the palladium has physical properties similar to gold and is less expensive than gold. Thus, in some embodiments, the formation of the palladium layer 290 reduces the amount of gold used to form the gold layer 240. Thus, in some embodiments, the manufacturing cost of the semiconductor device structure 100 is decreased by forming the palladium layer 290.FIG. 3 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 3, in some embodiments, the semiconductor device structure 100 further includes a conductive wire 310 connecting the gold layer 240 to a bond pad 320. The conductive wire 310 includes gold, aluminum, or other suitable conductive material. In some embodiments, the bond pad 320 is positioned over a substrate 330. The bond pad 320 comprises a conductive material, such as copper or aluminum, in some embodiments.The substrate 330 includes a semiconductor material, a plastic material, a metal material, a glass material, a ceramic material, or another suitable material. In some embodiments, an adhesion layer 340 is formed between the semiconductor substrate 250 and the substrate 330. The adhesion layer 340 comprises a polymeric material in some embodiments. In some other embodiments, the semiconductor substrate 250 is not over the substrate 330.FIG. 4 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 4, in some embodiments, the semiconductor device structure 100 further includes a conductive bump 410 over the gold layer 240. The conductive bump 410 is electrically connected to the gold layer 240 in some embodiments. The conductive bump 410 includes a conductive material in some embodiments. The conductive bump 410 includes a solder material such as tin (Sn) and copper (Cu), in some embodiments.In some embodiments, the semiconductor device structure 100 does not have a bond pad 180, and is described in detail as follows by way of example.FIGS. 5A and 5B are cross-sectional views of various stages of a process for manufacturing a semiconductor device structure, in accordance with some example embodiments. In some embodiments, after the step of FIG. 1B, portions of the dielectric layer 150 and the semiconductor substrate 110 are removed, as shown in FIG. 5A. After removal, in some embodiments, an opening 152 and a recess 116 are formed.In some embodiments, the recess 152 extends through the dielectric layer 150. In some embodiments, the recess 116 is formed in the semiconductor substrate 110 from the surface 112. The recess 116 extends through the semiconductor substrate 110, in some embodiments. The recess 116 exposes a portion of the insulating layer 10 in some embodiments. In some embodiments, the removal process includes a photolithography process and an etching process.As shown in FIG. 5A, in some embodiments, an insulating layer 160 is formed in the opening 152 and the recess 116. The insulating layer 160 is in direct contact with the insulating layer 10 in some embodiments. the insulating layer 160 includes an oxide, such as silicon oxide.As shown in FIG. 5A, in some embodiments, the steps of FIGS. 1H through 11 are performed to form an opaque layer 210 and recesses 156. In some embodiments, the opaque layer 210 is formed on the top surface 154 of the dielectric layer 150.The opaque layer 210 has light blocking portions 212 and mesh portions 214 in some embodiments. As shown in FIG. 5A, depressions 156 are formed in the dielectric layer 150 and between the grid portions 214 or between the grid portion 214 and the light blocking portion 212 in some embodiments.As shown in FIG. 5B, in some embodiments, portions of the insulating layers 160 and 10 and the dielectric layer 120 are removed. In some embodiments, a via hole H and an opening 122 are formed after the removal. Via hole H passes through insulating layers 160 and 10, in some embodiments.The opening 122 is in the dielectric layer 120 and below the recess 116, in some embodiments. In some embodiments, the opening 122 is connected to the via hole H. The opening 122 and the through hole H together expose a part of the wiring layer 132 in some embodiments. The removing includes a photolithography process and an etching process.As shown in FIG. 5B, in some embodiments, a nickel layer 230 is formed in the via hole H and the opening 122. The opening 122 is filled with the nickel layer 230 in some embodiments. The via hole H is partially filled with the nickel layer 230 in some embodiments. In some other embodiments, the via hole H is filled with the nickel layer 230.In some embodiments, the nickel layer 230 is electrically connected to the wiring layer 132. The nickel layer 230 is in direct contact with the wiring layer 132 in some embodiments. In some embodiments, the nickel layer 230 is in direct contact with the insulating layers 160 and 10 and the dielectric layer 120.In some embodiments, the nickel layer 230 is formed using an electroless plating process. The nickel layer 230 contains nickel as a main component in some embodiments. The nickel layer 230 contains at least 60% by mass nickel in some embodiments. The nickel layer 230 contains at least 80 mass % nickel in some embodiments.As shown in FIG. 5B, in some embodiments, a gold layer 240 is formed over the nickel layer 230. The gold layer 240 contains gold as a main constituent in some embodiments. The gold layer 240 contains at least 60% by mass gold in some embodiments.The gold layer 240 contains at least 80 mass % gold in some embodiments. The gold layer 240 is formed using an immersion plating process in some embodiments. In some embodiments, the gold layer 240 and the nickel layer 230 do not extend to the surface 112. In this step, the semiconductor device structure 500 is formed in substantial parts, according to some embodiments.FIG. 6 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 6, in some embodiments, the semiconductor device structure 500 further comprises a palladium layer 290. The palladium layer 290 is formed between the nickel layer 230 and the gold layer 240 in some embodiments. The palladium layer 290 is in direct contact with the insulating layer 160 in some embodiments. The palladium layer 290 is formed using an electroless plating process in some embodiments.FIG. 7 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 7, in some embodiments, the semiconductor device structure 500 further includes a conductive wire 310 connecting the gold layer 240 to a bond pad 320. The conductive wire 310 is in direct contact with the gold layer 240 and the bond pad 320, in some embodiments. In some embodiments, bond pad 320 is positioned over a substrate 330. The bond pad 320 comprises a conductive material, such as copper or aluminum, in some embodiments.The substrate 330 includes a semiconductor material, a plastic material, a metal material, a glass material, a ceramic material, or another suitable material. In some embodiments, an adhesion layer 340 is formed between the semiconductor substrate 250 and the substrate 330. The adhesion layer 340 comprises a polymeric material in some embodiments. In some other embodiments, the semiconductor substrate 250 is not over the substrate 330.FIG. 8 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 8, in some embodiments, the semiconductor device structure 100 further includes a conductive bump 410 over the gold layer 240. The conductive bump 410 is electrically connected to the gold layer 240 in some embodiments.The conductive bump 410 is in direct contact with the gold layer 240 in some embodiments. The conductive bump 410 includes a conductive material in some embodiments. The conductive bump 410 includes a solder material such as tin (Sn) and copper (Cu), in some embodiments.FIG. 9 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 9, a semiconductor device structure 900 is similar to the semiconductor device structure 100 of FIG. 1L, except that in some embodiments, the semiconductor device structure 900 further includes a dielectric layer 910, a passivation layer 920, a dielectric layer 930, a passivation layer 940, an insulating layer 950, and a conductive via structure 960.The dielectric layer 910 is formed over the dielectric layer 120 and the wiring layer 136, in some embodiments. Dielectric layers 910 and 120 have the same material in some embodiments. In some embodiments, the passivation layer 920 is formed over the dielectric layer 910. The passivation layer 920 includes an oxide (e.g., silicon oxide) or a nitride in some embodiments.The wiring substrate S further includes the dielectric layer 930 and the passivation layer 940 in some embodiments. The dielectric layer 930 is formed over the wiring layer 278 and the dielectric layer 260 in some embodiments.The dielectric layers 930 and 260 have the same material in some embodiments. In some embodiments, the passivation layer 940 is formed over the dielectric layer 930. The passivation layer 940 includes an oxide (e.g., silicon oxide) or a nitride in some embodiments. Passivation layers 920 and 940 are connected together in some embodiments.As shown in FIG. 9, in some embodiments, a via hole H 1 passes through the dielectric layer 150, the semiconductor substrate 110, and the insulating layer 10. As shown in FIG. 9, in some embodiments, the insulating layer 950 is formed on an inner wall W 1 of the through hole H 1. The insulating layer 950 includes an oxide, such as silicon oxide, in some embodiments.As shown in FIG. 9, in some embodiments, a via hole H 2 passes through the dielectric layer 120. As also shown in FIG. 9, in some embodiments, the wiring layer 136 has an opening 136 abetween the via hole H 1 and the wiring layer 278.As shown in FIG. 9, in some embodiments, a via hole H 3 passes through the dielectric layer 910, the passivation layer 920, the dielectric layer 930, and the passivation layer 940. The via holes H 1, H 2, and H 3 expose a portion of the wiring layer 278 in some embodiments. The through holes H 1, H 2, and H 3 and the opening 136 acommunicate (or are connected) with each other in some embodiments.In some embodiments, the conductive via structure 960 is formed in the vias H 1, H 2, and H 3 and the opening 136 a. In some embodiments, via holes H 1, H 2, and H 3 and opening 136 aare filled with conductive via pattern 960. The conductive via structure 960 passes through the dielectric layer 150, the semiconductor substrate 110, the insulating layer 10, the dielectric layer 120, the dielectric layer 910, the passivation layer 920, the passivation layer 940, and the dielectric layer 930 sequentially in some embodiments.In some embodiments, the conductive via structure 960 electrically connects the wiring layer 136 to the wiring layer 278. In some embodiments, the conductive via structure 960 includes a conductive material. The conductive material includes tungsten, aluminum, copper, or other suitable conductive material.FIG. 10 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 10, in some embodiments, the semiconductor device structure 900 further includes a palladium layer 290. The palladium layer 290 is formed between the nickel layer 230 and the gold layer 240 in some embodiments. The palladium layer 290 is formed using an electroless plating process in some embodiments.FIG. 11 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 11, in some embodiments, the semiconductor device structure 900 further includes a conductive wire 310 connecting the gold layer 240 to a bond pad 320. In some embodiments, the bond pad 320 is positioned over a substrate 330. The bond pad 320 comprises a conductive material, such as copper or aluminum, in some embodiments.The substrate 330 includes a semiconductor material, a plastic material, a metal material, a glass material, a ceramic material, or another suitable material. In some embodiments, an adhesion layer 340 is formed between the semiconductor substrate 250 and the substrate 330. The adhesion layer 340 comprises a polymeric material in some embodiments. In some other embodiments, the semiconductor substrate 250 is not over the substrate 330.FIG. 12 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 12, in some embodiments, the semiconductor device structure 900 further includes a conductive bump 410 over the gold layer 240. The conductive bump 410 is electrically connected to the gold layer 240 in some embodiments.The conductive bump 410 is in direct contact with the gold layer 240 in some embodiments. The conductive bump 410 includes a conductive material in some embodiments. The conductive bump 410 includes a solder material such as tin (Sn) and copper (Cu), in some embodiments.FIG. 13 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 13, a semiconductor device structure 1300 is similar to the semiconductor device structure 500 of FIG. 5B, except that in some embodiments, the semiconductor device structure 1300 further includes a dielectric layer 910, a passivation layer 920, a dielectric layer 930, a passivation layer 940, an insulating layer 950, and a conductive via structure 960.The dielectric layer 910 is formed over the dielectric layer 120 and the wiring layer 136, in some embodiments. Dielectric layers 910 and 120 have the same material in some embodiments. In some embodiments, the passivation layer 920 is formed over the dielectric layer 910. The passivation layer 920 includes an oxide (e.g., silicon oxide) or a nitride in some embodiments.As shown in FIG. 13, in some embodiments, the wiring substrate S further includes the dielectric layer 930 and the passivation layer 940. The dielectric layer 930 is formed over the wiring layer 278 and the dielectric layer 260 in some embodiments.The dielectric layers 930 and 260 have the same material in some embodiments. In some embodiments, the passivation layer 940 is formed over the dielectric layer 930. The passivation layer 940 includes an oxide (e.g., silicon oxide) or a nitride in some embodiments. Passivation layers 920 and 940 are connected together in some embodiments.As shown in FIG. 13, in some embodiments, a via hole H 1 passes through the dielectric layer 150, the semiconductor substrate 110, and the insulating layer 10. As shown in FIG. 13, in some embodiments, the insulating layer 950 is formed on an inner wall W 1 of the through hole H 1. The insulating layer 950 includes an oxide, such as silicon oxide, in some embodiments.As shown in FIG. 13, in some embodiments, a via hole H 2 passes through the dielectric layer 120. As also shown in FIG. 13, in some embodiments, the wiring layer 136 has an opening 136 abetween the via hole H 1 and the wiring layer 278.As shown in FIG. 13, in some embodiments, a via hole H 3 passes through the dielectric layer 910, the passivation layer 920, the dielectric layer 930, and the passivation layer 940. In some embodiments, the via holes H 1, H 2, and H 3 and the opening 136 atogether expose a portion of the wiring layer 278. The through holes H 1, H 2, and H 3 and the opening 136 acommunicate (or are connected) with each other in some embodiments.In some embodiments, the conductive via structure 960 is formed in the vias H 1, H 2, and H 3 and the opening 136 a. In some embodiments, via holes H 1, H 2, and H 3 and opening 136 aare filled with conductive via pattern 960.The conductive via structure 960 passes through the dielectric layer 150, the semiconductor substrate 110, the insulating layer 10, the dielectric layer 120, the dielectric layer 910, the passivation layer 920, the passivation layer 940, and the dielectric layer 930 sequentially in some embodiments.In some embodiments, the conductive via structure 960 electrically connects the wiring layer 136 to the wiring layer 278. In some embodiments, the conductive via structure 960 includes a conductive material. The conductive material includes tungsten, aluminum, copper, or other suitable conductive material.FIG. 14 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 14, in some embodiments, the semiconductor device structure 1300 further includes a palladium layer 290. The palladium layer 290 is formed between the nickel layer 230 and the gold layer 240 in some embodiments. The palladium layer 290 is formed using an electroless plating process in some embodiments.FIG. 15 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 15, in some embodiments, the semiconductor device structure 1300 further includes a conductive wire 310 connecting the gold layer 240 to a bond pad 320. In some embodiments, the bond pad 320 is positioned over a substrate 330. The bond pad 320 comprises a conductive material, such as copper or aluminum, in some embodiments.The substrate 330 includes a semiconductor material, a plastic material, a metal material, a glass material, a ceramic material, or another suitable material. In some embodiments, an adhesion layer 340 is formed between the semiconductor substrate 250 and the substrate 330. The adhesion layer 340 comprises a polymeric material in some embodiments. In some other embodiments, the semiconductor substrate 250 is not over the substrate 330.FIG. 16 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 16, in some embodiments, the semiconductor device structure 1300 further includes a conductive bump 410 over the gold layer 240. The conductive bump 410 is electrically connected to the gold layer 240 in some embodiments. The conductive bump 410 includes a conductive material in some embodiments. The conductive bump 410 includes a solder material such as tin (Sn) and copper (Cu), in some embodiments.FIG. 17 is a cross-sectional view of a semiconductor device structure 1700, in accordance with some example embodiments. As shown in FIG. 17, the semiconductor device structure 1700 is similar to the semiconductor device structure 1300 of FIG. 16, except that in some embodiments the semiconductor device structure 1700 further includes a thick wiring layer 1710 below the nickel layer 230.The nickel layer 230 is in direct contact with the thick wiring layer 1710, in some embodiments. The nickel layer 230 is electrically connected to the thick wiring layer 1710 in some embodiments. The thick wiring layer 1710 is adjacent to the wiring layers 132 and 134 and the conductive via structure 142, in some embodiments.The thick wiring layer 1710 has a thickness T 1 in some embodiments. The wiring layer 132 has a thickness T 2 in some embodiments. The conductive via structure 142 has a thickness T 3 in some embodiments. The wiring layer 134 has a thickness T 4 in some embodiments. The thickness T 1 is greater than the thickness T 2, T 3, or T 4 in some embodiments. The thickness T 1 is greater than or equal to the sum of the thicknesses T 2, T 3, and T 4 in some embodiments.Via H may be overetched into thick wiring layer 1710. Since the thick wiring layer 1710 has a large thickness T 1, the via hole H is prevented from passing through the thick wiring layer 1710. Thus, by forming the thick wiring layer 1710, the performance of the semiconductor device structure 1700 is improved.FIG. 18A is a cross-sectional view of a semiconductor device structure 1800, in accordance with some embodiments. FIG. 18B is a top view of a nickel layer 320, a conductive ring structure R 1, and a portion of a wiring layer 132 of the semiconductor device structure 1800, in accordance with some embodiments.As shown in FIGS. 18A and 18B, the semiconductor device structure 1800 is similar to the semiconductor device structure 1300 of FIG. 16, except that in some embodiments the semiconductor device structure 1800 continues to have conductive ring structures R 1, R 2, and R 3.The conductive ring structure R 1 is formed in the dielectric layer 120 and over the wiring layer 132, in some embodiments. The conductive ring structure R 1 is connected to the wiring layer 132 in some embodiments. The conductive ring structure R 2 is formed in the dielectric layer 120 and between the wiring layers 132 and 134, in some embodiments.The conductive ring structure R 2is connected to the wiring layers 132 and 134 in some embodiments. The conductive ring structure R 3 is formed in the dielectric layer 120 and between the wiring layers 134 and 136, in some embodiments. The conductive ring structure R 3 is connected to the wiring layers 134 and 136 in some embodiments. The conductive ring structures R 1, R 2, and R 3 and the wiring layers 132 and 134 are made of the same material in some embodiments.In some embodiments, the conductive ring structures R 1, R 2, and R 3 and the wiring layers 132 and 134 have openings P 1, P 2, P 3, 132A, and 134 a, respectively. The openings P 1, P 2, P 3, 132A, and 134 aare connected to each other in some embodiments. The nickel layer 230 extends further into the openings P 1, P 2, P 3, 132A, and 134a in some embodiments. The conductive ring structures R 1, R 2, and R 3 and the wiring layers 132 and 134 surround the nickel layer 230 in some embodiments.In some embodiments, the conductive ring structures R 1, R 2, and R 3 and the wiring layers 132 and 134 together prevent the electrolyte (for forming the nickel layer 230) from diffusing into the dielectric layer 230. Thereby, in some embodiments, the performance of the semiconductor device structure 1800 is improved.FIG. 19 is a cross-sectional view of a semiconductor device structure, in accordance with some example embodiments. As shown in FIG. 19, in some embodiments, the semiconductor device structure 1900 is similar to the semiconductor device structure 1700 of FIG. 17, except that the semiconductor device structure 1900 further includes a conductive wire 310 connecting the gold layer 240 to a bond pad 320, and the semiconductor device structure 1900 does not include the conductive bump 410.In some embodiments, the bond pad 320 is positioned over a substrate 330. The bond pad 320 comprises a conductive material, such as copper or aluminum, in some embodiments. The substrate 330 includes a semiconductor material, a plastic material, a metal material, a glass material, a ceramic material, or another suitable material.In some embodiments, an adhesion layer 340 is formed between the semiconductor substrate 250 and the substrate 330. The adhesion layer 340 comprises a polymeric material in some embodiments. In some other embodiments, the semiconductor substrate 250 is not over the substrate 330.FIG. 20 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. As shown in FIG. 20, in some embodiments, the semiconductor device structure 2000 is similar to the semiconductor device structure 1800 of FIG. 18A, except that the semiconductor device structure 2000 further includes a conductive wire 310 connecting the gold layer 240 to a bond pad 320, and the semiconductor device structure 2000 does not include the conductive bump 410.In some embodiments, the bond pad 320 is positioned over a substrate 330. The bond pad 320 comprises a conductive material, such as copper or aluminum, in some embodiments. The substrate 330 includes a semiconductor material, a plastic material, a metal material, a glass material, a ceramic material, or another suitable material.In some embodiments, an adhesion layer 340 is formed between the semiconductor substrate 250 and the substrate 330. The adhesion layer 340 comprises a polymeric material in some embodiments. In some other embodiments, the semiconductor substrate 250 is not over the substrate 330.In some embodiments, semiconductor device structures and methods for their fabrication are provided. In the methods (for manufacturing the semiconductor device structure), a nickel layer is formed over a bond pad to prevent the bond pad from becoming detached. In the methods, a gold layer is formed over the nickel layer to equalize the bonding voltage generated by a wire bonding process or a nail head bonding process. Thus, the formation of the nickel layer and the gold layer improves the reliability of the semiconductor device structure.In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor substrate having a first surface, a second surface, and a recess. The second surface is opposite the first surface. The depression runs through the first semiconductor substrate. The semiconductor device structure includes a first wiring layer on the second surface. The semiconductor device structure includes a first bond pad in the recess that extends to the first wiring layer to be electrically connected to the first wiring layer. The semiconductor device structure includes a nickel layer over the first bond pad. The semiconductor device structure includes a gold layer over the nickel layer.In some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor substrate having a surface and a recess. The depression runs through the first semiconductor substrate. The semiconductor device structure includes a first wiring layer on the surface. The semiconductor device structure includes a nickel layer in the recess that extends to the first wiring layer so as to be electrically connected to the first wiring layer. The semiconductor device structure includes a gold layer over the nickel layer.In some embodiments, a method of manufacturing a semiconductor device structure is provided. The method includes providing a first semiconductor substrate having a surface. The method includes forming a first wiring layer on the surface. The method includes forming a recess in the first semiconductor substrate. The recess passes through the first semiconductor substrate to expose the first wiring layer. The method includes forming a first bond pad in the recess. The first bond pad extends to the first wiring layer to be electrically connected to the first wiring layer. The method includes forming a nickel layer over the first bond pad. The method includes forming a gold layer over the nickel layer.

Claims

A semiconductor device structure (1800, 2000), comprising: a first semiconductor substrate (110) having a surface (114) and a recess (116), the recess (116) extending through the first semiconductor substrate (110); a first wiring layer (132) below the surface (114); a nickel layer (230) in the recess (116) extending to the first wiring layer (132) to be electrically connected to the first wiring layer (132); a gold layer (240) over the nickel layer (230); and a conductive ring structure (R1) between the first wiring layer (132) and the first semiconductor substrate (110), the conductive ring structure (R1) surrounding the nickel layer (230) and being connected to the first wiring layer (132).The semiconductor device structure (1800, 2000) of claim 1, further comprising: a dielectric layer (120) on the surface (114), wherein the first wiring layer (132) is in the dielectric layer (120), the dielectric layer (120) has an opening (122) below the recess (116) and exposes a portion of the first wiring layer (132), and the opening (122) is filled with the nickel layer (230).The semiconductor device structure (1800, 2000) of claim 1 or 2, wherein the nickel layer (230) is in direct contact with the first wiring layer (132).The semiconductor device structure (1800, 2000) of any preceding claim, further comprising a palladium layer (290) between the nickel layer (230) and the gold layer (240).The semiconductor device structure of any preceding claim, further comprising: a second wiring layer (132, 134) below the surface (114), the first wiring layer (1710) being thicker than the second wiring layer (132, 134).The semiconductor device structure (1800, 2000) of any preceding claim, further comprising an insulating layer (160) in the recess (116) surrounding the nickel layer (230).The semiconductor device structure (2000) of any preceding claim, further comprising a conductive wire (310) connecting the gold layer (240) to a second bond pad (320).The semiconductor device structure (1800) of any preceding claim, further comprising a conductive bump (410) over the gold layer (240).The semiconductor device structure of any preceding claim, further comprising: a first dielectric layer (120) on the surface (114), the first wiring layer (132) being in the first dielectric layer (120); a third wiring layer (136) embedded in the first dielectric layer (120); a second semiconductor substrate (250); a second dielectric layer (260) over the second semiconductor substrate (250) connected to the first dielectric layer (120); and a fourth wiring layer (278) embedded in the second dielectric layer (260) and connected to the third wiring layer (136).The semiconductor device structure (1800, 2000) of any of claims 1 to 8, further comprising: a first dielectric layer (120) on the surface (114), the first wiring layer (132) being in the first dielectric layer (120); a third wiring layer (136) embedded in the first dielectric layer (120); a second semiconductor substrate (250); a second dielectric layer (260) over the second semiconductor substrate (250); a fourth wiring layer (278) embedded in the second dielectric layer (260); and a conductive via (960) passing through the first semiconductor substrate (110) and the first dielectric layer (120) to electrically connect the third wiring layer (136) to the fourth wiring layer (278).The semiconductor device structure (1800, 2000) of any preceding claim, wherein the surface (114) is a first surface of the first semiconductor substrate (110), and the first semiconductor substrate (110) further comprises a second surface (112) opposite the first surface (114), wherein the nickel layer (230) and the gold layer (240) do not extend to the second surface (112).The semiconductor device structure (1800, 2000) of any preceding claim, further comprising: a dielectric fill layer (160) filling the recess (116), wherein the dielectric fill layer (160) has an opening (H) exposing a portion of the first wiring layer (132), and the nickel layer (230) and the gold layer (240) are located in the opening (H).A method of manufacturing a semiconductor device structure (1800, 2000), comprising the steps of: providing a first semiconductor substrate (110) having a surface (114); forming a first wiring layer (132) under the surface (114); forming a conductive ring structure (R1) between the first wiring layer (132) and the first semiconductor substrate (110), the conductive ring structure (R1) being connected to the first wiring layer (132) and having an opening (P1); forming a recess (116) in the first semiconductor substrate (110), the recess (116) passing through the first semiconductor substrate (110) to expose the first wiring layer (132); forming a nickel layer (230) in the recess (116), the nickel layer (230) extending into the opening (P1) and extending to the first wiring layer (132) to be electrically connected to the first wiring layer (132); and forming a gold layer (240) over the nickel layer (230).The method of manufacturing a semiconductor device structure (1800, 2000) of claim 13, wherein the forming of the nickel layer (230) comprises: performing an electroless process on the first wiring layer (132) to form the nickel layer (230).The method of manufacturing a semiconductor device structure (2000) of claim 13 or 14, further comprising: forming a conductive wire (310) connecting the gold layer (240) to a second bond pad (320).The method of manufacturing a semiconductor device structure (1800) of any of claims 13 to 15, further comprising: forming a conductive bump (410) over the gold layer (240).The method of manufacturing a semiconductor device structure (1800, 2000) of any of claims 13 to 16, further comprising: forming a first dielectric layer (120) on the surface (114), the first wiring layer (132) being located in the first dielectric layer (120); providing a second semiconductor substrate (250), a second dielectric layer (260), and a second wiring layer (278), the second dielectric layer (260) being located over the second semiconductor substrate (250), and the second wiring layer (278) being embedded in the second dielectric layer (260); and electrically connecting the first wiring layer (132) to the second wiring layer (278).

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