SEMICONDUCTOR STRUCTURE AND METHOD FOR ITS MANUFACTURE

Abstract

Procedure with the following steps: Arranging gate structures (140-144) over a first active region (111), a second active region (112) and a non-active region (113) of a substrate of a semiconductor structure, wherein the first and second active regions (111, 112) are doped regions and are separated by the non-active region (113), and wherein the gate structures (140-144) are arranged parallel to one another and each extend longitudinally over the first active region (111), the non-active region (113) and the second active region (112), wherein the non-active region (113) lies between the first active region (111) and the second active region (112) and is different from them; Arranging contacts (130) over the first and second active areas (111, 112); Arranging at least one gate via (GV0-GV7) over the first active region or the second active region (111, 112), wherein the at least one gate via (GV0-GV7) is electrically connected to one of the gate structures (140-144); and selectively arranging at least one local connection (LIC) over the non-active region (113) and between two adjacent first and second gate structures (142, 143) to connect at least one first contact (130) over the first active region (111) to at least one second contact (130) over the second active region (112), wherein portions of the first gate structure (142) and the second gate structure (143) directly over the non-active region (113) have no via; wherein the gate structures (140-144) each comprise an intermediate layer, a gate dielectric layer and one or more metal layers, wherein the intermediate layer comprises a dielectric material.

Description

Background of the invention

[0001] The IC (semiconductor integrated circuit) industry has experienced rapid growth. Over the course of IC evolution, the number of interconnected components per chip area has generally increased, while the smallest component that can be produced using a manufacturing process has decreased. This process of miniaturization increases the complexity of IC processing and manufacturing.DE 10 2014 110 957 describes a static random access memory (SRAM) cell comprising a first inverter including a first pull-up (PU) device, a first pull-down (PD) device, and a second PD device; a second inverter cross-coupled to the first inverter, the second inverter including a second PU device, a third PD device, and a fourth PD device; first and second pass gate (PG) devices connected to the first inverter to form a first terminal; and third and fourth PG devices connected to the second inverter to form a second terminal. The first and second PG devices, the first PD device of the first inverter, and the third PD device of the second inverter are configured on a first active area.The third and fourth PG devices, the second PD device of the first inverter, and the fourth PD device of the second inverter are configured on a second active area.

[0002] US 2015 0 332 962 A1 discloses a semiconductor device and a method for its fabrication. The semiconductor device comprises a substrate having source / drain regions and a channel region between the source / drain regions, a gate structure above the substrate and adjacent to the channel region, source / drain contacts above the source / drain regions that electrically connect to the source / drain regions, and a contact protection layer above the source / drain contacts. The gate structure comprises a gate stack and a spacer. A top surface of the source / drain contacts is lower than a top surface of the spacer that is substantially coplanar with a top surface of the contact protection layer. The contact protection layer prevents accidental short circuits between the gate stack and the source / drain regions when gate vias are formed over the gate stack.Therefore, gate vias can be formed over any part of the gate stack, even in areas that overlap with the channel region when viewed from above.

[0003] WO 2015 / 019 411 A1 discloses a configuration for an embedded SRAM memory cell structure with 3 differential write and read ports, wherein, for example, an N-well region is arranged in the center of the cell and P-well regions are arranged on both sides thereof.

[0004] Further prior art is known from US 2016 / 0 049 395 and US 2014 / 0 252 477 A1.

[0005] The invention provides a method according to claim 1 and a semiconductor structure according to claim 10. Embodiments of the inventions are specified in the dependent claims. Short description of the drawings

[0006] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1A is a top view of a schematic layout of a semiconductor structure according to some embodiments of the present invention. Fig. Figure 1B is a cross-sectional view of the semiconductor structure of Fig. 1A, according to some embodiments of the present invention. Fig. 2A is a plan view of a schematic layout of a semiconductor structure according to an unclaimed example. Fig. Figure 2B is a cross-sectional view of the semiconductor structure of Fig. 2A, according to the unclaimed example. Fig. Figure 3 is a circuit diagram showing a cross-coupling structure with four transistors. The Fig. 4A to 4E are each a plan view of a schematic layout of a semiconductor structure corresponding to a part of the semiconductor structure of Fig. 1A, according to various embodiments of the present invention. Fig. 5 is a top view of a schematic layout of a semiconductor structure according to some further embodiments of the present invention. Fig. 6 is a top view of a portion of a schematic layout of a semiconductor structure according to alternative embodiments of the present invention. Fig. 7 is a flowchart illustrating a method for designing layouts for semiconductor structures, according to some embodiments of the present invention. Detailed description

[0007] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to facilitate the present invention. For example, the fabrication of a first element over or on a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0009] Field-effect transistors (FETs) typically have active regions and gate structures over the active regions. Conductive features, including contacts and vias, are fabricated on the FETs to provide an electrical connection from one terminal (e.g., source, drain, or gate) of one FET to one or more terminals of another FET, for example. With continued miniaturization in semiconductor process technology, process variations in the manufacture of integrated circuits (ICs) are becoming increasingly difficult to manage. US patent application US 2015 0 332 962 A1 provides some embodiments for implementing gate vias in active regions of a semiconductor device.

[0010] Fig. Figure 1A is a top view of a schematic layout of a semiconductor structure 101 according to some embodiments of the present invention. The semiconductor structure 101 discussed in the present invention is for illustrative purposes.

[0011] In some embodiments, at least a portion of the semiconductor structure 101 shown in Fig. 1A and the semiconductor structures described with reference to the Fig. 2A and 4A to 6, represents a standard cell. The standard cell, in some embodiments, refers to a pre-designed cell that has been created and stored in a circuit library, which is in the form of a database. Furthermore, in some embodiments, the standard cell is stored in a physical storage medium, including, for example, a hard disk. When designing integrated circuits, the standard cell is retrieved from the circuit library and is placed in a placement operation. The placement operation is performed, for example, using a computer running integrated circuit design software. The software includes a circuit configuration tool that has the function of placement and routing.

[0012] In some embodiments, the semiconductor structure 101 and the semiconductor structures described with reference to the Fig. 2A and 4A to 6 are implemented in a semiconductor device. In some further embodiments, the Fig. 1A and the semiconductor structures described with reference to the Fig. 2A and 4A through 6, each represents an intermediate device fabricated during processing of an integrated circuit (IC) or a portion thereof. In some embodiments, the IC or portion thereof includes static random access memory (SRAM) and / or other logic circuitry, passive components such as resistors, capacitors, and inductors, and active components such as p-type field-effect transistors (PFETs), n-type FETs (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, high-voltage transistors, high-frequency transistors, other memory cells, and combinations thereof.

[0013] As in Fig. 1A, the semiconductor structure 101 includes a first active region 111 and a second active region 112 formed on a substrate (not shown). The first active region 111 and the second active region 112 are spaced apart by a non-active region 113. In some embodiments, the substrate is a silicon substrate. In some further embodiments, the substrate comprises: another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. In still further embodiments, the substrate is a semiconductor on insulator (SOI). The foregoing substrate types are for illustrative purposes only.Various types of substrate 110 are within the intended scope of the present invention.

[0014] In some embodiments, the first active region 111 and the second active region 112 have the same conductivity type, for example, n or p. In some further embodiments, the first active region 111 and the second active region 112 have different conductivity types, for example, one region is n-type and the other region is p-type.

[0015] For example, in Fig. 1A, the semiconductor structure 101 further comprises gate structures 140 to 144 and gate vias GVo to GV7. For simplicity of discussion, only the gate structures 140 to 144 and the gate vias GVo to GV7 are shown in Fig. 1A. Various numbers of gate structures and gate vias are within the intended scope of the present invention.

[0016] The gate structures 140 to 144 are arranged on the first active region 111, the second active region 112 and the non-active region 113, respectively, as shown in Fig. 1A. For illustration, the gate structures 140 to 144 are arranged in parallel and extend longitudinally over the first active region 111, the non-active region 113, and the second active region 112.

[0017] The gate vias GV0 to GV7 are arranged on the gate structures 140 to 144, as shown in Fig. 1A. In some embodiments, gate vias GV0 to GV7 are electrically connected to gate structures 140 to 144, respectively.

[0018] In some embodiments, at least one of the gate vias GV0 to GV7 is arranged over the first active region 111, the second active region 112 and / or the non-active region 113. For illustration, Fig. 1A, the gate vias GV0, GV1 and GV7 are arranged over the non-active region 113, the gate vias GV2, GV4 and GV6 are arranged over the first active region 111, and the gate vias GV3 and GV5 are arranged over the second active region 112.

[0019] In some embodiments, the gate structures 140 to 144 are made of metal. In some further embodiments, the gate structures 140 to 144 are made of a conductive non-metallic material, such as a conductive polymer material or graphene material.

[0020] In some embodiments, gate structures 140, 141, 142, 143, and 144 each include an interlayer (not shown) and a polysilicon layer (not shown) over the interlayer. In some embodiments, gate structures 140-144 further include a dielectric gate layer (not shown) and a metal gate layer (not shown) disposed between the interlayer and the polysilicon layer. In some embodiments, gate structures 140-144 include one or more metal layers instead of the polysilicon layer. In various embodiments, the interlayer comprises a dielectric material, such as silicon oxide (SiO2) or silicon oxynitride (SiON), and may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods.In some embodiments, the polysilicon layer is formed using a suitable deposition method, such as low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, the gate dielectric layer uses a high-k dielectric material, such as hafnium oxide (HfO2), Al2O3, lanthanum oxides, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, or a combination thereof, or another suitable material, and the gate dielectric layer is formed by ALD and / or another suitable method. The metal gate layer comprises a p-type work function metal or an n-type work function metal and is deposited by CVD, PVD, and / or another suitable method. Exemplary p-type work function metals are TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, other suitable p-type work function metals, or combinations thereof.Exemplary n-type work function metals are Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function metals, or combinations thereof. The one or more metal layers use aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), and / or other suitable materials and are formed by CVD, PVD, plating, and / or other suitable processes. The fabrication methods and / or materials for the gate structures 140-144 are illustrative only. Various fabrication methods and / or materials for the gate structures 140-144 are within the intended scope of the present invention.

[0021] As in Fig. 1A, source / drain contacts 130 are arranged above the first active region 111 and the second active region 112, respectively. In some embodiments, the source / drain contacts 130 are spaced from the gate structures 140 to 144, for example, by spacers 152 and spacers 134, which are shown in Fig. 1B. For example, in Fig. 1A, between two adjacent gate structures 140 to 144, a source / drain contact 130 is arranged above the first active region 111 and a source / drain contact 130 is arranged above the second active region 112.

[0022] In some embodiments, the semiconductor structure 101 further comprises source / drain vias SDV. The source / drain vias SDV are electrically connected to the source / drain contacts 130. The source / drain vias SDV are arranged above the first active region 111 and the second active region 112, respectively, as shown in Fig. 1A. In some embodiments, the gate vias GV0 to GV7 and the source / drain vias SDV are connected to vias (not shown) in another part of the semiconductor structure 101. In some further embodiments, the gate vias GV0 to GV7 and the source / drain vias SDV are connected by conductive features (not shown), for example, including metal interconnects, in another layer of the semiconductor structure 101 to form a semiconductor device.

[0023] For the sake of simplicity of discussion, Fig. 1A only some designations “SDV” are indicated, and similar elements that are Fig. 1A are also referred to as source / drain vias SDV. Furthermore, the term "source / drain" discussed above refers to a region that may be a source region or a drain region.

[0024] Fig. 1B is a sectional view of the semiconductor structure 101 of Fig. 1A along the line A - A, according to some embodiments of the present invention. For better understanding, elements in Fig. 1B, which are similar to those in the embodiments of Fig. 1A are designated by the same reference symbols.

[0025] In the Fig. 1A and Fig. 1B, in some embodiments, spacers 152 are formed around the gate structures 140 to 144. For example, in Fig. 1B, spacers 152 are fabricated around gate structures 141 to 143, and spacers 134 are fabricated around source / drain contacts 130. Spacers 152 and spacers 134 are disposed between gate structures 141 to 143 and the corresponding source / drain contacts 130. In some embodiments, spacers 152 comprise dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, other dielectric materials, and / or combinations thereof.

[0026] In some embodiments, Fig. 1B, gate openings 153 are arranged above the gate structures 141 and 143. In some embodiments, the gate openings 153 are intermediate stages in the formation of openings in the gate structures 141 to 143. After the gate opening 153 has been removed, the gate structures 141 to 143 may be exposed. For example, in Fig. 1B a gate opening above the gate structure 142, which in Fig. 1B, is etched and removed to obtain the gate via GV2. In some embodiments, the gate openings 153 are made of metal, such as aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), or a combination thereof, or of another suitable material. In some embodiments, the gate openings 153 are also referred to as self-aligned contacts (SACs), and they are manufactured using a self-aligned manufacturing process.

[0027] The layout of the semiconductor structure 101, which is shown in Fig. 1A illustrates distributions of gates, sources, and drains of transistors. The transistors are each fabricated with two source / drain contacts 130 and a corresponding one of the gate structures 140 to 144 between the two source / drain contacts 130.

[0028] As in Fig. 1B, source / drain regions 131 are formed in corresponding parts of the first active region 111 for illustrative purposes. The source / drain contacts 130 are arranged over the source / drain regions 131. Similarly, source / drain regions 131 are also formed in the second active region 112, but for simplicity of discussion, they are not shown in the figures. In some embodiments shown in Fig. 1B, lightly doped diffusion regions (LDD regions) 132 are illustrated around the source / drain regions 131 and in corresponding parts of the first active region 111 of Fig. 1B manufactured.

[0029] In Fig. 1B, in some embodiments, the semiconductor structure 101 further comprises a contact protection layer 154 over the source / drain contacts 130. The contact protection layer 154 is formed to prevent the source / drain contacts 130 from accidentally contacting, for example, the source / drain contacts 130 during the manufacturing processes. Fig. 1B. In some embodiments, the contact protection layer 154 comprises a dielectric material. In various embodiments, the contact protection layer 154 is made of titanium oxide (TiO2), silicon oxide (SiO2), silicon oxide nitride (SiON), silicon nitride (SiN3), a combination thereof, or another suitable material.

[0030] In some embodiments, the thickness of the contact protection layer 154 is different from the height of at least one of the gate structures 140 to 144. For example, in Fig. 1B, the contact protection layer 154 is formed with a thickness H2, and the gate structures 140 to 144 each have a height H1. In some embodiments, the thickness H2 is at least 0.2 times the height H1 to ensure a dielectric function. In some further embodiments, the thickness H2 is not more than 1.7 times the height H1 to avoid the contact protection layer 154 taking up too much space and / or the delay time becoming longer due to a high capacitance caused by the thickness H2. In alternative embodiments, the thickness H2 of the contact protection layer 154 is approximately 0.2 to 1.7 times the height H1 of the gate structures 140 to 144. In further embodiments, the thickness H2 is approximately 0.2 to 1.5 times the height H1.

[0031] For example, in Fig. 1B, in some embodiments, the semiconductor structure 101 further comprises an ILD (interlayer dielectric) layer 150. The gate via GV2 is formed in an opening through the ILD layer 150. In this configuration, the gate via GV2 provides a connection between the gate structure 142 and other terminals of the semiconductor structure 101. In some embodiments, the ILD layer 150 comprises dielectric materials such as silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN3), and / or other suitable dielectric materials.

[0032] In some embodiments, the semiconductor structure 101 further comprises a barrier layer 151. For example, in Fig. 1B, the barrier layer 151 is formed on the sidewalls of the opening in which the gate via GV2 is disposed, as explained above. The barrier layer 151 is formed between the gate via GV2 and the ILD layer 150 to prevent the material of the gate via GV2 from diffusing into the ILD layer 150.

[0033] In some embodiments, a local interconnect LIC is arranged over the non-active region 113 between two adjacent gate structures 140 to 144. For example, in Fig. 1A, the local connection LIC is arranged between the gate structures 142 and 143. The local connection LIC is electrically connected to two corresponding opposite source / drain contacts 130, which are individually arranged above the first active region 111 and the second active region 112, as shown in Fig. 1A is shown.

[0034] In some embodiments, the local connection LIC is formed by extending the respective aforementioned source / drain contacts 130 in a longitudinal direction. For example, in Fig. 1A, the corresponding source / drain contact 130 disposed above the first active region 111 is extended in the longitudinal direction toward the second active region 112 to establish the local connection LIC above the non-active region 113. Alternatively, the corresponding source / drain contact 130 disposed above the second active region 112 is extended in the longitudinal direction toward the first active region 111 to establish the local connection LIC above the non-active region 113. In other words, the source / drain contacts 130 disposed above the corresponding first active region 111 and the corresponding second active region 112 are connected to each other.

[0035] In some embodiments, the local connection LIC is formed at a gap GP1 in Fig. 1A to interconnect the source / drain contacts 130 above the corresponding first active region 111 and the corresponding second active region 112. For example, in Fig. 1A, the gap GP1 between the gate structures 142 and 143 above the non-active region 113. No gate via is arranged on the gate structures 142 and 143 above the non-active region 113, so that the local connection LIC arranged at the gap GP1 does not adjoin a gate via on the adjacent gate structures 142 and 143.

[0036] Fig. 2A is a top view of a schematic layout of a semiconductor structure 102 according to an example. Fig. 2B is a cross-sectional view of the semiconductor structure 102 of Fig. 2A along the line B - B. For better understanding, elements in Fig. 2A and Fig. 2B, which are similar to those in the embodiments of Fig. 1A and Fig. 1B are denoted by the same reference symbols. The semiconductor structure 102 discussed in the present invention is for illustrative purposes only.

[0037] In contrast to the semiconductor structure 101 of Fig. 1A, in some embodiments, shows the semiconductor structure 102 of Fig. 2A further comprises fin structures, such as fin structures FIN1, FIN2, FIN3 and FIN4, but not the first active region 111 and the second active region 112. In Fig. 2A, the fin structures FIN1, FIN2, FIN3 and FIN4 are shown for ease of illustration, but various numbers of fin structures implemented in the semiconductor structure 102 are part of the example.

[0038] In some embodiments, at least one of the fin structures FIN1, FIN2, FIN3, and FIN4 is made of a material such as silicon, silicon germanium, and the like. Various materials for fabricating the fin structures FIN1, FIN2, FIN3, and FIN4 are included in the example.

[0039] For example, in Fig. 2A and Fig. 2B shows the fin structure FIN2 under the gate structure 141 from the position where the gate structure 140 is located to the position where the gate structure 142 is located. The gate structure 141 and the source / drain contacts 130A and 130B are arranged to implement a fin field-effect transistor (FinFET) with the fin structure FIN2.

[0040] For the corresponding explanation of Fig. 2B: The fin structure FIN2 is arranged on a substrate 114. Also located on the substrate 114 is an STI (shallow trench isolation) layer 160, which is arranged around the fin structure FIN2. An epitaxial source / drain layer 161 is arranged between the source / drain contact 130A and the fin structure FIN2. Another epitaxial source / drain layer 162 is arranged between the source / drain contact 130B and the fin structure FIN2.

[0041] In some embodiments, the region for receiving the fin structure FIN2 is considered an active region. Accordingly, the regions for receiving the fin structures FIN1, FIN3, and FIN4 are also considered active regions. For the corresponding explanation of Fig. 2A: A non-active region 113 is located in a region where none of the fin structures FIN1, FIN2, FIN3, and FIN4 are arranged. In some embodiments, the source / drain contacts 130 and 130A to 130H do not extend beyond the non-active region 113, as shown in Fig. 2A is shown.

[0042] For the corresponding explanation of Fig. 2A: The fin structure FIN1 under the gate structure 142 extends from the position where the gate structure 141 is located to the position where the gate structure 143 is located. The gate structure 142 and the source / drain contacts 130B and 130F are arranged to implement a fin field-effect transistor (FinFET) with the fin structure FIN1. In Fig. 2A, the fin structure FIN3 extends under the gate structure 141 from the position where the gate structure 140 is located to the position where the gate structure 142 is located. The gate structure 141 and the source / drain contacts 130G and 130H are arranged to implement another FinFET with the fin structure FIN3. In Fig. 2A, the fin structure FIN4 extends under the gate structure 143 from the position where the gate structure 142 is located to the position where the gate structure 144 is located. The gate structure 143 and the source / drain contacts 130D and 130E are arranged to implement another FinFET with the fin structure FIN4.

[0043] In some embodiments, a local connection LIC is provided over the non-active region 113 in Fig. 2A. For example, in Fig. 2A, the local connection LIC is arranged between the gate structures 142 and 143 to connect the source / drain contact 130F and the source / drain contact 130D, which are arranged on opposite sides of the non-active region 113.

[0044] The devices in which the semiconductor structures discussed in the present invention are implemented are for illustrative purposes only. Various devices in which the semiconductor structures discussed in the present invention are implemented are within the intended scope of the present invention. For example, the semiconductor structures discussed in the present invention can be implemented in planar FETs.

[0045] In various embodiments, some rules are established in the following paragraphs of the present invention to indicate when and / or where the local connection LIC in the semiconductor structure 101 of Fig. 1A and / or in the semiconductor structure 102 of Fig. 2A is to be arranged or produced.

[0046] Fig. Figure 3 is a circuit diagram showing a cross-coupling structure CPS with four transistors T1, T2, T3 and T4. In some embodiments, the Fig. 3 shown cross-coupling structure CPS is used in some electronic circuits, such as a multiplexer, a memory, a decoder or an equivalent logic unit. As shown in Fig. As shown in Figure 3, the source / drain contacts of transistors T1 and T2 are connected to a node ND1, and the source / drain contacts of transistors T3 and T4 are connected to a node ND2. For illustrative purposes, the two nodes ND1 and ND2 are interconnected by the aforementioned local connection LIC.

[0047] To implement the above cross-coupling structure CPS, it is determined whether the local connection LIC is, for example, in Fig. 1A and Fig. 2A. In some embodiments, a first rule is established to determine whether the local connection LIC should be arranged. If the first rule is followed, the local connection LIC can, for example, be arranged in Fig. 1A to form the cross-coupling structure CPS of Fig. 3. The first rule is explained below with reference to the embodiments of the Fig. 4A to 4E are discussed.

[0048] The Fig. 4A to 4E are each a plan view of a schematic layout of a semiconductor structure corresponding to a part of the semiconductor structure 101 of Fig. 1A, according to various embodiments of the present invention. For better understanding, elements in the Fig. 4A to 4E, which correspond to those in the embodiments of Fig. 1A and Fig. 3 are similar, are designated by the same reference symbols. Fig. 4A to 4E show the embodiments in which at least one local connection is arranged when the first rule is followed.

[0049] As in Fig. As shown in Figure 4A, the gate vias GV2 and GV4 are arranged over the first active region 111, and the gate vias GV3 and GV5 are arranged over the second active region 112. The gate vias GV2 and GV3 are connected to the gate structure 142. The gate vias GV4 and GV5 are connected to the gate structure 143. A local connection LIC1 is arranged in a region that is, for example, Fig. 4A is defined by the first active region 111, the second active region 112 and the gate structures 142 and 143.

[0050] For example, in Fig. 4A, the gate vias GV2 to GV5 are not aligned with each other. The gate via GV2 and the gate via GV3 are separated by a distance Pa. The gate via GV4 and the gate via GV5 are separated by a distance Pb. In some embodiments, the distance Pa is equal to the distance Pb. In various embodiments, the distance Pa is in the range of about 0.7 Pb to about 1.3 Pb, indicating that in some embodiments, the distance Pa is substantially equal to the distance Pb.

[0051] For the first rule, three conditions must be met. If all three conditions are met, the local connection LIC1 can be established. The first condition of the first rule is that there is at least one gate via located outside the non-active area 113. For example, in Fig. 4A, the gate vias GV2 to GV5 are arranged outside the non-active region 113. The second condition of the first rule is that there is no gate via above the non-active region 113 around which the local connection LIC1 is to be made. For example, in Fig. 4A, no gate via is present on the gate structure 142 / 143 above the non-active region 113. The third condition of the first rule is that the distances between the gate vias on opposite sides of the local interconnect LIC1 are substantially equal. For example, in Fig. 4A, the distance Pa between the gate via GV2 and the gate via GV3 is substantially equal to the distance Pb between the gate via GV4 and the gate via GV5.

[0052] The aforementioned distributions and configurations of the gate vias GV2 to GV5 and the relationship between the distances Pa and Pb are considered the first rule in some embodiments. Following the first rule determines that the Fig. 4A is to be arranged in the aforementioned region to connect the corresponding source / drain contacts 130 above the first active region 111 and the second active region 112.

[0053] In some embodiments, a spacer CPO1 is disposed to separate electronic signals transmitted over different gate vias. For example, in Figure 4A, the spacer CPO1 is disposed on the gate structure 142 and between the gate vias GV2 and GV3. The spacer CPO1 separates the electronic signal transmitted over the gate via GV2 from the electronic signal transmitted over the gate via GV3.

[0054] In some embodiments, a spacer CPO2 is also arranged to separate electronic signals transmitted via different gate vias. For example, the spacer CPO2 is arranged on the gate structure 143 and between the gate vias GV4 and GV5. With the spacer CPO2, the electronic signal transmitted via the gate via GV4 is separated from the electronic signal transmitted via the gate via GV5. In some embodiments, at least one of the spacers CPO1 and CPO2 is made of a dielectric material. In some embodiments, the spacers CPO1 and CPO2 are polysilicon cut layers, which are intermediate products in semiconductor manufacturing and are no longer present in the final semiconductor circuit.

[0055] As in Fig. 4A, a cross-coupling structure CPS is prepared which is similar to the cross-coupling structure CPS of Fig. 3. In some embodiments, the cross-coupling structure CPS is formed with the transistors T1 to T4 of Fig. 3 by the embodiments of Fig. 4A. In various embodiments, the cross-coupling structure CPS is implemented with the transistors T1 to T4 of Fig. 3 also implemented by the embodiments described below with reference to the Fig. 4B to 4E are explained.

[0056] Below, configurations of transistors T1 to T4 are shown to explain Fig. 4A. The transistor T1 has two source / drain contacts 130, the gate structure 142, and the gate via GV2 over the first active region 111. The transistor T2 has two source / drain contacts 130, the gate structure 143, and the gate via GV4 over the first active region 111. The transistor T3 has two source / drain contacts 130, the gate structure 142, and the gate via GV3 over the second active region 112. The transistor T4 has two source / drain contacts 130, the gate structure 143, and the gate via GV5 over the second active region 112. As shown in Fig. 4A, the transistors T1 and T2 have in common a source / drain contact 130 which is connected to the node ND1 of Fig. 3, and the transistors T3 and T4 have a source / drain contact 130 in common, which corresponds to the node ND2 of Fig. 3 corresponds.

[0057] To connect the nodes ND1 and ND2, which are in Fig. 3, the local connection LIC1 is Fig. 4A, as explained above. To separate the gates of the transistors T1 and T3 and the gates of the transistors T2 and T4, the spacers CPO1 and CPO2 are Fig. 4A, as explained above. In some embodiments, the spacer CPO1, the spacer CPO2 and the local connection LIC1 are arranged in Fig. 4A within a width WD indicating three contacted polysilicon pitches (3-CPP) to create the cross-coupling structure CPS.

[0058] As in Fig. 4B, the configurations of the gate vias GV2 to GV5 and the relationship between the distances Pa and Pb are similar to those shown in Fig. 4A. Based on the above discussion, the first rule is also followed.

[0059] In the embodiments of Fig. 4A the positions of the gate vias GV2 to GV5 are shown in Fig. 4B of the positions of the gate vias GV2 to GV5 in Fig. 4A. For example, compared to the Fig. 4A, the positions of the gate vias GV2 and GV3 to the top of Fig. 4B, and the positions of the gate vias GV4 and GV5 are shifted to the bottom of Fig. 4B postponed.

[0060] In Fig. 4B, in some embodiments, the distance Pa between the gate vias GV2 and GV3 is still equal to the distance Pb between the gate vias GV4 and GV5, or it is still substantially equal to the distance Pb in some further embodiments discussed above.

[0061] By following the first rule, the local connection LIC1 can also be in the corresponding area, which for example is Fig. 4B by the first active region 111, the second active region 112 and the gate structures 142 and 143, to connect the corresponding source / drain contacts 130 in the first active region 111 and the second active region 112.

[0062] As in Fig. 4C, the distributions and configurations of the gate vias GV2 to GV5 and the relationship between the distances Pa and Pb are similar to those shown in Fig. 4A. Based on the above discussion, the first rule is also followed.

[0063] Compared to the versions of Fig. 4A is in Fig. 4C, a further local connection LIC2 is arranged. For example, the local connection LIC2 is arranged in a region defined, for example, by the first active region 111, the second active region 112, and the gate structures 141 and 142. The local connection LIC2 is arranged to connect the corresponding source / drain contacts 130 above the first active region 111 and the second active region 112.

[0064] As in Fig. 4D, the distributions and configurations of the gate vias GV2 to GV5 and the relationship between the distances Pa and Pb are similar to those shown in Fig. 4C. Based on the above discussion, the first rule is also followed.

[0065] Compared to the versions of Fig. 4C is in Fig. 4D, another local connection LIC3, but not the local connection LIC2, is arranged. For example, the local connection LIC3 is arranged in a region defined by the first active area 111, the second active area 112, and the gate structures 143 and 144. The local connection LIC3 is arranged to connect the corresponding source / drain contacts 130 above the first active area 111 and the second active area 112.

[0066] As in Fig. 4E, the distributions and configurations of the gate vias GV2 to GV5 and the relationship between the distances Pa and Pb are similar to those shown in Fig. 4D. Based on the above discussion, the first rule is also followed.

[0067] Compared to the versions of Fig. 4C and Fig. 4D are in the embodiments of Fig. 4E which in Fig. 4C shown local connection LIC2 and the one in Fig. 4D shown local connection LIC3.

[0068] Based on the above discussion, the embodiments in the Fig. 4A to 4E represent the first rule relating to arranging the layout according to the cross-coupling structure CPS of Fig. 3 refers.

[0069] Fig. 5 is a top view of a schematic layout of a semiconductor structure 103 according to some further embodiments of the present invention. For better understanding, elements in Fig. 5, which are similar to those in the embodiments of Fig. 1A are designated by the same reference symbols.

[0070] For example, in Fig. 5 Source / drain contacts 130a and 130c are arranged over the first active region 111, and source / drain contacts 130b and 130d are arranged over the second active region 112. Gate structures 141 and 142 are both arranged over the first active region 111, the second active region 112, and the non-active region 113. Gate vias GV8 and GV9 are arranged over the first active region 111.

[0071] In Fig. 5, the source / drain contacts 130a and 130c are spaced from the source / drain contacts 130b and 130d above the first active region 111 by the non-active region 113. In some embodiments, the source / drain contact 130a is connected to an H-level interconnect 161 via an interconnect 171, and the source / drain contact 130b is connected to the H-level interconnect 161 via an interconnect 172. Thus, the source / drain contacts 130a and 130b are interconnected by the interconnect 171, the H-level interconnect 161, and the interconnect 172. In some embodiments, the H-level interconnect 161 is formed in a metal one (M1) layer. In some embodiments, the interconnect elements 171 and 172 are each a contact and are fabricated in a layer different from the M1 layer.

[0072] In some embodiments, the interconnect elements 171 and 172 are each a via disposed between the source / drain contacts 130a and 130b, respectively, and the H-level interconnect 161, which is an M1 layer.

[0073] As in Fig. As shown in Figure 5, in some embodiments, source / drain contact 130c is connected to an H-level connection 162 via an interconnect 173, and source / drain contact 130d is connected to the H-level connection 162 via an interconnect 174. Thus, source / drain contacts 130c and 130d are connected to each other by interconnect 173, H-level connection 162, and interconnect 174. In some embodiments, H-level connection 162 is formed in the M1 layer. In some embodiments, interconnects 173 and 174 are each a contact and are formed in a layer different from the M1 layer.

[0074] Fig. 6 is a plan view of a portion of a schematic layout of a semiconductor structure 104 according to alternative embodiments of the present invention. For clarity, elements in Fig. 6, which are similar to those in the embodiments of Fig. 5 are similar, are designated by the same reference symbols. In some embodiments, a second rule is established to determine whether to arrange a local connection LIC4 which is in Fig. 6 is designated. Fig. Figure 6 shows some embodiments in which the local connection LIC4 is arranged when the second rule is followed. In contrast to the embodiments of Fig. 5 are the embodiments of Fig. 6 are designed in such a way that they have the local connection LIC4, but do not have the connecting elements 173 and 174.

[0075] In some embodiments, the gate via GV9 and the gate structure 142 are in Fig. 6 configured to receive a fixed voltage, such as a high system voltage VDD, a low system voltage VSS, a ground voltage GND, or the like.

[0076] The aforementioned distribution of the gate via GV9 and the configuration of the gate via GV9 for receiving the fixed voltage satisfy the second rule for implementing, for example, the local connection LIC4 to connect the source / drain contacts 130c and 130d. By following the second rule, it is determined that the local connection LIC4 should be arranged in an area that is Fig. 6 is defined by the first active region 111, the second active region 112 and the gate structures 141 and 142.

[0077] The distributions and configurations of the layouts used in Fig. 6 are for illustrative purposes only. Different distributions and configurations of the layouts in Fig. 6 are within the intended scope of the present invention. For example, in various embodiments, the embodiments in Fig. 6 is still configured without the gate via GV9. In these embodiments, the gate structure 142 has a floating configuration and is configured as a floating gate. By distributing the gate via GV8 and configuring the gate structure 142 as a floating gate, the second rule allows the local connection LIC4 to be implemented in the aforementioned area. With the local connection LIC4, fewer connection elements for the semiconductor structure 104 are required. Fig. 6 than required for the semiconductor structure 103, which is the layout of Fig. 5. In some embodiments, "floating" also means that the gate structure has a floating voltage or is not electrically connected to another non-floating conductor.

[0078] In some embodiments, a third rule is further established to determine whether the local connection LIC4 of Fig. 6. In some embodiments, in the third rule, the local connection LIC4 is prohibited and / or not arranged if at least one of the source / drain contacts 130a to 130d of Fig. 6 is an output drain of a standard cell. In some embodiments, the standard cell is, for example, an inverter cell, a NAND gate logic cell, a NOR gate logic cell, or an equivalent cell.

[0079] In some approaches, the parasitic capacitance of an output drain increases when a local connection is established around the output drain of a standard cell. As the parasitic capacitance increases, the speed of access to the output drain decreases. Furthermore, in related approaches, when an output drain is present, an access pin connected to the output drain is required, thereby increasing the size of the overall semiconductor structure with the local connection. Based on the above discussion, in the third rule, the local connection LIC4 is prohibited and / or not arranged if at least one of the source / drain contacts 130a to 130d of Fig. 6 is an output drain of a standard cell.

[0080] Fig. 7 is a flowchart illustrating a method 700 for designing layouts for semiconductor structures, according to some embodiments of the present invention. The method 700 is used, for example, to design the layouts of the semiconductor structures in the Fig. 1A, 2A and 4A to 6. In some embodiments, method 700 is used to verify and / or adjust layouts of semiconductor structures.

[0081] In some embodiments, for example, method 700 is performed using a computer (not shown) running integrated circuit design software. The software includes a circuit configuration tool having placement and routing functionality. In some embodiments, the computer includes a physical storage medium (not shown), including, for example, a hard disk, for storing a standard cell represented by at least a portion of the above semiconductor structures. In some embodiments, the computer includes a processing unit (not shown) for retrieving the standard cell from the physical storage medium and for performing layout and / or placement operations associated with the standard cell during placement.

[0082] For example, in Fig. 7, the method 700 is performed to determine whether the above local interconnect LIC should be disposed in the semiconductor structure. Therefore, the method 700 will be discussed below on the basis that no local interconnect LIC is disposed in the semiconductor structure. The method 700 is for illustrative purposes only. Various operations of the method 700, for example, performed when the local interconnect LIC has been disposed in the semiconductor structure, are within the intended scope of the present invention.

[0083] In step S701, a layout of a semiconductor structure, for example, is input into the aforementioned computer. Fig. The layout of the semiconductor structure 101 shown in Fig. 1A is input to be verified to determine whether the local interconnection LIC should be arranged in the semiconductor structure 101.

[0084] In step S702, it is determined whether or not there is at least one gate via disposed over the first active area or the second active area. For example, in Fig. 1A determines whether or not at least one of the gate vias GV0 to GV7 is disposed over the first active area 111 or the second active area 112. If not, step S700 of method is terminated, since without a gate via, the rule associated with the distributions and configurations of gate vias need not be established or followed. However, if a gate via is present, step S703 is subsequently executed.

[0085] In step S703, it is determined whether or not the layout of the semiconductor structure follows the first aforementioned rule and / or the second aforementioned rule. If so, the step of method 700 is terminated, since the adjustment and / or redesign of the layout need not be performed if the layout follows the first rule and / or the second rule. If not, step S704 is subsequently executed.

[0086] In step S704, the layout is adapted and / or redesigned by at least one aforementioned local connection over, for example, the non-active area 113 in Fig. 1A is used. With local interconnection, the source / drain contacts on different active regions are connected across the non-active region without implementing H-level interconnects. The size of the semiconductor structure can be reduced because H-level interconnects are not required to interconnect the source / drain contacts on different active regions.

[0087] If the layout of the semiconductor structure 101 of Fig. 1A follows the first rule, it is adapted and / or redesigned by additionally using the local connection LIC. If the layout of the semiconductor structure 104 of Fig. 6 follows the second rule, it is adapted and / or redesigned by additionally using the local connection LIC4.

[0088] In some embodiments, in step S703, it is further determined whether or not the layout of the semiconductor structure follows both the aforementioned second rule and the aforementioned third rule. If so, the step of method 700 is terminated because, as explained above, the local interconnect LIC is prohibited and / or not arranged if the layout follows the second rule and the third rule. Therefore, step S704 does not need to be executed.

Claims

[1] Procedure with the following steps: Arranging gate structures (140-144) over a first active region (111), a second active region (112) and a non-active region (113) of a substrate of a semiconductor structure, wherein the first and second active regions (111, 112) are doped regions and are separated by the non-active region (113), and wherein the gate structures (140-144) are arranged parallel to one another and each extend longitudinally over the first active region (111), the non-active region (113) and the second active region (112), wherein the non-active region (113) lies between the first active region (111) and the second active region (112) and is different from them; Arranging contacts (130) over the first and second active areas (111, 112); Arranging at least one gate via (GV0-GV7) over the first active region or the second active region (111, 112), wherein the at least one gate via (GV0-GV7) is electrically connected to one of the gate structures (140-144); and selectively arranging at least one local connection (LIC) over the non-active region (113) and between two adjacent first and second gate structures (142, 143) to connect at least one first contact (130) over the first active region (111) to at least one second contact (130) over the second active region (112), wherein portions of the first gate structure (142) and the second gate structure (143) directly over the non-active region (113) have no via; wherein the gate structures (140-144) each comprise an intermediate layer, a gate dielectric layer and one or more metal layers, wherein the intermediate layer comprises a dielectric material. [2] The method of claim 1, wherein selectively arranging the at least one local connection comprises: following a first rule and, if the first rule is followed, arranging the at least one local connection (LIC) adjacent to the first gate structure (142) or the second gate structure (143), wherein the first rule requires that a first of the gate vias (GV2) and a second of the gate vias (GV3) be connected to the first gate structure (142), a third of the gate vias (GV4) and a fourth of the gate vias (GV5) be connected to the second gate structure (143), at least one of the first to fourth gate vias (GV2-GV5) be arranged over the first active area (111) or the second active area (112),and a first distance between the first gate via (GV2) and the second gate via (GV3) is equal to or substantially equal to a second distance between the third gate via (GV4) and the fourth gate via (GV5). [3] The method of claim 1 or 2, wherein arranging the at least one local connection comprises: Arranging the at least one local connection in a region defined by the first active region (111), the second active region (112) and the first gate structure (142) and the second gate structure (143). [4] A method according to any one of the preceding claims, wherein arranging the at least one local connection (LIC) comprises: Arranging a first local connection (LIC1) between a first pair of adjacent gate structures (142, 143) to interconnect a first pair of contacts over the first active region (111) and the second active region (112); and Arranging a second local connection (LIC 2) between a second pair of adjacent gate structures (141, 142) to interconnect a second pair of contacts over the first active region (111) and the second active region (112). [5] A method according to any one of the preceding claims, wherein arranging the at least one local connection comprises: Arranging a plurality of local connections (LIC1, LIC2) each between two adjacent gate structures (140-144), wherein each of the plurality of local connections (LIC1, LIC2) is connected to two corresponding contacts between the two corresponding adjacent gate structures, above the first active region (111) and the second active region (112). [6] A method according to any one of the preceding claims, wherein selectively arranging the at least one local connection comprises: Following a second rule requiring that one of the gate structures (140-144) be configured to be floating or to receive a fixed voltage, and, if the second rule is followed, arranging the at least one local interconnect (LIC) adjacent to the gate structure. [7] The method of claim 6, wherein selectively disposing the at least one local interconnect comprises: following a third rule requiring that at least one of the contacts over the first active area (111) and the second active area (112) be an output drain of a standard cell, and, if the second rule and the third rule are followed, not disposing a local interconnect (LIC) around the output drain. [8] The method of claim 1, wherein selectively disposing the at least one local interconnect (LIC) comprises: following a rule requiring that at least one of the contacts above the first active area (111) and the second active area (112) is an output drain of a standard cell, and, if the rule is followed, not disposing a local interconnect (LIC) around the output drain. [9] Semiconductor structure with: a plurality of gate structures (140-144) arranged over a first active region (111), a second active region (112), and a non-active region (113), wherein the first active region (111) and the second active region (112) are doped regions and are separated by the non-active region (113), wherein the non-active region (113) lies between and is different from the first active region (111) and the second active region (112), and wherein the gate structures (140-144) are arranged parallel to one another and extend longitudinally over the first active region (111), the non-active region (113), and the second active region (112), wherein the gate structures (140-144) each comprise an intermediate layer, a gate dielectric layer, and one or more metal layers, wherein the intermediate layer comprises a dielectric material; a plurality of contacts (130) disposed over the first active region (111) and the second active region (112); at least one gate via over the first active region or the second active region, wherein the at least one gate via is electrically connected to one of the gate structures; and at least one local connection (LIC) arranged above the non-active region (113) between two adjacent ones of the gate structures (141, 142, 143), wherein parts of the first gate structure (142) and the second gate structure (143) directly above the non-active region (113) do not have a via, wherein the local connection (LIC) is electrically connected to a first of a plurality of source / drain contacts (130) in the first active region (111) and a second of a plurality of source / drain contacts (130) in the second active region (112). [10] Semiconductor structure according to claim 9, wherein the at least one local connection (LIC) is arranged in a region defined by the first active region (111), the second active region (112) and the two adjacent gate structures (142, 143). [11] The semiconductor structure of claim 9 or 10, wherein the at least one gate via comprises a first gate via (GV2) and a second gate via (GV3) connected to a first gate structure (142) of the gate structures, and a third gate via (GV4) and a fourth gate via (GV5) connected to a second gate structure (143) of the gate structures, at least one of the first to fourth gate vias (GV2-GV5) is arranged above the first active region (111) or the second active region (112), and a first distance between the first gate via (GV2) and the second gate via (GV3) is similar to a second distance between the third gate via (GV4) and the fourth gate via (GV5), wherein the at least one local connection is arranged around the first gate structure (142) or the second gate structure (143) is arranged. [12] The semiconductor structure of claim 11, wherein the width of the first gap is about 0.7 to about 1.3 times the width of the second gap. [13] Semiconductor structure according to one of claims 9 to 12, wherein the at least one local connection (LIC) comprises: a first local connection (LIC1) arranged between the two adjacent gate structures (142, 143), the first local connection (LIC1) interconnecting a first pair of contacts over the first active region (111) and the second active region (112); and a second local connection (LIC2) arranged between two adjacent gate structures (141, 142) of the gate structures, the second local connection interconnecting a second pair of contacts over the first active region (111) and the second active region (112). [14] Semiconductor structure according to one of claims 9 to 12, wherein the at least one local connection comprises: a plurality of local connections each between two corresponding gate structures, wherein each of the plurality of local connections (LIC1, LIC2) is connected to two corresponding contacts between the two corresponding gate structures, above the first active region and the second active region. [15] A semiconductor structure according to any one of claims 9 to 14, wherein when a gate structure of the gate structures is configured to be floating or to receive a fixed voltage, the at least one local interconnection (LIC) is arranged adjacent to the gate structure. [16] A semiconductor structure according to any one of claims 9 to 15, wherein when at least one of the contacts above the first active region (111) and the second active region (112) is an output drain of a standard cell, no local connection is arranged around the output drain.

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