Driver device for a semiconductor element

Abstract

Driver device (3a-3f) for driving a semiconductor element (2a-2f), comprising: an identification signal generating circuit (11) that generates an identification signal depending on a type of an input error signal; a protective operation signal generation circuit (14) that generates a protective operation signal having a pulse width equal to that of one of the error signal and the identification signal having a longer pulse width; an identification signal terminal (FO) that inputs and outputs the identification signal; a protection operation signal terminal (FO_T) that inputs and outputs the protection operation signal; and a protection circuit (18) which performs a fault protection operation depending on a self-phase protection operation signal generated by the protection operation signal generation circuit (14) and an extraneous phase protection operation signal inputted through the protection operation signal terminal (FO_T).

Description

BACKGROUND OF THE INVENTIONField of InterestThe present invention relates to a driving device for driving a semiconductor element.BackgroundIn a semiconductor device such as a three-phase inverter, a plurality of driving devices for driving a plurality of semiconductor elements are arranged. Each of the driving devices has an FO function of informing a control device (MCU) side of an abnormal state simultaneously with an operation suspension of the semiconductor element when an error signal is detected by state monitoring (SC, OC, OT, UV, or the like) of the semiconductor element (see, for example, Japanese Unexamined Patent Publication JP 2012-010 544 A).FIG. 13 is a schematic diagram showing a conventional driving device for a semiconductor element. FIG. 14 is a timing chart showing an operation of the conventional driving device for a semiconductor element. When each driving device receives an error signal from an ERR terminal, the driving device outputs an identification signal from an FO terminal to an MCU. Since the identification signal has different pulse widths depending on the kinds of the error signals, the MCU side can identify a kind of error. When one driving device receives an identification signal from another driving device, the corresponding device recognizes that the other driving device is performing a fault protection operation, and also performs a fault protection operation by itself.SummaryA conventional driving device outputs an identification signal and detects a fault protection operation with an FO terminal. For this reason, when a pulse width of the identification signal is determined depending on the type of an error signal, an error protection operation corresponding to an error signal having a length longer than the pulse width cannot be performed. On the other hand, when the pulse width of the identification signal is matched with the length of the error signal, the MCU side cannot identify an error type.A plurality of error signals cannot be continuously input without mixing identification signals with each other. For example, when a control power supply voltage drop protection (UV) operation increases a contact temperature of a semiconductor element so that a temperature occurrence detection (OT) operation is activated, the protection operation is executed for both failures. On the other hand, as an identification signal serving as a trigger of a failure, an identification signal corresponding to the UV operation should be previously output. However, since an identification signal corresponding to the UV operation and an identification signal corresponding to the OT operation are mixed together, the MCU side cannot distinguish the errors from each other.In a three-phase inverter system or the like, the FO terminals of a plurality of driving devices are commonly connected to an MCU. Thus, as shown in FIG. 14, when errors occur continuously in an own phase and an extraneous phase, identification signals in both phases are mixed together, so that it becomes impossible to distinguish types of errors on the MCU side from each other.US 2014 / 0 009 983 A1 discloses a control device for a power conversion device, which includes a plurality of drive circuits having an alarm signal generation circuit that adjusts a pulse signal at about one cycle per period. The one cycle period includes a determination period of which a different period is set for each of the plurality of protection circuits that acquire information for performing a protection operation of semiconductor elements configuring a power conversion device, and a constant period in which a state changes With respect to the determination period, a protection circuit for which it is first recognized that a protection operation is required takes a first-come-first-served protection circuit, and outputs the pulse signal corresponding to the first-come-first-served protection circuit as an alarm signal, wherein the alarm signal generation circuit is configured such that a reset condition of the alarm signal is a condition that a protection operation is stopped.The present invention has been developed to solve the above problem, and has an object to obtain a driving device for a semiconductor element which can perform a fault protection operation regardless of an identification signal and can identify a fault type based on an output identification signal.The object on which the invention is based is achieved in a driver device according to the invention with the features of claim 1. Advantageous refinements are the subject matter of the respective dependent claims.According to the present invention, a driving device for driving a semiconductor element includes: an identification signal generation circuit that generates an identification signal depending on a type of an input error signal; a protection operation signal generation circuit that generates a protection operation signal having a pulse width equal to that of one of the error signal and the identification signal having a longer pulse width; an identification signal terminal that inputs and outputs the identification signal; a protection operation signal terminal that inputs and outputs the protection operation signal; and a protection circuit that performs an error protection operation depending on an intrinsic phase protection operation signal generated by the protection operation signal generation circuit and an external phase protection operation signal input by the protection operation signal terminal.In the present invention, a protection operation signal having a pulse width equal to that of one of an error signal or an identification signal having a longer pulse width is generated. The identification signal terminal that inputs and outputs an identification signal and the protection operation signal terminal that inputs and outputs a protection operation signal are independently designed. In this way, a fault protection operation can also be carried out independently of the identification signal. Thus, an error protection operation that bypasses an error signal having a pulse width larger than that of the identification can also be performed. Identification signals having pulse widths varying depending on the kinds of error signals are outputted to make it possible to identify a kind of error on the MCU side.Other and further objects, features and advantages of the invention will become more apparent from the following description.Brief Description of the DrawingsFIG. 1 is a schematic diagram showing a power conversion device according to an embodiment of the present invention. FIG. 2 is a schematic diagram showing a driving device for a semiconductor element according to the embodiment of the present invention. FIG. 3 is a schematic diagram showing an identification signal generation circuit and a protection operation signal generation circuit according to the embodiment of the present invention. FIGS. 4 to 7 are timing charts showing operations of the identification signal generation circuit and the protection operation signal generation circuit according to the embodiment of the present invention. FIG. 8 is a schematic diagram showing a first example of a timer circuit according to the embodiment of the present invention. FIG. 9 is a schematic diagram showing a second example of a timer circuit according to the embodiment of the present invention. FIG. 10 is a schematic diagram showing a third example of a timer circuit according to the embodiment of the present invention. FIG. 11 is a schematic diagram showing a foreign phase identification signal favor circuit according to the embodiment of the present invention. FIG. 12 is a timing chart showing an operation of the external-phase identification signal favor circuit according to the embodiment of the present invention. FIG. 13 is a schematic diagram showing a conventional driving device for a semiconductor element. FIG. 14 is a timing chart showing an operation of the conventional driving device for a semiconductor element.DESCRIPTION OF THE EMBODIMENTSFIG. 1 is a schematic diagram showing a power conversion device according to an embodiment of the present invention. The power conversion device includes an inverter 1 and driving devices 3 ato 3 fwhich independently drive six semiconductor elements 2 ato 2 fwhich constitute the inverter 1.The semiconductor elements 2 ato 2 fare IGBTs (insulated gate bipolar transistors). A series circuit including the semiconductor elements 2 aand 2 d, a series circuit including the semiconductor elements 2 band 2 e, and a series circuit including the semiconductor elements 2 cand 2 fare connected in parallel with each other between a positive electrode line Lp and a negative electrode line Ln connected to a DC power supply that provides DC power to the lines Lp and Ln. Free-wheeling diodes 4a to 4f are connected in antiparallel with the semiconductor elements 2a to 2f, respectively.The semiconductor elements 2 a, 2 b, and 2 care respectively defined as U-phase, V-phase, and W-phase semiconductor elements to form an upper arm UA, and the semiconductor elements 2 d, 2 e, and 2 fare defined as X-phase, Y-phase, and Z-phase semiconductor elements to form a lower arm LA. Three-phase AC powers are output from a connection point between the semiconductor elements 2 aand 2 d, a connection point between the semiconductor elements 2 band 2 e, and a connection point between the semiconductor elements 2 cand 2 f, and the three-phase AC powers are provided to AC loads such as an electric motor.Each of the semiconductor elements 2 ato 2 fincludes a current sensor transistor 5 that measures a current flowing between a collector terminal and an emitter terminal, and a temperature detection diode 6 that is accommodated in the same chip as that of the corresponding semiconductor element. The collector terminal and the gate terminal of the current sensor transistor 5 are connected to the collector terminal and the gate terminal of the corresponding semiconductor element, respectively.The driving devices 3 ato 3 feach have the same arrangements. Each of the driving devices 3 ato 3 fincludes an input terminal IN receiving a pulse width modulation signal for gate driving from an external control device 7 (MUC), an output terminal OUT outputting a gate driving signal to the gate terminal of the corresponding semiconductor element, error terminals ERR 1, ERR 2, and ERR 3, a FO terminal (identification signal terminal) inputting and outputting an identification signal, and a FO_T terminal (protection operation signal terminal) inputting and outputting a protection operation signal. The FO terminals of the driving devices 3 ato 3 fare commonly connected to the control device 7. The FO_T terminals of the driving devices 3 ato 3 fare connected to each other.The fault terminal ERR 1 receives a driving power supply voltage provided to each of the driving devices, the fault terminal ERR 2 is connected to the emitter terminal of the current sensor transistor 5, and the fault terminal ERR 3 is connected to the anode terminal of the temperature sensing diode 6.FIG. 2 is a schematic diagram showing a driving device for a semiconductor element according to the embodiment of the present invention. An input circuit 8 performs signal processing such as waveform shaping on a pulse width modulation signal input from the input terminal IN.An amplifier 9 amplifies an output signal from the input circuit 8, so that the output terminal OUT outputs the amplified signal as a gate drive signal.Error signal generation units 10 a, 10 b, and 10 crespectively generate error signals depending on signals received from the error terminals ERR 1, ERR 2, and ERR 3. More specifically, the error signal generation unit 10 aoutputs an error signal corresponding to power supply voltage drop protection (UV) when the driving power supply voltage decreases to a predetermined voltage or lower. The fault signal generation unit 10 boutputs a fault signal corresponding to overcurrent protection (OC) and short circuit protection (SC) when an input current flowing in the current sensor transistor 5 increases to an overcurrent threshold value or higher. The fault signal generation unit 10 cdetects a chip temperature based on a voltage between the terminals of the temperature detection diode 6, and outputs a fault signal corresponding to overheat protection (OT) when the detected chip temperature rises to a predetermined overheat threshold or higher.An identification signal generating circuit 11 generates an identification signal having pulse widths (modes) varying depending on the kinds of the input error signals. The identification signal is output from the FO terminal through a third-phase identification signal favor circuit 12 and a transistor 13.A protection operation signal generation circuit 14 generates a protection operation signal having a pulse width equal to that of one of the error signal and the identification signal having a larger pulse width. The protection operation signal is output from the FO_T terminal through a transistor 15.The protection operation signal output from the protection operation signal generation circuit 14 is input to an AND circuit 16, and a third-phase protection operation signal input through the FO_T terminal is also input to the AND circuit 16 through an inverter 17. An output signal from the AND circuit 16 is input to the protection circuit 18. The protection circuit 18 performs operation interruption (fail-safe operation) of the semiconductor element depending on a self-phase protection operation signal generated by the protection operation signal generation circuit 14 and a foreign-phase protection operation signal input through the FO_T terminal.FIG. 3 is a schematic diagram showing an identification signal generation circuit and a protection operation signal generation circuit according to the embodiment of the present invention. The error signals ERR1, ERR2 and ERR3 are respectively input through AND circuits 19a, 19b and 19c and inverters 20a, 20b and 20c to T terminals of D flip-flop circuits 21a, 21b and 21c. High-level voltages are applied to D terminals of the D flip-flop circuits 21a, 21b and 21c. Output signals from the AND circuits 19a, 19b and 19c and output signals from the D flip-flop circuits 21a, 21b and 21c are input to OR circuits 22a, 22b and 22c.Output signals ff1d, ff2d and ff3d from the D flip-flop circuits 21a, 21b and 21c are input to an OR circuit 23, and an output signal from the OR circuit 23 serves as an identification signal. Output signals ff1q, ff2qand ff3qfrom the OR circuits 22 a, 22 band 22 care input to an OR circuit 24, and an output signal from the OR circuit 24 serves as a protection operation signal.The signal ff1q is input to the OR circuits 25b and 25c, the signal ff2q is input to the OR circuits 25a and 25c, and the signal ff3q is input to the OR circuits 25a and 25b. Output signals from the OR circuits 25a, 25b and 25c are respectively inputted invertedly to the AND circuits 19a, 19b and 19c. When a predetermined period of time has elapsed after the timer circuit 26 receives the signals ff1d, ff2d and ff3d, the timer circuit 26 outputs a reset signal of each R terminal of the D flip-flop circuits 21a, 21b and 21c.The OR circuits 22a, 22b, 22c and 24 of the above arrangement correspond to the protection operation signal generation circuit 14, and the other arrangement corresponds to the identification signal generation circuit 11. In the identification signal generation circuit 11, the D flip-flop circuits 21a, 21b and 21c use the error signals ERR1, ERR2 and ERR3 as edge triggers, respectively. The timer circuit 26 starts to operate depending on the outputs of the D flip-flop circuits 21a, 21b and 21c, and after a predetermined time has elapsed, the timer circuit 26 resets the D flip-flop circuits 21a, 21b and 21c. In this manner, the identification signal generation circuit 11 changes an output period, i.e., a pulse width of an identification signal, depending on output signals of the timer circuit 26.When one of the protection operation signals ff1q, ff2q, and ff3q is output, the preferred circuit including the AND circuits 19a, 19b, and 19c and the OR circuits 25a, 25b, and 25c prevents an error signal corresponding to another protection operation signal from being input to the D flip-flop circuit. Thus, the identification signal generation circuit 11 does not generate the identification signal corresponding to the second error signal when a second error signal is input, while a protection operation signal corresponding to a first error signal previously input is output.FIGS. 4 to 7 are timing charts showing operations of the identification signal generation circuit and the protection operation signal generation circuit according to the embodiment of the present invention. As shown in FIG. 4, when the error signal ERR 1 is input, the protection operation signal ff 1 qhaving a pulse width t 1 is generated. When the error signal ERR 2 is input after the protection operation signal ff 1 qis output, the protection operation signal ff 2 qhaving a pulse width t 2 is generated.On the other hand, as shown in FIG. 5, although the error signal ERR 2 is input while the protection operation signal ff 1 qis output, the error signal ERR 2 is not input to the D flip-flop circuit 21 b, and an identification signal and a protection operation signal corresponding to the error signal ERR 2 are not generated.As shown in FIG. 6, when a pulse width terr of the error signal ERR 1 is shorter than the pulse width t 1 of the identification signal ff 1 dcorresponding to the error signal ERR 1, the protection operation signal ff 1 qhaving the same pulse width t 1 as that of the identification signal ff 1 dis generated.On the other hand, as shown in FIG. 7, when the pulse width terr of the error signal ERR 1 is longer than the pulse width t 1 of the identification signal ff 1 dcorresponding to the error signal ERR 1, the protection operation signal ff 1 qhaving the same pulse width terr as that of the error signal ERR 1 is generated. Thus, an error protection operation corresponding to an error signal having a pulse width larger than that of an identification can also be performed.FIG. 8 is a schematic diagram showing a first example of a timer circuit according to the embodiment of the present invention. The signals ff1d, ff2d and ff3d corresponding to the error signals are input to an OR circuit 27, and an output signal from the OR circuit 27 is input to a NOR circuit 28. A transistor 29 connects or disconnects a capacitor 30 from ground. When one of the signals ff1d, ff2d and ff3d is input, the transistor 29 is turned off and a current source 31 starts to electrically charge the capacitor 30. A comparator 32 outputs a time that has elapsed until a voltage of the capacitor 30 reaches a threshold voltage V.In the first example, a selector 33 selects a current value of the power source 31 that electrically charges the capacitor 30 depending on the kinds of the error signals. In this way, identification signals can be generated that have pulse widths that vary depending on the types of the error signals. In addition, the circuit can be simplified because the selection of the current value can be adjusted only by changing a current mirror unit.FIG. 9 is a schematic diagram showing a second example of the timer circuit according to the embodiment of the present invention. The timer circuit 26 of the second example enables a selector 34 to switch threshold voltages V1, V2 and V3 depending on the kinds of the error signals. In this way, identification signals can be generated that have pulse widths that vary depending on the types of the error signals. In addition, in the comparator 32, since a relatively accurate threshold voltage can be generated therein by an internal power supply and a resistive division, the accuracy of the output period of the identification signal can be improved.FIG. 10 is a schematic diagram showing a third example of the timer circuit according to the embodiment of the present invention. The signals ff1d, ff2d and ff3d are input to a NOR circuit 35. In response to the output signals of the NOR circuit 35, the transistor 29 connects or disconnects a chopped wave generating circuit 36 to the ground point. When one of the signals ff1d, ff2d, and ff3d corresponding to the error signals is input, the transistor 29 is turned off, and a fundamental wave generated by the chopped wave generation circuit 36 is output from the comparator 32. This fundamental wave is frequency divided by T flip-flop circuits 37a, 37b and 37c. A selector 38 switches frequency division ratios N depending on the kinds of the error signals, so that a frequency-divided pulse signal is output. In this way, although the fundamental waves fluctuate, a signal having a pulse width N times the pulse width of the fundamental wave can be generated. For this reason, an output signal stable against variation in processes and having relatively high accuracy can be obtained.FIG. 11 is a schematic diagram showing a foreign phase identification signal favor circuit according to the embodiment of the present invention. In this case, any two of the driving devices 3 ato 3 fare exemplified as A-phase and B-phase driving devices. In each of the driving devices, arrangements other than an arrangement around a third-phase identification signal favor circuit 11 are not shown.A rising edge detection circuit 38 outputs a single pulse according to the rising edge of an own phase identification signal. A falling edge detection circuit 39 outputs a single pulse according to the falling edge of the self-phase identification signal. The output signal from the rising edge detecting circuit 38 is input to an OR circuit 40, and the output signal from the falling edge detecting circuit 39 is also input to the OR circuit 40 through an AND circuit 41. A foreign phase identification signal input through the FO terminal is input to a D terminal of a D flip-flop circuit 42 and is input through an inverter 43 to an AND circuit 41. An output signal of the OR circuit 40 is input to a T terminal of the D flip-flop circuit 42. An output signal from the D flip-flop circuit 42 allows the transistor 13 to be turned on / off.FIG. 12 is a timing chart showing an operation of the external-phase identification signal favor circuit according to the embodiment of the present invention. When an external phase identification signal is input through the FO terminal, an input signal to the D terminal changes to a low level. For this reason, although the one-shot pulse is input to the T terminal from the rising edge detection unit 38, no signal is output from a Q terminal of the D flip-flop circuit 42. Thus, the external-phase identification signal favor circuit 12 does not allow an internal-phase identification signal to be output from the FO terminal when an external-phase identification signal is input through the FO terminal.As described above, a protection operation signal having a pulse width equal to that of one of the error signals and an identification signal having a larger pulse width are generated in the embodiment of the present invention. The FO terminal that receives / outputs an identification signal and the FO_T terminal that receives / outputs a protection operation signal are independently configured. In this way, a fault protection operation can also be carried out independently of the identification signal. Thus, an error protection operation coping with an error signal having a longer pulse width than that of the identification can also be carried out. Identification signals having pulse widths varying depending on the kinds of the error signals are outputted to make it possible to identify a kind of error on the MCU side.When a second error signal is input while a protection operation signal corresponding to a previously input first error signal is output, the identification signal generation circuit 11 does not generate an identification signal corresponding to the second error signal. In this way, although a plurality of errors continuously occur in a self phase, identification signals corresponding to the errors are not mixed with each other. For this reason, the MCU page can identify a failure type.The external-phase identification signal favor circuit 12 does not allow an internal-phase identification signal to be output from the FO terminal when an external-phase identification signal is input through the FO terminal. More specifically, when an identification signal is output in a foreign phase, an identification signal is prevented from being output in a self phase. In this way, although errors continuously occur in the inherent phase and the foreign phase, identification signals in both phases are not mixed with each other. Thus, the MCU page can identify a fault type.Since a change in pulse widths of identification signals can be achieved by a timer circuit in the identification signal generation circuit 11, the circuit can be simplified.In summary, a driving device for driving a semiconductor element includes: an identification signal generation circuit that generates an identification signal depending on a type of an input error signal; a protection operation signal generation circuit that generates a protection operation signal having a pulse width equal to that of one of the error signal and the identification signal having a longer pulse width; an identification signal terminal that inputs and outputs the identification signal; a protection operation signal terminal that inputs and outputs the protection operation signal; and a protection circuit that performs an error protection operation depending on an intrinsic phase protection operation signal generated by the protection operation signal generation circuit and an external phase protection operation signal input by the protection operation signal terminal.List of reference characters1 Inverter 2 a- 2 f Halbleiter element 3 a- 3 f Treiber device 4 a- 4 f Freilauf diode 5 Current sensor transistor 6 Temperature detection diode 7 Control device 8 Input circuit 9 Amplifier 10 a- 10 cError signal generation unit 11 Identification signal generation circuit 12 External phase identification signal preference circuit 13 Transistor 14 Protection operation signal generation circuit 15 Transistor 16 AND circuit 17 Inverter 18 Protection circuit 19 a- 19 cAND circuit 20 a- 20 c Inverter 21 a- 21 cD flip-flop circuit 22 a- 22 cOR circuit 23, 24 OR circuit 25a-25c OR circuit 26 timer circuit 27 OR circuit 28 NOR circuit (NOR circuit) 29 transistor 30 capacitor 31 current source 32 comparator 33, 34 selector 35 NOR circuit (NOR circuit) 36 chopped wave generation circuit 37a-37c T flip-flop circuit 38 selector 39 detection circuit 40 OR circuit 41 AND circuit 42, 43 inverter

Claims

A driving device (3a-3f) for driving a semiconductor element (2a-2f), comprising: an identification signal generating circuit (11) that generates an identification signal depending on a type of an input error signal; a protection operation signal generating circuit (14) that generates a protection operation signal having a pulse width equal to that of one of the error signal and the identification signal having a longer pulse width; an identification signal terminal (FO) that inputs and outputs the identification signal; a protection operation signal terminal (FO_T) that inputs and outputs the protection operation signal; and a protection circuit (18) that performs a fault protection operation depending on a self-phase protection operation signal generated by the protection operation signal generation circuit (14) and an external-phase protection operation signal input through the protection operation signal terminal (FO_T).The driving apparatus (3a-3f) according to claim 1, wherein the identification signal generating circuit (11) does not output the identification signal corresponding to a second error signal when the second error signal is input, while outputting a protection operation signal corresponding to a previously input first error signal.The driving apparatus (3a-3f) according to claim 1 or 2, further comprising a third-phase identification signal favor circuit (12) which does not allow the third-phase protection operation signal to be output from the identification signal terminal (FO) when the third-phase identification signal is input through the identification signal terminal (FO).The driving device (3a-3f) according to any one of claims 1 to 3, wherein the identification signal has a pulse width that varies depending on the type of the error signal.The driving device (3a-3f) according to claim 4, wherein the identification signal generation circuit (11) changes the pulse width of the identification signal depending on an output signal from a timer circuit (26), and when the error signal is input, the timer circuit (26) starts electrically charging a capacitor (30), outputs a time elapsed until a voltage of the capacitor (30) reaches a threshold voltage, and selects a current value for electrically charging the capacitor (30) depending on the type of the error signal.The driving device (3a-3f) according to claim 4, wherein the identification signal generation circuit (11) changes the pulse width of the identification signal depending on an output signal from a timer circuit (26), and when the error signal is input, the timer circuit (26) starts electrically charging a capacitor (30), outputs a time elapsed until a voltage of the capacitor (30) reaches a threshold voltage, and selects the threshold voltage depending on the type of the error signal.The driving apparatus (3a-3f) according to claim 4, wherein the identification signal generation circuit (11) changes the pulse width of the identification signal depending on an output signal from a timer circuit (26), and when the error signal is input, the timer circuit (26) frequency-divides a fundamental wave and switches a frequency division ratio depending on the type of the error signal.

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