Level converter

Abstract

Level converter, comprehensive: an input that operates within an input voltage range; an inverter circuit (101) operating in the input voltage range for inverting an input signal (IN) to generate an inverted input signal (INB); an intermediate circuit (102) operating in an intermediate voltage range for generating an intermediate signal (OUTB); an output buffer circuit (103) for generating an output signal (OUT) at least partially based on the inverted input signal (INB) and the intermediate signal (OUTB); and an output for outputting the output signal (OUT) in an output voltage range, wherein the intermediate circuit (102) comprises two pull-low NMOS transistors (MN1, MN2), two cross-coupling PMOS transistors (MP1, MP2), and stacked PMOS transistors (MP3, MP4) between the two pull-low NMOS transistors (MN1, MN2) and the two cross-coupling PMOS transistors (MP1, MP2), where the threshold voltage of the cross-coupling PMOS transistors (MP1, MP2) and the stacked PMOS transistors (MP3, MP4) is equal to or lower than the threshold voltage of the pull-low NMOS transistors (MN1, MN2).

Description

TECHNICAL AREA

[0001] This invention relates to semiconductor devices and in particular level-shifting semiconductor devices that are capable of achieving increased voltage differences between an input voltage range and an output voltage range. TECHNICAL BACKGROUND

[0002] A level shifter is a semiconductor device capable of receiving a digital input signal in a first voltage range and outputting a corresponding digital signal in a second voltage range. The second voltage range can be higher or lower than the first. Typically, such a level shifter is used in circuits between sections of the circuit that have different voltage requirements. In this way, those parts of the circuit that can operate in a lower voltage range can operate in the lower voltage range, and parts of the circuit that are intended to operate in a higher voltage range can operate within the higher voltage range. The level shifter provides an interface between the two parts of the circuit, allowing them to communicate with each other.

[0003] A level converter is known from US 5,136,190 A.

[0004] US 2003 / 0001628A1 discloses a voltage level converter comprising a static voltage level converter and a split-level output circuit coupled to the static voltage level converter. In a further embodiment, the voltage level converter comprises a static voltage level converter, a first transistor, and a second transistor. The static voltage level converter includes an input node, a first pull-up node, a second pull-up node, a converter output node, and an output node. The first transistor is coupled to the input node and the first pull-up node. The second transistor is coupled to the second pull-up node and the inverter output node. Further prior art is known from LANUZZA, Marco; CORSONELLO, Pasquale; PERRI, Stefania: Low-power level shifter for multi-supply voltage designs. In: IEEE transactions on circuits and systems II: express briefs, Vol. 59, 2012, No. 12, pp. 922-956, ISSN 1549-7747.

[0005] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present invention is best understood with reference to the following detailed description, which is read in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily increased or decreased for the clarity of the discussion. Fig. Figure 1 shows a block diagram of an example of a level converter according to some embodiments. Fig. Figure 2 shows a schematic diagram of a first example of a level converter according to some embodiments. Fig. Figure 3 shows a schematic diagram of a second example of a level converter according to some embodiments. Fig. Figure 4 shows a schematic diagram of a third example of a level converter according to some embodiments. Fig. Figure 5 shows a schematic diagram of a fourth example of a level converter according to some embodiments. Fig. Figure 6 shows a flowchart to illustrate the operation of a level converter according to some embodiments. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments, or examples, for realizing various features of the provided subject matter. Certain examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. Additionally, the present disclosure may repeat reference numerals in the various examples. This repetition serves simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed herein.

[0008] A level shifter is a semiconductor device that can receive a digital input signal in a first voltage range and output a corresponding digital signal in a second voltage range. The second voltage range can be higher or lower than the first. Such a level shifter is used in circuits between parts of the circuit that have different voltage requirements, using an array of transistors to perform the desired conversion. In this way, parts of the circuit that can operate in a lower voltage range can operate in that lower voltage range, and parts of the circuit that are intended to operate in a higher voltage range can operate within that higher voltage range. The level shifter couples with both parts of the circuit so that they can communicate with each other.When it functions as an interface, a level converter can be described as the conversion from an input voltage range (e.g., a voltage range from a V to b V) to an output voltage range (e.g., a voltage range from x V to y V).

[0009] Level shifters are susceptible to several limitations. For example, the magnitude of the difference between the input voltage range and the output voltage range (e.g., the difference between a-to-x and b-to-y) is typically limited to certain ranges due to the various limitations and characteristics of the level shifter transistors. Additionally, there is a delay associated with level shifter devices due to the number of transistors an input signal passes through before reaching the output. For example, a typical delay associated with a level shifter might be a three-gate delay. Furthermore, some level shifter designs are affected by leakage current during operation, which increases the level shifter's power consumption.

[0010] Level-shifting devices described herein can be implemented using various types of semiconductor devices (e.g., MOSFETs, CMOS, etc.) which, in some embodiments, achieve various combinations of one or more of the following advantages: an increased voltage difference between an input voltage range and an output voltage range, increased speed of the level-shifting process, and reduced leakage current. In some embodiments, one or more of these advantages can be achieved by using an intermediate circuit that operates in an intermediate voltage range between the lower and higher voltage ranges, as described in more detail below.

[0011] Fig. Figure 1 is a block diagram of an example of a level shifter according to some embodiments. As shown in Fig. As shown in Figure 1, a level shifter 100 comprises one input (IN) and one output (OUT). Input signals are in an input voltage range (Vdd), and output signals are in an output voltage range (Vddm). As discussed previously, the input voltage range (Vdd) can be higher or lower than the output voltage range (Vddm). In the Fig. In the embodiment shown in Figure 1, the output voltage range (Vddm) is higher than the input voltage range (Vdd).

[0012] As described herein, the input signal at IN and the output signal at OUT are digital signals. Accordingly, the signals have a logic low value (e.g., 0 volts) and a logic high value (e.g., 3 volts). In the input voltage range (Vdd), the logic high voltage can be Vdd volts. In the output voltage range (Vddm), the logic high voltage can be Vddm volts.

[0013] The in Fig. The level converter 100 shown comprises an inverter circuit 101 operating in an input voltage range (Vdd) for inverting an input signal to generate an inverted input signal INB. The level converter 100 also includes an intermediate circuit 102 for receiving the input signal IN and generating an intermediate signal OUTB in an intermediate voltage range (Vint). The output INB of the inverter circuit 101 is also an input for the intermediate circuit 102. The intermediate signal OUTB and an inverted input signal INB are fed into an output buffer circuit 103 to generate, at least partially, an output signal OUT in an output voltage range based on the inverted input signal INB and the intermediate signal OUTB. As shown, the inverter circuit 101 can be operated at an input range voltage (Vdd), and the output buffer circuit 103 can be operated at the output range voltage (Vddm).The intermediate circuit 102 can be operated with an intermediate voltage Vint that lies between the input range voltage (Vdd) and the output range voltage (Vddm). In embodiments, the intermediate voltage can be slightly lower than the output voltage (Vddm) (e.g., closer to Vddm than to Vdd). In some embodiments, the intermediate voltage (Vint) can be generated by applying a voltage drop across the output voltage (Vddm).

[0014] Fig. Figure 2 shows a schematic diagram of a first example of a level converter according to some embodiments. As in Fig. As shown in Figure 2, a level converter 200 contains one input (IN) and one output (OUT). The level converter 200 can be represented by a circuit diagram that corresponds to the block diagram of the level converter 100 in Figure 2. Fig. 1 corresponds to input signals within an input voltage range (Vdd) and output signals within an output voltage range (Vddm). As discussed previously, the input voltage range (Vdd) can be higher or lower than the output voltage range (Vddm). In the Fig. In the embodiment shown in Figure 2, the output voltage range (Vddm) is higher than the input voltage range (Vdd).

[0015] As described herein, the input signal at IN and the output signal at OUT are digital signals. Accordingly, the signals have a logic low value (e.g., 0 volts) and a logic high value (e.g., 3 volts). In the input voltage range (Vdd), the logic high voltage can be Vdd volts. In the output voltage range (Vddm), the logic high voltage can be Vddm volts.

[0016] As in Fig. As shown in Figure 2, the level shifter 100 is implemented using complementary metal-oxide-semiconductor (CMOS) technology (e.g., NMOS and PMOS transistors). In operation, CMOS transistors function like switches – in an ON state, the switch is closed, and in an OFF state, the switch is open. For NMOS transistors (e.g., MN1, MN2, MN3), if a voltage exceeding a threshold voltage (Vth) of the NMOS transistor is applied to the gate, the NMOS transistor switches on and a current flows between a source and a drain; otherwise, the NMOS transistor is OFF and a current between the source and the drain is prevented. For a PMOS transistor (e.g.,MP1, MP2, MP3, MP4, MP5, MP6) applies if a voltage exceeding the threshold voltage (Vth) of the PMOS transistor is applied to the gate, the PMOS transistor is OFF and a current between the source and the drain is prevented; otherwise, the PMOS transistor is ON and a current flows between the source and the drain.

[0017] The level shifter 200 includes an inverter INV 101, which operates in the Vdd voltage range. The level shifter 200 also includes an intermediate circuit 102, which in turn comprises two pull-low NMOS transistors (MN1, MN2), two cross-coupling PMOS transistors (MP1, MP2), and stacked PMOS transistors (MP3, MP4) between the pull-low NMOS transistors (MN1, MN2) and the cross-coupling PMOS transistors (MP1, MP2). The transistors MP1, MP2, MP3, MP4, MN1, and MN2 operate in an intermediate voltage range between Vdd and Vddm. In some embodiments, these transistors can form a circuit such as shown in Fig. The intermediate circuit 102 shown in Figure 1 forms the basis for this. As shown, a voltage Vddm is applied to a voltage drop circuit VDC, which is configured to reduce the voltage applied to MP1 and MP2 to a voltage less than Vddm. In some embodiments, the voltage drop can be less than a threshold voltage of one or more of the transistors shown in the level shifter 200 (e.g., less than or equal to the threshold voltage of MP5). The level shifter 200 further comprises an output buffer circuit 103 with two stacked PMOS transistors (MP5, MP6) and one NMOS transistor (MN3). The output buffer circuit 103 operates within a voltage range of Vddm.

[0018] In Fig. In step 2, the intermediate signal OUTB is coupled to the gate of MP5, and the intermediate signal INB is coupled to the inputs of MP6 and MN3. In some embodiments, the threshold voltage of MP5 can be greater than the voltage drop generated by the voltage drop circuit VDC. As discussed in more detail below, the voltage drop circuit VDC can be implemented in various ways (e.g., a regulator, a PMOS device configured as a diode, or an NMOS device configured as a diode).

[0019] During operation, an input signal at IN is sent to inverter INV 101 and to MN1 and MP3. If the input signal at IN is a logic low (e.g., 0 volts), the output of inverter INV 101 is a logic high (e.g., Vdd volts), MN1 remains OFF, and MP3 is switched on. The output of inverter INV 101 causes the NMOS transistor MN2 to switch on, resulting in a logic low voltage being applied to MP1, which then switches MP1 on. Since both MP1 and MP3 are switched on, the voltage at OUTB is the intermediate voltage Vddm minus the voltage drop caused by the voltage drop circuit. A logic high for OUTB causes MP5 to switch off, and a logic high for INB causes MP6 to remain off while MN3 is switched on. As a result, the voltage at output OUT is the same as the voltage at input IN – e.g., 0 volts.

[0020] If the input signal at input IN is a logic high value (e.g., Vdd volts), the output of inverter INV 101 is a logic low value (e.g., 0 volts), MN1 is switched on, and MP3 is switched off. As a result, the intermediate signals OUTB and INB are both a logic low value (e.g., 0 volts). This causes MP5 and MP6 to be switched on, while MN3 is switched off. Consequently, the voltage at output OUT is a logic high value – e.g., Vddm volts.

[0021] In some embodiments, to reduce leakage current, the threshold voltage (Vth) of MP5 can be chosen to be greater than the voltage drop of the voltage drop circuit (VDC). Consequently, when OUTB is logic high, the intermediate voltage (Vddm minus the voltage drop) can completely turn off MP5, since the intermediate voltage remains greater than the threshold voltage (Vth) of MP5.

[0022] According to the invention, the threshold voltage of MP1, MP2, MP3, and MP4 is equal to or lower than the threshold voltage of MN1 and MN2. In some embodiments, it may be desirable to increase the threshold voltage of MN1 and MN2 as much as possible. In particular, this configuration holds MN1 and MN2 in a logic high state for a longer period of time and allows MN1 and MN2 to turn off more quickly when transitioning to a logic low state. By delaying these transitions of MN1 and MN2 to an ON state, the level shifter is affected by reduced leakage current, since the time during the transitions when the current flows through MN1 and MN2 to ground is shorter.

[0023] In some embodiments, transistor MP6 can be used to prevent a DC current between Vddm and ground. For example, when the input signal at IN transitions from a logic high to a logic low, the INB signal transitions to a logic high before the OUTB signal transitions to a logic high. Furthermore, when the input signal IN transitions from a logic high to a logic low, the INB signal also transitions to a logic high. This turns MP6 off, thus preventing current from Vddm to ground, even if MP5 may still be turned on. As can be seen from the discussion above, the operation of the level shifter 200 differs depending on the value of the input signal (IN). When the input signal transitions from a logic high to a logic low, the gate delay for INB is a 1 (1) gate delay, which is attributed to the inverter (INV 101).This means that when the input signal at the IN voltage drops below the threshold voltage (Vth) of the transistors in the INV 101 inverter circuit, the INB signal transitions to a logic high value (e.g., Vdd volts), and the delay in this transition is only one (1) gate delay. When the input signal transitions from a logic high to a logic low value, the gate delay for OUTB is three (3) gate delays, which are attributed to the INV 101 inverter, MN2, and MP1. In other words, when the input signal voltage drops below the threshold voltage (Vth) of the transistors in the INV 101 inverter circuit, the INB signal transitions to a logic high value (e.g., Vdd volts), MN2 is turned on, and its drain (or the gate of MP1) is pulled low (ground) at the source of MN2, thus turning MP1 on. Since MP3 and MP1 are enabled, OUTB goes to a logical high value at the source of MP1 (i.e.,The source voltage of MP1 is equal to the intermediate voltage. This results in a total of three (3) gate delays for INV 101, MN2, and MP1. As a result, MP5 is not turned off until, after three (3) gate delays, MP6 disconnects the voltage Vddm from ground at the source of MN3.

[0024] As described above, the gate delay attributed to level shifter 200 when the input signal (IN) transitions from high to low is a 3 (3) gate delay. However, when the input signal (IN) transitions from low to high, the gate delay is a 2 (2) gate delay – transistor MN1 is turned on, so OUTB is pulled low (ground) at the source of MN1. Then, output buffer 103 switches the output value at OUT to a logical high (Vddm) at the source of MP5. Accordingly, in some embodiments the cumulative gate delay for the level converter 200 may be less than a three (3) gate delay (e.g. a delay of 2.5 gate delay, which is equal to the average of 3 gate delay and 2 gate delay).

[0025] In exemplary embodiments, the level converter 200 can operate in various Vdd / Vddm ranges. In some embodiments, for example, Vdd can be between 0.33 and 1.115 volts and Vddm between 0.6 and 1.15 volts. In embodiments, the Vdd and Vddm can be any combination of these Vdd and Vddm values, including, for example, a Vdd of less than 0.5 volts and a Vddm of greater than 0.9 volts.

[0026] Fig. Figure 3 shows a schematic diagram of a second example of a level converter according to some embodiments. The one in Fig. The level converter 300 shown is essentially similar to the level converter 200 of the Fig. 2, except that the OUTB signal is connected to MP6 and MN3 (instead of MP5), and the INB signal is connected to MP5 (instead of MP6 and MN3). In operation, the level shifter 300 functions similarly to the above, except that the operation of the output buffer 103 is reversed. Accordingly, when OUTB is a logic low, MP6 is turned on and MN3 is off; when OUTB is a logic high, MP6 is turned off and MN3 is on; when INB is a logic low, MP5 is turned on; and when INB is a logic high, MP5 is turned off. Overall, the level shifter 300 operates in the same way as the level shifter 200, which is described with reference to Fig. 2 was described.

[0027] Fig. Figure 4 shows a schematic diagram of a third example of a level converter according to some embodiments. The one in Fig. The level converter 400 shown is essentially similar to the level converter 200 of the Fig. 2, except that the voltage drop circuit VDC is replaced by a PMOS transistor MPH. As shown, the gate of the PMOS transistor is coupled to the drain of the transistor to create a two-junction diode. This configuration of MPH causes a voltage drop across MPH that is essentially equal to the threshold voltage (Vth) of MPH. Accordingly, the intermediate voltage in the level shifter is 400 Vddm minus the Vth of MPH. In some embodiments, the threshold voltage (Vth) of MPH is lower than the threshold voltage of MP5.

[0028] Fig. Figure 5 shows a schematic diagram of a fourth example of a level converter according to some embodiments. The one in Fig. The level converter 500 shown in Figure 5 is essentially similar to the level converter 400. Fig. 4 except that the OUTB signal is connected to MP6 and MN3 (instead of MP5) and the INB signal is connected to MP5 (instead of MP6 and MN3), as in the Fig. 3. Accordingly, the level converter 500 operates similarly to the one shown in Figure 3. Fig. The operation shown in Figure 3 is similar to that described above, except that the operation of output buffer 103 is reversed. Accordingly, when OUTB is a logic low, MP6 is turned on and MN3 is off; when OUTB is a logic high, MP6 is turned off and MN3 is on. When INB is a logic low, MP5 is turned on; and when INB is a logic high, MP5 is turned off.

[0029] Fig.Figure 6 shows a flowchart illustrating the operation of a level shifter according to some embodiments. In operation 601, the level shifter 100 receives an input signal at an input IN. The input voltage signal is within an input voltage range (e.g., Vdd). In operation 602, the level shifter 100 generates a first intermediate signal INB within the input voltage range (e.g., Vdd) by inverting the input signal. In some embodiments, an inverter (101, INV) can be used to invert the input signal and the output INB. In operation 603, the level shifter 100 generates a second intermediate signal OUTB within an intermediate voltage range (e.g., Vddm minus a voltage drop).In some embodiments, the part of the level shifter 100 for generating the second intermediate signal can include an intermediate circuit 102 comprising two pull-low NMOS transistors (MN1, MN2), two cross-coupling PMOS transistors (MP1, MP2), and stacked PMOS transistors (MP3, MP4) between the pull-low NMOS transistors (MN1, MN2) and the cross-coupling PMOS transistors (MP1, MP2). Transistors MP1, MP2, MP3, MP4, MN1, and MN2 operate in the intermediate voltage range (Vint). In operation 604, the level shifter 100 generates an output signal at OUT in an output voltage range (e.g., Vddm) using the first intermediate signal INB and the second intermediate signal OUTB. In some embodiments, the part of the level shifter 100 for generating the output signal can be an output buffer circuit 103 comprising two stacked PMOS transistors (MP5, MP6) and one NMOS transistor MN3. The buffer circuit 103 operates in a voltage range of Vddm.

[0030] Some embodiments described herein may include a level shifter having an input operating within an input voltage range and an output for outputting a signal within an output voltage range. The level shifter further includes an inverter circuit for inverting an input signal operating within the input voltage range to generate an inverted input signal. The level shifter also includes an intermediate circuit operating within an intermediate voltage range to generate an intermediate signal. An output buffer circuit generates the output signal at least partially based on the inverted input signal and the intermediate signal.

[0031] Some embodiments described herein may include a level shifter comprising an inverter circuit, an intermediate circuit, and an output buffer circuit. The inverter circuit operates in an input voltage range to invert an input signal in order to generate an inverted input signal. The intermediate circuit receives the input signal and generates an intermediate signal in an intermediate voltage range. The intermediate circuit comprises two pull-low NMOS transistors, two cross-coupling PMOS transistors, and stacked PMOS transistors between the pull-low NMOS transistors and the cross-coupling PMOS transistors. The level shifter also includes an output buffer circuit for generating an output signal in an output voltage range at least partially based on the inverted input signal and the intermediate signal. The output buffer signal comprises at least two inputs, two stacked PMOS transistors, and one NMOS transistor.

[0032] Some embodiments described herein may include a method for operating a level converter, comprising receiving an input signal in an input voltage range and generating a first intermediate signal in the input voltage range by inverting the input signal. The method further comprises generating a second intermediate signal in an intermediate voltage range and generating an output signal in an output voltage range at least partially based on the first and second intermediate signals.

[0033] The foregoing outlines features of some embodiments so that the person skilled in the art may better understand the aspects of the present disclosure. The person skilled in the art should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or the same advantages of the embodiments described herein. The person skilled in the art should also recognize that such equivalent designs do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications to it without deviating from the spirit and scope of the present disclosure.

Claims

[1] Level converter, comprising: an input that operates within a specific input voltage range; an inverter circuit (101) operating in the input voltage range for inverting an input signal (IN) to generate an inverted input signal (INB); an intermediate circuit (102) operating in an intermediate voltage range for generating an intermediate signal (OUTB); an output buffer circuit (103) for generating an output signal (OUT) at least partially based on the inverted input signal (INB) and the intermediate signal (OUTB); and an output for outputting the output signal (OUT) in an output voltage range, wherein the intermediate circuit (102) comprises two pull-low NMOS transistors (MN1, MN2), two cross-coupling PMOS transistors (MP1, MP2), and stacked PMOS transistors (MP3, MP4) between the two pull-low NMOS transistors (MN1, MN2) and the two cross-coupling PMOS transistors (MP1, MP2), where the threshold voltage of the cross-coupling PMOS transistors (MP1, MP2) and the stacked PMOS transistors (MP3, MP4) is equal to or lower than the threshold voltage of the pull-low NMOS transistors (MN1, MN2). [2] Level shifter according to claim 1, wherein the output buffer circuit (103) comprises two stacked PMOS transistors (MP5, MP6) and one NMOS transistor (MN3). [3] Level converter according to one of the preceding claims, wherein the output buffer circuit (103) comprises two inputs, and the intermediate signal (OUTB) is fed into one input and the inverted input signal (INB) is fed into the other input. [4] Level converter according to one of the preceding claims, wherein an input voltage (Vdd) is applied to the inverter circuit (101), an intermediate voltage (Vint) is applied to the intermediate circuit (102), and an output voltage (Vddm) is applied to the output buffer circuit (103). [5] Level converter according to claim 4, wherein the input voltage (Vdd) is equal to, less than, or greater than the output voltage (Vddm). [6] Level converter according to claim 4, wherein the intermediate voltage (Vint) is smaller than the output voltage (Vddm) and larger than the input voltage (Vdd). [7] Level converter according to any one of claims 4 to 6, wherein the intermediate voltage (Vint) is generated by applying a voltage drop to the output voltage (Vddm). [8] Level converter according to claim 7, wherein the voltage drop is generated by a MOS transistor (MPH) configured as a diode. [9] Level converter according to any of the preceding claims, wherein there is a two-gate delay from the input to the output when the input transitions from a logical low value to a logical high value. [10] Level converter according to one of the preceding claims, wherein a cumulative gate delay for the level converter is less than a 3-gate delay. [11] Level converter, comprising: an inverter circuit (101) that operates in an input voltage range, to invert an input signal (IN) to generate an inverted input signal (INB); an intermediate circuit (102) for receiving the input signal (IN) and for generating an intermediate signal (OUTB) in an intermediate voltage range, wherein the intermediate circuit (102) comprises two pull-low NMOS transistors (MN1, MN2), two cross-coupling PMOS transistors (MP1, MP2) and stacked PMOS transistors (MP3, MP4) between the pull-low NMOS transistors (MN1, MN2) and the cross-coupling PMOS transistors (MP1, MP2); and an output buffer circuit (103) for generating an output signal (OUT) in an output voltage range at least partially based on the inverted input signal (INB) and the intermediate signal (OUTB), wherein the output buffer circuit (103) comprises at least two inputs, two stacked PMOS transistors (MP5, MP6) and one NMOS transistor (MN3), where an input voltage (Vdd) is applied to the inverter circuit (101), an intermediate voltage (Vint) is applied to the intermediate circuit (102), and an output voltage (Vddm) is applied to the output buffer circuit (103), where the intermediate voltage (Vint) is generated by reducing the output voltage (Vddm) using a voltage drop circuit (VDC), where the threshold voltage of one or more of the stacked PMOS transistors (MP5, MP6) is greater than the voltage drop generated by the voltage drop circuit (VDC). [12] Level converter according to claim 11, wherein the output buffer circuit (103) comprises two inputs, and the intermediate signal (OUTB) is fed into one input and the inverted input signal (INB) is fed into the other input. [13] Level converter according to claim 11 or 12, wherein the input voltage (Vdd) is equal to, less than, or greater than the output voltage (Vddm). [14] Level converter according to any one of claims 11 to 13, wherein the intermediate voltage (Vint) is equal to, less than, or greater than the output voltage (Vddm) and greater than the input voltage (Vdd). [15] Level shifter according to one of claims 11 to 14, wherein the voltage drop is generated by a MOS transistor (MPH) configured as a diode. [16] Level converter according to any one of claims 11 to 15, wherein a cumulative gate delay for the level converter is less than a 3-gate delay.

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