Cable routing design for dummy metal cap and redistribution cable

Abstract

Package (100) containing: a first dielectric layer (28); a device die (36) which is arranged above and attached to the first dielectric layer; an active via (32A) and a dummy via (32B); an encapsulation material (48) that encapsulates the device die (36), the active via (32A) and the dummy via (32B); a second dielectric layer (50) over and in contact with the device die (36), the active via (32A) and the dummy via (32B); an active metal cap (56A) which is arranged over and in contact with the second dielectric layer (50) and is electrically connected to the active via (32A), wherein the active metal cap (56A) covers the active via (32A); a dummy metal cap (56B) over and in contact with the second dielectric layer (50), wherein the dummy metal cap (56B) covers the dummy via (32B) and the dummy metal cap (56B) is divided by a first gap into a first part and a second part; and a first redistribution line (56C) passing through the gap, wherein the first part of the dummy metal cap (56B), the second part of the dummy metal cap (56B), the first gap and the first redistribution line (56C) are arranged at the same level.

Description

Background of the invention

[0001] With the advancement of semiconductor technologies, semiconductor chips / dies are becoming increasingly smaller. More functions now need to be integrated into the semiconductor die. Therefore, semiconductor dies must have ever-increasing numbers of I / O pads integrated into smaller units of area, and the density of I / O pads is increasing rapidly over time. This makes packaging of semiconductor dies more difficult, which affects packaging yield.

[0002] Conventional packaging technologies can be divided into two categories. In the first category, dies are packaged on a wafer before being sawn. This packaging technology has several advantages, such as higher throughput and lower cost. It also requires less underfill or mold compound. However, this packaging technology also has disadvantages, as die sizes are becoming smaller and the packages can only be fan-in packages, where the I / O pads of each die are confined to an area directly above the surface of the respective die. If the die areas are limited, the number of I / O pads is restricted by the restriction of the I / O pad pitch. If the pad pitch is to be reduced, solder bridges can occur.If a fixed ball size is required, the solder balls must also have a specific size, which in turn limits the number of solder balls that can be integrated on the surface of a die.

[0003] In the other packaging category, the dies are separated from the wafers before being packaged. One advantage of this packaging technology is the ability to produce fan-out packages, which means the I / O pads on a die can be redistributed over a larger area than the die itself, thus increasing the number of I / O pads integrated on the die surfaces. Another advantage of this packaging technology is that only proven good dies are packaged, and defective dies are discarded, thus avoiding wasted cost and effort on defective dies.

[0004] In a fan-out package, a component die is encapsulated in a mold compound, which is then planarized to expose the component die. Redistribution lines are then fabricated and connected to the component die. The fan-out package may also include vias that extend through the mold compound.

[0005] US 2016 / 0093572 A1 relates to a device comprising a first redistribution layer (RDL) having first lands arranged on a lower surface of the first RDL and active contact areas arranged on an upper surface of the first RDL. Short description of the drawings

[0006] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. The Fig. 1 to 14 are cross-sectional views of intermediate stages in the fabrication of a package with front-side redistribution lines according to some embodiments. The Fig. 15 and Fig. 16 are cross-sectional views of intermediate stages in the fabrication of a package with front and back redistribution lines according to some embodiments. Fig. 17 is a top view of a package according to some embodiments. The Fig. 18 to 21 are plan views of dummy metal caps according to some embodiments. Fig. 22 shows a process flow for manufacturing a package according to some embodiments. Detailed description

[0007] The invention is defined by the subject-matter of the independent claims. The dependent claims relate to corresponding further developments. The following description provides many different embodiments or examples for implementing various features of the provided subject-matter. Specific examples of components and arrangements are described below to facilitate the present invention. These are, of course, only examples and are not intended to be limiting. For example, the manufacture of a first element over or on a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact.Furthermore, reference numerals and / or letters may be repeated in the various examples throughout the present invention. This repetition is for simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of an element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0009] A package and a method of manufacturing the same are provided according to various exemplary embodiments. Intermediate stages of manufacturing the package according to some embodiments are explained. Furthermore, some variations of some embodiments are discussed. Throughout the various illustrations and illustrative embodiments, similar reference symbols are used to refer to similar elements.

[0010] The Fig. 1 to 14 show sectional views of intermediate steps in the manufacture of a package according to some embodiments. The steps shown in the Fig. 1 to 14 are also schematically indicated in the process flow 200 shown in Fig. 22 is shown.

[0011] Fig. 1 shows a carrier 20 and a release layer 22 applied to the carrier 20. The carrier 20 may be a glass carrier, a ceramic carrier, or the like. The carrier 20 may have a round plan view shape and may be the size of a silicon wafer. For example, the carrier 20 may have a diameter of 8 in., 12 in., or the like. The release layer 22 may be made of an LTHC (light-to-heat conversion) coating material that is removed along with the carrier 20 from overlying structures fabricated in later steps. In some embodiments of the present invention, the release layer 22 is made of a heat-removable, epoxy-based material. The release layer 22 may be applied to the carrier 20.

[0012] A dielectric layer 28 is formed over the release layer 22. The underside of the dielectric layer 28 may be in contact with the top side of the release layer 22. In some embodiments of the present invention, the dielectric layer 28 is made of a polymer, which may be a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In alternative embodiments, the dielectric layer 28 is made of an inorganic dielectric material, which may be a nitride such as silicon nitride, an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), or the like.

[0013] The Fig. 2 to 4 show the manufacture of metal columns 32A and 32B, collectively referred to as metal columns 32. The corresponding step is indicated as step 202 in the process flow shown in Fig. 22. Throughout the description, the metal pillars 32 are alternatively referred to as vias 32 because the metal pillars 32 pass through the encapsulation material that will be distributed later.

[0014] In Fig. 2, a metal seed layer 29 is formed, for example, by physical vapor deposition (PVD). The metal seed layer 29 may comprise copper, or in some embodiments, it may comprise a titanium layer and a copper layer over the titanium layer. A photoresist 30 is formed over the metal seed layer 29. The photoresist 30 is then exposed using a photolithographic mask (not shown). After subsequent development, openings 31 are formed in the photoresist 30. Some portions of the metal seed layer 29 are exposed through the openings 31.

[0015] As in Fig. 3, the vias 32 (comprising 32A and 32B) are then formed by plating a metal material in the openings 31. The plated metal material may be copper or a copper alloy. In subsequent steps, the photoresist 30 is removed, thereby exposing the underlying portions of the metal seed layer 29. The exposed portions of the metal seed layer 29 are then removed in an etching step. The resulting vias 32 are shown in Fig. 4. Throughout the description, the remaining portions of the metal seed layer 29 are considered parts of the vias 32 and are not illustrated individually. The vias 32 include functional (active) vias 32A and dummy vias 32B, the functions of which are discussed in subsequent paragraphs.

[0016] Fig. 5 shows the placement / arrangement of a component die 36. The corresponding step is indicated as step 204 in the process flow shown in Fig. 22. The device die 36 is attached to the dielectric layer 28 via a die attach layer (DAF) 38, which is an adhesion layer. The device die 36 may have a semiconductor substrate with a backside (the surface facing down) that is in physical contact with the DAF 38. The device die 36 may have integrated circuit elements (such as active devices including, for example, transistors; not shown) on the frontside (the surface facing up) of the semiconductor substrate. The device die 36 may be a logic die, such as a CPU die (Central Processing Unit), a GPU die (Graphics Processing Unit), a mobile application die, or the like.

[0017] In some example embodiments, metal pillars 42 (such as copper pillars) are prefabricated as portions of the device die 36, with the metal pillars 42 being electrically connected to the integrated circuit elements, such as transistors (not shown), within the device die 36. In some embodiments of the present invention, a polymer fills the gaps between adjacent metal pillars 42 to form a top dielectric layer 44. The top dielectric layer 44 may also include a portion that covers and protects the metal pillars 42. The polymer layer 44 may be made of PBO or polyimide in some embodiments of the present invention.

[0018] Then, the device die 36 and the metal pillars 32 are encapsulated with an encapsulation material 48, as shown in Fig. 6. The corresponding step is indicated as step 206 in the process flow shown in Fig. 22. The encapsulant material 48 fills the gaps between adjacent vias 32 and the gaps between the vias 32 and the device die 36. The encapsulant material 48 may be a molding compound, a mold underfill, an epoxy, and / or a resin. The top surface of the encapsulant material 48 is higher than the top ends of the metal pillars 42. The molding compound may include a base material, which may be a polymer, a resin, an epoxy, or the like, and filler particles (not shown) in the base material. The filler particles may be dielectric particles of SiO2, Al2O3, silicon dioxide, or the like, and may be spherical.

[0019] In a subsequent step, which is Fig. 7, a planarization, such as a chemical mechanical polishing (CMP) or a mechanical grinding process, is performed to thin the encapsulation material 48 until the vias 32 and the metal pillars 42 are exposed. The corresponding step is indicated as step 206 in the process flow shown in Fig. 22. Due to the planarization, the upper ends of the vias 32 are substantially level (coplanar) with the top surfaces of the metal pillars 42 and substantially coplanar with the top surface of the encapsulation material 48.

[0020] The Fig. 8 and Fig. 9 show the fabrication of a first layer of front-side redistribution layers (RDLs) and the respective dielectric layer. In Fig. 8, a dielectric layer 50 is produced. The corresponding step is indicated as step 208 in the process flow shown in Fig. 22. In some embodiments of the present invention, the dielectric layer 50 is made of a polymer, such as PBO, polyimide, or the like. In alternative embodiments, the dielectric layer 50 is made of silicon nitride, silicon oxide, or the like. Openings 52 are then formed, for example, using a photolithographic process. The active vias 32A and the metal pillars 42 are exposed through the openings 52. In some embodiments of the present invention, the dummy vias 32B are exposed through the openings 52. In alternative embodiments of the present invention, the openings 52 are not formed to expose some or all of the dummy vias 32B, and therefore, after the openings 52 are formed, some or all of the dummy vias 32B are still completely covered by the dielectric layer 50.

[0021] Then in Fig. 6 metal structural elements 56 (comprising 56A, 56B, and 56C) are fabricated over the dielectric layer 50. The conductive structural elements 56 include (active) metal caps 56A, dummy metal caps 56B, and RDLs 56C over the dielectric layer 50, wherein the structural elements 56A, 56B, and 56C are arranged in the same metal layer and at the same level. The corresponding step is indicated as step 210 in the process flow shown in Fig. 22. Vias 54A are formed in the dielectric layer 50 to connect the metal pillars 42 and the active vias 32A to the overlying metal caps 56A and the RDLs 56C. The RDLs 56C include metal traces (metal lines) over the dielectric layer 50. In some embodiments of the present invention, the metal features 56 and the vias 54 (which include 54A and 54B) are formed in a plating process that includes depositing a seed layer (not shown), forming and patterning a photoresist (not shown) over the seed layer, and plating a metal material, such as copper or aluminum, over the seed layer. The seed layer and the plated material may be the same material or different materials.The patterned photoresist is then removed, and then the parts of the seed layer that were previously covered by the patterned photoresist are etched.

[0022] The metal caps 56A cover the corresponding active vias 32A, and the dummy metal caps 56B cover the corresponding dummy vias 32B. The metal caps 56A and the dummy metal caps 56B are larger than the vias 32, so that they are protected from the stress caused by the respective underlying vias 32A and 32B. In some embodiments where the openings 52 ( Fig. 8) are fabricated to expose the dummy vias 32B, the dummy vias 54B are fabricated in the dielectric layer 50, and they physically and electrically connect some or all of the dummy metal caps 56B to the dummy vias 32B. In alternative embodiments, no opening 52 ( Fig. 8) are fabricated to expose the dummy vias 32B, and the dummy metal caps 56B are separated from the underlying dummy vias 32B by the dielectric layer 50. The dummy vias 54B are represented by dashed lines to indicate that they may or may not be fabricated, and some dummy vias 54B may be fabricated while others are not.

[0023] As also in Fig. 9, the dummy metal caps 56B are divided into two (or more) parts, with the RDLs 56C passing through the gap / space between the separated parts of the dummy metal caps 56B. The metal caps 56A and the dummy metal caps 56B may have round top view shapes, as shown in the Fig. 17 to 21, so that the mechanical stress they impose on the surrounding dielectric structures is minimized. In alternative embodiments, the metal caps 56A and the dummy metal caps 56B may have other polygonal shapes, such as hexagonal shapes, octagonal shapes, or the like. The RDLs 56C may be connected to the metal caps 56A, the vias 54A, the metal pillars 42, and other conductive structural elements. The RDLs 56C are used to carry voltages, signals, currents, and the like.

[0024] In Fig. 10, in some embodiments of the present invention, a dielectric layer 60 is applied over the Fig. 9 is fabricated, and then openings are formed in the dielectric layer 60. Thus, some portions of the metal caps 56A and the RDLs 56C are exposed through the openings. The dielectric layer 60 may be fabricated using a material selected from the same group of candidate materials as used to fabricate the dielectric layer 50, such as PBO, polyimide, or BCB. Metal structural elements (RDLs) 58, including 58A and possibly 58B, are then fabricated. The RDLs 58A extend into the openings in the dielectric layer 60 to contact the metal caps 56A and / or the RDLs 56C.

[0025] In some embodiments of the present invention, some of the RDLs 58 (denoted by 58B and also referred to as metal bridges) are fabricated to connect the separated parts of the dummy metal caps 56B. As a result, the separated parts of one and the same dummy metal cap 56B and the respective overlying metal bridges 58B together form integrated metal structural elements. Therefore, the metal bridges 58B can improve the integrity of the dummy metal caps 56B, and thus the stress protection effect of the dummy metal caps 56B is enhanced.

[0026] In alternative embodiments of the present invention, some or all of the metal bridges 58B are not fabricated. Therefore, the separated portions of a single dummy metal cap 56B are electrically isolated from one another, and no metal structural element connects them. The metal bridges 58B are depicted by dashed lines to indicate that some or all of the metal bridges 58B may or may not be fabricated. When a dummy metal cap 56B does not have a connecting metal bridge thereover, the entire top surface of each of the separated portions of the dummy metal cap 56B is completely covered by the dielectric layer 60. Additionally, one or more of the separated portions of a dummy metal cap 56B may be completely enclosed by the dielectric layers 50 and 60.

[0027] Fig. Figure 11 illustrates the fabrication of a dielectric layer 62 and RDLs 64. The dielectric layer 60 may be fabricated from a material selected from the same group of candidate materials as used to fabricate the dielectric layers 50 and 60. The RDLs 64 may also be made from a metal, such as aluminum, copper, or tungsten, and / or an alloy thereof. It should be understood that the RDLs may have any number of layers, such as one layer or more than two layers, although in the illustrated exemplary embodiments, three RDLs (56, 58, and 64) are fabricated.

[0028] Fig. 12 illustrates the formation of a dielectric layer 66, under-bump metallizations (UBMs) 68, and electrical interconnect elements 70 according to some exemplary embodiments. The corresponding step is indicated as step 214 in the process flow illustrated in Fig. 22. The dielectric layer 66 may be formed from a material selected from the same group of candidate materials as used to form the dielectric layers 50 and 60. The dielectric layer 66 may be formed, for example, using PBO, polyimide, or BCB. Openings are formed in the dielectric layer 66 to expose the underlying metal pads that are parts of the RDLs 64. In some embodiments of the present invention, the UBMs 68 are formed to extend into the openings in the dielectric layer 66 to contact the RDLs 64. The UBMs 68 may be formed from nickel, copper, titanium, or multiple layers thereof.

[0029] The electrical interconnects 70 are then fabricated. Fabricating the electrical interconnects 70 may include placing solder balls on the exposed portions of the UBMs 68 and then reflowing the solder balls. In alternative embodiments of the present invention, fabricating the electrical interconnects 70 includes performing plating to form solder layers over the UBMs 68 and then reflowing the solder layers. The electrical interconnects 70 may also include metal pillars or metal pillars and solder caps, which may also be fabricated by plating. Throughout this specification, the structure including the dielectric layer 28 in combination with the overlying structure is referred to as a package 100, which is a composite wafer (and will also be referred to below as composite wafer 100) comprising a plurality of device dies 36.

[0030] Then, the package 100 is detached from the carrier 20, for example, by projecting UV light or a laser beam onto the release layer 22, so that the release layer 22 decomposes due to the heat of the UV light or the laser beam. This separates the package 100 from the carrier 20. The resulting package 100 is shown in Fig. 13. In some embodiments of the present invention, the resulting package 100 leaves the dielectric layer 28 as a lower portion of the package 100, protecting the vias 32. Laser drilling is then performed to remove some portions of the dielectric layer 28 to create openings 72 to expose the active vias 32A and the dummy vias 32B. Die dicing is then performed to separate the composite wafer 100 into individual packages 100'. The corresponding step is indicated as step 218 in the process flow shown in Fig. 22 is shown.

[0031] Fig. Figure 14 shows the bonding of a package 400 to the package 100', forming a package-on-package (PoP) structure 300 (package 300). The corresponding step is indicated as step 220 in the process flow shown in Fig. 22. Bonding is performed through solder regions 74, which connect vias 32A and 32B to metal pads 406 in the underlying package 400. In some embodiments of the present invention, package 400 includes a package substrate 404 and one or more device dies 402, which may be memory dies, such as SRAM (Static Random Access Memory) dies, DRAM (Dynamic Random Access Memory) dies, or the like.

[0032] In alternative embodiments of the present invention, backside RDLs are fabricated on the backside of the device die 36 instead of the openings 72 ( Fig. 13) in the dielectric layer 28 and then bond the package 400 directly to the package 200'. To fabricate the rear RDLs, first a carrier switching is performed at the Fig. 12, in which the electrical connecting elements 70 are attached to a carrier 80 ( Fig. 15) before the carrier 20 is removed.

[0033] Then the carrier 20 ( Fig. 12) is peeled off from the composite wafer 100, and the dielectric layer 28 is exposed. Metal features 26 (including metal caps 26A, dummy metal caps 26B, and RDLs 26C) and vias 25 / 25B are then fabricated. Fabrication may be performed in a manner similar to the fabrication of the conductive features 56 and vias 54, and therefore, the details will not be repeated.

[0034] Then, a dielectric layer 24 and metal structural elements 86A, 86B, 84A and 84B are produced, which are in Fig. 15. The corresponding step is indicated as step 216 in the process flow shown in Fig. 22. The dielectric layer 44 may be formed from a material selected from the same group of candidate materials as for the formation of the dielectric layers 50 and 60. The metal features 86A / 84A (including metal traces 86A and vias 84A) may also be formed from a metal such as aluminum, copper, or tungsten, and / or an alloy thereof. Some vias 84B1 are shown by dashed lines to indicate that these vias may or may not be formed, and solder regions 74 ( Fig. 16) may be electrically connected to some (but not all) of the separate parts in a dummy metal cap 26B, or they may be connected to all of the separate parts in a dummy metal cap 56B via the vias 84B1. A dielectric layer 85 may (or may not) be formed. Then, the composite wafer 100 is detached from the carrier 80, and a dicing / die sawing is performed to separate the composite wafer 100 into individual packages 100'. The resulting package 100' is then bonded to the package 400, and the resulting package 300 is in Fig. 16 shown.

[0035] In some embodiments described in the Fig. 14 and Fig. 16, the dummy vias 32B are electrically floating. For example, on the bottom surfaces of the dummy vias 32B, the metal pads 406 in the package 400 may be dummy pads, and they will not be electrically connected to underlying metal lines and the device dies 402. On the top surfaces of the dummy vias 32A, the entire top surfaces of the dummy vias 32B are covered with the dielectric layer 50 when the vias 54A are not formed. The dummy metal cap 56B may be fully embedded in the dielectric layers 50 and 60 (when the vias 54B and the metal bridges 58B are not formed), or it may form an integrated metal structure along the metal bridge 58B that is fully embedded in the dielectric layers 50, 60, and 62 (when the vias 54B are not formed).The integrated structural element is electrically floating. When the vias 54B are fabricated to connect them to the dummy vias 32B, respective metal bridges 58B, the vias 54B, and the dummy vias 32B may form interconnected metal structural elements that may be electrically floating.

[0036] The dummy vias 32B may also be electrically grounded or connected to one or more ungrounded voltages, and the electrically grounded or ungrounded voltages may be provided by the device dies 402. In some embodiments, the vias 32B are still dummy vias because they are configured to prevent currents from flowing through them. This may be achieved by terminating the traces at metal bridges 58B that are not electrically connected to an overlying metal structure. The traces may also be terminated at the dummy metal caps 56B if no metal bridges 58B are formed. The traces may also be terminated at the top ends of the dummy vias 32B if no vias 54B are formed.

[0037] In some embodiments of the present invention, the conductive structural elements located in a region 78 ( Fig. 16) and including vias 84B, metal traces / pads 86B, and solder region 70 are not fabricated. Thus, in a region 88, all metal features together are completely isolated within dielectric materials 24, 28, 48, 50, 60, and 62 and are electrically floating. Alternatively, vias 25B are not fabricated, and thus features 32B, 54B, 56B, and / or 58B are completely isolated within dielectric materials.

[0038] In alternative embodiments of the present invention, a plurality of vias 84B may be formed, each connected to one of the separate portions of the same dummy metal cap 26B, and the plurality of vias 84B may be electrically connected to the same solder region 74. In these embodiments, the dummy metal caps 26B may also be completely isolated within the dielectric layers 24 and 28 when the vias 84B are not formed.

[0039] Fig. Figure 17 shows a plan view of a portion of the package 100' that is shown in the Fig. 14 and Fig. 16, wherein the component die 36, the active vias 32A, and the dummy vias 32B are illustrated, while other structural elements are not illustrated. It should be understood that the illustrated layout of the vias 32 is merely an example, and that the actual number and positions of the vias 32A and 32B are determined based on the deflection situation of the package 100' and are selected to reduce the deflection of the package 100'. The sectional views of the package 100' shown in the Fig. 14 and Fig. 16 can be obtained from the plane that forms the line A - A of Fig. 17 contains.

[0040] Fig. Figure 18 shows a top view of the active metal caps 56A and the dummy metal caps 56B according to some embodiments. The dummy metal caps 56B can be divided into two parts 56B1 and 56B2 to allow the RDL 56C to pass through a gap / space therebetween. Therefore, although the dummy metal caps 56B are large and occupy a fairly large area, the gap used by the dummy metal caps 56B can still be used to guide the RDLs 56C. The dummy metal cap 56B on the left side of Fig. Figure 18 shows an example where the RDL 56C passes through the center of the dummy metal cap 56B. Therefore, no via 54B (see Fig. 14 and Fig. 16) for connection to the respective dummy metal cap 56B. The dummy metal cap 56B in the middle of Fig. Figure 18 shows an example where the RDL 56C passes through a location away from the center of the dummy metal cap 56B. Therefore, the via 54B may be made to connect to the respective dummy metal cap 56B (or not). The metal cap 56 on the right side of Fig. 18 represents an active metal cap 56A. Alternatively, the metal cap 56 on the right side of Fig. 18 represents a dummy metal cap 56B which is not subdivided and can be manufactured in areas with few RDLs.

[0041] Fig. Figure 19 shows some embodiments where more than one RDL 56C passes through a dummy metal cap 56B. The left dummy metal cap 56B is divided into three parts with two gaps between them, each gap having a passing RDL 56C. The right dummy metal cap 56B is divided into two parts, with two (or more) RDLs 56C passing through the same gap.

[0042] The Fig. 20 and Fig. 21 show some embodiments in which the RDLs 56C are not straight. The RDLs 56C may have two or more parts that form an angle α of about 30 degrees to about 150 degrees. In the examples shown in the Fig. 18 to 21, the metal bridges 58B are shown by dashed lines to indicate that they are optionally manufactured.

[0043] Here are some sample dimensions. Please note that these dimensions are only examples. Fig. 19, Fig. 20 and Fig. 21, a width A of the RDL 56C and distances B and C can be less than about 30 µm (where Fig. 18 has similar dimensions). A diameter D (or a length or width) of the dummy metal cap 56B may range from about 140 µm to about 230 µm. A diameter E (or a length or width) of the dummy via 32B may range from about 100 µm to about 190 µm. A diameter F (or a length or width) of the dummy via 54B may range from about 10 µm to about 60 µm.

[0044] Let us return to Fig. 16. On the back side of the component die 36, the dummy metal caps 26B are fabricated, with the RDLs 26C passing through the dummy metal caps 26B. The layouts of the dummy metal caps 26B and the RDLs 26C and the respective dimensions can be substantially the same as those shown in the Fig. 19 to 21, and they are not repeated here.

[0045] Embodiments of the present invention have several advantages. Dummy vias are formed to provide additional anchoring force for bonding to package 400 and to reduce package deflection. However, the dummy vias introduce stress into the RDL layers. To shield the stress caused by the dummy vias, large dummy metal caps are formed directly above or below the dummy vias. The dummy vias occupy a large die area and interfere with the routing of the RDLs. Therefore, in embodiments of the present invention, the dummy metal caps are divided into smaller pieces, and the RDLs are routed through the gaps between the smaller pieces.

[0046] According to some embodiments of the present invention, a package includes: a first dielectric layer; a device die disposed over and attached to the first dielectric layer; an active via and a dummy via; and an encapsulation material encapsulating the device die, the active via, and the dummy via. The package further includes a second dielectric layer disposed over and in contact with the device die, the active via, and the dummy via. An active metal cap is disposed over and in contact with the second dielectric layer and is electrically connected to the active via. The active metal cap covers the active via. A dummy metal cap is disposed over and in contact with the second dielectric layer.The dummy metal cap covers the dummy via. The dummy metal cap is divided into a first and a second part by a gap. A redistribution line runs through the gap between the first and second parts of the dummy metal cap.

[0047] According to some embodiments of the present invention, a package comprises: a device die; a dummy via; an encapsulation material encapsulating the device die and the dummy via; and a first dielectric layer over and in contact with the device die, the dummy via, and the encapsulation material. A dummy metal cap is disposed over and in contact with the first dielectric layer, the dummy metal cap covering the dummy via and extending beyond edges of the dummy via. A redistribution line is located at the same level as the dummy metal cap. The redistribution line separates the dummy metal cap into a first part and a second part.

[0048] According to some embodiments of the present invention, a method comprises the steps of: attaching a device die to a first dielectric layer; forming an active via and a dummy via over the first dielectric layer; encapsulating the device die, the active via, and the dummy via in an encapsulation material; forming a second dielectric layer over the encapsulation material; and depositing an active metal cap, a redistribution line, and a dummy metal cap in a common process. The active metal cap and the dummy metal cap cover the active via and the dummy via, respectively. The dummy metal cap is divided into a first part and a second part by the redistribution line.

Claims

[1] Package (100) with: a first dielectric layer (28); a device die (36) disposed over and attached to the first dielectric layer; an active via (32A) and a dummy via (32B); an encapsulation material (48) that encapsulates the device die (36), the active via (32A) and the dummy via (32B); a second dielectric layer (50) over and in contact with the device die (36), the active via (32A) and the dummy via (32B); an active metal cap (56A) disposed over and in contact with the second dielectric layer (50) and electrically connected to the active via (32A), the active metal cap (56A) covering the active via (32A); a dummy metal cap (56B) over and in contact with the second dielectric layer (50), the dummy metal cap (56B) covering the dummy via (32B) and the dummy metal cap (56B) being divided into a first part and a second part by a first gap; and a first redistribution line (56C) passing through the gap, wherein the first part of the dummy metal cap (56B), the second part of the dummy metal cap (56B), the first gap and the first redistribution line (56C) are arranged at the same level. [2] The package of claim 1, wherein the first part and the second part of the dummy via (56B) together form a substantially round shape, a hexagonal shape, or an octagonal shape. [3] Package according to claim 1 or 2, wherein the first part and / or the second part of the dummy via (56B) are electrically floating. [4] The package of any preceding claim, further comprising a via (54B) in the second dielectric layer (50), the via (54B) being connected to the first portion of the dummy metal cap (56B), and the dummy via (56B) and the first portion of the dummy metal cap (56B) being electrically floating together. [5] The package of any one of claims 1 to 3, further comprising a via (54B) in the second dielectric layer (50), the via being connected to the first part of the dummy metal cap (56B), and the dummy via (54A) and the first part of the dummy metal cap being commonly connected to a voltage and configured to prevent currents from flowing therethrough. [6] Package according to one of the preceding claims, further comprising a metal bridge (58B) connecting the first part to the second part of the dummy metal cap (56B). [7] The package of claim 6, wherein the metal bridge (58B) and the first and second parts of the dummy metal cap (56B) are electrically floating together. [8] A package according to any preceding claim, further comprising a second redistribution line (54B) passing through the first gap. [9] Package according to one of the preceding claims, wherein the dummy metal cap (56B) is divided into a third part by a second gap between the second part and a third part of the dummy metal cap (56B), and the package further comprises a second redistribution line (54B) in the second gap. [10] Package (100) with: a device die (36); a dummy via (32B); an encapsulation material (48) encapsulating the device die (36) and the dummy via (32B); a first dielectric layer (50) over and in contact with the device die (36), the dummy via (32B) and the encapsulation material (48); a first dummy metal cap (56B) over and in contact with the first dielectric layer (50), the first dummy metal cap (56B) covering the dummy via (32B) and extending beyond edges of the dummy via (32B); and a first redistribution line (56C), wherein the first redistribution line (56C) separates the first dummy metal cap (56B) into a first part and a second part and is at the same level as the first part and the second part of the dummy metal cap (56B). [11] The package of claim 10, wherein the first and second parts of the first dummy metal cap (56B) are electrically separated from each other. [12] The package of claim 10 or 11, further comprising a metal bridge (58B) over the first dummy metal cap (56B), the metal bridge (58B) connecting the first part to the second part of the first dummy metal cap (56B). [13] The package of any one of claims 10 to 12, further comprising a via (54B) in the first dielectric layer (50), the via (54B) connecting the first portion of the first dummy metal cap (56B) to the dummy via (32B), and the second portion of the first dummy metal cap (56B) is electrically floating. [14] Package according to one of claims 10 to 13, further comprising: a second dielectric layer (28) below and in contact with the dummy via (32B) and the encapsulation material (48); a second dummy metal cap (26B) below and in contact with the second dielectric layer (28), wherein the dummy via (32B) covers a portion of the second dummy metal cap (26B); and a second redistribution line (26C) at the same level as the second dummy metal cap (26B), the second redistribution line (26C) dividing the second dummy metal cap (26B) into a third part and a fourth part that are physically separated from each other. [15] The package of claim 14, wherein the first and second parts of the second dummy metal cap (26B) are each completely embedded in dielectric materials. [16] Procedure with the following steps: Attaching a device die (36) to a first dielectric layer (28); Producing an active via (23A) and a dummy via (32B) over the first dielectric layer (28); Encapsulating the device die (36), the active via (32A) and the dummy via (32B) in an encapsulation material (48); Producing a second dielectric layer (50) over the encapsulation material (48); and Depositing an active metal cap (56A), a redistribution line (56C) and a dummy metal cap (56B) in a common process, wherein the active metal cap (56A) and the dummy metal cap (56B) cover the active via (32A) and the dummy via (32B), respectively, and the dummy metal cap (56B) is divided into a first part and a second part by the redistribution line (56C), wherein the first part of the dummy metal cap (56B), the second part of the metal cap (56B) and the first redistribution line (56C) are arranged at the same level. [17] The method of claim 16, wherein the first and second parts of the dummy metal cap (56B) are separated from the redistribution line (56C) by a first gap and a second gap, respectively, and the method further comprises forming a third dielectric layer (60) filling the first gap and the second gap. [18] The method of claim 17, further comprising forming a plurality of conductive structural elements (58A, 58B) extending into the third dielectric layer (60), wherein the first and second portions of the dummy metal cap (56B) are electrically floating. [19] The method of claim 17, further comprising forming a plurality of conductive features (58A, 58B) extending into the third dielectric layer (60), wherein a metal bridge (58B) in the plurality of conductive features connects the first portion to the second portion of the dummy metal cap (56B), and the metal bridge (58B) is electrically floating. [20] The method of any one of claims 16 to 19, further comprising, in the joint process, forming a via (54B) connecting the first portion of the dummy metal cap (56B) to the dummy via (32B), wherein the via (32B) is located in the second dielectric layer (50), and no via in the second dielectric layer (50) is connected to the second portion of the dummy metal cap (56B).

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