Integrated circuit layouts with fill element shapes

Abstract

Method (200) comprising the following steps: Preparing (202) a layout (300, 800) for the manufacture of an integrated circuit (100); Inserting (204) a plurality of fill cells (302, 902) into the layout (300, 800), the plurality of fill cells (302, 902) comprising a plurality of fill line shapes (304, 306, 602, 604, 912, 1102) corresponding to conductive lines (126) of the integrated circuit (100); subsequently inserting (206) a design (402, 802) comprising a plurality of functional shapes (404, 406, 408, 804, 806, 808, 810, 812) into the layout (300, 800); Removing (208) a conflicting subset (304, 306, 912) of the plurality of fill line shapes (304, 306, 602, 604, 912, 1102) of the plurality of fill cells (302, 902) that conflicts with the plurality of functional shapes (404, 406, 408, 804, 806, 808, 810, 812); and Providing (214) the layout (300, 800) comprising the plurality of fill cells (302, 902) and the design (402, 802) for the manufacture of the integrated circuit (100); wherein the plurality of fill line shapes (304, 306, 602, 604, 912, 1102) of the plurality of fill cells (302, 902) is a first plurality (304, 306, 912) of fill line shapes (304, 306, 602, 604, 912, 1102); wherein the method, after removing (208) the conflicting subset (304, 306, 912), further comprises inserting (210) into the layout (300, 800) a second plurality (604, 606, 1102) of fill line shapes (304, 306, 602, 604, 912, 1102) corresponding to conductive lines (126) of the integrated circuit (100); wherein the first plurality (304, 306, 912) of fill line shapes (304, 306, 602, 604, 912, 1102) has a center-to-center spacing (608, 1104) different from that (610, 1106) of the plurality of functional shapes (404, 406, 408, 804, 806, 808, 810, 812); and wherein the second plurality (604, 606, 1102) of fill line shapes (304, 306, 602, 604, 912, 1102) and the plurality of functional shapes (404, 406, 408, 804, 806, 808, 810, 812) have the same center-to-center distance (610, 612, 1106, 1108).

Description

Background of the invention

[0001] The IC (semiconductor integrated circuit) industry has experienced rapid growth. Over the course of IC evolution, feature density (i.e., the number of interconnected components per chip area) has generally increased, while feature size (i.e., the smallest component or circuit that can be produced using a manufacturing process) has decreased. This process of downsizing generally offers advantages by increasing production output and reducing associated costs. However, with this downsizing has also come greater complexity in the design and manufacture of devices that use these ICs. Parallel advances in manufacturing have enabled the production of increasingly complex designs with high levels of precision and reliability.

[0002] Advances have been made in the fabrication of devices as well as the network of conductors that connect them. In this context, an integrated circuit may include an interconnect structure for electrically connecting the circuit elements, e.g., fin field-effect transistors (FinFETs), planar FETs, bipolar transistors (BJTs), light-emitting diodes (LEDs), memory devices, other active and / or passive devices, etc. The interconnect structure may comprise a number of dielectric layers stacked vertically, with conductive lines running horizontally within the layers. Vias may run vertically to connect conductive lines in one layer to conductive lines in an adjacent layer. Likewise, contacts may run vertically between the conductive lines and substrate-level features.Together, the leads, vias, and contacts transfer signals, power, and ground between the components, enabling them to operate as a circuit.

[0003] Methods for filling integrated circuits with fill lines are disclosed in WO 00 / 19490 A2, US 2002 / 0199162 A1, US 2009 / 0089732 A1 and US 2002 / 0185664 A1. Short description of the drawings

[0004] The present invention can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale and are for purposes of illustration only. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1A is a plan view of a portion of a device according to various aspects of the present invention. Fig. 1B is a cross-sectional view of the device according to various aspects of the present invention. Fig. 2 is a flow diagram of a method for supplementing a layout with conductive feature shapes according to various aspects of the present invention. The Fig. 3 to 6 are plan view illustrations of a portion of a layout according to various aspects of the present invention. Fig. 7 is a flowchart of a method for supplementing a layout with fill elements according to various aspects of the present invention. The Fig. 8 to 11 are plan view illustrations of a portion of a layout augmented with filler elements according to various aspects of the present invention. Fig. 12 is a block diagram of a computing system according to various aspects of the present invention. Detailed description

[0005] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to facilitate the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, dictate any relationship between the various embodiments and / or configurations discussed beyond the scope stated.

[0006] Furthermore, in the description below, the fabrication of an element on, or in conjunction with, another element may include embodiments where the elements are fabricated in direct contact, and may also include embodiments where further elements may be fabricated between the elements such that the elements are not in direct contact. Furthermore, to simplify the description of the relationship of one element to another element, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above," "over," "below," "beneath," "upward," "downward," "top," "down," etc., as well as their derivatives (e.g., "horizontal," "downward," "up," etc.), are used. The spatially relative terms are intended to cover various orientations of the device having the structural elements.

[0007] As device size decreases, the final size of an integrated circuit may depend as much on the interconnect structure as on the circuit elements. However, shrinking the interconnect structure has generally not been achieved. While the thickness of the conductive lines of the interconnect structure can be reduced, allowing more lines to be integrated into a given area, it has proven difficult to reliably fabricate thinner lines.

[0008] For example, it has been found that interconnect layers with thinner lines are more prone to surface irregularities. One reason may be that, due to differences in hardness, bumps or depressions appear in areas of dielectric interconnect layers that are not reinforced by a certain amount of conductive lines, even after chemical mechanical polishing / planarization (CMP). This results in the area having an irregular surface when the layer undergoes CMP. The irregular surface makes adding additional layers more risky, as alignment errors due to layer fluctuations often worsen with each additional interconnect layer. As interconnect sizes decrease, the interconnect layers can become more sensitive to line density.Furthermore, as interconnect sizes decrease, the influence of vias on reinforcing the dielectric layer becomes increasingly significant. However, at smaller via sizes, vias that are not connected to a conductive line (i.e., isolated vias) are often difficult to fabricate and suffer from shrinkage, necking, and other etching and filling problems.

[0009] As set forth below, the present invention provides a method for inserting additional conductive lines and vias into an interconnect structure to improve the uniformity of the interconnect layer. With the improved uniformity, the integrity of the interconnect structure can be improved and additional layers can be added to the interconnect structure. In some examples, these filler lines and vias (which may also be referred to as dummy lines or vias) are inserted into areas of a layout where functional lines and vias are missing. The filler lines and vias can be left floating or connected to a power source or ground, but unlike their functional counterparts, they generally do not contribute to the operation of the circuit.In some such examples, the fill lines and vias are contained within fill cells, and each cell can pattern the fill lines to properly cover the fill vias so that the fill vias are not interrupted.

[0010] In some examples, the fill cells may first be inserted into a layout, and the functional design is overlaid on top of the fill cells. The fill lines and vias that conflict with the functional design can be removed to create a layout for manufacturing. The remaining fill elements provide enough conductors to ensure that the final layout meets minimum line and via densities, thereby consistently maintaining layer uniformity. Because the fill cells provide fill lines that properly cover the fill vias, intermittent vias can be avoided.

[0011] In addition to vias and conductive lines, the interconnect structure may also have contacts that run vertically from a conductive line down to a semiconductor structure, such as a raised feature or a substrate on which the interconnect structure is fabricated. Discontinuous contacts can present many of the same manufacturing issues as discontinuous vias. To address this, in some examples, the design is populated with fill cells that include front end of line (FEOL) features (e.g., raised features, substrate features, and / or other semiconductor structures) and back end of line (BEOL) features (e.g., conductive lines) so that the fill contacts are uninterrupted. This can significantly improve the uniformity of the lowest layers of the interconnect structure.

[0012] Thus, some embodiments of the present invention enable greater uniformity of the interconnect structure. However, unless otherwise stated, no embodiment may offer a particular advantage.

[0013] Fig. 1A is a plan view of a portion of a device 100 according to various aspects of the present invention. Fig. 1B is a sectional view of the device 100 along a line 102 according to various aspects of the present invention. Fig. 1A and Fig. 1B have been simplified for clarity and to better illustrate the principles of the present invention. Additional structural elements may be incorporated into device 100, and in other embodiments of device 100, some of the structural elements described below may be replaced or omitted.

[0014] The device 100 includes a substrate 104 having one or more integrated circuit elements fabricated thereon. In various examples, the substrate 104 includes: an elemental (single-element) semiconductor, such as silicon or germanium in a crystal structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; a non-semiconductor material, such as soda-lime glass, fused silica, fused silica, and / or calcium fluoride (CaF2); and / or combinations thereof.

[0015] The substrate 104 may have a uniform composition or may include various layers. The layers may have similar or different compositions, and in various embodiments, some substrate layers may not have uniform compositions to induce a device voltage and thereby adjust device performance. Examples of multilayer substrates include silicon-on-insulator (SOI) substrates 104. In some examples, a layer of the substrate 104 may include an insulator, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxide nitride, a semiconductor carbide, and / or other suitable insulating materials.

[0016] Various circuit elements can be fabricated in and on the substrate 104. In some examples, the substrate 104 includes doped regions, such as source / drain regions 106. In various examples, the source / drain regions 106 are doped with p-type (p+) dopants, such as boron or BF2, or with n-type (n+) dopants, such as phosphorus or arsenic. The source / drain regions 106 may be disposed within the substrate 104 in an example of a planar circuit element or may extend from the substrate 104 in an example of a non-planar circuit element (e.g., a FinFET).

[0017] In some examples, device 100 includes gate stacks 108 disposed on substrate 104 between source / drain regions 106 to define a channel region therebetween. The flow of carriers (electrons for an n-channel device and holes for a p-channel device) through the channel region between source / drain regions 106 is controlled with a voltage applied to gate stack 108. Suitable gate stacks 108 include both polysilicon and metal gates.

[0018] The gate stacks 108 may include multiple layers, each of which may have one or more sublayers. In one example, the gate stack 108 includes: an interlayer 110 disposed on the substrate 104; a gate dielectric layer 112 disposed on the interlayer 110; and a gate electrode layer 114 disposed on the interlayer 110. The first layer, the interlayer 110, may include a metal silicate (e.g., HfSiO), a metal or semiconductor oxide, a metal or semiconductor nitride, a metal or semiconductor oxide nitride, and / or another suitable material. Disposed on the interlayer 110 is the gate dielectric layer 112, which may be characterized by its dielectric constant relative to silicon dioxide. A high-k gate dielectric layer 112 may include: a metal oxide, e.g.,LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HffaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, etc.; a metal silicate, e.g., HfSiO, LaSiO, AlSiO, etc.; a metal or semiconductor nitride; a metal or semiconductor oxide nitride; combinations thereof and / or other suitable materials. Finally, the gate electrode layer 114 may include layers of Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, and / or other suitable materials. In some examples, sidewall spacers are fabricated on one or more side surfaces of the gate stacks 108.

[0019] The device 100 includes an interconnect structure 116 for electrically connecting circuit elements, such as the source / drain regions 106 and the gate stack 108. The interconnect structure 116 includes a number of conductive features sandwiched between layers of an interlevel dielectric (ILD) 118. The ILD 118 may comprise any suitable material, such as a semiconductor oxide, a semiconductor nitride, a semiconductor oxide nitride, a semiconductor carbide, TEOS oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), carbon-doped silicon oxide, Black Diamond®, xerogel, aerogel, amorphous fluorocarbon, parylene, BCB (bis-benzocyclobutene), SiLK® (a registered trademark of Dow Chemicals, Midland, Michigan), polyimide, other suitable materials, or combinations thereof. Layers of ILD 118 function to support and electrically isolate the conductive structural elements.

[0020] In a bottom layer 120A of the interconnect structure 116, the ILD 118 may support and electrically isolate the gate stacks 108 as well as contacts that connect to substrate features, such as source / drain (S / D) contacts 122, that extend to and electrically connect to the source / drain regions 106. Contacts, such as the S / D contacts 122, may include one or more layers of conductive materials, such as metals (e.g., Ti, Ta, W, Al, Ni, Cu, Co, etc.), metal nitrides, metal oxides, metal carbides, and / or other suitable materials. In one example, an S / D contact 122 includes adhesion layers of Ti and TiN disposed on the substrate 104, with a fill layer of W or Al disposed on the adhesion layers.The contacts in the bottom layer 120A may be formed simultaneously with the gate stacks 108, and a CMP process to planarize the bottom layer 120A may cause the top surfaces of these contacts (e.g., the S / D contacts 122) to become substantially coplanar with the top surfaces of the gate stacks 108.

[0021] The next layer 120B of the interconnect structure 116 may include mid-level contacts 124 in the ILD 118 that extend to and electrically connect to the S / D contacts 122 and the gate stacks 108. Like the S / D contacts 122, the mid-level contacts 124 may include one or more layers of conductive materials, such as metals (e.g., Ti, Ta, W, Al, Ni, Cu, Co, etc.), metal nitrides, metal oxides, metal carbides, and / or other suitable materials. The mid-level contacts 124 in layer 120B may also electrically and physically connect to features at higher levels in the interconnect structure 116, such as conductive lines 126 in a layer 120C.

[0022] As can be seen, each layer 120 of the interconnect structure 116 may include contacts (e.g., the S / D contacts 122 and the mid-plane contacts 124), the conductive lines 126, vias 128, or combinations thereof disposed within the ILD 118. For example, layer 120C includes conductive lines 126, while layer 120D includes conductive lines 126 and vias 128. The conductive lines 126 and the vias 128 may include any suitable conductive material, such as metals (e.g., Ti, Ta, W, Al, Ni, Cu, Co, etc.), metal nitrides, metal oxides, metal carbides, and / or other suitable materials arranged in a number of layers. The conductive lines 126 and the vias 128 may be formed separately or simultaneously in a single- or dual-damascene process.

[0023] Due to the structural differences between the ILD 118 and the conductive features (e.g., the S / D contacts 122, the midplane contacts 124, the conductive lines 126, the vias 128, etc.), each layer of the interconnect structure 116 may have at least a minimum density of the contacts 122 / 124, the conductive lines 126, and the vias 128 throughout the device 100 to avoid surface irregularities when the layers are planarized. A method for incorporating fill features into a design suitable for fabricating a device, such as the device 100 of Fig. 1, is used below with reference to the Fig. 2 to 7.

[0024] Fig. 2 is a flowchart of a method 200 for supplementing a layout 300 with conductive feature shapes according to various aspects of the present invention. Additional steps may be provided before, during, and after the method 200, and some of the described steps may be replaced or omitted in further embodiments of the method 200. Fig. 3 through 6 are top view illustrations of a portion of layout 300 according to various aspects of the present invention. For clarity, only a limited number of layers are shown in layout 300, although in implementation, layout 300 may have any number of suitable structural elements in any number of layers.

[0025] In Block 202 of Fig. 2 and in Fig. 3, the layout 300 is prepared. In various examples, the layout 300 takes the form of a data file stored in a non-transitory machine-readable medium and represented in a design standard, such as GDSII, OASIS, and / or MEBES®, a registered trademark of Applied Materials. The layout 300 may be a digital representation of an integrated circuit, and structural elements of the layout 300 may correspond to physical structural elements of the device 100 of Fig. 1. For example, line shapes 304 and 306 in layout 300 may correspond to conductive lines 126 of Fig. 1, and via shapes 308 in the layout 300 may correspond to the vias 128 of Fig. 1 correspond.

[0026] Preparation of the layout 300 may include: defining the structural elements and layers supported by the layout; defining rules regarding sizes, spacing, and other aspects of the structural elements; defining a boundary of the integrated circuit; and / or other preparation steps.

[0027] Due to material differences, bumps or depressions may be formed in regions of an ILD that are not reinforced by a certain amount of conductive features (e.g., conductive lines, contacts, vias, etc.) during a CMP process, resulting in the regions having an irregular surface. To reinforce the dielectric, fill cells 302 are inserted into the integrated circuit layout 300, as shown in block 204 of Fig. 2 and in Fig. 3 is shown.

[0028] In some examples, the fill cells 302 include a first set of conductive shapes 304 in a first layer extending in a first direction 305 and a second set of conductive shapes 306 in a second layer extending in a second direction 307 perpendicular to the first direction. The fill cells 302 may also include via shapes 308 extending between the conductive shapes 304 in the first layer and the conductive shapes 306 in the second layer, where the conductive shapes 304 and 306 may have enlarged portions or pads 310 adjacent to the via shapes 308 to facilitate proper via fabrication and connectivity.

[0029] In some examples, fill cells 302 reinforce one or more layers of ILD 118 and include enough conductive feature shapes on the respective layers to achieve a minimum line density, a minimum via density, and / or a minimum contact density throughout layout 300. However, for clarity, only a limited number of shapes are shown on a limited number of layers. Each layer may have a unique set of minimum densities based on the dielectric materials, the conductive feature materials, the feature geometries, the layer geometries, and / or other factors, and therefore, fill cells 302 may have different numbers and arrangements of shapes on each layer based on these factors.In some examples, fill cells 302 are configured to have conductive lines in at least about 50% of the available routing area (excluding the area reserved to maintain minimum line spacing) and to have vias / contacts in at least about 6.25% of the available via / contact area (excluding the area reserved to maintain minimum spacing) measured in an 80 nm by 80 nm control window. In further examples, fill cells 302 are configured to exceed the minimum line density, the minimum via density, and / or the minimum contact density for each layer by one guard band, such that the layout 300 does not degrade below a minimum when some fill cell shapes are removed.

[0030] The shapes of fill cells 302, including line shapes 304 and 306, via shapes 308, and / or contact shapes, may be left floating or connected to a line voltage or ground. However, they differ from functional shapes in the same layers because they are not involved in the operation of the integrated circuit fabricated using layout 300. Therefore, the shapes of fill cells 302 may have different sizes, spacings, and / or aspects than the functional shapes, as explained in more detail later.

[0031] In Block 206 of Fig. 2 and in Fig. 4, a design 402 containing functional shapes is obtained and inserted into the layout 300. The design 402 may have any number of shapes on any number of interconnect structure layers, but for clarity, only a limited number of shapes on a limited number of layers are shown. In some examples, the design 402 includes a first set of functional line shapes 404 in the first layer running in the first direction 305 and a second set of functional line shapes 406 in the second layer running in the second direction 307. The design 402 may also include functional via shapes 408 running between the functional line shapes 404 in the first layer and the functional line shapes 406 in the second layer.The functional line shapes 404 and 406 may have enlarged portions or pads adjacent to the functional via shapes 408 to support proper via fabrication and connectivity. The functional shapes of the design 402 correspond to and define physical structural elements of the device 100 of FIG. Fig. 1 involved in the operation of the integrated circuit fabricated using layout 300. For example, functional line shapes 404 and 406 in layout 300 may correspond to conductive lines 126 of Fig. 1, and the functional via shapes 408 in the layout 300 may correspond to the vias 128 of Fig. 1 correspond.

[0032] In Block 208 of Fig. 2 and in Fig. 5, shapes of the fill cells 302 (e.g., the line shapes 304 and 306 and the via shapes 308) that conflict with the shapes of the design 402 are removed. This removal may include removing individual shapes from a fill cell 302 while retaining other fill cells and / or removing the fill cells 302 in their entirety. Fill cells that overlap with functional shapes may be removed, as well as those that are smaller than a minimum fill distance from the functional shapes. The minimum fill distance may be the same as or different from the minimum shape distance for the functional shapes of the design 402. Therefore, in some examples where the minimum line distance for functional lines is about 30 nm, the minimum fill distance is a multiple thereof (e.g., 30 nm, 60 nm, 90 nm, etc.).The minimum fill distance may vary based on direction, and in some examples, a layer has a first minimum fill distance in a trace direction (i.e., the direction in which the functional trace shapes 404 extend in that layer) and a second minimum fill distance between traces (i.e., perpendicular to the trace direction). Each layer of the interconnect structure may have its own set of minimum fill distances.

[0033] The line forms 304 and 306 may be completely removed or shortened to meet the minimum fill clearances. In some examples where a line form is shortened, block 208 includes removing those via forms 308 that no longer extend between the shortened line forms or that are not far enough from one end of a shortened line form.

[0034] As stated above, in some examples, the minimum fill distances for block 208 are set to be greater than the minimum mold spacing for the functional shapes of the design 402 (e.g., two, three, or four times the minimum mold spacing for functional shapes). This allows additional fill elements to be inserted between the structural elements of the fill cells 302 and the functional structural elements of the design 402 in a subsequent process. In block 210 and in Fig. 6, fill line shapes 602 are added to the first layer, and fill line shapes 604 are added to the second layer. In block 212 and in Fig. 6, fill line shapes 606 are added when fill line shapes 602 and 604 overlap and when the distance from the line ends of fill line shapes 602 and 604 is large enough. Like the aforementioned shapes, these shapes also correspond to and define physical structural elements of the integrated circuit. In this context, fill line shapes 602 and 604 may correspond to the conductive lines 126 of Fig. 1, and the fill via shapes 606 may correspond to the vias 128 of Fig. 1 correspond.

[0035] By removing shapes from fill cells 302 and then adding more fill shapes, some examples of method 600 provide a higher fill shape density than using fill cells 302 alone. For example, in some examples, line shapes 304 and 306 in fill cells 302 are arranged at a pitch 608 that is different from (and not an integer multiple of) a pitch 610 of functional line shapes 404 and 406, and the traces of fill cell line shapes 304 and 306 are not aligned with the traces of functional line shapes 404 and 406. However, in these particular examples, later-added line shapes 602 and 604 have the same pitch 612 and trace alignment as functional line shapes 404 and 406.As a result, the line shapes 602 and 604 can be produced closer to the functional line shapes 404 and 406 than those of the fill cells 302.

[0036] After the processes in blocks 202 to 212, the layers of the layout 300 each have sufficient shapes to maintain a minimum line density (e.g., at least 50% of the available routing area), a minimum via density (e.g., at least 6.25% of the available via area), and / or a minimum contact density (e.g., at least 6.25% of the available contact area), thereby promoting the integrity of the interconnect layers in which the shapes are to be manufactured. In block 214 of Fig. 2, the device manufacturing layout 300 is provided, which is used to fabricate the integrated circuit defined by the layout 300. Manufacturing may include a number of process steps, such as lithography, etching, deposition, epitaxy, annealing, CMP, cleaning, and / or other processes for fabricating a physical integrated circuit device.

[0037] Although some of the above examples describe inserting fill cells 302 into the layout 300 before adding the design 402, fill cells may be added to a layout in addition to or alternatively before adding the design. Some such examples are described below with reference to Fig. 7 to 11.

[0038] Fig. 7 is a flowchart of a method 700 for supplementing a layout 800 with fill elements according to various aspects of the present invention. Further steps may be provided before, during, and after the method 700, and some of the described steps may be replaced or omitted in further embodiments of the method 700. The method 700 may be performed as part of the method 200 and concurrently therewith, or as a separate method. Fig. 8 to 11 are top view illustrations of a portion of layout 800 supplemented with filler elements, according to various aspects of the present invention. For clarity, only a limited number of layers are shown in layout 800, although in implementation, layout 800 may have any number of suitable structural elements in any number of layers. While layout 300 of Fig. 3 to 6 shows two metal layers and a via layer in between, the layout 800 of the Fig. 8 to 11 structural elements at the device level, a metal layer, and contacts between them. However, in some examples, layout 300 and layout 800 represent different layers of the same layout.

[0039] In Block 702 of Fig. 7 and in Fig. 8, the layout 800 is prepared. This may be done substantially in the manner described in block 202, and the layout 800 may be substantially similar to the layout 300 described above. In some examples, the layout 800 takes the form of a data file stored in a non-transitory machine-readable medium. The layout 800 may be a digital representation of an integrated circuit, and structural elements of the layout 800 may correspond to physical structural elements of the device 100 of Fig. 1 and define them.

[0040] In Block 704 of Fig. 7 and in Fig. 8, a design 802 containing functional shapes is obtained and inserted into the layout 800. The design 802 may be substantially similar to the above design 402, although different layers are illustrated. The design 802 may have any number of shapes on any number of interconnect structure layers, but for clarity, only a limited number of shapes are illustrated on a limited number of layers. The shapes correspond to and define physical structure elements. In various examples, the design 802 includes: source / drain shapes 804 defining the source / drain regions 106 of the integrated circuit; S / D contact shapes 806 defining the S / D contacts 122; gate shapes 808 defining the gate stacks 108; midplane contact shapes 810 defining the midplane contacts 124; functional conductive shapes 812 defining the conductive lines 126; and / or other shapes.The functional line dies 812 may have enlarged portions or pads adjacent to the mid-plane contact dies 810 to facilitate proper via fabrication and connectivity. These dies may be divided into front end of line (FEOL) dies (e.g., the source / drain dies 804, the gate dies 808, the S / D contact dies 806, the mid-plane contact dies 810, etc.) and back end of line (BEOL) dies (e.g., the line dies 812).

[0041] In block 706 of Fig. 7 and in Fig. 9, fill cells 902 are inserted into the integrated circuit layout 800. The fill cells 902 may be substantially similar to the above fill cells 302 or may be different from them. The fill cells 902 may have shapes on a number of interconnect structure layers to provide a region of the layout 800 with enough features to maintain a minimum line density, a minimum via density, and / or a minimum contact density throughout the design. Each layer may have a unique set of minimum densities based on the dielectric materials, the conductive feature materials, the feature geometries, the layer geometries, and / or other factors, and therefore, the fill cells 902 may have different numbers and arrangements of shapes on each layer based on these factors.In some examples, the fill cells 902 are configured to exceed the minimum line density, the minimum via density, and / or the minimum contact density for each layer by one guard band, such that the layout 800 does not decrease below a minimum when some fill cell shapes are removed.

[0042] In various examples, fill cells 902 include: fill source / drain shapes 904 defining the source / drain regions 106 of the integrated circuit; fill S / D contact shapes 906 defining the S / D contacts 122; fill gate shapes 908 defining the gate stacks 108; fill midplane contact shapes 910 defining the midplane contacts 124; fill line shapes 912 defining the conductive lines 126; and / or other shapes. The shapes of fill cells 902 may be left floating or connected to a voltage source or to ground. They are different from functional shapes in the same layers because they are not involved in the operation of the integrated circuit fabricated using layout 800. Therefore, the shapes of the fill cells 902 may have different sizes, spacings, and / or different aspects than the functional shapes.

[0043] The fill cells 902 may be placed according to a first set of design criteria, and in some examples, the placement is determined by FEOL shape rules. In other words, the fill cells 902 are inserted into block 706 at the locations where the FEOL shapes of the fill cells 902 do not overlap the FEOL shapes of the design 802 and are at least a minimum fill distance away from the FEOL shapes of the design 802. The minimum fill distance may be equal to or different from the minimum shape distance for the functional shapes of the design 802. Therefore, in some examples, the minimum fill distance is a multiple of the minimum shape distance of the functional shapes. The minimum fill distance may change based on direction, and in some examples, a shape type has a first minimum fill distance in a first direction and a second minimum fill distance in a second direction perpendicular to the first direction.Each mold type can have its own set of minimum fill distances.

[0044] Although the placement of the fill cells 902 may satisfy the first set of design criteria, the fill cells 902 may not satisfy other criteria. In block 708 of Fig. 7 and in Fig. 10, shapes are removed from the fill cells 902 according to a second set of design criteria, such as BEOL shape rules. In some examples, BEOL shapes in the fill cells 902 that conflict with the BEOL shapes of the design 802 are removed. This removal may include removing individual shapes from a fill cell 902 while retaining other fill cells and / or removing the fill cells 902 in their entirety. Fill cells that overlap with functional shapes may be removed, as well as those that are smaller than a minimum fill distance from the functional shapes.

[0045] In block 710 of Fig. 7 and in Fig. 11, further fill shapes, such as fill line shapes 1102, are added to the layout 800. This can be done essentially in the manner described in block 210 of Fig. 6. The additional fill line shapes 1102 may provide a higher fill line density than the fill cells 902 alone. In some examples, for example, the line shapes 912 in the fill cells 902 are arranged at a pitch 1104 that is different from (and not an integer multiple of) a pitch 1106 of the functional line shapes 812, and the conductive traces of the fill cell line shapes 912 are not aligned with the conductive traces of the functional line shapes 812. However, in these particular examples, the later-added line shapes 1102 have the same pitch 1108 and the same conductive trace alignment as the functional line shapes 812. This allows the line shapes 1102 to be created closer to the functional line shapes 812 than those of the fill cells 902.

[0046] After the processes in blocks 702 to 710, the layers of the layout 800 each have sufficient shapes to maintain a minimum line density (e.g., at least 50% of the available routing area), a minimum via density (e.g., at least 6.25% of the available via area), and / or a minimum contact density (e.g., at least 6.25% of the available contact area), thereby promoting the integrity of the interconnect layers in which the shapes are to be manufactured. In block 712 of Fig. 7, the device fabrication layout 800 is provided, which is used to fabricate the specified integrated circuit. Fabrication may include a number of process steps, such as lithography, etching, deposition, epitaxy, annealing, CMP, cleaning, and / or other processes for fabricating a physical integrated circuit device.

[0047] In various embodiments, the method is performed using combinations of dedicated fixed-function computing elements and programmable computing elements that execute software instructions. It should therefore be appreciated that each of the steps of method 200 and / or method 700 may be implemented with a computing system using corresponding instructions stored on or in a non-transitory machine-readable medium accessible by a processing system. Examples of such a system and a non-transitory machine-readable medium are described with reference to Fig. 12. In this context, Fig. 12 is a block diagram of a computing system 1200 according to various aspects of the present invention.

[0048] Computing system 1200 includes a processing resource 1202, which may include any number and type of processing elements, such as central processing units (CPUs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), microcontrollers, and / or other suitable processing elements. Processing resource 1202 is communicatively coupled to a physical non-transitory machine-readable medium 1204 to execute instructions stored on medium 1204. For purposes of this description, physical non-transitory machine-readable medium 1204 may be a device capable of storing the program for use by, or in connection with, the instruction execution system, apparatus, or device.The medium may comprise non-volatile memory, such as magnetic memory, solid-state memory, optical memory, cache memory, and / or battery-backed random access memory (RAM).

[0049] In various examples, the physical non-transitory machine-readable medium 1204 stores instructions that cause the processing resource 1202 to perform the processes of methods 200 and / or 700. In some examples, the medium 1204 stores instructions that cause the processing resource 1202 to prepare a layout for fabricating an integrated circuit, as illustrated in block 202 of Fig. 2, and insert fill cells containing conductive line shapes and via shapes into the layout substantially as described in block 204 of Fig. 2. In some examples, the medium 1204 stores instructions that cause the processing resource 1202 to insert a design containing functional shapes into the layout substantially as described in block 206 of Fig. 2. In some examples, the medium 1204 stores instructions that cause the processing resource 1202 to remove from the fill cells those conductive line shapes and via shapes that conflict with the functional shapes of the design, substantially as described in block 208 of Fig. 2. In some examples, the medium 1204 stores instructions that cause the processing resource 1202 to insert additional fill line shapes into the layout substantially as described in block 210 of Fig. 2, and insert further fill via shapes into the layout substantially as described in block 212 of Fig. 2. In some examples, the medium 1204 stores instructions that cause the processing resource 1202 to provide the layout for fabricating the integrated circuit substantially as described in block 214 of Fig. 2 is described.

[0050] In further examples, the medium 1204 stores instructions that cause the processing resource 1202 to prepare a layout for fabricating an integrated circuit substantially as described in block 702 of Fig. 7. In some examples, the medium 1204 stores instructions that cause the processing resource 1202 to insert a design containing functional shapes into the layout substantially as described in block 706 of Fig. 7. In some examples, medium 1204 stores instructions that cause processing resource 1202 to insert fill cells containing fill shapes into the layout according to a first set of design criteria substantially as described in block 706 of Fig. 7. In some examples, the medium 1204 stores instructions that cause the processing resource 1202 to remove fill shapes from the fill cells according to a second set of design criteria substantially as described in block 708 of Fig. 7. In some examples, the medium 1204 stores instructions that cause the processing resource 1202 to insert additional fill shapes into the layout substantially as described in block 710 of Fig. 7. In some examples, the medium 1204 stores instructions that cause the processing resource 1202 to provide the layout for fabricating the integrated circuit substantially as described in block 714 of Fig. 7 is described.

[0051] Thus, the present invention provides examples of a system and method for adding conductive features to an integrated circuit to enhance an interconnect structure. In some examples, a method includes preparing a layout for fabrication of an integrated circuit. A plurality of fill cells comprising a plurality of fill line shapes corresponding to conductive lines of the integrated circuit are inserted into the layout. A design having a plurality of functional shapes is then inserted into the layout, and a conflicting subset of the plurality of fill line shapes of the plurality of fill cells that conflicts with the plurality of functional shapes is removed. The layout comprising the plurality of fill cells and the design is provided for fabrication of the integrated circuit.In some examples, the plurality of fill line shapes comprises a first set of line shapes corresponding to conductive lines in a first layer of an interconnect structure, and a second set of line shapes corresponding to conductive lines in a second layer of the interconnect structure adjacent to the first layer. In some examples, the fill cells further comprise a plurality of fill via shapes extending between shapes of the first set of line shapes and shapes of the second set of line shapes. The plurality of fill via shapes correspond to vias of the integrated circuit.In some examples, the plurality of fill line shapes and the plurality of fill via shapes of the plurality of fill cells are configured such that the layout comprising the plurality of fill cells and the design adheres to a metric selected from the group consisting of minimum conductive line density and minimum via density. In some examples, the plurality of fill line shapes of the plurality of fill cells is a first plurality of fill line shapes, and a second plurality of fill line shapes corresponding to conductive lines of the integrated circuit are inserted into the layout after the conflicting subset is removed. In some examples, the first plurality of fill line shapes has a center-to-center pitch that is different from that of the plurality of functional shapes, and the second plurality of fill line shapes and the plurality of functional shapes have the same center-to-center pitch.In some examples, the first plurality of fill line shapes have a trace orientation different from that of the plurality of functional shapes, and the second plurality of fill line shapes and the plurality of functional shapes have the same trace orientation. In some examples, removing the conflicting subset comprises removing a first fill cell of the plurality of fill cells in its entirety and removing a shape from a second fill cell of the plurality of fill cells, leaving a remainder of the second fill cell.In some examples, removing the conflicting subset comprises removing a first conductive shape of the plurality of fill conductive shapes that overlaps with a first functional shape of the plurality of functional shapes, and removing a second conductive shape of the plurality of fill conductive shapes that is less than the minimum fill distance from a second functional shape of the plurality of functional shapes. In some examples, the minimum fill distance comprises a minimum distance within a conductive trace and a minimum distance between conductive traces.

[0052] In further examples, a method comprises obtaining an integrated circuit layout and inserting fill cells into the integrated circuit layout. The fill cells include fill line shapes defining conductive lines of an integrated circuit and fill via shapes defining vias of the integrated circuit. After inserting the fill cells, a functional design is inserted into the integrated circuit layout. A subset of the fill line shapes that conflict with the functional design is removed, and a subset of the fill via shapes that conflict with the functional design is removed. The integrated circuit layout is then provided for use in fabricating the integrated circuit.In some examples, the fill line shapes include a first set of line shapes defining conductive lines in a first layer of an interconnect structure and a second set of line shapes defining conductive lines in a second layer of the interconnect structure adjacent to the first layer. In some examples, the fill line shapes and the fill via shapes are configured such that the integrated circuit layout adheres to a metric selected from the group consisting of minimum conductive line density and minimum via density. In some examples, the fill line shapes are a first set of fill line shapes, and a second set of fill line shapes is inserted into the integrated circuit layout after the subset of the first set of fill line shapes that conflicts with the functional design is removed.In some examples, the first set of fill line shapes has a different pitch than the functional design. In some examples, the second set of fill line shapes and the functional design have the same pitch.

[0053] In further examples, a non-transitory machine-readable medium stores instructions that, when executed by a processing resource, cause the processing resource to perform the steps of: preparing a layout for fabrication of an integrated circuit; inserting a design comprising a first set of front end of line (FEOL) shapes of the integrated circuit and a first set of back end of line (BEOL) shapes of the integrated circuit; inserting filler cells into the layout, the filler cells comprising a second set of FEOL shapes of the integrated circuit and a second set of BEOL shapes of the integrated circuit; removing a subset of the second set of BEOL shapes that conflicts with the design; and providing the layout for fabrication of the integrated circuit.In some examples, the fill cells are configured such that the layout from which the subset of the second set of BEOL shapes has been removed meets a metric from the group consisting of minimum contact density, minimum conductive line density, and minimum via density. In some examples, the fill cells are inserted such that the second set of FEOL shapes does not conflict with the design. In some examples, the fill cells include contact shapes that extend to an element from the group consisting of source / drain shape and gate stack shape.

[0054] In further examples, a method comprises obtaining an integrated circuit layout and inserting, into the integrated circuit layout, a design comprising a first set of integrated circuit front end of line (FEOL) shapes and a first set of integrated circuit back end of line (BEOL) shapes. A set of filler cells is inserted into the integrated circuit layout, which includes a second set of integrated circuit FEOL shapes and a second set of integrated circuit BEOL shapes. The second set of BEOL shapes includes contact shapes defining contacts of the integrated circuit. A subset of the second set of BEOL shapes that conflict with the design is removed, and the layout comprising the design and the set of cells is provided for fabrication of the integrated circuit.In some examples, the contact shapes define contacts for connecting to source / drain regions of the integrated circuit and contacts for connecting to gate stacks of the integrated circuit. In some examples, the second set of BEOL shapes includes conductive line shapes connected to the contact shapes. In some examples, removing the subset of the second set of BEOL shapes includes removing a subset of the conductive line shapes that are smaller than a minimum fill distance from a shape of the design and removing a subset of the contact shapes due to the removed subset of the conductive line shapes. In some examples, the second set of FEOL shapes and the second set of BEOL shapes are configured such that the layout comprising the design and the set of cells adheres to a metric selected from the group consisting of minimum contact density, minimum conductive line density, and minimum via density.In some examples, the second set of BEOL shapes has a center-to-center spacing that is different from that of the first set of BEOL shapes. In some examples, the set of cells is inserted such that the second set of FEOL shapes does not conflict with the first set of FEOL shapes.

[0055] In further examples, a non-transitory machine-readable medium stores instructions that, when executed by a processing resource, cause the processing resource to perform the steps of: obtaining a layout for fabricating an integrated circuit; inserting a design comprising front end of line (FEOL) shapes of the integrated circuit and back end of line (BEOL) shapes of the integrated circuit; and inserting filler cells into the layout. The filler cells include: source / drain shapes; source / drain contact shapes extending from the source / drain shapes; a first set of contacts extending from the source / drain contact shapes; gate stack shapes; a second set of contacts extending from the gate stack shapes; and conductive lines connected to the first set of contacts and the second set of contacts.The instructions further cause the processing resource to remove a subset of the conductive lines that conflict with the design and to prepare the layout containing the design and fill cells for fabrication of the integrated circuit.

[0056] In still further examples, a non-transitory machine-readable medium stores instructions that, when executed by a processing resource, cause the processing resource to perform the following steps: preparing a layout for fabricating an integrated circuit; and inserting fill cells into the layout. The fill cells include a first plurality of fill line shapes defining conductive lines in a first layer of the integrated circuit.The instructions further cause the processing resource to perform the following steps: after inserting the fill cells, inserting the functional design into the layout; removing a subset of the first plurality of fill line shapes that conflicts with the functional design; inserting a second plurality of fill line shapes into the layout that define conductive lines in the first layer of the integrated circuit; and providing the layout that includes the fill cells, the design, and the second plurality of fill line shapes for fabrication of the integrated circuit.In some examples, the fill cells may further comprise: a third plurality of fill line shapes defining conductive lines in a second layer of the integrated circuit adjacent to the first layer; and a plurality of fill via shapes defining vias of the integrated circuit and extending between shapes of the first plurality of fill line shapes and shapes of the third plurality of fill line shapes.

[0057] Features of various embodiments have been described above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can readily use the present invention as a basis for designing or modifying other methods and structures for achieving the same objectives and / or obtaining the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent designations do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention.

Claims

[1] Method (200) comprising the following steps: Preparing (202) a layout (300, 800) for the manufacture of an integrated circuit (100); Inserting (204) a plurality of fill cells (302, 902) into the layout (300, 800), the plurality of fill cells (302, 902) comprising a plurality of fill line shapes (304, 306, 602, 604, 912, 1102) corresponding to conductive lines (126) of the integrated circuit (100); subsequently inserting (206) a design (402, 802) comprising a plurality of functional shapes (404, 406, 408, 804, 806, 808, 810, 812) into the layout (300, 800); Removing (208) a conflicting subset (304, 306, 912) of the plurality of fill line shapes (304, 306, 602, 604, 912, 1102) of the plurality of fill cells (302, 902) that conflicts with the plurality of functional shapes (404, 406, 408, 804, 806, 808, 810, 812); and Providing (214) the layout (300, 800) comprising the plurality of fill cells (302, 902) and the design (402, 802) for the manufacture of the integrated circuit (100); wherein the plurality of fill line shapes (304, 306, 602, 604, 912, 1102) of the plurality of fill cells (302, 902) is a first plurality (304, 306, 912) of fill line shapes (304, 306, 602, 604, 912, 1102); wherein the method, after removing (208) the conflicting subset (304, 306, 912), further comprises inserting (210) into the layout (300, 800) a second plurality (604, 606, 1102) of fill line shapes (304, 306, 602, 604, 912, 1102) corresponding to conductive lines (126) of the integrated circuit (100); wherein the first plurality (304, 306, 912) of fill line shapes (304, 306, 602, 604, 912, 1102) has a center-to-center spacing (608, 1104) different from that (610, 1106) of the plurality of functional shapes (404, 406, 408, 804, 806, 808, 810, 812); and wherein the second plurality (604, 606, 1102) of fill line shapes (304, 306, 602, 604, 912, 1102) and the plurality of functional shapes (404, 406, 408, 804, 806, 808, 810, 812) have the same center-to-center distance (610, 612, 1106, 1108). [2] The method (200) of claim 1, wherein the plurality of fill line shapes (304, 306, 602, 604, 912, 1102) comprises: a first set (304, 602) of line shapes corresponding to conductive lines (126) in a first layer of an interconnect structure (116); and a second set (306, 604) of conductive shapes corresponding to conductive lines (126) in a second layer of the interconnect structure (116) adjacent to the first layer. [3] Method (200) according to claim 2, wherein the fill cells (302, 902) further comprise a plurality of fill via shapes (308, 606) extending between shapes of the first set (304, 602) of conductive shapes and shapes of the second set (306, 604) of conductive shapes, and the plurality of fill via shapes (308, 606) corresponds to vias (128) of the integrated circuit (100). [4] The method (200) of claim 2 or 3, wherein the plurality of fill line shapes (304, 306, 602, 604, 912, 1102) and the plurality of fill via shapes (308, 606) of the plurality of fill cells (302, 902) are configured such that the layout (300, 800) comprising the plurality of fill cells (302, 902) and the design (402, 802) maintains a metric from the group of minimum conductive line density (126) and minimum via density. [5] Method (200) according to one of the preceding claims, wherein the first plurality (304, 306, 912) of fill line shapes (304, 306, 602, 604, 912, 1102) has a conductor track orientation that is different from that of the plurality of functional shapes (404, 406, 408, 804, 806, 808, 810, 812), and the second plurality (604, 606, 1102) of fill line shapes (304, 306, 602, 604, 912, 1102) and the plurality of functional shapes (404, 406, 408, 804, 806, 808, 810, 812) have the same trace orientation. [6] The method (200) of any preceding claim, wherein removing (208) the conflicting subset (304, 306, 912) comprises: Removing a first fill cell (302, 902) of the plurality of fill cells (302, 902) in their entirety; and Removing a mold (804, 808, 904, 906, 908, 910) from a second fill cell of the plurality of fill cells (302, 902), leaving a remainder of the second fill cell. [7] The method (200) of any preceding claim, wherein removing (208) the conflicting subset (304, 306, 912) comprises: Removing a first line shape of the plurality of fill line shapes (304, 306, 602, 604, 912, 1102) that overlaps with a first functional shape (404, 406, 408, 804, 806, 808, 810, 812) of the plurality of functional shapes (404, 406, 408, 804, 806, 808, 810, 812); and Removing a second conduit shape of the plurality of fill conduit shapes (304, 306, 602, 604, 912, 1102) that is smaller than a minimum fill distance from a second functional shape (404, 406, 408, 804, 806, 808, 810, 812) of the plurality of functional shapes (404, 406, 408, 804, 806, 808, 810, 812). [8] The method (200) of claim 7, wherein the minimum fill distance comprises a minimum distance within a conductive trace and a minimum distance between conductive traces. [9] Method (200) comprising the following steps: Obtaining an integrated circuit layout (300, 800); Inserting (204) fill cells (302, 902) into the integrated circuit layout (300, 800), the fill cells comprising fill line shapes (304, 306, 602, 604, 912, 1102) defining conductive lines (126) of an integrated circuit (100) and fill via shapes (308, 606) defining vias (128) of the integrated circuit (100); after inserting (204) the filler cells (302, 902), inserting (206) a functional design (402, 802) into the integrated circuit layout (300, 800); Removing (208) a subset (304, 306, 912) of the fill line shapes (304, 306, 602, 604, 912, 1102) that conflicts with the functional design (402, 802); Removing (208) a subset (308, 910) of the fill via shapes (308, 606, 910) that conflicts with the functional design (402, 802); and subsequently providing (214) the integrated circuit layout (300, 800) for use in the manufacture of the integrated circuit (100); wherein the fill line shapes (304, 306, 602, 604, 912, 1102) comprise a first set (304, 306, 912) of fill line shapes (304, 306, 602, 604, 912, 1102); wherein the method, after removing (208) the subset (304, 306, 912) of the first set (304, 306, 912) of fill line shapes (304, 306, 602, 604, 912, 1102) that conflicts with the functional design (402, 802), further comprises inserting (210) a second set (602, 604, 1102) of fill line shapes (304, 306, 602, 604, 912, 1102) into the integrated circuit layout (300, 800); wherein the first set (304, 306, 912) of fill line shapes (304, 306, 602, 604, 912, 1102) has a grid spacing (608, 1104) different from that (610, 1106) of the functional design (402, 802); and wherein the second set (602, 604, 1102) of fill line shapes (304, 306, 602, 604, 912, 1102) and the functional design (402, 802) have the same grid spacing (610, 612, 1106, 1108). [10] The method (200) of claim 9, wherein the fill line shapes (304, 306, 602, 604, 912, 1102) comprise: a first set (304, 602) of line shapes defining conductive lines (126) in a first layer of an interconnect structure (116); and a second set (306, 604) of line shapes defining conductive lines (126) in a second layer of the interconnect structure (116) adjacent to the first layer. [11] The method (200) of claim 9 or 10, wherein the fill line shapes (304, 306, 602, 604, 912, 1102) and the fill via shapes (308, 606, 910) are configured such that the integrated circuit layout (300, 800) maintains a metric from the group of minimum conductive line (126) density and minimum via density. [12] A non-transitory machine-readable medium (1204) storing instructions that, when executed by a processing resource (1202), cause the processing resource (1202) to perform the steps of a method according to any one of the preceding claims.

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