Flip-flop

Abstract

Flip-flop (100; 200; 300; 400; 500) which has the following: a first node loading circuit (120) configured to load a first node (N1) with inverted input data (DN); a second node loading circuit (140) configured to load a second node (N2) with input data (D); a first n-channel metal oxide semiconductor, NMOS, transistor (NT1) having a first terminal connected to the first node (N1), a second terminal and a gate terminal; a second NMOS transistor (NT2) having a first terminal connected to the second terminal of the first NMOS transistor (NT1), a second terminal connected to a low voltage (GND), and a gate terminal; a third NMOS transistor (NT3) having a first terminal connected to the first node (N1), a second terminal and a gate terminal connected to the second node (N2); a fourth NMOS transistor (NT4) having a first terminal connected to the second node (N2), a second terminal, and a gate terminal; a fifth NMOS transistor (NT5) having a first terminal connected to the second terminal of the fourth NMOS transistor (NT4), a second terminal connected to the low voltage (GND), and a gate terminal; a sixth NMOS transistor (NT6) having a first terminal connected to the second node (N2), a second terminal and a gate terminal connected to the first node (N1); a seventh NMOS transistor (NT7) having a first terminal connected to the second terminal of the third NMOS transistor (NT3), a second terminal connected to a sixth node (N6), and a gate terminal configured to receive a clock signal (CK); and an eighth NMOS transistor (NT8) having a first terminal connected to the second terminal of the sixth NMOS transistor (NT6), a second terminal connected to a fifth node (N5), and a gate terminal configured to receive the clock signal (CK), wherein the flip-flop (100; 200; 300; 400; 500) is configured to latch the input data (D) on rising edges of the clock signal (CK) and to output the latched input data (D) as output data (Q), and wherein the gate terminal of the first NMOS transistor (NT1) is connected to the second node (N2), and the gate terminal of the second NMOS transistor (NT2) is configured to receive the input data (D), or the gate terminal of the first NMOS transistor (NT1) is configured to receive the input data (D), and the gate terminal of the second NMOS transistor (NT2) is connected to the second node, and / or where the gate terminal of the fourth NMOS transistor (NT4) is connected to the first node (N1), and the gate terminal of the fifth NMOS transistor (NT5) is configured to receive the inverted input data (DN), or the gate terminal of the fourth NMOS transistor (NT4) is configured to receive the inverted input data (DN), and the gate terminal of the fifth NMOS transistor (NT5) is connected to the first node.

Description

BACKGROUND 1. Technical field

[0001] Example embodiments generally relate to a logic circuit. More specifically, some example embodiments relate to a flip-flop that latches input data on rising edges of a clock signal and outputs latched input data as output data. 2. Description of the state of the art

[0002] Recently, in line with the mobile convergence trend, there has been increasing interest in low-power technology for mobile devices (e.g., smartphones, smartpads, etc.). Generally, since mobile devices use limited power such as batteries, it is necessary to manufacture (or design) mobile devices with low-power chips including low-power flip-flops, and to efficiently manage the power consumption of the mobile device. A master-slave flip-flop has been used for a long time because of its relatively small size and high reliability.However, since a conventional master-slave flip-flop has internal nodes that are repeatedly charged and discharged (e.g., alternately) in response to a clock signal, the conventional master-slave flip-flop consumes power even while input data is unchanged. Therefore, the conventional master-slave flip-flop cannot meet the low-power requirements required by recent mobile devices with relatively high operating frequencies.

[0003] JP 2004 - 214 997 A discloses the following: The flip-flop is provided with a first latch stage for fetching the input data when the clock signals are at a high level, and a second latch stage for latching the latched data of the first latch stage. The first latch stage is provided with a preset part capable of charging electric charges to a first output node and a second output node when the clock signals are at a low level and setting them to the high level. In the case where the level of the input data signals and the inversion signals is not changed, the electric charges are not charged to the first output node and the second output node even when the clock signals are at the low level.

[0004] US 7 265 599 B1 discloses the following: An edge-triggered flip-flop tolerates arbitrarily slow clock edge rates by using complex gates with weighted transistors to electrically isolate the master latch from the data inputs before the master latch and the slave latch are electrically connected together, and to electrically isolate the master latch from the slave latch before the master latch and the data inputs are electrically connected together. SUMMARY

[0005] The scope of the invention is defined by the appended claims.

[0006] Some example embodiments provide a flip-flop (or sometimes referred to as a switching device) that can consume no power while input data is not changed (e.g., the flip-flop can operate at low power) by not including an internal node that is repeatedly charged and discharged in response to a clock signal.

[0007] According to one aspect of some exemplary embodiments, a flip-flop may include a first node charging circuit configured to charge a first node with inverted input data, a second node charging circuit configured to charge a second node with input data, a first n-channel metal oxide semiconductor (NMOS) transistor having a first terminal connected to the first node, a second terminal, and a gate terminal, a second NMOS transistor having a first terminal connected to the second terminal of the first NMOS transistor, a second terminal connected to a low voltage or low power voltage, and a gate terminal, a third NMOS transistor having a first terminal connected to the first node, a second node, and a gate terminal,which is connected to the second node, a fourth NMOS transistor having a first terminal connected to the second node, a second terminal, and a gate terminal, a fifth NMOS transistor having a first terminal connected to the second terminal of the fourth NMOS transistor, a second terminal connected to the low-power voltage, and a gate terminal, a sixth NMOS transistor having a first terminal connected to the second node, a second terminal, and a gate terminal connected to the first node, a seventh NMOS transistor having a first terminal connected to the second terminal of the third NMOS transistor, a second terminal connected to a sixth node, and a gate terminal configured to receive a clock signal,and an eighth NMOS transistor having a first terminal connected to the second terminal of the sixth NMOS transistor, a second terminal connected to a fifth node, and a gate terminal configured to receive the clock signal. Here, the flip-flop may be configured to latch the input data on rising edges of the clock signal and to output the latched input data as output data.

[0008] According to another aspect of some exemplary embodiments, a flip-flop may include a first OR gate or OR gate element having a first input terminal configured to receive a clock signal, a second input terminal configured to receive input data, and an output terminal configured to output an OR operation result or OR operation result between the clock signal and the input data, a first NAND gate element having a first input terminal connected to the output terminal of the first OR gate element, a second input terminal connected to a second node, and an output terminal connected to a first node, wherein the output terminal of the first NAND gate element is configured,to output a NAND operation result between the OR operation result of the first OR gate element and a voltage signal of the second node at the first node, a second OR gate element having a first input terminal configured to receive inverted input data, a second input terminal configured to receive the clock signal, and an output terminal configured to output an OR operation result between the inverted input data and the clock signal, a second NAND gate element having a first input terminal connected to the first node, a second input terminal connected to the output terminal of the second OR gate element, and an output terminal connected to the second node, wherein the output terminal of the second NAND gate element is configured,to output a NAND operation result between a voltage signal of the first node and the OR operation result of the second OR gate element at the second node, a first inverter element connected between the second input terminal of the first OR gate element and the first input terminal of the second OR gate element, the first inverter element being configured to invert the input data and to output the inverted input data, a third AND gate element having a first input terminal connected to the first node, a second input terminal configured to receive the clock signal, and an output terminal configured to output an AND operation result between the clock signal and the voltage signal of the first node, a first NOR gate element having a first input terminal,which is connected to the output terminal of the third AND gate element, a second input terminal connected to a sixth node, and an output terminal connected to a fifth node, wherein the output terminal of the first NOR gate element is configured to output a NOR operation result between the AND operation result of the third AND gate element and a voltage signal of the sixth node at the fifth node, a fourth AND gate element having a first input terminal connected to the second node, a second input terminal configured to receive the clock signal, and an output terminal configured to output an AND operation result between the voltage signal of the second node and the clock signal, and a second NOR gate element having a first input terminal,which is connected to the fifth node, a second input terminal connected to the output terminal of the fourth AND gate element, and an output terminal connected to the sixth node, wherein the output terminal of the second NOR gate element is configured to output a NOR operation result between a voltage signal of the fifth node and the AND operation result of the fourth AND gate element at the sixth node.

[0009] Thus, according to some example embodiments, a flip-flop may include an internal node loaded by inverted input data (e.g., data generated by inverting input data) and an internal node loaded by the input data, wherein the internal nodes operate complementarily (e.g., node values ​​of the internal nodes are determined complementarily) because the internal nodes are cross-connected, so that the flip-flop can prevent unnecessary power consumption while the input data is not changed. That is, the flip-flop can operate with low power by preventing the internal nodes from being repeatedly charged and discharged in response to a clock signal while the input data is not changed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Illustrative non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Fig. 1A is a circuit diagram illustrating a flip-flop according to some example embodiments. Fig. 1B is a detailed circuit diagram showing the flip-flop of the Fig. 1A illustrates. Fig. 2 is a block diagram illustrating an example in which the flip-flop of the Fig. 1B is implemented by logic elements. Fig. 3 is a timing diagram illustrating an example in which the flip-flop of the Fig. 1B works. Fig. 4 is a circuit diagram illustrating a flip-flop according to some example embodiments. The Fig. 5A and Fig. 5B are diagrams for describing an operation of the flip-flop of the Fig. 4. Fig. 6 is a block diagram illustrating an example in which the flip-flop of the Fig. 4 is implemented by logic elements. The Fig. 7A and Fig. 7B are diagrams for describing an operation of the flip-flop of the Fig. 6. Fig. 8 is a circuit diagram illustrating a flip-flop according to some example embodiments. The Fig. 9A and Fig. 9B are diagrams for describing an operation of the flip-flop of the Fig. 8. Fig. 10 is a block diagram illustrating an example in which the flip-flop of the Fig. 8 is implemented by logic elements. The Fig. 11A and Fig. 11B are diagrams for describing an operation of the flip-flop of the Fig. 6. Fig. 12 is a circuit diagram illustrating a flip-flop according to some example embodiments. The Fig. 13A and Fig. 13B are diagrams for describing an operation of the flip-flop of the Fig. 12. Fig. 14 is a block diagram illustrating an example in which the flip-flop of the Fig. 12 is implemented by logic elements. The Fig. 15A and Fig. 15B are diagrams for describing an operation of the flip-flop of the Fig. 14. Fig. 16 is a circuit diagram illustrating a flip-flop according to some example embodiments. Fig. 17 is a block diagram illustrating an example in which the flip-flop of the Fig. 12 is implemented by logic elements. Fig. 18 is a block diagram illustrating an integrated circuit having a scan chain circuit according to some example embodiments. Fig. 19 is a timing chart for describing an operation of a flip-flop used in a scan chain circuit of the integrated circuit of the Fig. 18 is included. Fig. 20 is a block diagram illustrating a test system for an integrated circuit according to some example embodiments. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] Hereinafter, some exemplary embodiments will be described with reference to the accompanying drawings.

[0012] Fig. 1A is a circuit diagram illustrating a flip-flop according to some example embodiments. Fig. 1 B is a detailed circuit diagram showing the flip-flop of the Fig. 1A illustrates. Fig. 2 is a block diagram illustrating an example in which the flip-flop of the Fig. 1B is implemented by logic elements. Fig. 3 is a timing diagram illustrating an example in which the flip-flop of the Fig. 1B works.

[0013] Referring to the Fig. 1A to 3, the flip-flop 100 may include a first node charging circuit 120, a second node charging circuit 140, and first to eighth n-channel metal oxide semiconductor (NMOS) transistors NT1 to NT8. In some example embodiments, the flip-flop 100 may further include an inverter circuit 160. Based on the above structure, the flip-flop 100 may latch input data D on rising edges of a clock signal CK and may output latched input data D as output data Q. In other words, the flip-flop 100 may be triggered on the rising edges of the clock signal CK.

[0014] The first node charging circuit 120 may charge a first node N1 with inverted input data DN, wherein the inverted input data DN is generated by inverting input data D. In an exemplary embodiment, the first node charging circuit 120 may include a first p-channel metal-oxide-semiconductor (PMOS) transistor PT1, a third PMOS transistor PT3, and a ninth PMOS transistor PT9. The first PMOS transistor PT1 may have a first terminal connected to a high-power voltage VDD, a second terminal connected to a third node N3, and a gate terminal receiving the clock signal CK. Thus, when the first PMOS transistor PT1 turns on in response to the clock signal CK, the high-power voltage VDD may be applied to the third node N3.The third PMOS transistor PT3 may have a first terminal connected to the third node N3, a second terminal connected to the first node N1, and a gate terminal receiving the input data D. Thus, when the third PMOS transistor PT3 turns on in response to the input data D, the third node N3 may be connected to the first node N1. The ninth PMOS transistor PT9 may have a first terminal connected to the third node PT3, a second terminal connected to a sixth node N6, and a gate terminal connected to a fifth node N5. Thus, when the ninth PMOS transistor PT9 turns on in response to a voltage signal from the fifth node N5, the third node N3 may be connected to the sixth node N6.In some example embodiments, the first node charging circuit 120 may further include transistors that perform an assisting operation, such as a keeper element that performs data retention.For example, the first node charging circuit 120 may further include a second PMOS transistor PT2 having a first terminal connected to the high-power voltage VDD, a second terminal connected to the third node N3, and a gate terminal connected to the second node N2, a fourth PMOS transistor PT4 having a first terminal connected to the high-power voltage VDD, a second terminal connected to the first node N1, and a gate terminal connected to the second node N2, and a ninth NMOS transistor PT9 having a first terminal connected to the sixth node N6, a second terminal connected to a low-power voltage GND, and a gate terminal connected to the fifth node N5. This structure will be described in detail with reference to FIG. Fig. 4 to 5 B are described.

[0015] The second node charging circuit 140 may charge the second node N2 with the input data D. In an exemplary embodiment, the second node charging circuit 140 may include a fifth PMOS transistor PT5, a seventh PMOS transistor PT7, and a tenth PMOS transistor PT10. The fifth PMOS transistor PT5 may have a first terminal connected to the high-power voltage VDD, a second terminal connected to a fourth node N4, and a gate terminal receiving the clock signal CK. Thus, when the fifth PMOS transistor PT5 turns on in response to the clock signal CK, the high-power voltage VDD may be applied to the fourth node N4. The seventh PMOS transistor PT7 may have a first terminal connected to the fourth node N4, a second terminal connected to the second node N2, and a gate terminal receiving the inverted input data DN.Thus, when the seventh PMOS transistor PT7 turns on in response to the inverted input data DN, the fourth node N4 may be connected to the second node N2. The tenth PMOS transistor PT10 may have a first terminal connected to the fourth node N4, a second terminal connected to the fifth node N5, and a gate terminal connected to the sixth node N6. Thus, when the tenth PMOS transistor PT10 turns on in response to a voltage signal from the sixth node N6, the fourth node N4 may be connected to the fifth node N5. In some example embodiments, the second node charging circuit 140 may further include transistors that perform an assist operation, such as a hold element that performs data retention.For example, the second node charging circuit 140 may further include a sixth PMOS transistor PT6 having a first terminal connected to the high-power voltage VDD, a second terminal connected to the fourth node N4, and a gate terminal connected to the first node N1, an eighth PMOS transistor PT8 having a first terminal connected to the high-power voltage VDD, a second terminal connected to the second node N2, and a gate terminal connected to the first node N1, and a tenth NMOS transistor NT10 having a first terminal connected to the fifth node N5, a second terminal connected to the low-power voltage GND, and a gate terminal connected to the sixth node N6. This structure will be described in detail with reference to FIG. Fig. 4 to 5B.

[0016] The first NMOS transistor NT1 and the second NMOS transistor NT2 may be connected in series between the first node N1 and the low-power voltage GND. For example, the low-power voltage GND may be a ground voltage. In an exemplary embodiment, as shown in the Fig. 1A and Fig. 1B, the first NMOS transistor NT1 has a first terminal connected to the first node N1, a second terminal connected to a first terminal of the second NMOS transistor NT2, and a gate terminal connected to the second node N2. The second NMOS transistor NT2 may have the first terminal connected to the second terminal of the first NMOS transistor NT1, a second terminal connected to the low-power voltage GND, and a gate terminal receiving the input data D. In this case, when the first NMOS transistor NT1 turns on in response to a voltage signal of the second node N2 and when the second NMOS transistor NT2 turns on in response to the input data D, the low-power voltage GND may be applied to the first node N1.In another exemplary embodiment, a first NMOS transistor NT1 may have a first terminal connected to the first node N1, a second terminal connected to a first terminal of the second NMOS transistor NT2, and a gate terminal that receives the input data D. The second NMOS transistor NT2 may have the first terminal connected to the second terminal of the first NMOS transistor NT1, a second terminal connected to the low-power voltage GND, and a gate terminal connected to the second node N2. In this case, when the first NMOS transistor NT1 turns on in response to the input data D and when the second NMOS transistor NT2 turns on in response to a voltage signal of the second node N2, the low-power voltage GND may be applied to the first node N1.The fourth NMOS transistor NT4 and the fifth NMOS transistor NT5 may be connected in series between the second node N2 and the low-power voltage GND. In an exemplary embodiment, as shown in FIGS. Fig. 1A and Fig. 1B, the fourth NMOS transistor NT4 may have a first terminal connected to the second node N2, a second terminal connected to a first terminal of the fifth NMOS transistor NT5, and a gate terminal connected to the first node N1. The fifth NMOS transistor NT5 may have the first terminal connected to the second terminal of the fourth NMOS transistor NT4, a second terminal connected to the low-power voltage GND, and a gate terminal receiving the inverted input data DN. In this case, when the fourth NMOS transistor NT4 turns on in response to a voltage signal of the first node N1 and when the fifth NMOS transistor NT5 turns on in response to the inverted input data DN, the low-power voltage GND may be applied to the second node N2.In another exemplary embodiment, the fourth NMOS transistor NT4 may have a first terminal connected to the second node N2, a second terminal connected to a first terminal of the fifth NMOS transistor NT5, and a gate terminal that receives the inverted input data DN. The fifth NMOS transistor NT5 may have a first terminal connected to the second terminal of the fourth NMOS transistor NT4, a second terminal connected to the low-power voltage GND, and a gate terminal connected to the first node N1. In this case, when the fourth NMOS transistor NT4 turns on in response to the inverted input data DN and when the fifth NMOS transistor NT5 turns on in response to a voltage signal of the first node N1, the low-power voltage GND may be applied to the second node N2.

[0017] The third NMOS transistor NT3 and the seventh NMOS transistor NT7 may be connected in series between the first node N1 and the sixth node N6. In particular, the third NMOS transistor NT3 may have a first terminal connected to the first node N1, a second terminal connected to a first terminal of the seventh NMOS transistor NT7, and a gate terminal connected to the second node N2. Thus, when the third NMOS transistor NT3 turns on in response to a voltage signal from the second node N2, the first terminal of the seventh NMOS transistor NT7 may be connected to the first node N1. The seventh NMOS transistor NT7 may have the first terminal connected to the second terminal of the third NMOS transistor NT3, a second terminal connected to the sixth node N6, and a gate terminal receiving the clock signal CK.Accordingly, when the seventh NMOS transistor NT7 turns on in response to the clock signal CK, the second terminal of the third NMOS transistor NT3 may be connected to the sixth node N6. In some example embodiments, the second terminal of the seventh NMOS transistor NT7 may alternatively be connected to the low-power voltage GND instead of the sixth node N6. Although in . Fig. 1A and Fig. 1B illustrates that the third NMOS transistor NT3 is connected to the first node N1, and the seventh NMOS transistor NT7 is connected to the sixth node N6. However, the positions of the third NMOS transistor NT3 and the seventh NMOS transistor NT7 may be interchanged with each other in some example embodiments. That is, the third NMOS transistor NT3 may alternatively be connected to the sixth node N6, and the seventh NMOS transistor NT7 may alternatively be connected to the first node N1. The sixth NMOS transistor NT6 and the eighth NMOS transistor NT8 may be connected in series between the second node N2 and the fifth node N5.Specifically, the sixth NMOS transistor NT6 may have a first terminal connected to the second node N2, a second terminal connected to a first terminal of the eighth NMOS transistor NT8, and a gate terminal connected to the first node N1. Thus, when the sixth NMOS transistor NT6 turns on in response to a voltage signal from the first node N1, the first terminal of the eighth NMOS transistor NT8 may be connected to the second node N2. The eighth NMOS transistor NT8 may have the first terminal connected to the second terminal of the sixth NMOS transistor NT6, a second terminal connected to the fifth node N5, and a gate terminal receiving the clock signal CK.Accordingly, when the eighth NMOS transistor NT8 turns on in response to the clock signal CK, the second terminal of the sixth NMOS transistor NT6 may be connected to the fifth node N5. In some example embodiments, the second terminal of the eighth NMOS transistor NT8 may alternatively be connected to the low-power voltage GND instead of the fifth node N5. Although in the . Fig. 1A and Fig. 1B illustrates that the sixth NMOS transistor NT6 is connected to the second node N2 and the eighth NMOS transistor NT8 is connected to the fifth node N5. In some example embodiments, the positions of the sixth NMOS transistor NT6 and the eighth NMOS transistor NT8 may be interchanged. That is, the eighth NMOS transistor NT8 may alternatively be connected to the second node N2, and the sixth NMOS transistor NT6 may alternatively be connected to the fifth node N5.As described above, an internal node loaded by the inverted input data DN (e.g., the first node N1) may be connected to the gate of the sixth NMOS transistor NT6 included in a right-hand structure, and an internal node loaded by the input data D (e.g., the second node N2) may be connected to the gate of the third NMOS transistor NT3 included in a left-hand structure. That is, the internal node loaded by the inverted input data DN (e.g., the first node N1) and the internal node loaded by the input data D (e.g., the second node N2) are cross-connected, so that the internal nodes (e.g., the first node N1 and the second node N2) can operate complementarily.Accordingly, node values ​​of the internal nodes (e.g., the first node N1 and the second node N2) are determined complementarily, so that the internal nodes (e.g., the first node N1 and the second node N2) cannot be repeatedly charged and discharged in response to the clock signal CK while the input data D is not changed. In addition, the internal node loaded by the inverted input data DN (e.g., the sixth node N6) and the internal node loaded by the input data D (e.g., the fifth node N5) are cross-connected, so that the internal nodes (e.g., the sixth node N6 and the fifth node N5) can operate complementarily.Accordingly, node values ​​of the internal nodes (for example, the sixth node N6 and the fifth node N5) are complementarily determined, so that the internal nodes (for example, the sixth node N6 and the fifth node N5) cannot be repeatedly charged and discharged in response to the clock signal CK while the input data D is not changed. As a result, the flip-flop 100 can prevent unnecessary power consumption while the input data D is not changed, and can thus operate at low power.

[0018] The inverter circuit 160 may be connected between the sixth node N6 and an output node OUT. Accordingly, the inverter circuit 160 may invert a voltage signal of the sixth node N6 (e.g., the inverted input data DN) to output the output data Q (e.g., the input data D latched at the rising edges of the clock signal CK) at the output node OUT. In an exemplary embodiment, the inverter circuit 160 may include an eleventh PMOS transistor PT11 and an eleventh NMOS transistor NT11. The eleventh PMOS transistor PT11 may have a first terminal connected to the high-power voltage VDD, a second terminal connected to the output node OUT, and a gate terminal connected to the sixth node N6.Thus, when the eleventh PMOS transistor PT11 turns on in response to a voltage signal from the sixth node N6, the high-power voltage VDD may be applied to the output node OUT. The eleventh NMOS transistor NT11 may have a first terminal connected to the output node OUT, a second terminal connected to the low-power voltage GND, and a gate terminal connected to the sixth node N6. Thus, when the eleventh NMOS transistor NT11 turns on in response to a voltage signal from the sixth node N6, the low-power voltage GND may be applied to the output node OUT. In this regard, an operation of the flip-flop 100 will be described based on a structure of the flip-flop 200 having transistors that perform an assist operation such as a hold element that performs data retention with reference to FIG. Fig. 4 to 5B. In other words, except that the flip-flop 100 does not have the transistors that perform the assist operation, the operation of the flip-flop 100 is substantially the same as an operation of the flip-flop 200.

[0019] In some example embodiments, the flip-flop 100 may be implemented (or expressed) by logic elements. In particular, the flip-flop 100 may include a first OR gate element OR1, a first NAND gate element NAND1, a first inverter element INV1, a second OR gate element OR2, a second NAND gate element NAND2, a third AND gate element AND3, a first NOR gate element NOR1, a fourth AND gate element AND4, and a second NOR gate element NOR2. Here, the first OR gate element OR1 and the first NAND gate element NAND1 may be implemented by an OR-AND-INVERTER gate element, and the second OR gate element OR2 and the second NAND gate element NAND2 may be implemented by an OR-AND-INVERTER gate element.Additionally, the third AND gate element AND3 and the first NOR gate element NOR1 may be implemented by an AND-OR INVERTER gate element, and the fourth AND gate element AND4 and the second NOR gate element NOR2 may be implemented by an AND-OR INVERTER gate element. In some example embodiments, the flip-flop 100 may further include a second inverter element INV2. The first OR gate element OR1 may have a first input terminal receiving the clock signal CK, a second input terminal receiving the input data D, and an output terminal outputting an OR operation result between the clock signal CK and the input data D.The first NAND gate element NAND1 may have a first input terminal connected to the output terminal of the first OR gate element OR1, a second input terminal connected to the second node N2, and an output terminal (e.g., the first node N1) that outputs a NAND operation result between the OR operation result of the first OR gate element OR1 and a voltage signal of the second node N2. The first inverter element INV1 may be connected between the second input terminal of the first OR gate element OR1 and the first input terminal of the second OR gate element OR2. The first inverter element INV1 may invert the input data D to output the inverted input data DN.The second OR gate element OR2 may have a first input terminal receiving the inverted input data DN, a second input terminal receiving the clock signal CK, and the output terminal outputting an OR operation result between the inverted input data DN and the clock signal CK. The second NAND gate element NAND2 may have a first input terminal connected to the first node N1, a second input terminal connected to the output terminal of the second OR gate element OR2, and an output terminal (e.g., the second node N2) outputting a NAND operation result between a voltage signal of the first node N1 and the OR operation result of the second OR gate element OR2.The third AND gate element AND3 may have a first input terminal connected to the first node N1, a second input terminal receiving the clock signal CK, a third input terminal receiving the inverted input data DN, and an output terminal outputting an AND operation result among the inverted input data DN, the clock signal CK, and a voltage signal of the first node N1. In some example embodiments, the third AND gate element AND3 may not receive the inverted input data DN. In this case, the third AND gate element AND3 may have a first input terminal connected to the first node N1, a second input terminal receiving the clock signal CK, and an output terminal outputting an AND operation result between the clock signal CK and a voltage signal of the first node N1.However, the AND operation result between the clock signal CK and the voltage signal of the first node N1 may be the same as the AND operation result among the inverted input data DN, the clock signal CK, and the voltage signal of the first node N1. The first NOR gate element NOR1 may have a first input terminal connected to the output terminal of the third AND gate element AND3, a second input terminal connected to the sixth node N6, and an output terminal (for example, the fifth node N5) that outputs a NOR operation result between the AND operation result of the third AND gate element AND3 and a voltage signal of the sixth node N6.The fourth AND gate element AND4 may have a first input terminal connected to the second node N2, a second input terminal receiving the clock signal CK, a third input terminal receiving the input data D, and an output terminal outputting an AND operation result among a voltage signal of the second node N2, the clock signal CK, and the input data D. In some example embodiments, the fourth AND gate element AND4 may not receive the input data D. In this case, the fourth AND gate element AND4 may have a first input terminal connected to the second node N2, a second input terminal receiving the clock signal CK, and an output terminal outputting an AND operation result between a voltage signal of the second node N2 and the clock signal CK.However, the AND operation result between the voltage signal of the second node N2 and the clock signal CK may be the same as the AND operation result between the voltage signal of the second node N2, the clock signal CK, and the input data D. The second NOR gate element NOR2 may have a first input terminal connected to the fifth node N5, a second input terminal connected to the output terminal of the fourth AND gate element AND4, and an output terminal (for example, the sixth node N6) that outputs a NOR operation result between a voltage signal of the fifth node N5 and an AND operation result of the fourth AND gate element AND4. The second inverter element INV2 may be connected between the sixth node N6 and the output node OUT. The second inverter element INV2 may invert the voltage signal of the sixth node N6 to output the output data Q.In this regard, an operation of the flip-flop 100 will be described based on a structure of the flip-flop 200 having logic elements that perform an assist operation such as a hold element that performs data retention, with reference to FIG. Fig. 6 to 7B. In other words, except that flip-flop 100 does not include the logic elements that perform the assist operation, the operation of the flip-flop is essentially the same as the operation of flip-flop 200.

[0020] As described above, the flip-flop 100 can latch the input data D on the rising edges of the clock signal CK and can output the latched input data D as the output data Q at the output node OUT. For example, as shown in Fig. 3, the flip-flop 100 can latch the input data D on a rising edge of the clock signal CK (indicated, for example, by T1A) and can output the latched input data D as the output data Q. Here, since the latched input data D has a logic "low" level, the flip-flop 100 can output the output data Q having a logic "low" level. The output data Q output from the flip-flop 100 cannot be changed until a next rising edge of the clock signal CK because the flip-flop is triggered only on rising edges of the clock signal CK. Next, the flip-flop 100 can latch the input data D on the next rising edge of the clock signal CK (indicated, for example, by T1B) and can output the latched input data D as the output data Q. Here, since the latched input data D has a logical “high” or “low” value,"High" level, the flip-flop 100 can output the output data Q having a logic "High" level. This means that the output data Q output from the flip-flop 100 can be changed from a logic "Low" level to a logic "High" level. Subsequently, the flip-flop 100 can latch the input data D at a next rising edge of the clock signal CK (indicated, for example, by TIC) and can output the latched input data D as the output data Q. Here, since the latched input data D has a logic "High" level, the flip-flop 100 can output the output data Q having a logic "High" level. This means that the output data Q output from the flip-flop 100 can be maintained to have a logic "High" level.Next, the flip-flop 100 may latch the input data D at a next rising edge of the clock signal CK (indicated, for example, by TID) and may output the latched input data D as the output data Q. Here, since the latched input data D has a logic "low" level, the flip-flop 100 may output the output data Q having a logic "low" level. That is, the output data Q output from the flip-flop 100 may change from a logic "high" level to a logic "low" level. Subsequently, the flip-flop 100 may latch the input data D at a next rising edge of the clock signal CK (indicated, for example, by TIE) and may output the latched input data D as the output data Q. Here, since the latched input data D has a logic “low” level, the flip-flop 100 can output the output data Q which has a logic “low” level.This means that the output data Q output from the flip-flop 100 can be maintained at a logic "low" level. Next, the flip-flop 100 can latch the input data D at a next rising edge of the clock signal CK (indicated, for example, by TIF) and can output the latched input data D as the output data Q. Here, since the latched input data D has a logic "high" level, the flip-flop 100 can output the output data Q having a logic "high" level. This means that the output data Q output from the flip-flop can be changed from a logic "low" level to a logic "high" level. Subsequently, the flip-flop 100 may latch the input data D at a next rising edge of the clock signal CK (indicated, for example, by TIG) and may output the latched input data D as the output data Q.Here, since the latched input data D has a logic "high" level, the flip-flop 100 can output the output data Q having a logic "high" level. That is, the output data Q output from the flip-flop 100 can be maintained at a logic "high" level.

[0021] In one exemplary embodiment, the flip-flop 100 may have a reset function that resets the output data Q to have a logic "low" level. In this case, the flip-flop 100 may receive a reset signal and may reset the output data Q to have a logic "low" level when the reset signal has a logic "high" level. In another exemplary embodiment, the flip-flop 100 may have an adjustment function that sets the output data Q to have a logic "high" level. In this case, the flip-flop 100 may receive an adjustment signal and may adjust the output data Q to have a logic "high" level when the adjustment signal has a logic "high" level.In yet another exemplary embodiment, the flip-flop 100 may include both a reset function that resets the output data Q to have a logic "low" level and a set function that sets the output data Q to have a logic "high" level. In this case, the flip-flop 100 may receive a reset signal and a set signal, may reset the output data Q to have a logic "low" level when the reset signal has a logic "high" level, and may set the output data Q to have a logic "high" level when the set signal has a logic "high" level. In some exemplary embodiments, the flip-flop 100 may further include a data retention function that performs data retention.Since a conventional master-slave flip-flop has an internal node that is repeatedly charged and discharged in response to the clock signal CK, the conventional master-slave flip-flop consumes power even while the input data D is not changed. Therefore, the conventional master-slave flip-flop cannot meet the low-power level required by a recent mobile device whose operating frequency is relatively high.On the other hand, the flip-flop 100 may have the internal node loaded by the inverted input data DN and the internal node loaded by the input data D, and the internal nodes of the flip-flop 100 may operate complementarily (e.g., the node values ​​of the internal nodes of the flip-flop 100 are determined complementarily), since the internal nodes of the flip-flop 100 are cross-connected, so that the flip-flop 100 can prevent unnecessary power consumption while the input data is not changed. Thus, the flip-flop 100 can operate with low power. That is, the internal nodes (e.g., the first node N1 and the second node N2) of the flip-flop 100 can be prevented from being repeatedly charged and discharged in response to the clock signal CK while the input data D is not changed.In addition, the internal nodes (e.g., the fifth node N5 and the sixth node N6) of the flip-flop 100 can be prevented from being repeatedly charged and discharged in response to the clock signal CK while the input data D is not changed. For this reason, the flip-flop 100 can meet the low-performance level required by a young mobile device whose operating frequency is relatively high, because the flip-flop 100 can consume much less power than the conventional master-slave flip-flop as an operating frequency (e.g., a frequency of the clock signal CK) increases. As a result, the flip-flop 100 can operate at a low power compared to the conventional master-slave flip-flop, so the flip-flop 100 can be applied to various low-power and high-performance chips constituting a low-power and high-performance mobile device.

[0022] Fig. 4 is a circuit diagram illustrating a flip-flop according to some example embodiments. Fig. 5A and Fig. 5B are diagrams for describing an operation of the flip-flop of the Fig. 4.

[0023] Referring to the Fig. 4 to 5B, the flip-flop 200 may include first to eleventh PMOS transistors PT1 to PT11 and first to eleventh NMOS transistors NT1 to NT11.

[0024] The first PMOS transistor PT1 may have a first terminal connected to the high-power voltage VDD, a second terminal connected to the third node N3, and a gate terminal receiving the clock signal CK. Thus, when the first PMOS transistor PT1 turns on in response to the clock signal CK, the high-power voltage VDD may be applied to the third node N3. The second PMOS transistor PT2 may have a first terminal connected to the high-power voltage VDD, a second terminal connected to the third node N3, and a gate terminal connected to the second node N2. Thus, when the PMOS transistor PT2 turns on in response to a voltage signal from the second node N2, the high-power voltage VDD may be applied to the third node N3.The third PMOS transistor PT3 may have a first terminal connected to the third node N3, a second terminal connected to the first node N1, and a gate terminal receiving the input data D. Thus, when the third PMOS transistor PT3 turns on in response to the input data D, the third node N3 may be connected to the first node N1. The first NMOS transistor NT1 and the second NMOS transistor NT2 may be connected in series between the first node N1 and the low-power voltage GND. For example, the low-power voltage GND may be a ground voltage. In an exemplary embodiment, as shown in FIG. Fig. 4, the first NMOS transistor NT1 has a first terminal connected to the first node N1, a second terminal connected to a first terminal of the second NMOS transistor NT2, and a gate terminal connected to the second node N2. The second NMOS transistor NT2 may have the first terminal connected to the second terminal of the first NMOS transistor NT1, a second terminal connected to the low-power voltage GND, and a gate terminal receiving the input data D. In this case, when the first NMOS transistor NT1 turns on in response to a voltage signal of the second node N2, and when the second NMOS transistor NT2 turns on in response to the input data D, the low-power voltage GND may be applied to the first node N1.In another exemplary embodiment, the first NMOS transistor NT1 may have a first terminal connected to the first node N1, a second terminal connected to a first terminal of the second NMOS transistor NT2, and a gate terminal that receives the input data D. The second NMOS transistor NT2 may have the first terminal connected to the second terminal of the first NMOS transistor NT1, a second terminal connected to the low-power voltage GND, and a gate terminal connected to the second node N2. In this case, when the first NMOS transistor NT1 turns on in response to the input data D, and when the second NMOS transistor NT2 turns on in response to a voltage signal of the second node N2, the low-power voltage GND may be applied to the first node N1.The fourth PMOS transistor PT4 may have a first terminal connected to the high-power voltage VDD, a second terminal connected to the first node N1, and a gate terminal connected to the second node N2. Thus, when the fourth PMOS transistor PT4 turns on in response to a voltage signal from the second node N2, the high-power voltage VDD may be applied to the first node N1. The third NMOS transistor NT3 may have a first terminal connected to the first node N1, a second terminal connected to a first terminal of the seventh NMOS transistor NT7, and a gate terminal connected to the second node N2. Thus, when the third NMOS transistor NT3 turns on in response to a voltage signal from the second node N2, the first terminal of the seventh NMOS transistor NT7 may be connected to the first node N1.

[0025] The fifth PMOS transistor PT5 may have a first terminal connected to the high-power voltage VDD, a second terminal connected to the fourth node N4, and a gate terminal receiving the clock signal CK. Thus, when the fifth PMOS transistor PT5 turns on in response to the clock signal CK, the high-power voltage VDD may be applied to the fourth node N4. The sixth PMOS transistor PT6 may have a first terminal connected to the high-power voltage VDD, a second terminal connected to the fourth node N4, and a gate terminal connected to the first node N1. Thus, when the sixth PMOS transistor PT6 turns on in response to a voltage signal from the first node N1, the high-power voltage VDD may be applied to the fourth node N4.The seventh PMOS transistor PT7 may have a first terminal connected to the fourth node N4, a second terminal connected to the second node N2, and a gate terminal receiving the inverted input data DN (e.g., data generated by inverting the input data D). Thus, when the seventh PMOS transistor PT7 turns on in response to the inverted input data DN, the fourth node N4 may be connected to the second node N2. The fourth NMOS transistor NT4 and the fifth NMOS transistor NT5 may be connected in series between the second node N2 and the low-power voltage GND. In an exemplary embodiment, as shown in FIG. Fig. 4, the fourth NMOS transistor NT4 has a first terminal connected to the second node N2, a second terminal connected to a first terminal of the fifth NMOS transistor NT5, and a gate terminal connected to the first node N1. The fifth NMOS transistor NT5 may have the first terminal connected to the second terminal of the fourth NMOS transistor NT4, a second terminal connected to the low-power voltage GND, and a gate terminal receiving the inverted input data DN. In this case, when the fourth NMOS transistor NT4 turns on in response to a voltage signal of the first node N1, and when the fifth NMOS transistor NT5 turns on in response to the inverted input data DN, the low-power voltage GND may be applied to the second node N2.In another exemplary embodiment, the fourth NMOS transistor NT4 may have a first terminal connected to the second node N2, a second terminal connected to a first terminal of the fifth NMOS transistor NT5, and a gate terminal that receives the inverted input data DN. The fifth NMOS transistor NT5 may have the first terminal connected to the second terminal of the fourth NMOS transistor NT4, a second terminal connected to the low-power voltage GND, and a gate terminal connected to the first node N1. In this case, when the fourth NMOS transistor NT4 turns on in response to the inverted input data DN, and when the fifth NMOS transistor NT5 turns on in response to a voltage signal of the first node N1, the low-power voltage GND may be applied to the second node N2.The eighth PMOS transistor PT8 may have a first terminal connected to the high-power voltage VDD, a second terminal connected to the second node N2, and a gate terminal connected to the first node N1. Thus, when the eighth PMOS transistor PT8 turns on in response to a voltage signal from the first node N1, the high-power voltage VDD may be applied to the second node N2. The sixth NMOS transistor NT6 may have a first terminal connected to the second node N2, a second terminal connected to a first terminal of the eighth NMOS transistor NT8, and a gate terminal connected to the first node N1. Thus, when the sixth NMOS transistor NT6 turns on in response to a voltage signal from the first node N1, the first terminal of the eighth NMOS transistor NT8 may be connected to the second node N2.

[0026] The seventh NMOS transistor NT7 may have a first terminal connected to a second terminal of the third NMOS transistor NT3, a second terminal connected to the sixth node N6, and a gate terminal receiving the clock signal CK. Thus, when the seventh NMOS transistor NT7 turns on in response to the clock signal CK, the second terminal of the third NMOS transistor NT3 may be connected to the sixth node N6. The ninth PMOS transistor PT9 may have a first terminal connected to the third node N3, a second terminal connected to the sixth node N6, and a gate terminal connected to the fifth node N5. Thus, when the ninth PMOS transistor PT9 turns on in response to a voltage signal from the fifth node N5, the third node N3 may be connected to the sixth node N6.The ninth NMOS transistor NT9 may have a first terminal connected to the sixth node N6, a second terminal connected to the low-power voltage GND, and a gate terminal connected to the fifth node N5. Thus, when the ninth NMOS transistor NT9 turns on in response to a voltage signal from the fifth node N5, the low-power voltage GND may be applied to the sixth node N6. The eighth NMOS transistor NT8 may have a first terminal connected to a second terminal of the sixth NMOS transistor NT6, a second terminal connected to the fifth node N5, and a gate terminal receiving the clock signal CK. Thus, when the eighth NMOS transistor NT8 turns on in response to the clock signal CK, the second terminal of the sixth NMOS transistor NT6 may be connected to the fifth node N5.The tenth PMOS transistor PT10 may have a first terminal connected to the fourth node N4, a second terminal connected to the fifth node N5, and a gate terminal connected to the sixth node N6. Thus, when the tenth PMOS transistor PT10 turns on in response to a voltage signal from the sixth node N6, the fourth node N4 may be connected to the fifth node N5. The tenth NMOS transistor NT10 may have a first terminal connected to the fifth node N5, a second terminal connected to the low-power voltage GND, and a gate terminal connected to the sixth node N6. Thus, when the tenth NMOS transistor NT10 turns on in response to a voltage signal from the sixth node N6, the low-power voltage GND may be applied to the fifth node N5.The eleventh PMOS transistor PT11 may have a first terminal connected to the high-power voltage VDD, a second terminal connected to the output node OUT, and a gate terminal connected to the sixth node N6. Thus, when the eleventh PMOS transistor PT11 turns on in response to a voltage signal from the sixth node N6, the high-power voltage VDD may be applied to the output node OUT. The eleventh NMOS transistor NT11 may have a first terminal connected to the output node OUT, a second terminal connected to the low-power voltage GND, and a gate terminal connected to the sixth node N6. Thus, when the eleventh NMOS transistor NT11 turns on in response to a voltage signal from the sixth node N6, the low-power voltage GND may be applied to the output node OUT.In other words, the eleventh PMOS transistor PT11 and the eleventh NMOS transistor NT11 form an inverter circuit, and thus an inverted voltage signal (for example, a voltage signal generated by inverting a voltage signal of the sixth node N6) can be output as the output data Q at the output node OUT.

[0027] Based on the above structure, the flip-flop 200 can latch the input data D at the rising edges of the clock signal CK and can output the latched input data D as the output data Q at the output node OUT. In particular, as shown in Fig. 5A, when the clock signal CK has a logic "low" level (for example, indicated by 0), a voltage signal of the third node N3 has a logic "high" level (for example, indicated by 1) due to the high-power voltage VDD. Here, since the third PMOS transistor PT3 turns on or off in response to the input data D, a voltage signal of the first node N1 may have a logic level corresponding to the inverted input data DN. For example, when the input data D has a logic "low" level, the first NMOS transistor NT1 and the second NMOS transistor NT2 may turn off, and the third PMOS transistor PT3 may turn on. Accordingly, a voltage signal of the third node N3 (for example, the high-power voltage VDD) may be applied to the first node N1, and thus, a voltage signal of the first node N1 may have a logic "high" level.On the other hand, when the input data D has a logic "high" level, the first NMOS transistor NT1 and the second NMOS transistor NT2 may turn on, and the third PMOS transistor PT3 may turn off. Thus, the low-power voltage GND may be applied to the first node N1, and thus a voltage signal of the first node N1 may have a logic "low" level. In other words, since a voltage signal of the first node N1 is opposite to a logic level of the input data D, a voltage signal of the first node N1 may have a logic level corresponding to the inverted input data DN. In addition, when the clock signal CK has a logic "low" level, a voltage signal of the fourth node N4 may have a logic "high" level due to the high-power voltage VDD.Here, since the seventh PMOS transistor PT7 turns on or off in response to the inverted input data DN, a voltage signal of the second node N2 may have a logic level corresponding to the input data D. For example, when the inverted input data DN has a logic "low" level, the fourth NMOS transistor NT4 and the fifth NMOS transistor NT5 may turn off, and the seventh PMOS transistor PT7 may turn on. Accordingly, a voltage signal of the fourth node N4 (for example, the high-power voltage VDD) may be applied to the second node N2, and thus a voltage signal of the second node N2 may have a logic "high" level. On the other hand, when the inverted input data DN has a logic "high" level, the fourth NMOS transistor NT4 and the fifth NMOS transistor NT5 may turn on, and the seventh PMOS transistor PT7 may turn off.Accordingly, the low-power voltage GND may be applied to the second node N2, and thus a voltage signal of the second node N2 may have a logic "low" level. In other words, since a voltage signal of the second node N2 is opposite to a logic level of the inverted input data DN, a voltage signal of the second node N2 may have a logic level corresponding to the input data D. Here, since the clock signal CK has a logic "low" level, the seventh NMOS transistor NT7 and the ninth NMOS transistor NT9 may turn off. Therefore, a voltage signal of the first node N1 may maintain a logic level corresponding to the inverted input data DN, and a voltage signal of the second node N2 may maintain a logic level corresponding to the input data D.

[0028] Below, as in Fig. 5B, when the clock signal CK changes from a logic "low" level to a logic "high" level (e.g., a rising edge of the clock signal CK), the seventh NMOS transistor NT7 and the eighth NMOS transistor NT8 turn on. Accordingly, a voltage signal of the fifth node N5 may have a logic level corresponding to the input data D, and a voltage signal of the sixth node N6 may have a logic level corresponding to the inverted input data DN.That is, since a voltage signal of the first node N1 (for example, the inverted input data DN) and a voltage signal of the second node N2 (for example, the input data D) are transmitted to the sixth node N6 and the fifth node N5 via the seventh NMOS transistor NT7 and the eighth NMOS transistor NT8, respectively, a voltage signal of the sixth node N6 may have a logic level corresponding to the inverted input data DN, and a voltage signal of the fifth node N5 may have a logic level corresponding to the input data D. In other words, the input data D and the inverted input data DN may be latched at the fifth node N5 and the sixth node N6, respectively.Here, since the eleventh PMOS transistor PT11 and the eleventh NMOS transistor NT11 function as the inverter circuit, a voltage signal of the output node OUT may be a voltage signal generated by inverting a voltage signal of the sixth node N6, and thus a voltage signal of the output node OUT may have a logic level corresponding to the input data D. That is, the input data D latched at the rising edges of the clock signal CK may be output as the output data Q at the output node OUT.As described above, when the flip-flop 200 performs the above operation, the first node N1 of the left structure and the second node N2 of the right structure can be cross-connected, so that the first node N1 of the left structure and the second node N2 of the right structure can operate complementarily (for example, a node value of the first node N1 of the left structure and a node value of the second node N2 of the right structure can be determined complementarily). Accordingly, the first node N1 of the left structure and the second node N2 of the right structure can be prevented from being repeatedly charged and discharged in response to the clock signal CK while the input data D is not changed.In addition, when the flip-flop 200 performs the above operation, the sixth node N6 of the left structure and the fifth node N5 of the right structure may be cross-connected, so that the sixth node N6 of the left structure and the fifth node N5 of the right structure can operate complementarily (for example, a node value of the sixth node N6 of the left structure and a node value of the fifth node N5 of the right structure can be determined complementarily). Accordingly, the sixth node N6 of the left structure and the fifth node N5 of the right structure can be prevented from being repeatedly charged and discharged in response to the clock signal CK while the input data D is not changed.That is, cross-connected internal nodes of the flip-flop 200 (for example, a pair of the first node N1 and the second node N2 and a pair of the fifth node N5 and the sixth node N6) can operate complementarily (for example, the node values ​​of the cross-connected internal nodes can be determined complementarily), so that the cross-connected internal nodes of the flip-flop 200 can be prevented from being repeatedly charged and discharged in response to the clock signal CK while input data D is not changed. Accordingly, the flip-flop 200 can prevent unnecessary power consumption while the input data D is not changed. As a result, the flip-flop 200 can operate at low power.

[0029] Fig. 6 is a block diagram illustrating an example in which the flip-flop of the Fig. 4 is implemented by logic element. The Fig. 7A and Fig. 7B are diagrams for describing an operation of the flip-flop of the Fig. 6.

[0030] Referring to the Fig. 6 to 7B, the flip-flop 200 may include a first AND gate element AND1, a first OR gate element OR1, a first NAND gate element NAND1, a first inverter element INV1, a second AND gate element AND2, a second OR gate element OR2, a second NAND gate element NAND2, a third OR gate element OR3, a third AND gate element AND3, a first NOR gate element NOR1, a fourth OR gate element OR4, a fourth AND gate element AND4, and a second NOR gate element NOR2. In some example embodiments, the flip-flop 200 may further include a second inverter element INV2.

[0031] The first AND gate element AND1 may have a first input terminal connected to the second node N2, a second input terminal receiving the clock signal CK, a third input terminal connected to the fifth node N5, and an output terminal outputting an AND operation result among a voltage signal of the second node N2, the clock signal CK, and a voltage signal of the fifth node N5. The first OR gate element OR1 may have a first input terminal connected to the output terminal of the first AND gate element AND1, a second input terminal receiving the input data D, and an output terminal outputting an OR operation result between the AND operation result of the first AND gate element AND1 and the input data D.The first NAND gate element NAND1 may have a first input terminal connected to the output terminal of the first OR gate element OR1, a second input terminal connected to the second node N2, and an output terminal (e.g., the first node N1) that outputs a NAND operation result between the OR operation result of the first OR gate element OR1 and a voltage signal of the second node N2. The first inverter element INV1 may be connected between the second input terminal of the first OR gate element OR1 and the first input terminal of the second OR gate element OR2. The first inverter element INV1 may invert the input data D to output the inverted input data DN.The second AND gate element AND2 may have a first input terminal connected to the first node N1, a second input terminal receiving the clock signal CK, a third input terminal connected to the sixth node N6, and an output terminal outputting an AND operation result among a voltage signal of the first node N1, the clock signal CK, and a voltage signal of the sixth node N6. The second OR gate element OR2 may have a first input terminal receiving the inverted input data DN, a second input terminal connected to the output terminal of the second AND gate element AND2, and an output terminal outputting an OR operation result between the inverted input data DN and the AND operation result of the second AND gate element AND2.The second NAND gate element NAND2 may have a first input terminal connected to the first node N1, a second input terminal connected to the output terminal of the second OR gate element OR2, and an output terminal (for example, the second node N2) that outputs a NAND operation result between a voltage signal of the first node N1 and the OR operation result of the second OR gate element OR2.

[0032] The third OR gate element OR3 may have a first input terminal receiving the inverted input data DN, a second input terminal connected to the first node N1, and an output terminal outputting an OR operation result between the inverted input data DN and the voltage signal of the first node N1. The third AND gate element AND3 may have a first input terminal connected to the output terminal of the third OR gate element OR3, a second input terminal receiving the clock signal CK, a third input terminal connected to the first node N1, and an output terminal outputting an AND operation result between the OR operation result of the third OR gate element OR3, the clock signal CK, and the voltage signal of the first node N1.The first NOR gate element NOR1 may have a first input terminal connected to the output terminal of the third AND gate element AND3, a second input terminal connected to the sixth node N6, and an output terminal (e.g., the fifth node N5) that outputs a NOR operation result between the AND operation result of the third AND gate element AND3 and the voltage signal of the sixth node N6. The fourth OR gate element OR4 may have a first input terminal connected to the second node N2, a second input terminal that receives the input data D, and an output terminal that outputs an OR operation result between the voltage signal of the second node N2 and the input data D.The fourth AND gate element AND4 may have a first input terminal connected to the second node N2, a second input terminal receiving the clock signal CK, a third input terminal connected to the output terminal of the fourth OR gate element OR4, and an output terminal outputting an AND operation result between the voltage signal of the second node N2, the clock signal CK, and the OR operation result of the fourth OR gate element OR4.The second NOR gate element NOR2 may have a first input terminal connected to the fifth node N5, a second input terminal connected to the output terminal of the fourth AND gate element AND4, and an output terminal (for example, the sixth node N6) that outputs a NOR operation result between the voltage signal at the fifth node N5 and the AND operation result of the fourth AND gate element AND4. The second inverter element INV2 may be connected between the sixth node N6 and the output node OUT. The second inverter element INV2 may invert the voltage signal of the sixth node N6 to output the output data Q.

[0033] Based on the above structure, the flip-flop 200 can latch the input data D at the rising edges of the clock signal CK and can output the latched input data D as the output data Q at the output node OUT. In particular, as shown in Fig. 7A, when the clock signal CK has a logic "low" level (for example, indicated by 0), the AND operation result of the first AND gate element AND1 has a logic "low" level. Here, since the first OR gate element OR1 performs an OR operation between the AND operation result of the first AND gate element AND1 (for example, a logic "low" level) and the input data D, the OR operation result of the first OR gate element OR1 may be the input data D. The first inverter element INV1 may invert the input data D to output the inverted input data DN. When the clock signal CK has a logic "low" level (for example, indicated by 0), the AND operation result of the second AND gate element AND2 may have a logic "low" level.Here, since the second OR gate element OR2 performs an OR operation between the AND operation result of the second AND gate element AND2 (for example, a logic "low" level) and the inverted input data DN, the OR operation result of the second OR gate element OR2 can be the inverted input data DN. As described above, the output terminal (for example, the first node N1) of the first NAND gate element NAND1 can be connected to the first input terminal of the second NAND gate element NAND2, and the output terminal (for example, the second node N2) of the second NAND gate element NAND2 can be connected to the second input terminal of the first NAND gate element NAND1.In other words, the first node N1 and the second node N2 can be cross-connected, and thus the first node N1 and the second node N2 can operate complementarily (e.g., node values ​​of the first node N1 and the second node N2 can be determined complementarily). Specifically, since the first NAND gate element NAND1 performs a NAND operation between the operation result of the first OR gate element OR1 (e.g., the input data D) and the voltage signal of the second node N2, the NAND operation result of the first NAND gate element NAND1 can be determined (e.g., fixed) to be the inverted input data DN.In addition, since the second NAND gate element NAND2 performs a NAND operation between the OR operation result of the second OR gate element OR2 (e.g., the inverted input data DN) and the voltage signal of the first node N1, the NAND operation result of the second NAND gate element NAND2 can be determined (e.g., fixed) to be the input data. As a result, the voltage signal of the first node N1 can maintain a logic level corresponding to the inverted input data DN, and the voltage signal of the second node N2 can maintain a logic level corresponding to the input data D. Since the third OR gate element OR3 receives the inverted input data DN at its first input terminal and receives the inverted input data DN at its second input terminal, the OR operation result of the third OR gate element OR3 can be the inverted input data DN.Since the fourth OR gate element OR4 receives the input data D at its first input terminal and receives the input data D at its second input terminal, the OR operation result of the fourth OR gate element OR4 may be the input data D. However, since the clock signal CK has a logic "low" level, the AND operation result of the third AND gate element AND3 and the AND operation result of the fourth AND gate element AND4 may have a logic "low" level.

[0034] Below, as in Fig. 7B, when the clock signal CK changes from a logic "low" level to the logic "high" level (for example, a rising edge of the clock signal CK), the third AND gate element AND3 may receive the inverted input data DN at its first input terminal, may receive the clock signal CK having the logic "high" level at its second input terminal, and may receive the inverted input data DN at its third input terminal. Thus, the AND operation result of the third AND gate element AND3 may be the inverted input data DN. In addition, the fourth AND gate element AND4 may receive the input data D at its first input terminal, may receive the clock signal CK having a logic "high" level at its second input terminal, and may receive the input data D at its third input terminal.Accordingly, the AND operation result of the fourth AND gate element AND4 may be the input data D. As described above, the output terminal of the first NOR gate element NOR1 (for example, the fifth node N5) may be connected to the first input terminal of the second NOR gate element NOR2, and the output terminal of the second NOR gate element NOR2 (for example, the sixth node N6) may be connected to the second input terminal of the first OR gate element OR1. In other words, the fifth node N5 and the sixth node N6 may be cross-connected, and thus the fifth node N5 and the sixth node N6 may operate complementarily (for example, node values ​​of the fifth node N5 and the sixth node N6 may be determined complementarily).Specifically, since the first NOR gate element NOR1 performs a NOR operation between the AND operation result of the third AND gate element AND3 (for example, the inverted input data DN) and the voltage signal of the sixth node N6, the NOR operation result of the first NOR gate element NOR1 can be determined (or fixed) to be the input data D. In addition, since the second NOR gate element NOR2 performs a NOR operation between the AND operation result of the fourth AND gate element AND4 (for example, the input data) and the voltage signal of the fifth node N5, the NOR operation result of the second NOR gate element NOR2 can be determined (or fixed) to be the inverted input data DN.As a result, the voltage signal of the fifth node N5 can maintain a logic level corresponding to the input data D, and the voltage signal of the sixth node N6 can maintain a logic level corresponding to the inverted input data DN. In other words, the input data and the inverted input data DN can be latched at the fifth node N5 and the sixth node N6, respectively. Thus, the second inverter element INV2 can invert the voltage signal of the sixth node N6 (for example, the inverted input data DN) to output the input data D as the output data Q. That is, since the voltage signal of the output node OUT of the voltage signal generated by inverting the voltage signal of the sixth node N6, the voltage signal of the output node OUT can have a logic level corresponding to the input data D.In short, the flip-flop 200 can latch the input data D on the rising edges of the clock signal CK and can output the latched input data D as the output data Q at the output node OUT.

[0035] Fig. 8 is a circuit diagram illustrating a flip-flop according to some example embodiments. Fig. 9A and Fig. 9B are diagrams for describing an operation of the flip-flop of the Fig. 8.

[0036] Referring to Fig. 8 to 9B, the flip-flop 300 may include first to thirteenth PMOS transistors PT1 to PT13 and first to thirteenth NMOS transistors NT1 to NT13. That is, the flip-flop 300 may have a structure in which the twelfth and thirteenth PMOS transistors PT12 and PT13 and the twelfth and thirteenth NMOS transistors NT12 and NT13 are added to the flip-flop 200 of the Fig. 4 are added to have the reset function. Accordingly, the description which is related to the flip-flop 200 of the Fig. 4 will not be repeated. Hereinafter, the description will focus on the twelfth and thirteenth PMOS transistors PT12 and PT13 and the twelfth and thirteenth NMOS transistors NT12 and NT13.

[0037] The flip-flop 300 may latch the input data D on the rising edges of the clock signal CK and may output the latched input data D as the output data Q at the output node OUT. In addition, the flip-flop 300 may receive a reset signal R and may reset the output data Q to have a logic "low" level when the reset signal R has a logic "high" level. For this operation, the flip-flop 300 may have a structure in which the twelfth and thirteenth PMOS transistors PT12 and PT13 and the twelfth and thirteenth NMOS transistors NT12 and NT13 are connected to the flip-flop 200 of the Fig. 4 are added. The twelfth PMOS transistor PT12 may be connected between the high-power voltage VDD and the eighth PMOS transistor PT8. That is, the twelfth PMOS transistor PT12 may have a first terminal connected to the high-power voltage VDD, a second terminal connected to a first terminal of the eighth PMOS transistor PT8, and a gate terminal receiving the reset signal R. Thus, when the twelfth PMOS transistor PT12 turns on in response to the reset signal R, the high-power voltage VDD may be applied to the first terminal of the eighth PMOS transistor PT8. The thirteenth PMOS transistor PT13 may be connected between the fourth node N4 and the fifth and sixth PMOS transistors PT5 and PT6.That is, the thirteenth PMOS transistor PT13 may have a first terminal connected to second terminals of the fifth and sixth PMOS transistors PT5 and PT6, a second terminal connected to the fourth node N4, and a gate terminal receiving the reset signal R. Accordingly, when the thirteenth PMOS transistor PT13 turns on in response to the reset signal R, the second terminals of the fifth and sixth PMOS transistors PT5 and PT6 may be connected to the fourth node N4. The twelfth NMOS transistor NT12 may be connected between the second node N2 and the low-power voltage GND. That is, the twelfth NMOS transistor NT12 may have a first terminal connected to the second node N2, a second terminal connected to the low-power voltage GND, and a gate terminal receiving the reset signal R.Accordingly, when the twelfth NMOS transistor NT12 turns on in response to the reset signal R, the low-power voltage GND may be applied to the second node N2. The thirteenth NMOS transistor NT13 may be connected between the fifth node N5 and the low-power voltage GND. That is, the thirteenth NMOS transistor NT13 may have a first terminal connected to the fifth node N5, a second terminal connected to the low-power voltage GND, and a gate terminal receiving the reset signal R. Accordingly, when the thirteenth NMOS transistor NT13 turns on in response to the reset signal R, the low-power voltage GND may be applied to the fifth node N5.

[0038] Based on the above structure, the flip-flop 300 can output the output data Q having a logic "low" level when the reset signal R has a logic "high" level. In particular, as shown in Fig. As illustrated in Figure 9A, when the reset signal R has a logic "low" level, the twelfth PMOS transistor PT12 can turn on, the thirteenth PMOS transistor PT13 can turn on, the twelfth NMOS transistor NT12 can turn off, and the thirteenth NMOS transistor NT13 can turn off. Accordingly, when the reset signal R has a logic "low" level, the flip-flop 300 has the same structure as the flip-flop 200 of the Fig. 4. As a result, the flip-flop 300 can latch the input data D on the rising edges of the clock signal CK and can output the latched input data D as the output data Q to the output node OUT. On the other hand, as shown in Fig. As illustrated in Figure 9B, when the reset signal R has a logic "high" level, the twelfth PMOS transistor PT12 may turn off, the thirteenth PMOS transistor PT13 may turn off, the twelfth NMOS transistor NT12 may turn on, and the thirteenth NMOS transistor NT13 may turn on. Accordingly, the voltage signal of the second node N2 and the voltage signal of the fifth node N5 may have a logic "low" level. Here, since the voltage signal of the second node N2 has the logic "low" level, the second PMOS transistor PT2 may turn on. As a result, the voltage signal of the first node N1 may have a logic "high" level. In addition, since the voltage signal of the fifth node N5 has a logic "low" level, the ninth PMOS transistor PT9 may turn on. As a result, the voltage signal of the sixth node N6 may also have a logic “high” level.Here, the eleventh PMOS transistor PT11 and the eleventh NMOS transistor NT11 may function as an inverter circuit. Accordingly, the voltage signal of the output node OUT may be a voltage signal generated by inverting the voltage signal of the sixth node N6, and thus, the voltage signal of the output node OUT may have a logic "low" level. In summary, the flip-flop 300 may reset the output data Q to have a logic "low" level when the reset signal R has a logic "high" level.

[0039] Fig. 10 is a block diagram illustrating an example in which the flip-flop of the Fig. 8 is implemented by logic elements. The Fig. 11A and Fig. 11B are diagrams for describing an operation of the flip-flop of the Fig. 10.

[0040] Referring to the Fig. 10 to 11B, the flip-flop 300 may include a first AND gate element AND1, a first OR gate element OR1, a first NAND gate element NAND1, a first inverter element INV1, a second AND gate element AND2, a second OR gate element OR2, a fifth AND gate element AND5, a third NOR gate element NOR3, a third OR gate element OR3, a third AND gate element AND3, a first NOR gate element NOR1, a fourth OR gate element OR4, a fourth AND gate element AND4, a second NOR gate element NOR2, and a second inverter element INV2. That is, the flip-flop 300 may have a structure in which the second NAND gate element NAND2 of the flip-flop 200 of the Fig. 6 is replaced by the fifth AND gate element AND5 and the third NOR gate element NOR3, and the reset signal R is additionally applied to the first NOR gate element NOR1 of the flip-flop 200 of the Fig. 6 to have the reset function. Accordingly, the description which is related to the flip-flop 200 of the Fig. 6 will not be repeated. Hereinafter, the description will focus on the fifth AND gate element AND5, the third NOR gate element NOR3, and the first NOR gate element NOR1.

[0041] The flip-flop 300 may latch the input data D on the rising edges of the clock signal CK and may output the latched input data D as the output data to the output node OUT. In addition, the flip-flop 300 may receive the reset signal R and may reset the output data Q to have a logic "low" level when the reset signal has a logic "high" level. For this operation, the flip-flop 300 may have a structure in which the second NAND gate element NAND2 of the flip-flop 200 of the Fig. 6 is replaced by the fifth AND gate element AND5 and the third NOR gate element NOR3, and the reset signal R is additionally applied to the first NOR gate element NOR1 of the flip-flop 200 of the Fig. 6. The fifth AND gate element AND5 may have a first input terminal connected to the first node N1, a second input terminal connected to the output terminal of the second OR gate element OR2, and an output terminal outputting an AND operation result between the voltage signal of the first node N1 and the OR operation result of the second OR gate element OR2. The third NOR gate element NOR3 may have a first input terminal receiving the reset signal R, a second input terminal connected to the output terminal of the fifth AND gate element AND5, and an output terminal (e.g., the second node N2) outputting a NOR operation result between the reset signal R and the AND operation result of the fifth AND gate element AND5.The first NOR gate element NOR1 may have a first input terminal connected to the output terminal of the third AND gate element AND3, a second input terminal receiving the reset signal R, a third input terminal connected to the sixth node N6, and an output terminal (for example, the fifth node N5) outputting a NOR operation result among the AND operation result of the third AND gate element AND3, the reset signal R, and the voltage signal of the sixth node N6.

[0042] Based on the above structure, the flip-flop 300 can output the output data Q having a logic "low" level when the reset signal R has a logic "high" level. In particular, as shown in Fig. 11A, when the reset signal R has a logic “low” level, the fifth AND gate element AND5 and the third NOR gate element NOR3 of the flip-flop 300 act as the second NAND gate element NAND2 of the flip-flop 200 of the Fig. 6, since the third NOR gate element NOR3 functions as an inverter element. In addition, when the reset signal R has a logic "low" level, the reset signal R supplied to the second input terminal of the first NOR gate element NOR1 cannot affect the NOR operation result of the first NOR gate element NOR1. Therefore, the first NOR gate element NOR1 of the flip-flop 300 can function as the first NOR gate element NOR1 of the flip-flop 200 of the Fig. 6. As a result, the flip-flop 300 can latch the input data D on the rising edges of the clock signal CK and can output the latched input data D as the output data Q to the output node OUT. On the other hand, as shown in Fig. As illustrated in Figure 11B, when the reset signal R has a logic "high" level, the NOR operation result of the third NOR gate element NOR3 may have a logic "low" level (for example, the voltage signal of the second node N2 may have a logic "low" level). Accordingly, the AND operation result of the fourth AND gate element AND4 may have a logic "low" level. In addition, when the reset signal R has a logic "high" level, the NOR operation result of the first NOR gate element NOR1 may have a logic "low" level (for example, the voltage signal of the fifth node N5 may have a logic "low" level). Accordingly, the second NOR gate element NOR2 can receive the voltage signal having a logic "low" level at the first input terminal, and can receive the voltage signal having a logic "low" level at the second input terminal.As a result, the NOR operation result of the second NOR gate element NOR2 may have a logic "high" level (for example, the voltage signal of the sixth node N6 may have a logic "high" level). Here, since the second inverter element INV2 inverts the voltage signal of the sixth node N6 to output the output data Q, the voltage signal of the output node OUT may be a voltage signal generated by inverting the voltage signal of the sixth node N6. Accordingly, the voltage signal of the output node OUT may have a logic "low" level. In summary, the flip-flop 300 may reset the output data Q to have a logic "low" level when the reset signal R has a logic "high" level.

[0043] Fig. 12 is a circuit diagram illustrating a flip-flop according to some example embodiments. Fig. 13A and Fig. 13B are diagrams for describing an operation of the flip-flop of the Fig. 12.

[0044] Referring to the Fig. 12 to 13B, the flip-flop 400 may include first to eleventh PMOS transistors PT1 to PT11, fourteenth and fifteenth PMOS transistors PT14 and PT15, first to eleventh NMOS transistors NT1 to NT11, and fourteenth and fifteenth NMOS transistors NT14 and NT15. ​​That is, the flip-flop 400 may have a structure in which the fourteenth and fifteenth PMOS transistors PT14 and PT15 and the fourteenth and fifteenth NMOS transistors NT14 and NT15 are added to the flip-flop 200 of the Fig. 4 are added to have the setting function. Accordingly, the description which is related to the flip-flop 200 of the Fig. 4 will not be repeated. Hereinafter, the description will focus on the fourteenth and fifteenth PMOS transistors PT14 and PT15 and the fourteenth and fifteenth NMOS transistors NT14 and NT15.

[0045] The flip-flop 400 may latch the input data D on the rising edges of the clock signal CK and may output the latched input data D as the output data Q at the output node OUT. In addition, the flip-flop 400 may receive a setting signal S and may set the output data Q to have a logic "high" level when the setting signal S has a logic "high" level. For this operation, the flip-flop 400 may have a structure in which the fourteenth and fifteenth PMOS transistors PT14 and PT15 and the fourteenth and fifteenth NMOS transistors NT14 and NT15 are connected to the flip-flop 200 of the Fig. 4 are added. The fourteenth PMOS transistor PT14 may be connected between the third node N3 and the second terminals of the first and second PMOS transistors PT1 and PT2. That is, the fourteenth PMOS transistor PT14 may have a first terminal connected to the second terminals of the first and second PMOS transistors PT1 and PT2, a second terminal connected to the third node N3, and a gate terminal receiving the setting signal S. Thus, when the fourteenth PMOS transistor PT14 turns on in response to the setting signal S, the second terminals of the first and second PMOS transistors PT1 and PT2 may be connected to the third node N3. The fifteenth PMOS transistor PT15 may be connected between the high-power voltage VDD and the fourth PMOS transistor PT4.That is, the fifteenth PMOS transistor PT15 may have a first terminal connected to the high-power voltage VDD, a second terminal connected to the first terminal of the fourth PMOS transistor PT4, and a gate terminal receiving the adjustment signal S. Accordingly, when the fifteenth PMOS transistor PT15 turns on in response to the adjustment signal, the high-power voltage VDD may be applied to the first terminal of the fourth PMOS transistor PT4. The fourteenth NMOS transistor NT14 may be connected between the first node N1 and the low-power voltage GND. That is, the fourteenth NMOS transistor NT14 may have a first terminal connected to the first node N1, a second terminal connected to the low-power voltage GND, and a gate terminal receiving the adjustment signal S.Accordingly, when the fourteenth NMOS transistor NT14 turns on in response to the setting signal S, the low-power voltage GND may be applied to the first node N1. The fifteenth NMOS transistor NT15 may be connected between the sixth node N6 and the low-power voltage GND. That is, the fifteenth NMOS transistor NT15 may have a first terminal connected to the sixth node N6, a second terminal connected to the low-power voltage GND, and a gate terminal receiving the setting signal S. Accordingly, when the fifteenth NMOS transistor NT15 turns on in response to the setting signal S, the low-power voltage GND may be applied to the sixth node N6.

[0046] Based on the above structure, the flip-flop 400 can output the output data Q having a logic "high" level when the setting signal S has a logic "high" level. In particular, as shown in Fig. 13A, when the setting signal S has a logic "low" level, the fourteenth PMOS transistor PT14 may turn on, the fifteenth PMOS transistor PT15 may turn on, the fourteenth NMOS transistor NT14 may turn off, and the fifteenth NMOS transistor NT15 may turn off. Thus, when the setting signal S has a logic "low" level, the flip-flop 400 may have the same structure as the flip-flop 200 of the Fig. 4. As a result, the flip-flop 400 can latch the input data D at the rising edges of the clock signal CK and can output the latched input data D as the output data Q at the output node OUT. On the other hand, as shown in Fig. As illustrated in Figure 13B, when the setting signal S has a logic "high" level, the fourteenth PMOS transistor PT14 may turn off, the fifteenth PMOS transistor PT15 may turn off, the fourteenth NMOS transistor NT14 may turn on, and the fifteenth NMOS transistor NT15 may turn on. Accordingly, the voltage signal of the first node N1 and the voltage signal of the sixth node N6 may have a logic "low" level. Here, since the voltage signal of the first node N1 has a logic "low" level, the sixth PMOS transistor PT6 may turn on. As a result, the voltage signal of the fourth node N4 may have a logic "high" level. In addition, since the voltage signal of the sixth node N6 has a logic "low" level, the tenth PMOS transistor PT10 may turn on. As a result, the voltage signal of the fifth node N5 may also have a logic “high” level.Furthermore, since the ninth NMOS transistor NT9 turns on when the voltage signal of the fifth node N5 has a logic "high" level, the voltage signal of the sixth node N6 can be determined (or fixed) to have a logic "low" level. Here, the eleventh PMOS transistor PT11 and the eleventh NMOS transistor NT11 can function as an inverter circuit. Thus, the voltage signal of the output node OUT can be a voltage signal generated by inverting the voltage signal of the sixth node N6, and thus the voltage signal of the output node OUT can have a logic "high" level. In summary, the flip-flop 400 can set the output data Q to have a logic "high" level when the setting signal S has a logic "high" level.

[0047] Fig. 14 is a block diagram illustrating an example in which the flip-flop of the Fig. 12 is implemented by logic elements. The Fig. 15A and Fig. 15B are diagrams for describing an operation of the flip-flop of the Fig. 14.

[0048] Referring to the Fig. 14 to 15B, the flip-flop 400 may include a first AND gate element AND1, a first OR gate element OR1, a first NAND gate element NAND1, a first inverter element INV1, a second AND gate element AND2, a second OR gate element OR2, a second NAND gate element NAND2, a third OR gate element OR3, a third AND gate element AND3, a first NOR gate element NOR1, a fourth OR gate element OR4, a fourth AND gate element AND4, a second NOR gate element NOR2, and a second inverter element INV2. That is, the flip-flop 400 may have a structure in which the setting signal S is applied to the second NOR gate element NOR2 of the flip-flop 200 of the Fig. 6 is additionally supplied to have the setting function. Accordingly, the description which is made with the flip-flop 200 of the Fig. 6 will not be repeated. Hereinafter, the description will focus on the second NOR gate element NOR2.

[0049] The flip-flop 400 may latch the input data D on the rising edges of the clock signal CK and may output the latched input data D as the output data Q at the output node OUT. In addition, the flip-flop 400 may receive the setting signal S and set the output data Q to have a logic "high" level when the setting signal S has a logic "high" level. For this operation, the flip-flop 400 may have a structure in which the setting signal S is additionally applied to the second NOR gate element NOR2 of the flip-flop 200 of the Fig. 6. The second NOR gate element NOR2 may have a first input terminal connected to the fifth node N5, a second input terminal receiving the setting signal S, a third input terminal connected to the output terminal of the fourth AND gate element AND4, and an output terminal (for example, the sixth node N6) outputting the NOR operation result between the voltage signal of the fifth node N5, the setting signal S, and the AND operation result of the fourth AND gate element AND4. Based on the above structure, the flip-flop 400 may output the output data Q having a logic "high" level when the setting signal S has a logic "high" level. In particular, as shown in Fig. 15A, when the setting signal S has a logic "low" level, the setting signal S supplied to the second input terminal of the second NOR gate element NOR2 does not affect the NOR operation result of the second NOR gate element NOR2. Accordingly, the second NOR gate element NOR2 of the flip-flop 400 can be used as the second NOR gate element NOR2 of the flip-flop 200 of the Fig. 6. As a result, the flip-flop 400 can latch the input data D on the rising edges of the clock signal CK and can output the latched input data D as the output data Q at the output node OUT. On the other hand, as shown in Fig. 15B, when the setting signal S has a logic "high" level, the NOR operation result of the second NOR gate element NOR2 has a logic "low" level (for example, the voltage signal of the sixth node N6 may have a logic "low" level). Here, since the second inverter element INV2 inverts the voltage signal of the sixth node N6 to output the output data Q, the voltage signal of the output node OUT may be a voltage signal generated by inverting the voltage signal of the sixth node N6. Accordingly, the voltage signal of the output node OUT may have a logic "high" level. In summary, the flip-flop 400 may set the output data Q to have a logic "high" level when the setting signal S has a logic "high" level.

[0050] Fig. 16 is a circuit diagram illustrating a flip-flop according to some example embodiments. Fig. 17 is a block diagram illustrating an example in which the flip-flop of the Fig. 16 is implemented by logic elements.

[0051] Referring to the Fig. 16 and Fig. 17, the flip-flop 500 may include first to fifteenth PMOS transistors PT1 to PT15 and first to fifteenth NMOS transistors NT1 to NT15. ​​That is, the flip-flop 500 may have a structure in which the twelfth and thirteenth PMOS transistors PT12 and PT13 are among the twelfth and thirteenth NMOS transistors NT12 and NT13 to the flip-flop 200 of the Fig. 4 are added to include the reset function, and the fourteenth and fifteenth PMOS transistors PT14 and PT15 and the fourteenth and fifteenth NMOS transistors NT14 and NT15 to the flip-flop 200 of the Fig. 4 are added to include the setting function. Since the twelfth to fifteenth PMOS transistors PT12 to PT15 and the twelfth to fifteenth NMOS transistors NT12 to NT15 are described above, duplicate description related thereto will not be repeated. When the flip-flop 500 is implemented (or expressed) by logic elements, the flip-flop 500 may include a first AND gate element AND1, a first OR gate element OR1, a first NAND gate element NAND1, a first inverter element INV1, a second AND gate element AND2, a second OR gate element OR2, a fifth AND gate element AND5, a third NOR gate element NOR3, a third OR gate element OR3, a third AND gate element AND3, a first NOR gate element NOR1, a fourth OR gate element OR4, a fourth AND gate element AND4, a second NOR gate element NOR2, and a second inverter element INV2.As described above, the flip-flop 500 may have a structure in which the second NAND gate element NAND2 of the flip-flop 200 of the . Fig. 6 is replaced by the fifth AND gate element AND5 and the third NOR gate element NOR3, the reset signal R is applied to the first NOR gate element NOR1 of the flip-flop 200 of the Fig. 6 is additionally supplied, and the setting signal S to the second NOR gate element NOR2 of the flip-flop 200 of the Fig. 6 is additionally supplied to provide both the reset function and the setting function. Since these logic elements are described above, duplicate descriptions related thereto will not be repeated.

[0052] Fig. 18 is a block diagram illustrating an integrated circuit having a scan chain circuit according to some example embodiments. Fig. 19 is a timing chart for describing an operation of a flip-flop used in a scan chain circuit of the integrated circuit of the Fig. 18 is included.

[0053] Referring to the Fig. 18 and Fig. 19, the integrated circuit 600 may include a combinational logic circuit 610 and a scan chain circuit 630. Here, the combinational logic circuit 610 may include a plurality of flip-flops 635, and the flip-flops 635 may form a scan path by being connected to the combinational logic circuit 610. Although in Fig. While Figure 18 illustrates that all combinational logic circuits 610 are connected to the scan chain circuit 630 in the integrated circuit 600, in some other example embodiments, some combinational logic circuits 610 for which a scan test is not performed may not be connected to the scan chain circuit 630 in the integrated circuit 600. In some example embodiments, the integrated circuit 600 may be implemented as a system-on-chip (SOC).

[0054] The combinational logic circuit 610 may include logic cones, multiplexers, etc. Here, the combinational logic circuit 610 may be connected to the scan chain circuit 630 so that a scan test is performed for the combinational logic circuit 610. In general, a scan test for the integrated circuit 600 may be performed by performing a shift-in operation, which sequentially loads a test pattern SI onto the scan chain circuit 630 (e.g., indicated by SHIFT-IN); by performing a capture operation, which stores an observation value SU of the combinational logic circuit 610 in the scan chain circuit 630 (e.g., indicated by CAPTURE); the observation value SO is generated based on the test pattern SI loaded onto the scan chain circuit 630 and by performing a shift-out operation.Shift-out operation that sequentially outputs the observation value SO stored in the scan chain circuit 630 (indicated, for example, by SHIFT-OUT). Here, the flip-flops 635 included in the scan chain circuit 630 can be triggered on rising edges of a clock signal CK. Here, except that a multiplexer that selectively provides a scan enable signal SE is included, each of the flip-flops 635 included in the scan chain circuit 630 can be the flip-flop 100 of the . Fig. 1A and Fig. 1B, the flip-flop 200 of the Fig. 4, the flip-flop 300 of the Fig. 8, the flip-flop 400 of the Fig. 12 or the flip-flop 500 of the Fig. 16. Since operations and structures of the flip-flops 635 are described above, duplicate description will not be repeated. For example, as shown in the Fig. 18 and Fig. 19, when the scan enable signal SE applied to the integrated circuit 600 has a logic "high" level, the shift-in operation, which sequentially applies a specific test pattern SI to the scan chain circuit 630 via a scan test input terminal SIP of the integrated circuit 600, may be performed (for example, indicated by SHIFT-IN). Next, the capture operation, which stores the observation value SO of the combinational logic circuit 610 into the scan chain circuit 630, may be performed (for example, indicated by CAPTURE), wherein the observation value SO is generated based on the test pattern SI loaded onto the scan chain circuit 630. Here, the scan enable signal SE applied to the integrated circuit 600 may have a logic "low" level.Subsequently, while the scan enable signal SE applied to the integrated circuit 600 again has a logic "high" level, the shift-out operation may be performed, which sequentially outputs the observation value SO stored in the scan chain circuit 630 via a scan test output terminal SOP of the integrated circuit 600 (e.g., indicated by SHIFT-OUT). In some exemplary embodiments, a plurality of test patterns SI may be used for the scan test. In this case, the shift-out operation, which outputs the observation value SO generated based on a test pattern SI, may be performed simultaneously with the shift-in operation, which supplies a next test pattern SI.

[0055] Fig. 20 is a block diagram illustrating a test system for an integrated circuit according to some example embodiments.

[0056] Referring to Fig. 20, the integrated circuit test system 1000 may include a test controller 1020, first to k-th integrated circuits 1040-1 to 1040-k, a memory device 1060, a test data generator 1070, and a test result generator 1080, where k is an integer greater than or equal to 1. Here, each of the first to k-th integrated circuits 1040-1 to 1040-k may include a combinational logic circuit and a scan chain circuit.

[0057] The test controller 1020 may control a scan test for each of the first to k-th integrated circuits 1040-1 to 1040-k by controlling the first to k-th integrated circuits 1040-1 to 1040-k, the memory device 1060, the test data generator 1070, and the test result generator 1080. The integrated circuit test system 1000 may perform the scan test for each of the first to k-th integrated circuits 1040-1 to 1040-k by performing a shift-in operation that sequentially loads a test pattern onto the scan chain circuit, by performing a capture operation that stores an observation value of the combinational logic circuit in the scan chain circuit, the observation value being generated based on the test pattern loaded onto the scan chain circuit, and by performing a shift-out operation that sequentially outputs the observation value stored in the scan chain circuit.Here, the scan chain circuit included in each of the first to k-th integrated circuits 1040-1 to 1040-k may include a plurality of flip-flops, and the flip-flops may form a scan path by being connected to the combinational logic circuit. In some example embodiments, each of the first to k-th integrated circuits 1040-1 to 1040-k may be implemented as a single-chip system. Here, the flip-flops of the scan chain circuit included in each of the first to k-th integrated circuits 1040-1 to 1040-k may be triggered on rising edges of the clock signal. For example, each of the flip-flops may be the flip-flop 100 of FIG. Fig. 1A and Fig. 1B, the flip-flop 200 of the Fig. 4, the flip-flop 300 of the Fig. 8, the flip-flop 400 of the Fig. 12 or flip-flop 500 of the Fig. 16. Since operations and structures of the flip-flops are described above, duplicate description will not be repeated.

[0058] In the integrated circuit test system 1000, the storage device 1600 may store data for the scan test. Specifically, the storage device 1060 may store the test pattern generated by the test data generator 1070 and applied to the scan chain circuit included in each of the first to k-th integrated circuits 1040-1 to 1040-k, the observation value of the combinational logic circuit generated based on the test pattern, a reference pattern compared with the observation value, a test result (e.g., a comparison result between the observation value and the reference pattern) output by the test result generator 1080, etc.For example, the memory device 1060 may include a volatile semiconductor memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc., and / or a non-volatile semiconductor memory device such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nanofloating gate memory (NFGN) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.In some example embodiments, the integrated circuit test system 1000 may further include a storage device such as a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc.

[0059] The test data generator 1070 may generate the test pattern applied to the scan chain circuit included in each of the first to k-th integrated circuits 1040-1 to 1040-k. The test result generator 1080 may generate the test result by comparing the observation value output from each of the first to k-th integrated circuits 1040-1 to 1040-k with the reference pattern. As described above, the observation value may be generated by performing the shift-in operation, which sequentially loads the test pattern onto the scan chain circuit, by performing the capture operation, which stores the observation value of the combinational logic circuit in the scan chain circuit, and by performing the shift-out operation, which sequentially outputs the observation value stored in the scan chain circuit.For example, if the observation value is consistent with the reference pattern, the test result generator 1080 may output the test result indicating that no defect exists in the combinational logic circuit. On the other hand, if the observation value is inconsistent with the reference pattern, the test result generator 1080 may output the test result indicating that a defect exists in the combinational logic circuit. In some example embodiments, in order to obtain a more accurate test result, the integrated circuit test system 1000 may perform the scan test for each of the first to k-th integrated circuits 1040-1 to 1040-k multiple times. Although a flip-flop, a scan chain circuit, and an integrated circuit test system according to some example embodiments are described with reference to FIG. Fig.1 to 20, the flip-flop, scan chain, and integrated circuit test system are not limited thereto. Accordingly, many modifications of the flip-flop, scan chain, and integrated circuit test system are possible without materially departing from the novel teachings and advantages described herein.

[0060] Some example embodiments may be applied to a flip-flop, a scan chain, and an integrated circuit (e.g., a system-on-chip, etc.) including the flip-flop and the scan chain. For example, some example embodiments may be applied to various integrated circuits included in a computer, a workstation, a laptop, a game console, a mobile phone, a smartphone, a smart pad, a smart watch, a tablet PC, etc.

Claims

[1] Flip-flop (100; 200; 300; 400; 500) which has the following: a first node loading circuit (120) configured to load a first node (N1) with inverted input data (DN); a second node charging circuit (140) configured to charge a second node (N2) with input data (D); a first n-channel metal oxide semiconductor, NMOS, transistor (NT1) having a first terminal connected to the first node (N1), a second terminal and a gate terminal; a second NMOS transistor (NT2) having a first terminal connected to the second terminal of the first NMOS transistor (NT1), a second terminal connected to a low voltage (GND), and a gate terminal; a third NMOS transistor (NT3) having a first terminal connected to the first node (N1), a second terminal and a gate terminal connected to the second node (N2); a fourth NMOS transistor (NT4) having a first terminal connected to the second node (N2), a second terminal and a gate terminal; a fifth NMOS transistor (NT5) having a first terminal connected to the second terminal of the fourth NMOS transistor (NT4), a second terminal connected to the low voltage (GND), and a gate terminal; a sixth NMOS transistor (NT6) having a first terminal connected to the second node (N2), a second terminal and a gate terminal connected to the first node (N1); a seventh NMOS transistor (NT7) having a first terminal connected to the second terminal of the third NMOS transistor (NT3), a second terminal connected to a sixth node (N6), and a gate terminal configured to receive a clock signal (CK); and an eighth NMOS transistor (NT8) having a first terminal connected to the second terminal of the sixth NMOS transistor (NT6), a second terminal connected to a fifth node (N5), and a gate terminal configured to receive the clock signal (CK), wherein the flip-flop (100; 200; 300; 400; 500) is configured to latch the input data (D) on rising edges of the clock signal (CK) and to output the latched input data (D) as output data (Q), and wherein the gate terminal of the first NMOS transistor (NT1) is connected to the second node (N2), and the gate terminal of the second NMOS transistor (NT2) is configured to receive the input data (D), or the gate terminal of the first NMOS transistor (NT1) is configured to receive the input data (D), and the gate terminal of the second NMOS transistor (NT2) is connected to the second node, and / or where the gate terminal of the fourth NMOS transistor (NT4) is connected to the first node (N1), and the gate terminal of the fifth NMOS transistor (NT5) is configured to receive the inverted input data (DN), or the gate terminal of the fourth NMOS transistor (NT4) is configured to receive the inverted input data (DN), and the gate terminal of the fifth NMOS transistor (NT5) is connected to the first node. [2] Flip-flop (100; 200; 300) according to claim 1, wherein the first node charging circuit (120) comprises: a first p-channel metal oxide semiconductor, PMOS, transistor (PT1) having a first terminal connected to a high voltage (VDD), a second terminal connected to a third node (N3), and a gate terminal configured to receive the clock signal (CK); a third PMOS transistor (PT3) having a first terminal connected to the third node (N3), a second terminal connected to the first node (N1), and a gate terminal configured to receive the input data (D); and a ninth PMOS transistor (PT9) having a first terminal connected to the third node (N3), a second terminal connected to the sixth node (N6), and a gate terminal connected to the fifth node (N5). [3] The flip-flop (100; 200; 300) of claim 2, wherein the first node charging circuit (120) further comprises: a second PMOS transistor (PT2) having a first terminal connected to the high voltage (VDD), a second terminal connected to the third node (N3), and a gate terminal connected to the second node (N2); a fourth PMOS transistor (PT4) having a first terminal connected to the high voltage (VDD), a second terminal connected to the first node (N1), and a gate terminal connected to the second node (N2); and a ninth NMOS transistor (NT9) having a first terminal connected to the sixth node (N6), a second terminal connected to the low voltage (GND), and a gate terminal connected to the fifth node (N5). [4] Flip-flop (100; 200; 300; 400) according to claim 1, wherein the second node charging circuit (140) comprises: a fifth PMOS transistor (PT5) having a first terminal connected to a high voltage (VDD), a second terminal connected to a fourth node (N4), and a gate terminal configured to receive the clock signal (CK); a seventh PMOS transistor (PT7) having a first terminal connected to the fourth node (N4), a second terminal connected to the second node (N2), and a gate terminal configured to receive the inverted input data (DN); and a tenth PMOS transistor (PT10) having a first terminal connected to the fourth node (N4), a second terminal connected to the fifth node (N5), and a gate terminal connected to the sixth node (N6). [5] The flip-flop (100; 200; 300; 400) of claim 4, wherein the second node charging circuit (140) further comprises: a sixth PMOS transistor (PT6) having a first terminal connected to the high voltage (VDD), a second terminal connected to the fourth node (N4) and a gate terminal connected to the first node (N1); an eighth PMOS transistor (PT8) having a first terminal connected to the high voltage (VDD), a second terminal connected to the second node (N2), and a gate terminal connected to the first node (N1); and a tenth NMOS transistor (NT10) having a first terminal connected to the fifth node (N5), a second terminal connected to the low voltage (GND), and a gate terminal connected to the sixth node (N6). [6] Flip-flop (100; 200; 300; 400; 500), which has the following: a first node loading circuit (120) configured to load a first node (N1) with inverted input data (DN); a second node charging circuit (140) configured to charge a second node (N2) with input data (D); a first n-channel metal oxide semiconductor, NMOS, transistor (NT1) having a first terminal connected to the first node (N1), a second terminal and a gate terminal; a second NMOS transistor (NT2) having a first terminal connected to the second terminal of the first NMOS transistor (NT1), a second terminal connected to a low voltage (GND), and a gate terminal; a third NMOS transistor (NT3) having a first terminal connected to the first node (N1), a second terminal and a gate terminal connected to the second node (N2); a fourth NMOS transistor (NT4) having a first terminal connected to the second node (N2), a second terminal and a gate terminal; a fifth NMOS transistor (NT5) having a first terminal connected to the second terminal of the fourth NMOS transistor (NT4), a second terminal connected to the low voltage (GND), and a gate terminal; a sixth NMOS transistor (NT6) having a first terminal connected to the second node (N2), a second terminal and a gate terminal connected to the first node (N1); a seventh NMOS transistor (NT7) having a first terminal connected to the second terminal of the third NMOS transistor (NT3), a second terminal connected to a sixth node (N6), and a gate terminal configured to receive a clock signal (CK); and an eighth NMOS transistor (NT8) having a first terminal connected to the second terminal of the sixth NMOS transistor (NT6), a second terminal connected to a fifth node (N5), and a gate terminal configured to receive the clock signal (CK), an inverter circuit (160) connected between the sixth node (N6) and an output node (OUT), wherein the inverter circuit (160) is configured to output the output data (Q) at the output node (OUT), wherein the flip-flop (100; 200; 300; 400; 500) is configured to latch the input data (D) on rising edges of the clock signal (CK) and to output the latched input data (D) as output data (Q). [7] Flip-flop (100; 200; 300; 400; 500) according to claim 6, wherein the inverter circuit (160) comprises: an eleventh PMOS transistor (PT11) having a first terminal connected to a high voltage (VDD), a second terminal connected to the output node (OUT), and a gate terminal connected to the sixth node (N6); and an eleventh NMOS transistor (NT11) having a first terminal connected to the output node (OUT), a second terminal connected to the low voltage (GND), and a gate terminal connected to the sixth node (N6). [8] Flip-flop (100; 200; 300; 400; 500), which has the following: a first OR gate element (OR1) having a first input terminal configured to receive a clock signal (CK), a second input terminal configured to receive input data (D), and an output terminal configured to output an OR operation result between the clock signal (CK) and the input data (D); a first NAND gate element (NAND1) having a first input connected to the output terminal of the first OR gate element (OR1), a second input terminal connected to a second node (N2), and an output terminal connected to a first node (N1), wherein the output terminal of the first NAND gate element (NAND1) is configured to output a NAND operation result between the OR operation result of the first OR gate element (OR1) and a voltage signal of the second node (N2) at the first node (N1); a second OR gate element (OR2) having a first input terminal configured to receive inverted input data (DN), a second input terminal configured to receive the clock signal (CK), and an output terminal configured to output an OR operation result between the inverted input data (DN) and the clock signal (CK); a second NAND gate element (NAND2) having a first input terminal connected to the first node (N1), a second input terminal connected to the output terminal of the second OR gate element (OR2), and an output terminal connected to the second node (N2), wherein the output terminal of the second NAND gate element (NAND2) is configured to output a NAND operation result between a voltage signal of the first node (N1) and the OR operation result of the second OR gate element (OR2) at the second node (N2); a first inverter element (INV1) connected between the second input terminal of the first OR gate element (OR1) and the first input terminal of the second OR gate element (OR2), the first inverter element (INV1) being configured to invert the input data (D) and to output the inverted input data (DN); a third AND gate element (AND3) having a first input terminal connected to the first node (N1), a second input terminal configured to receive the clock signal (CK), and an output terminal configured to output an AND operation result between the clock signal and the voltage signal of the first node (N1); a first NOR gate element (NOR1) having a first input terminal connected to the output terminal of the third AND gate element (AND3), a second input terminal connected to the sixth node (N6), and an output terminal connected to a fifth node (N5), wherein the output terminal of the first NOR gate element (NOR1) is configured to output a NOR operation result between the AND operation result of the third AND gate element (AND3) and a voltage signal of the sixth node (N6) to the fifth node (N5); a fourth AND gate element (AND4) having a first input terminal connected to the second node (N2), a second input terminal configured to receive the clock signal (CK), and an output terminal configured to output an AND operation result between the voltage signal of the second node (N2) and the clock signal (CK); and a second NOR gate element (NOR2) having a first input terminal connected to the fifth node (N5), a second input terminal connected to the output terminal of the fourth AND gate element (AND4), and an output terminal connected to the sixth node (N6), wherein the output terminal of the second NOR gate element (NOR2) is configured to output a NOR operation result between a voltage signal of the fifth node (N5) and the AND operation result of the fourth AND gate element (AND4) at the sixth node (N6), wherein the third AND gate element (AND3) further comprises a third input terminal configured to receive the inverted input data (DN), and the fourth AND gate element (AND4) further comprises a third input terminal configured to receive the input data (D). [9] Flip-flop (100; 200; 300; 400; 500), which has the following: a first OR gate element (OR1) having a first input terminal configured to receive a clock signal (CK), a second input terminal configured to receive input data (D), and an output terminal configured to output an OR operation result between the clock signal (CK) and the input data (D); a first NAND gate element (NAND1) having a first input connected to the output terminal of the first OR gate element (OR1), a second input terminal connected to a second node (N2), and an output terminal connected to a first node (N1), wherein the output terminal of the first NAND gate element (NAND1) is configured to output a NAND operation result between the OR operation result of the first OR gate element (OR1) and a voltage signal of the second node (N2) at the first node (N1); a second OR gate element (OR2) having a first input terminal configured to receive inverted input data (DN), a second input terminal configured to receive the clock signal (CK), and an output terminal configured to output an OR operation result between the inverted input data (DN) and the clock signal (CK); a second NAND gate element (NAND2) having a first input terminal connected to the first node (N1), a second input terminal connected to the output terminal of the second OR gate element (OR2), and an output terminal connected to the second node (N2), wherein the output terminal of the second NAND gate element (NAND2) is configured to output a NAND operation result between a voltage signal of the first node (N1) and the OR operation result of the second OR gate element (OR2) at the second node (N2); a first inverter element (INV1) connected between the second input terminal of the first OR gate element (OR1) and the first input terminal of the second OR gate element (OR2), the first inverter element (INV1) being configured to invert the input data (D) and to output the inverted input data (DN); a third AND gate element (AND3) having a first input terminal connected to the first node (N1), a second input terminal configured to receive the clock signal (CK), and an output terminal configured to output an AND operation result between the clock signal and the voltage signal of the first node (N1); a first NOR gate element (NOR1) having a first input terminal connected to the output terminal of the third AND gate element (AND3), a second input terminal connected to the sixth node (N6), and an output terminal connected to a fifth node (N5), wherein the output terminal of the first NOR gate element (NOR1) is configured to output a NOR operation result between the AND operation result of the third AND gate element (AND3) and a voltage signal of the sixth node (N6) to the fifth node (N5); a fourth AND gate element (AND4) having a first input terminal connected to the second node (N2), a second input terminal configured to receive the clock signal (CK), and an output terminal configured to output an AND operation result between the voltage signal of the second node (N2) and the clock signal (CK); and a second NOR gate element (NOR2) having a first input terminal connected to the fifth node (N5), a second input terminal connected to the output terminal of the fourth AND gate element (AND4), and an output terminal connected to the sixth node (N6), wherein the output terminal of the second NOR gate element (NOR2) is configured to output a NOR operation result between a voltage signal of the fifth node (N5) and the AND operation result of the fourth AND gate element (AND4) at the sixth node (N6), and a second inverter element (INV2) connected between the sixth node (N6) and an output node (OUT), wherein the second inverter element (INV2) is configured to invert the voltage signal of the sixth node (N6) and to output output data (Q) at the output node (OUT). [10] Flip-flop (100; 200; 300; 400; 500) which has the following: a first internal node (N1) configured to be loaded with inverted input data (DN) by a first node loading circuit (120); and a second internal node (N2) configured to be loaded with input data (D) by a second node loading circuit (140), wherein the first internal node (N1) and the second internal node (N2) are cross-connected such that node values of the first and second internal nodes (N1, N2) are determined complementarily, wherein the input data (D) are latched on rising edges of the clock signal (CK) and latched input data (D) are output as output data (Q) at an output node (OUT), and wherein the flip-flop (100; 200; 300; 400; 500) is configured to operate at low power by preventing the first and second internal nodes from being repeatedly charged and discharged in response to the clock signal (CK) while the input data (D) is not changed, and wherein a gate terminal of a first NMOS transistor (NT1) is connected to the second node (N2), and a gate terminal of a second NMOS transistor (NT2) is configured to receive input data (D), or the gate terminal of the first NMOS transistor (NT1) is configured to receive the input data (D), and the gate terminal of the second NMOS transistor (NT2) is connected to the second node, and / or where a gate terminal of a fourth NMOS transistor (NT4) is connected to the first node (N1), and a gate terminal of a fifth NMOS transistor (NT5) is configured to receive inverted input data (DN), or the gate terminal of the fourth NMOS transistor (NT4) is configured to receive the inverted input data (DN), and the gate terminal of the fifth NMOS transistor (NT5) is connected to the first node. [11] Flip-flop (100; 200; 300; 400; 500) according to claim 10, further comprising: a first inverter element (INV1) configured to invert the input data (D) and to output the inverted input data (DN). [12] The flip-flop (100; 200; 300; 400; 500) of claim 10, wherein the flip-flop (100; 200; 300; 400; 500) is further configured to: reset the output data (Q) to have a logic “low” level in response to receiving a reset signal having a logic “high” level, and setting the output data (Q) to have a logic "high" level in response to receiving a setting signal having a logic "high" level. [13] Flip-flop (100; 200; 300; 400; 500) according to claim 10, further comprising: a plurality of NMOS transistors; and a plurality of PMOS transistors. [14] Flip-flop (100; 200; 300; 400; 500) according to claim 10, further comprising: a plurality of logic elements, the plurality of logic elements comprising one or more of OR gate elements, AND gate elements, NOR gate elements, and NAND gate elements.

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