Optoelectronic semiconductor chip and method for producing an optoelectronic semiconductor chip

Abstract

Optoelectronic semiconductor chip (10) with: - a p-doped region (11), - an active region (12) which is designed to emit electromagnetic radiation during operation of the optoelectronic semiconductor chip (10) and which has a main extension plane, - an n-doped region (13), and - a barrier area (14), wherein - the active region (12) is arranged in a vertical direction (z) between the p-doped region (11) and the n-doped region (13), wherein the vertical direction (z) is perpendicular to the main extension plane of the active region (12), - the active region (12) is based on a III-V semiconductor compound, - the barrier region (14) extends parallel to the active region (12), - the barrier region (14) comprises AlGaIn, and - the barrier region (14) is designed to inhibit the penetration of defects into the active region (12), wherein - a cover layer (19) is arranged on the barrier region (14) and the cover layer (19) has a structured surface (15) which is arranged on the side of the cover layer (19) facing away from the barrier region (14), and - the barrier region (14) acts as a defect diffusion barrier for defects which are lattice defects, vacancies or impurities from a region of the structured surface (15).

Description

An optoelectronic semiconductor chip and a method for producing an optoelectronic semiconductor chip are specified.US 2013 / 0 056 745 A1 describes a buffer layer for a GaN-on-Si LED.US 2013 / 0 032 781 A1 describes an epitaxial substrate and a method for producing an epitaxial substrate.U.S. Pat. No. 5,040,186 A describes an InP-based quantum well laser.One object to be achieved is to specify an optoelectronic semiconductor chip which can be operated efficiently. A further object to be achieved is to specify a method for producing an optoelectronic semiconductor chip which can be operated efficiently.This object is achieved with the subject matter having the features of claim 1 and with the method according to claim 11. Further developments and embodiments are the subject matter of the dependent claims.The optoelectronic semiconductor chip comprises a p-doped region. The p-doped region is doped with at least one p-dopant. The p-doped region may comprise one or more p-doped semiconductor layers.The optoelectronic semiconductor chip may further comprise a semiconductor body which has the p-doped region. The semiconductor body may have a main extension plane. The semiconductor body can be a three-dimensional body which has, for example, the shape of a cuboid or a cylinder. The main plane of extension of the semiconductor body runs parallel to one of the cover surfaces of the cuboid or of the cylinder. The semiconductor body may be formed with a semiconductor material such as a III-V compound semiconductor material. Furthermore, the p-doped region may extend over the entire lateral extent of the semiconductor body. The lateral extent of the semiconductor body is parallel to the main extension plane of the semiconductor body.The optoelectronic semiconductor chip comprises an active region which is designed to emit electromagnetic radiation during operation of the optoelectronic semiconductor chip and which has a main extension plane. The semiconductor body may include the active region. The main extension plane of the active region may run parallel to the main extension plane of the semiconductor body. The semiconductor chip is, for example, a luminescent diode chip such as a light-emitting diode chip or a laser diode chip. The active region can thus be designed to emit light during operation. The active region can have at least one quantum well structure.The optoelectronic semiconductor chip comprises an n-doped region. The n-doped region is doped with at least one n-dopant. The n-doped region may comprise one or more n-doped semiconductor layers. The semiconductor body may comprise the n-doped region. Furthermore, the n-doped region may extend over the entire lateral extent of the semiconductor body.The optoelectronic semiconductor chip comprises a barrier region. The barrier region may extend over the entire lateral extent of the semiconductor body. The semiconductor body may include the barrier region. It is further possible that the barrier region is arranged adjacent to the semiconductor body. For example, the barrier region may be arranged above or below the semiconductor body in a vertical direction which is perpendicular to the main extension plane of the active region. Furthermore, the n-doped region may comprise the barrier region. That is, the barrier region may be disposed in the n-doped region. Alternatively, the p-doped region may comprise the barrier region. That is, the barrier region may be disposed in the p-doped region. The barrier region may be formed with at least one semiconductor material.The semiconductor body, which may include the p-doped region, the active region, the n-doped region and the barrier region, may be based on a III-V semiconductor compound.The active region is arranged in a vertical direction between the p-doped region and the n-doped region. In this case, the p-doped region, the active region and the n-doped region may have the same or a similar lateral extent. The optoelectronic semiconductor chip can have a radiation exit side at which the electromagnetic radiation emitted by the active region during operation can exit the optoelectronic semiconductor chip. The radiation exit side can be arranged, for example, on a side of the n-doped region facing away from the active region. It is further possible for the radiation exit side to be arranged on a side of the p-doped region facing away from the active region.The active region is based on a III-V semiconductor compound. This means that the active region may be formed with III-V semiconductor materials or semiconductor compounds. It is also possible for the active region to have III-V semiconductor materials or semiconductor compounds at least in places.The barrier region extends parallel to the active region. This means that the barrier region can have a main extension plane which is parallel to the main extension plane of the active region. The barrier region can have a uniform thickness in the vertical direction, in particular.According to at least one embodiment of the optoelectronic semiconductor chip, the barrier region comprises gallium. The barrier region thus comprises gallium at least in places. The barrier region may have a uniform gallium concentration or distribution. Alternatively, the barrier region may have an irregular gallium concentration or distribution. The barrier region can additionally comprise further materials, for example further semiconductor materials.The amount of gallium in the barrier region may be indicated by the product of the thickness of the barrier region in the vertical direction and the gallium concentration in the barrier region. The thickness of the barrier region in the vertical direction is given by the extension of the barrier region in the vertical direction. The product of the thickness of the barrier region in the vertical direction and the gallium concentration in the barrier region can be, for example, at least 0.5, wherein the thickness of the barrier region is given in μm and the gallium concentration in %. This means that, at a gallium concentration of 20%, for example, in the barrier region 20% of the atoms are gallium. It is further possible that the product of the thickness of the barrier region in the vertical direction and the gallium concentration in the barrier region is at least 1.5.The barrier region is designed to inhibit the penetration of defects into the active region. For this purpose, the barrier region can be arranged between the active region and a further region of the semiconductor chip from which defects can penetrate into adjacent regions. In this case, the barrier region can act as a barrier for the defects from the further region. By arranging the barrier region in the optoelectronic semiconductor chip, the number of defects in the active region can be reduced. This means that, by arranging the barrier region in the optoelectronic semiconductor chip, the number of defects which penetrate into the active region is reduced in comparison with an otherwise structurally identical semiconductor chip without a barrier region.The optoelectronic semiconductor chip comprises a p-doped region, an active region which is designed to emit electromagnetic radiation during operation of the optoelectronic semiconductor chip and which has a main extension plane, an n-doped region, and a barrier region. The active region is arranged in a vertical direction between the p-doped region and the n-doped region, wherein the vertical direction is perpendicular to the main extension plane of the active region and the active region is based on a III-V semiconductor compound. The barrier region extends parallel to the active region, comprises gallium, and is configured to inhibit the penetration of defects into the active region.The optoelectronic semiconductor chip described here is based, inter alia, on the concept that the penetration of defects into the active region can be reduced by arranging the barrier region in the optoelectronic semiconductor chip. Defects can arise in different regions of the optoelectronic semiconductor chip. By way of example, defects can arise on a surface of the optoelectronic semiconductor chip, which is processed or structured. By roughening a surface, for example, defects can be produced in the optoelectronic semiconductor chip. The defects are lattice defects, voids or impurities. The defects can then diffuse at elevated temperature or during operation of the optoelectronic semiconductor chip and penetrate into the active region. Defects in the active region can lead to a reduction in the intensity of the electromagnetic radiation emitted by the active region during operation. The brightness of the electromagnetic radiation emitted by the optoelectronic semiconductor chip during operation can thus be reduced by the penetration of the defects into the active region. In addition, the brightness of the electromagnetic radiation emitted by the optoelectronic semiconductor chip during operation can decrease in the course of operation of the optoelectronic semiconductor chip, for example by the influence of electromagnetic radiation impinging on the optoelectronic semiconductor chip.The barrier region is arranged such that the penetration of defects into the active region is inhibited. It has been found that a barrier region comprising gallium can act as a barrier for the penetration of defects into the active region. Thus, the barrier region may reduce the diffusion of defects into the active region. The barrier region may act as a diffusion barrier. Surprisingly, it has been shown that the effect as a barrier depends on the gallium quantity. That is, the amount of gallium is critical for the barrier effect, and not the thickness in the vertical direction of the barrier region or the gallium concentration in the barrier region.Since fewer defects can penetrate into the active region by arranging the barrier region, the attenuation of the intensity of the electromagnetic radiation emitted by the active region during operation is reduced. Thus, the optoelectronic semiconductor chip can emit electromagnetic radiation with a greater intensity or brightness over an operating duration. That is, light aging can be reduced over a longer period of time. The brightness of the electromagnetic radiation emitted by the optoelectronic semiconductor chip during operation can decrease less strongly over a certain period of time. The optoelectronic semiconductor chip can thus be operated more efficiently.According to at least one embodiment of the optoelectronic semiconductor chip, the optoelectronic semiconductor chip has a structured surface, wherein the barrier region is arranged between the active region and the structured surface in the vertical direction. The structured surface can be a surface on an outer side of the optoelectronic semiconductor chip. For example, the structured surface can be arranged on the radiation exit side of the optoelectronic semiconductor chip. It is further possible for the structured surface to be arranged on a side facing away from the radiation exit side.The structured surface can be structured in the production process of the optoelectronic semiconductor chip. For example, the structured surface may be structured by etching, dry chemical processes, mechanical processes or by plasma treatment. The structured surface may be a roughened surface. Furthermore, the structured surface can have an irregular or regular surface topography. In particular, the structured surface is not a smooth surface. In addition, the structured surface can be a damaged surface. This means that the surface can be damaged during the production process of the optoelectronic semiconductor chip. In this case, for example, the structure or the topography of the surface can be changed. For example, the surface may be damaged by roughening.The barrier region is arranged in the vertical direction between the active region and the structured surface in order to reduce or reduce the penetration of defects into the active region from the region of the structured surface. The barrier region acts as a diffusion barrier for defects. This prevents the brightness of the electromagnetic radiation emitted by the optoelectronic semiconductor chip during operation from being reduced by defects in the active region. Therefore, the optoelectronic semiconductor chip can be operated more efficiently.According to at least one embodiment of the optoelectronic semiconductor chip, the barrier region comprises aluminum at least in places. Thus, the barrier region may be based on a III-V semiconductor compound including gallium and aluminum. In addition, the barrier region may comprise arsenic and / or phosphorus. These materials are particularly suitable for encapsulation layers for optoelectronic semiconductor chips. Thus, the barrier region may be arranged, for example, within an encapsulation layer. The encapsulation layer can protect the optoelectronic semiconductor chip from moisture, for example.The barrier region comprises AlGaIn. In addition, the barrier region may comprise arsenic and / or phosphorus. These materials are particularly suitable for encapsulation layers for optoelectronic semiconductor chips.According to at least one embodiment of the optoelectronic semiconductor chip, the barrier region comprises a layer sequence which comprises pairs of alternating layers, each pair comprising a first layer and a second layer. This means that the layer sequence has alternating first and second layers. In this case, the first layers and the second layers are arranged one above the other in the vertical direction. Each of the first layers and each of the second layers may extend over the entire lateral extent of the barrier region. At least one first layer can directly adjoin a second layer on a first side and directly adjoin a further second layer on a second side which is remote from the first side. In addition, at least one second layer can directly adjoin a first layer on a first side and directly adjoin a further first layer on a second side which is remote from the first side.At least one of the first layer and the second layer includes gallium. The layer sequence can thus act as a barrier for a diffusion of defects into the active region.According to at least one embodiment of the optoelectronic semiconductor chip, the first layer and the second layer of each pair differ in their gallium concentration. For example, all first layers may have a first gallium concentration that is different from a second gallium concentration of the second layers. In addition, the ratio between gallium and aluminum in the first layers may be different from the ratio between gallium and aluminum in the second layers. For example, each of the first layers may have a first ratio between aluminum and gallium different from a second ratio between aluminum and gallium of the second layers. Thus, the first layers differ in their composition from the second layers. It has been shown that a barrier region having a layer sequence in which the first layer and the second layer of each pair differ in their gallium concentration constitutes a particularly effective barrier against the diffusion of defects into the active region.According to at least one embodiment of the optoelectronic semiconductor chip, the first layer and the second layer comprise gallium. In addition, the first layer and the second layer may differ in gallium concentration. Because the barrier region comprises gallium, it acts as a barrier for the diffusion of defects into the active region.According to at least one embodiment of the optoelectronic semiconductor chip, either the first layer or the second layer is nominally free of gallium. In this case, the layers which comprise gallium can each have the same gallium concentration. The fact that a layer is nominally free of gallium may mean that no gallium is deposited for the growth of the respective layer. However, it is possible that gallium diffuses from adjacent layers into this layer. In the layer, which is nominally free of gallium, a gallium profile can be established in the vertical direction, in which the gallium concentration initially decreases, has a local minium and subsequently increases again. Because the barrier region comprises gallium either in the first layer or in the second layer, it acts as a barrier for the diffusion of defects into the active region.According to at least one embodiment of the optoelectronic semiconductor chip, in each case one layer of each pair is compressively stressed and the respective other layer of each pair is tensilly stressed. The layers of each pair can each be compressive or tensile stressed in that they differ in their material composition. The first layers and the second layers may each have a thickness of, for example, at least 1 nm and at most 100 nm. Therefore, the growth of layers of different material compositions may result in one layer of each pair being compressively stressed and the other layer of each pair being tensilly stressed. The fact that the layers are compressiveally or tensilally stressed can be demonstrated, for example, by transmission electron microscopy.It has been found that, for a layer sequence in which in each case one layer of each pair is compressively stressed and the respective other layer of each pair is tensilly stressed, a smaller amount of gallium is required overall in order to achieve improved brightness of the electromagnetic radiation emitted by the optoelectronic semiconductor chip during operation after a specific operating duration than for a layer sequence in which the layers are not stressed. Since, for example, in the AlGaAsP material system, the absorption of the electromagnetic radiation emitted by the active region is increased by a larger amount of gallium in the barrier region, it is advantageous if an improved brightness of the electromagnetic radiation emitted by the optoelectronic semiconductor chip during operation can be achieved after a specific operating duration even with a smaller amount of gallium. The smaller the amount of gallium in the barrier region, the lower the absorption of electromagnetic radiation generated in the active region in the barrier region. Consequently, a small amount of gallium in the barrier region can increase the brightness of the electromagnetic radiation emitted by the optoelectronic semiconductor chip after a specific operating duration.Furthermore, for a barrier region having a layer sequence in which in each case one layer of each pair is compressively strained and the respective other layer of each pair is tensil strained, a smaller amount of gallium overall can be required for improving the brightness than for a barrier region which has no layer sequence.According to at least one embodiment of the optoelectronic semiconductor chip, the first layer and the second layer of each pair differ in their indium concentration. For example, the indium concentration of the first layers may differ by at least 0.2% and at most 10% from the indium concentration of the second layers. Due to the difference in indium concentration between the first layer and the second layer, one layer of each pair can be compressively stressed and the other layer can be tensilly stressed. In addition, the ratio between aluminum and gallium in the first layer may be different from the ratio between aluminum and gallium in the second layer. Thus, the first layer of each pair has a different material composition as a whole than the second layer of each pair. In this case, a bracing of the layers, such that in each case one layer of each pair is compressively braced and the respective other layer of each pair is tensil braced, can be achieved by different material combinations.One layer of each pair may be formed with AlGaInP, for example, and the other layer of each pair may be formed with AlInP, respectively. Furthermore, the layer sequence can have at least two pairs of alternating layers and at most 100 pairs of alternating layers.A method for producing an optoelectronic semiconductor chip is also specified. The optoelectronic semiconductor chip can preferably be produced using a method described here. In other words, all features disclosed for the optoelectronic semiconductor chip are also disclosed for the method for producing an optoelectronic semiconductor chip and vice versa.The method comprises a method step in which a p-doped region is provided. The p-doped region can be grown, for example, on a growth substrate.The method comprises a method step in which an active region is provided which is designed to emit electromagnetic radiation during operation of the optoelectronic semiconductor chip and which has a main extension plane. The active region may be disposed on the p-doped region.The method comprises a method step in which an n-doped region is provided. The n-doped region may be grown on the active region. It is further possible that the n-doped region is grown on a growth substrate, that the active region is arranged on the n-doped region and that the p-doped region is arranged on the active region. The optoelectronic semiconductor chip may be free of a growth substrate.The method comprises a method step in which gallium is deposited in a barrier region. This means, for example, that the product of the thickness of the barrier region in the vertical direction and the gallium concentration in the barrier region is, for example, at least 0.5, wherein the thickness of the barrier region is given in μm. In this case, the barrier region can additionally comprise further materials. These may be deposited simultaneously with the gallium.According to at least one embodiment of the method, the method comprises a method step in which a surface of the optoelectronic semiconductor chip is structured. The surface can be etched, for example. It is further possible that the surface is treated with a plasma. If the surface is arranged on a radiation exit side of the optoelectronic semiconductor chip, structuring of the surface can increase the coupling-out efficiency of the electromagnetic radiation emitted by the active region during operation.The structuring of the surface can damage it. This means that, for example, the surface structure of the surface after the structuring is different from the surface structure before the structuring. Damage to the surface can result in defects in the area of the surface.The active region is arranged in a vertical direction between the p-doped region and the n-doped region, wherein the vertical direction is perpendicular to the main extension plane of the active region.The barrier region extends parallel to the active region. The barrier region may completely cover the active region.According to at least one embodiment of the method, the barrier region is arranged in the vertical direction between the active region and the surface which is patterned. Thus, the barrier region can inhibit the penetration of defects into the active region from the surface being patterned.The optoelectronic semiconductor chip described here and the method described here for producing an optoelectronic semiconductor chip are explained in more detail below in conjunction with exemplary embodiments and the associated figures. FIG. 1 shows a schematic cross section through an optoelectronic semiconductor chip according to an exemplary embodiment. FIG. 2 shows a schematic cross section through an optoelectronic semiconductor chip according to a further exemplary embodiment.FIG. 3 plots the intensity of emitted radiation from various optoelectronic semiconductor chips.Identical, similar or identically acting elements are provided with the same reference numerals in the figures. The figures and the proportions of the elements shown in the figures with respect to one another are not to be considered as true to scale. Rather, individual elements may be represented with exaggerated size for better clarity and / or for better understanding.FIG. 1 shows a schematic cross section through an exemplary embodiment of an optoelectronic semiconductor chip 10. The optoelectronic semiconductor chip 10 has a p-doped region 11. An active region 12 is arranged on the p-doped region 11, which is designed to emit electromagnetic radiation during operation of the optoelectronic semiconductor chip 10. The active region 12 is based on a III-V semiconductor compound and can have a quantum well structure. In addition, the active region 12 has a main extension plane. An n-doped region 13 is arranged on the active region 12. Thus, the active region 12 is arranged in a vertical direction z between the p-doped region 11 and the n-doped region 13, wherein the vertical direction z is perpendicular to the main extension plane of the active region 12.A barrier region 14 is arranged on the n-doped region 13. The barrier region 14 extends parallel to the active region 12, which means, for example, that a main extension plane of the barrier region 14 is parallel to the main extension plane of the active region 12. Furthermore, the barrier region 14 comprises gallium and is designed to inhibit the penetration of defects into the active region 12.A cover layer 19 is arranged on the barrier region 14. The cover layer 19 can be the uppermost layer of the optoelectronic semiconductor chip 10. For example, the electromagnetic radiation emitted by the active region 12 during operation can emerge from the optoelectronic semiconductor chip 10 through the cover layer 19. In this case, a radiation exit side 20 of the optoelectronic semiconductor chip 10 is arranged on a side of the cover layer 19 facing away from the barrier region 14.The cover layer 19 has a structured surface 15 which is arranged on the side of the cover layer 19 facing away from the barrier region 14. The patterned surface 15 may be patterned to have a surface topography or to have a rough surface. The structured surface 15 can be structured during the production process of the optoelectronic semiconductor chip 10, for example by etching or by plasma treatment. Defects can thereby be produced in the cover layer 19 and on the surface 15. The barrier region 14 is designed to inhibit the penetration of the defects into the active region 12 and the barrier region 14 is arranged between the active region 12 and the surface 15 in the vertical direction z. Since defects in the active region 12 can reduce the brightness of the electromagnetic radiation emitted by the optoelectronic semiconductor chip 10 during operation after a certain operating time, a reduction in the brightness of the electromagnetic radiation emitted by the optoelectronic semiconductor chip 10 during operation is advantageously prevented or reduced by arranging the barrier region 14 between the surface 15 and the active region 12.FIG. 2 shows a schematic cross section through a further exemplary embodiment of an optoelectronic semiconductor chip 10. The structure in FIG. 2 differs from the exemplary embodiment shown in FIG. 1 merely in the structure of the barrier region 14. The layer sequence 16 comprises pairs of alternating layers, each pair comprising a first layer 17 and a second layer 18. The first layer 17 and the second layer 18 of each pair may differ in their material composition. In this case, each of the layers in the layer sequence 16 can comprise gallium or in each case one of the first layers 17 and the second layers 18 can comprise gallium.FIG. 3 plots the intensity of emitted radiation from various optoelectronic semiconductor chips. The product of the layer thickness of the barrier region 14 in μm and the gallium fraction in the barrier region 14 in % is applied on the x-axis. The x-axis thus relates to the amount of gallium in the barrier region 14. The y-axis plots the intensity of the electromagnetic radiation emitted by the optoelectronic semiconductor chip 10 during operation after an operating period of 170 hours as a percentage of the intensity of the electromagnetic radiation emitted by the optoelectronic semiconductor chip 10 during operation before the 170 hours operating period, i.e. at 0 hours operating period. This means that the ratio between the intensity of the electromagnetic radiation emitted by the optoelectronic semiconductor chip 10 during operation after an operating period of 170 hours and the intensity during an initial operation at an operating period of 0 hours is plotted on the y-axis. The ratio of the intensities is plotted for various exemplary embodiments of the optoelectronic semiconductor chip 10. During the 170 hour operating period, the optoelectronic semiconductor chips 10 are also exposed to external electromagnetic radiation which impinges on the optoelectronic semiconductor chip 10.The embodiments A and B in FIG. 3 correspond to the embodiment shown in FIG. 1. In this case, the barrier region 14 includes AlGaIn. Embodiments A and B have substantially the same construction and composition. At a value of less than 2 on the x-axis, the intensity of the electromagnetic radiation emitted by the optoelectronic semiconductor chip 10 is greatly reduced compared to the initial intensity after the operating duration of 170 hours. With an increasing value on the x-axis, the intensity is less reduced after 170 hours than compared to a smaller amount of gallium in the barrier region 14. With a value of approximately 7 on the x-axis, the intensity of the electromagnetic radiation emitted by the optoelectronic semiconductor chip 10 is between 90 and 99% of the initial intensity after an operating duration of 170 hours.Embodiment C corresponds to the embodiment shown in FIG. 2, wherein the first layer 17 of each pair comprises AlInP and the second layer 18 of each pair comprises AlGaInP. The first layers 17 and the second layers 18 are hardly stressed or are not stressed at all in this exemplary embodiment. The intensity of the electromagnetic radiation emitted by the optoelectronic semiconductor chip 10 according to exemplary embodiment C after an operating time of 170 hours is similar to that in exemplary embodiments A and B.Example D in FIG. 3 corresponds to the structure shown in FIG. 2, but barrier region 14 does not include gallium. In each case one layer of each pair of the layer sequence 16 is compressively stressed and the respective other layer of each pair is tensilly stressed. In this case, too, the intensity of the emitted electromagnetic radiation is greatly reduced after an operating period of 170 hours compared with an initial intensity.The embodiment E corresponds to the embodiment shown in FIG. 2, wherein the first layer 17 comprises AlInP and the second layer 18 comprises AlGaInP. In addition, in each case one layer of each pair of the layer sequence 16 is compressively stressed and the respective other layer of each pair is tensilly stressed. Even at a value of approximately 1.5 on the x-axis, the intensity of the electromagnetic radiation emitted by the optoelectronic semiconductor chip 10 amounts to approximately 95% of the initial intensity after an operating duration of 170 hours. Thus, in this embodiment, a much smaller amount of gallium is needed than for embodiments A and B to achieve a similar percent intensity. However, compared with Embodiment E, Embodiments A and B are easier to manufacture.List of reference characters10 Optoelectronic semiconductor chip 11 P-doped region 12 Active region 13 N-doped region 14 Barrier region 15 Surface 16 Layer sequence 17 First layer 18 Second layer 19 Cover layer 20 Radiation exit side z Vertical direction

Claims

Optoelectronic semiconductor chip (10) having: - a p-doped region (11), - an active region (12) which is designed to emit electromagnetic radiation during operation of the optoelectronic semiconductor chip (10) and which has a main extension plane, - an n-doped region (13), and - a barrier region (14), wherein - the active region (12) is arranged in a vertical direction (z) between the p-doped region (11) and the n-doped region (13), wherein the vertical direction (z) is perpendicular to the main extension plane of the active region (12), - the active region (12) is based on a III-V semiconductor compound, - the barrier region (14) extends parallel to the active region (12), - the barrier region (14) has AlGaIn, and - the barrier region (14) is designed to inhibit the penetration of defects into the active region (12), wherein - a cover layer (19) is arranged on the barrier region (14) and the cover layer (19) has a structured surface (15) which is arranged on the side of the cover layer (19) facing away from the barrier region (14), and - the barrier region (14) acts as a defect diffusion barrier for defects which are lattice defects, vacancies or impurities from a region of the structured surface (15).Optoelectronic semiconductor chip (10) according to Claim 1, in which the barrier region (14) is arranged between the active region (12) and the structured surface (15) in the vertical direction (z).Optoelectronic semiconductor chip (10) according to one of the preceding claims, in which the barrier region (14) comprises arsenic and / or phosphorus.Optoelectronic semiconductor chip (10) according to one of the preceding claims, in which the barrier region (14) has a layer sequence (16) which has pairs of alternating layers, each pair having a first layer (17) and a second layer (18).Optoelectronic semiconductor chip (10) according to claim 4, wherein the first layer (17) and the second layer (18) of each pair differ in their gallium concentration.Optoelectronic semiconductor chip (10) according to either of Claims 4 and 5, in which the first layer (17) and the second layer (18) comprise gallium.Optoelectronic semiconductor chip (10) according to either of Claims 4 and 5, in which either the first layer (17) or the second layer (18) is nominally free of gallium.Optoelectronic semiconductor chip (10) according to one of Claims 4 to 7, in which at least one layer of each pair is stressed either compressiveally or tensilly.Optoelectronic semiconductor chip (10) according to one of Claims 4 to 8, in which in each case one layer of each pair is compressively stressed and the respective other layer of each pair is tensilly stressed.Optoelectronic semiconductor chip (10) according to one of Claims 4 to 9, in which the first layer (17) and the second layer (18) of each pair differ in their indium concentration.Method for producing an optoelectronic semiconductor chip (10), comprising the steps of: - providing a p-doped region (11), - providing an active region (12) which is designed to emit electromagnetic radiation during operation of the optoelectronic semiconductor chip (10) and which has a main extension plane, - providing an n-doped region (13), - depositing gallium in a barrier region (14), and - structuring a surface (15) of the optoelectronic semiconductor chip (10), wherein - the active region (12) is arranged in a vertical direction (z) between the p-doped region (11) and the n-doped region (13), wherein the vertical direction (z) is perpendicular to the main extension plane of the active region (12), and - the barrier region (14) extends parallel to the active region (12), wherein - the barrier region (14) comprises AlGaIn, - a cover layer (19) is arranged on the barrier region (14) and the cover layer (19) comprises a structured surface (15) which is arranged on the side of the cover layer (19) facing away from the barrier region (14), and - the barrier region (14) acts as a defect diffusion barrier for defects which are lattice defects, vacancies or impurities from a region of the structured surface (15).Method according to claim 11, wherein the barrier region (14) is arranged in the vertical direction (z) between the active region (12) and the structured surface (15).Method according to claim 11 or 12, wherein the barrier region (14) comprises arsenic and / or phosphorus.

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