LOADING OPTIMIZATION OF CRITICAL DIMENSIONS OF FINS

Abstract

Integrated circuit device comprising: a substrate (16); a logic region (12) comprising a first fin structure (20A; 220B) with two fins (22A; 222B) and a third fin structure (20B; 220C) with one or two fins (22B; 222C), wherein the first fin structure (20A; 220B) and the third fin structure (20B; 220C) are included in a first FinFET; an input / output region (14) comprising a second fin structure (20C; 220A) having three or more fins (22C; 222A); wherein the fins (22A, 222B) of the first fin structure (20A; 220B) have a first width (w1), the fins (22B; 222C) of the third fin structure (20B; 220C) have a third width (w3), and the fins (22C; 222A) of the second fin structure (20C; 220A) have a second width (w2), the first width (w1) and the third width (w3) being greater than the second width (w2); wherein the first fin structure (20A; 220B), the second fin structure (20C; 220A) and the third fin structure (20B; 220C) are arranged above the substrate (16); wherein the first fin structure (20A; 220B) has a first center-to-center distance between adjacent fins, the first center-to-center distance between adjacent fins being a sum of a right center-to-center distance (P R ) a first fin of the first fin structure (20A; 220B) and a left center distance (P L ) of the first fin, with the right center distance (P R ) of the first fin defines a distance between a center of the first fin and a center of an adjacent fin which is arranged to the right of the first fin and which is a fin of the third fin structure (20B; 220C), and the left center distance (P L) the first fin defines a distance between the center of the first fin and a center of an adjacent fin which is arranged to the left of the first fin and which is a fin of the first fin structure (20A; 220B); where the left center distance (P L ) of the first fin is substantially equal to a minimum fin center-to-center distance; wherein the first center-to-center distance of adjacent fins is greater than or equal to three times the minimum fin center-to-center distance; and wherein the second fin structure (20C; 220A) has a second center-to-center distance between adjacent fins, the second center-to-center distance between adjacent fins being a sum of a right center-to-center distance (P R ) an intra-fin of the second fin structure (20C; 220A) and a left center distance (P L ) the intra-fin; and wherein the second center-to-center spacing of adjacent fins is substantially equal to twice the minimum fin center-to-center spacing.

Description

BACKGROUND

[0001] The IC industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. As ICs have evolved, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This downsizing process generally provides benefits by increasing production efficiency and reducing associated costs.

[0002] Such downsizing has also increased the complexity of IC processing and manufacturing, and for these advances to be realized, similar developments in IC processing and manufacturing are required. For example, as fin-type field-effect transistor (FinFET) technologies progress toward smaller feature sizes, FinFET manufacturing processes are significantly limited by narrowing process windows. In particular, when multiple fin densities are present, decreasing fin pitches and increasing fin heights prevent conventional etching processes from completely or sufficiently removing the material between the fins. Consequently, not all of the advantages of FinFET devices can be realized.

[0003] US 2017 / 0 148 681 A1 discloses a semiconductor device comprising a first plurality of fin structures having a first width in a first region of a substrate and a second plurality of fin structures having a second width in a second region of the substrate, wherein the second width is smaller than the first width. A first gate structure is formed on the first plurality of fin structures. A second gate structure is formed on the second plurality of fin structures. US 2013 / 0 221491 A1 discloses a semiconductor device comprising fin field-effect transistors (FinFETs) with controlled fin heights. The device comprises a high fin density region and a low fin density region. Each fin density region comprises fins and dielectric material between the fins. The dielectric material contains different dopant concentrations for different fin density ranges.US 020160293600 A1 describes a semiconductor device with four fins in a first region and single fins in other regions. US 2013 / 0 037 871 A1, US 9 691 664 B1, and US 020170213767 A1 disclose further conventional FinFET structures. Zhang, Xiaoxiao et al.: Addressing FinFET metrology challenges in 1x node using tiltbeam critical dimension scanning electron microscope. In: J. Micro / Nanolith., MEMS, MOEMS, Vol. 13, 2014, No. 4, pp. 041407-1 to 6 describes loading effects in the fabrication of semiconductor structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The invention relates to an integrated circuit device according to claim 1 and a method as specified in claim 9.

[0005] The present disclosure is best understood from the following detailed description when read with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, various elements are not drawn to scale and are for descriptive purposes only. Indeed, the dimensions of the various features may be exaggerated or reduced at will for clarity of description. The Fig. 1A-1C, 2A-2C, 3A-3C, 4A-4E, 5A-5E and 6A-6E are partial schematic views of an integrated circuit device, in part or in whole, at various stages of manufacture according to various aspects of the present disclosure. Fig. 7 is a flowchart of a method of manufacturing an integrated circuit device according to various aspects of the present disclosure. Fig. 8 is a fragmentary cross-sectional view of an integrated circuit device, in part or in whole, according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0006] The present disclosure relates generally to integrated circuit devices and, more particularly, to fin-type field effect transistor (FinFET) devices.

[0007] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first element over or on top of a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first element and the second element such that the first and second elements need not be in direct contact.

[0008] Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, impose any relationship between the various described embodiments and / or configurations. Moreover, the formation of a feature on, connected to, and / or coupled to another feature in the present disclosure may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed to be disposed between the features such that the features need not be in direct contact.Furthermore, spatially relative terms of the relationship of one feature to another feature, such as "bottom," "top," "horizontal," "vertical," "above," "over," "below," "beneath," "under," "up," "down," "upper," "lower," etc., as well as derivatives thereof (e.g., "horizontal," "downward," "upward," etc.), are used to simplify the present disclosure. The spatially relative terms are intended to cover various orientations of the device, including the features.

[0009] The Fig. 1A-1C, Fig. 2A-2C, 3A-3C, 4A-4E, 5A-5E, and 6A-6E are fragmentary schematic views of an integrated circuit device 10, in part or in whole, at various stages of fabrication according to various aspects of the present disclosure. The integrated circuit device 10 includes various device regions, such as a core region (often referred to as a logic region), a memory region (such as a static random access memory (SRAM) region), an analog region, a peripheral region (often referred to as an input / output (I / O) region), a dummy region, another suitable region, or combinations thereof.In the illustrated embodiment, the integrated circuit device 10 includes a core region 12 and an I / O region 14, both of which may include various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. As described herein, the core region 12 and the I / O region 14 each include one or more fin-type field-effect transistors (FinFETs). The integrated circuit device 10 may be incorporated into a microprocessor, memory, and / or other integrated circuit device.In some implementations, the integrated circuit device 10 may be part of an IC chip, a system-on-chip (SoC), or a portion thereof. Fig. 1A-1C, Fig. 2A-2C, 3A-3C, 4A-4E, 5A-5E, and 6A-6E have been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional features may be added to the integrated circuit device 10, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the integrated circuit device 10.

[0010] Referring to the Fig. 1A-1C is Fig. 1A is a plan view of the integrated circuit device 10, Fig. 1B is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 1B-1B of Fig. 1 and Fig. 1C is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 1C-1C of Fig. 1A. The core region 12 and the I / O region 14 each comprise at least one fin structure disposed over a substrate (wafer) 16. In the embodiment shown, the substrate 16 comprises silicon. Alternatively or additionally, the substrate 16 comprises another elemental semiconductor such as germanium; a compound semiconductor such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as silicon germanium (SiGe), SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Alternatively, the substrate 16 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.Semiconductor-on-insulator substrates may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable techniques. In some implementations, substrate 16 comprises one or more Group III-V materials. In some implementations, substrate 16 comprises one or more Group II-IV materials. Substrate 16 includes various doped regions (not shown) depending on the design requirements of core region 12 and I / O region 14. For example, core region 12 is an n-type device region, a p-type device region, or a combination thereof, and I / O region 14 is an n-type device region, a p-type device region, or a combination thereof. In some implementations, substrate 16 includes p-doped regions (e.g., p-wells) doped with p-type dopants such as boron, indium, another p-type dopant, or combinations thereof.In some implementations, the substrate 16 includes n-doped regions (e.g., n-wells) doped with n-type dopants such as phosphorus, arsenic, another n-type dopant, or combinations thereof. In some implementations, the substrate 16 includes doped regions formed with a combination of p-type dopants and n-type dopants. The various doped regions may be formed directly on and / or within the substrate 16, for example, by providing a p-well structure, an n-well structure, a dual-well structure, a raised structure, or combinations thereof.

[0011] The core region 12 includes at least one fin structure with two fins or fewer, and the I / O region 14 includes at least one fin structure with three fins or more. For example, the core region 12 includes a fin structure 20A (with two fins 22A) and a fin structure 20B (with two fins 22B), and the I / O region 14 includes a fin structure 20C (with six fins 22C). Although the fin structures 20A-20C are multiple fin structures in the illustrated embodiment, the present disclosure contemplates embodiments where the fin structure 20A and / or the fin structure 20B include only one fin. According to a non-claimed embodiment, the fin structures 20A-20C belong to a first FinFET device, a second FinFET device, and a third FinFET device, respectively, of the integrated circuit device 10. According to the invention, the fin structure 20A and the fin structure 20B belong to a first FinFET device.In some embodiments, fin structure 20C is associated with a second FinFET device. In some implementations, fins 22A-22C are a part of substrate 16 (such as a part of a material layer of substrate 16). For example, if substrate 16 comprises silicon, fins 22A-22C comprise silicon. Alternatively, in some implementations, fins 22A-22C are defined in a material layer, such as one or more semiconductor material layers, overlying substrate 16. For example, fins 22A-22C may comprise a semiconductor layer stack having various semiconductor layers (such as a heterostructure) disposed over substrate 16. The semiconductor layers may comprise any suitable semiconductor materials, such as silicon, germanium, silicon-germanium, other suitable semiconductor materials, or combinations thereof.The semiconductor layers may include the same or different materials, etch rates, atomic fractions of the components, weight fractions of the components, thicknesses (heights), and / or configurations, depending on the design requirements of the integrated circuit device 10. In some implementations, the semiconductor layer stack includes alternating semiconductor layers, such as semiconductor layers made of a first material and semiconductor layers made of a second material. For example, the semiconductor layer stack alternates silicon layers and silicon-germanium layers (e.g., SiGe / Si / SiGe / Si / SiGe / Si from bottom to top). In some implementations, the semiconductor layer stack includes semiconductor layers made of the same material but with alternating atomic fractions, such as semiconductor layers having a component of a first atomic fraction and semiconductor layers having a component of a second atomic fraction.For example, the semiconductor layer stack comprises silicon-germanium layers with alternating silicon and / or germanium atomic fractions (for example, Si. a Ge b / Si c Ge d / Si a Ge b / Si c Ge d / Si a Ge b / Si c Ge d from bottom to top, where a and c are different atomic fractions of silicon and b and d are different atomic fractions of germanium). In some implementations, fins 22A, fins 22B, and / or fins 22C comprise the same materials and / or the same semiconductor layer stacks, depending on the design requirements of their respective FinFET device. In some implementations, fins 22A, fins 22B, and / or fins 22C comprise different materials and / or different semiconductor layer stacks, depending on the design requirements of their respective FinFET device.

[0012] Fin critical dimension (CD) loading optimization is achieved between the core region 12 and the I / O region 14 for subsequent processing by configuring fin structures of the core region 12 and the I / O region 14 with different critical dimensions. In some implementations, critical dimension generally refers to a dimension, such as a fin width and / or a fin pitch, defined by design requirements to achieve a desired performance of the integrated circuit device 10. In the Fig. 1A-1C, the fins 22A each have a width w 1 , the fins 22B each have a width w 2 and the fins 22C each have a width w 3 , where the fin width is the critical dimension, and the width w 1 , the width w 2 and the width w 3are configured to provide fin CD loading optimization. In some implementations, fin CD loading is defined as a difference between a core fin CD (or core fin width) of core region 12 and an I / O fin CD (or I / O fin width) of I / O region 14. Fin CD loading optimizes the spacing between fins for etching processes used during gate formation when fin CD loading is greater than o (in other words, fin CD loading = core fin CD - I / O fin CD ≥ o). For example, if the core fin CD is greater than the I / O fin CD (in other words, fins 22A and 22B each have a width greater than a width of fins 22C (for example, w 1 > w 3 and w 2 > w 3 )), a distance S 1 (distance) between adjacent fins 22A and / or a distance S 2between adjacent fins 22B smaller than a distance S 3 between adjacent fins 22C (in other words, S 1 < S 3 and S 2 < S 3 ). In some implementations, the width is w 1 about 1 nm to about 30 nm, the width w 2 about 1 nm to about 30 nm and the width w 3 about 1 nm to about 30 nm. In some implementations, the distance S 1 about 10 nm to about 30 nm, the distance S 2 about 10 nm to about 30 nm and the distance S 3 about 10 nm to about 30 nm. In continuation of the embodiment shown, the fins 22A and the fins 22B have substantially the same width (in other words, w 1 ≈ w 2 ) and the fins 22A and the fins 22B have substantially the same distance (in other words, S 1 ≈ S 2 ). In some implementations, the width w 1and / or the distance S 1 the fins 22A of width w 2 and / or the distance S 2 of the fins 22B, depending on the design requirements of core area 12. In the Fig. 1A-1C the fins 22A each have a height h 1 and a length l 1 ; the fins 22B each have a height h 2 and a length l 2 ; and the fins 22C each have a height h 3 and a length l 3 In some implementations, the height h 1 about 30 nm to about 150 nm, the height h 2 about 30 nm to about 150 nm and the height h 3 about 30 nm to about 150 nm. In some implementations, the length l 1 is about 30 nm to about 60 nm, the length l 2 about 30 nm to about 60 nm and the length l 3 about 30 nm to about 60 nm.

[0013] A center distance P 1of the fin structure 20A generally denotes a sum of a width w 1 of the fins 22A and a distance between adjacent fins 22A (as S 1 ) (in other words, P 1 = w 1 + S 1 ). A center distance P 2 of the fin structure 20B generally refers to a sum of a width w 2 of the fins 22B and a distance between adjacent fins 22B (as S 2 ) (in other words, P 2 = w 2 + S 2 ). A center distance P 3 of the fin structure 20C generally refers to a sum of a width w 3 of the fins 22C and a distance between adjacent fins 22C (such as S 3 ) (in other words, P 3 = w 3 + S 3 ). In the embodiment shown, the center distance P defines 1 , the center distance P 2 and the center distance P 3a center-to-center distance between the fins. In some implementations, the center-to-center distance P 1 , the center distance P 2 and the center distance P 3 approximately 10 nm to approximately 80 nm. In some implementations, the center-to-center pitch P 1 about 10 nm to about 600 nm, the center-to-center distance P 2 about 10 nm to about 600 nm and the center-to-center distance P 3 about 10 nm to about 80 nm. In some implementations, the fin structures 20A-20C have approximately the same center-to-center pitches. In some implementations, the fin structures 20A-20C have different center-to-center pitches. In some implementations, the center-to-center pitch P 1 , the center distance P 2 and / or the center distance P 3 equal to a minimum fin center distance (P m). In some implementations, the minimum fin pitch generally refers to a smallest fin pitch achievable by a lithography process and / or a fin fabrication process (e.g., deposition, lithography, and / or etching processes) of a given IC technology node. In some implementations, the minimum fin pitch generally refers to a smallest fin pitch specified by design requirements for the integrated circuit device 10.

[0014] Each of the fins 22A-22C has a pitch of adjacent fins that may be configured to further optimize the spacing between the fins for etching processes used during gate formation in the core region 12 and the I / O region 14. A pitch of adjacent fins is a sum of a right pitch (P R ) of the fin and a left center distance (P L) of the fin. The right center distance P R defines a distance between a center of the fin and a center of an adjacent fin located to the right of the fin, and the left center distance P L defines a distance between the center of the fin and a center of an adjacent (neighboring) fin located to the left of the fin. In some implementations, the fin and the neighboring fin belong to the same fin structure and / or the same FinFET device. In some implementations, the fin and the neighboring fin belong to different fin structures and / or different FinFET devices. The core region 12 has fin structures with a center-to-center pitch of neighboring fins in the core (P Kern-benachbart ) which is greater than or equal to three times the minimum fin center-to-center distance (in other words, P Kern-benachbart ≥ 3P m), and the I / O area 14 has fin structures with a center-to-center distance between adjacent fins in the I / O (P IO-benachbart ) which is less than or equal to twice the minimum fin center-to-center distance (in other words, P IO-benachbart ≤ 2P m ). For example, in the core region 12, the rightmost fin 22A of the fin structure 20A has a left center-to-center distance equal to the minimum fin center-to-center distance (P L = P m ), and a right center distance equal to twice the minimum fin center distance (P R = 2P m ), so that their center-to-center distance of adjacent fins is equal to three times the minimum fin center-to-center distance (in other words, P 20A-benachbart = P m + 2P m = 3P m). In some implementations, the right center-to-center pitch of the rightmost fin 22A is greater than twice the minimum fin center-to-center pitch and / or the left center-to-center pitch of the rightmost fin 22A is less than the minimum fin center-to-center pitch. In contrast, in the I / O region 14, one of the middle fins 22C of the fin structure 20C has a left center-to-center pitch equal to the minimum fin center-to-center pitch (P L = P m ), and a right center distance equal to the minimum fin center distance (P R = P m ), so that their center-to-center distance of adjacent fins is equal to twice the minimum fin center-to-center distance (in other words, P 20C-benachbart = P m + P m = 2P m). In some implementations, the left center pitch and / or the right center pitch of the center fin 22C is smaller than the minimum fin pitch. In the illustrated embodiment, since the fin structure 20A and the fin structure 20B have two fins or fewer, the fins 22A and the fins 22B each have a center pitch of adjacent fins that defines the left center pitch and / or the right center pitch between a fin of a first FinFET device and a fin of a second FinFET device. Continuing the illustrated embodiment, since the fin structure 20C has three or more fins, the center fins 22C each have a center pitch of adjacent fins that defines the left center pitch and the right center pitch between fins of the same FinFET device.

[0015] The present disclosure contemplates variations in the height, width, and / or length of the fins 22A-22C that may result from the processing and manufacturing of the integrated circuit device 10. In the embodiment shown, the fins 22A-22C have tapered widths along their respective heights, with the width w 1 , the width w 2 and the width w 3each represent an average of the varying widths. For example, the widths of fins 22A-22C decrease from the lower portions of fins 22A-22C to the upper portions of fins 22A-22C, such that the average widths of the upper portions are smaller than the average widths of the lower portions of fins 22A-22C. In some implementations, the widths may vary from about 5 nm to about 15 nm along fins 22A-22C, depending on where the widths are measured along the height of fins 22A-22C. In some implementations, the fin width varies depending on a position of a fin relative to other fins and / or relative to other features of integrated circuit device 10. For example, for fin structure 20C, the width w 3 the central fin (in the embodiment shown, the fin structure 20C comprises four central fins 22C) is greater than the width w 3of the peripheral fins 22C (here the leftmost fin 22C and the rightmost fin 22C, which enclose the four middle fins 22C). In another example, the width w 3 the middle fins smaller than the width w 3 of the peripherals. In both such implementations, the width w 3 smaller than the width w 1 and the width w 2 . In continuation of such implementations, the width w 3 of the peripheral grooves represent a mean width of the peripheral grooves and the width w 3 The center fins may represent a mean width of the center fin. Although fins 22A-22C are shown as having a tapered width, in some implementations, fins 22A-22C have substantially the same width along their respective heights.

[0016] The fins 22A-22C are formed over the substrate 16 using any suitable method. In some implementations, a combination of deposition, lithography, and / or etching processes is performed to define the fins 22A-22C extending from the substrate 16, as shown in the Fig. 1A-1C. For example, forming fins 22A-22C includes performing a lithography process to form a patterned resist layer over substrate 16 (or a material layer, such as a heterostructure, disposed over substrate 16) and performing an etching process to transfer a pattern defined in the patterned resist layer to substrate 16 (or the material layer, such as the heterostructure, disposed over substrate 16). The lithography process may include forming a resist layer on substrate 16 (for example, by spin coating), performing a pre-exposure bake process, performing an exposure process using a mask, performing a post-exposure bake process, and performing a development process.During the exposure process, the resist layer is irradiated with radiant energy (such as ultraviolet (UV) light, deep UV light (DUV), or extreme UV light (EUV)), with the mask blocking, transmitting, and / or reflecting radiation onto the resist layer, depending on a mask pattern and / or mask type (for example, a binary mask, a phase-shift mask, or an EUV mask), so that an image corresponding to the mask pattern is projected onto the resist layer. Because the resist layer is sensitive to radiant energy, exposed portions of the resist layer undergo chemical changes, and exposed (or unexposed) portions of the resist layer are dissolved during the development process, depending on the properties of the resist layer and the properties of the developing solution used in the development process.After development, the patterned resist layer comprises a resist pattern corresponding to the mask. The etching process uses the patterned resist layer as an etch mask to remove portions of the substrate 16 (or a material layer disposed over the substrate 16). The etching process may comprise a dry etching process (for example, a reactive ion etching (RIE) process), a wet etching process, another suitable etching process, or combinations thereof. After the etching process, the patterned resist layer is removed from the substrate 16, for example, by a resist stripping process.Alternatively, the fins 22A-22C are formed by a multi-patterning process, such as a double-patterning lithography (DPL) process (for example, a lithography-etch-lithography-etch (LELE) process, a self-aligned double-patterning (SADP) process, a spacer-as-dielectric (SID) SADP process, another double-patterning process, or combinations thereof), a triple-patterning process (for example, a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple-patterning (SATP) process, another triple-patterning process, or combinations thereof), another multi-patterning process (for example, a self-aligned quadruple-patterning (SAQP) process), or combinations thereof. In some implementations, directed self-assembly (DSA) techniques are implemented while fins 22A-22C are being trained.Furthermore, in some implementations, the exposure method may implement maskless lithography, electron beam (e-beam) writing, ion beam writing, and / or nanoprinting technology to pattern the resist layer.

[0017] In some implementations, a pattern defined in the patterned resist layer (or patterned mask layer) includes first openings having a first width for defining fin structure 20A and fin structure 20B, and second openings having a second width for defining fin structure 20C, wherein the first width is greater than the second width. In such implementations, an etching process then uses the patterned resist layer as an etch mask to remove portions of substrate 16 (or a material layer disposed over substrate 16) to form fin CD-loaded fins 22A-22C between core region 12 and I / O region 14 as described herein.In some implementations, a pattern defined in the patterned resist layer (or patterned mask layer) includes first openings, second openings, and third openings for defining the fin structure 20A, the fin structure 20B, and the fin structure 20C, wherein the first openings, the second openings, and the third openings have the same width. In such implementations, an etching process then uses the patterned resist layer as an etch mask to remove portions of the substrate 16 (or a material layer disposed over the substrate 16) such that the fins 22A-22C have the same width. In continuation of such implementations, a trimming process is then performed to trim the fin structure 20C, thereby reducing a width of the fins 22C such that the fins 22A-22C are fabricated with fin CD loading between the core region 12 and the I / O region 14 as described herein.The trimming process implements any suitable method for reducing the dimension of the fins 22C. For example, in some implementations, the trimming process includes an etching process that can selectively etch the fins 22C relative to other features of the integrated circuit device 10. The etching process is a dry etching process, a wet etching process, or combinations thereof. In some implementations, a wet etching process implements an etching solution containing ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ), sulfuric acid (H 2 SO 4 ), tetramethylammonium hydroxide (TMAH), another suitable wet etching solution, or combinations thereof. For example, the wet etching solution may comprise NH 4 OH:H 2 O 2 -solution, an NH 4 OH: H 2 O 2 :H 2 O solution (known as ammonia peroxide mixture (APM)) or a H 2 SO 4 :H 2 O2 solution (known as sulfur peroxide mixture (SPM)). In some implementations, a dry etching process implements an etching gas that contains a fluorine-containing etching gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 and / or C 2 F 6 ), an oxygen-containing gas, a chlorine-containing gas (e.g. Cl 2 , CHCl 3 , CCl 4 and / or BCl 3 ), a bromine-containing gas (e.g. HBr and / or CHBr 3 ), an iodine-containing gas, other suitable gases and / or plasmas, or combinations thereof. In some implementations, the trimming process implements an oxidation process. For example, the trimming process may expose the fins 22C to an ozone environment, thereby oxidizing a portion of the fins 22C, which is subsequently removed by a cleaning process and / or an etching process.

[0018] Referring to the Fig. 2A-2C is Fig. 2A is a plan view of the integrated circuit device 10, Fig. 2B is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 2B-2B of Fig. 2A and Fig. 2C is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 2C-2C of Fig. 2A. One or more isolation features 30 are formed over and / or within the substrate 16 to isolate various regions, such as various device regions, of the integrated circuit device 10. For example, the isolation feature 30 separates and isolates the core region 12 from the I / O region 14. The isolation feature 30 separates and isolates the fins 22A-22C from each other. In the embodiment shown, the isolation feature 30 surrounds a bottom region of the fins 22A-22C. The isolation feature 30 comprises silicon oxide, silicon nitride, silicon oxynitride, another suitable isolation material (e.g., comprising silicon, oxygen, nitrogen, carbon, or another suitable isolation element), or combinations thereof. The isolation feature 30 may include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or local oxidation of silicon (LOCOS) structures.In some implementations, the STI features may be formed by depositing an insulator material over the substrate 16 after forming the fins 22A-22C (in some implementations such that the insulator material layer fills gaps (trenches) between the fins 22A-22C) and etching back the insulator material layer to form the isolation feature 30. In some implementations, the STI features may be formed by etching a trench in the substrate 16 (e.g., using a dry etching process and / or a wet etching process) and filling the trench with insulator material (e.g., using a chemical vapor deposition process or a spin-on-glass process). A chemical mechanical polishing (CMP) process may be performed to remove excess insulator material and / or planarize a top surface of the isolation feature 30.In some implementations, the isolation feature 30 comprises a multi-layer structure that fills trenches, such as a bulk dielectric layer disposed over a dielectric liner layer, where the bulk dielectric layer and the dielectric liner layer comprise materials depending on design requirements (e.g., a bulk dielectric layer comprising silicon nitride disposed over a dielectric liner layer comprising thermal oxide). In some implementations, the isolation feature 30 comprises a dielectric layer disposed over a doped liner layer (comprising, for example, borosilicate glass (BSG) or phosphosilicate glass (PSG)).

[0019] Referring to the Fig. 3A-3C is Fig. 3A is a plan view of the integrated circuit device 10, Fig. 3B is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 3B-3B of Fig. 3A and Fig. 3C is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 3C-3C of Fig. 3A. A gate layer 40 is formed over the fin structures 20A-20C, each disposed in the core region 12 and the I / O region 14. For example, at least one deposition process is performed to form the gate layer 40 over the substrate 16, specifically over the fin structures 20A-20C and the isolation feature 30. The gate layer 40 fills gaps between the fin structures 20A-20C and fills gaps between the fins 22A-22C. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable processes, or combinations thereof. A CMP process may then be performed to planarize a top surface of the gate layer 40.In the embodiment shown, the gate layer 40 comprises a polysilicon layer. In some implementations, the gate layer 40 further comprises an interface layer (comprising a dielectric such as silicon oxide) disposed between the fin structures 20A-20C and the polysilicon layer. In some implementations, the gate layer 40 is a dummy gate stack comprising a dummy gate electrode and a dummy gate dielectric layer. In such implementations, a deposition process is performed to form a dummy gate dielectric layer over the substrate 16, and a deposition process is performed to form a dummy gate electrode layer over the gate dielectric layer. In continuation of such implementations, the dummy gate electrode comprises polysilicon or other suitable dummy gate material, and the dummy gate dielectric comprises a dielectric (e.g.,Silicon oxide), a high-k dielectric, another suitable dielectric, or combinations thereof. Examples of high-k dielectrics include HfO. 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnia-alumina (HfO 2 -Al 2 O 3 ) alloy, other suitable high-k dielectrics, or combinations thereof. The gate layer 40 may include numerous other layers, such as capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In one example, a capping layer, such as a titanium nitride (TiN) capping layer, is disposed between the dummy gate dielectric (or the substrate 16 if the dummy gate dielectric is omitted) and the dummy gate electrode.

[0020] Referring to the Fig. 4A-4C is Fig. 4A is a plan view of the integrated circuit device 10, Fig. 4B is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 4B-4B of Fig. 4A, Fig. 4C is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 4C-4C of Fig. 4A, Fig. 4D is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 4D-4D of Fig. 4A and Fig. 4E is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 4E-4E of Fig. 4A. In the Fig. 4A-4E, a patterning layer 50 is formed over the gate layer 40, wherein the patterning layer 50 includes openings 52 exposing portions of the gate layer 40 in the core region 12 and openings 54 exposing portions of the gate layer 40 in the I / O region 14. In the embodiment shown, the patterning layer 50 includes a mask layer 56 disposed over the gate layer 40 and a resist layer 58 (also referred to as a photoresist layer, light-sensitive layer, imaging layer, patterning layer, or radiation-sensitive layer) disposed over the mask layer 56. The mask layer 56 includes a material having a different etch rate than a material of the gate layer 40. For example, the mask layer 56 includes silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, another suitable material, or combinations thereof.In some implementations, mask layer 56 comprises a material having a low etch rate compared to a material of gate layer 40 so that gate layer 40 can be selectively etched relative to mask layer 56. Mask layer 56 is formed by any suitable process, such as a CVD process, to any suitable thickness. In some implementations, a silicon-containing and nitrogen-containing mask layer is formed using LPCVD. In some implementations, a silicon-containing and nitrogen-containing mask layer is formed by performing a process that includes thermal nitriding of a silicon-containing layer. Resist layer 58 comprises any suitable resist material.The patterning layer 50 is formed by a lithography patterning process that includes resist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing, rinsing, drying (e.g., hard baking), other suitable processes, or combinations thereof. Alternatively, the lithography exposure process is supported, implemented, or replaced by other processes such as maskless lithography, electron beam writing, or ion beam writing. In yet another alternative, the lithography patterning process implements nanoimprint technology. In some implementations, the lithography process implements an etching process, such as a dry etch, wet etch, another etching process, or combinations thereof. A rinsing process, such as a deionized (DI) water rinse, may be applied to the gate layer 40 prior to forming the patterning layer 50.

[0021] Referring to the Fig. 5A-5C is Fig. 5A is a plan view of the integrated circuit device 10, Fig. 5B is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 5B-5B of Fig. 5A, Fig. 5C is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 5C-5C of Fig. 5A, Fig. 5D is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 5D-5D of Fig. 5A and Fig. 5E is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 5E-5E of Fig. 5A. In the Fig. 5A-5E, an etching process is performed using the patterning layer 50 as a mask to remove exposed portions of the gate layer 40, thereby forming gate structures 40A-40H. The etching process may include a dry etching process (e.g., a reactive ion etching (RIE) process), a wet etching process, another suitable etching process, or combinations thereof. The etching process is not capable of completely removing exposed portions of the gate layer 40 in the openings 54 in the I / O region 14, leaving remaining gate layer portions 40' between the fins 22C. The gate structures 40F-40H thus have widths that vary along their length and height, while the gate structures 40A-40E have widths that are substantially the same along their length and height. Fig. 5A, along their length, a width of the gate structures 4oF-4oH arranged above the fins 22C is smaller than a width of the gate structures 4oF-4oH arranged between the fins 22C. Along their height, the gate structures 40F-40H have tapered widths. For example, in Fig. 5E, a portion of a gate structure 40G disposed between the fins 22C has a width that decreases along its height, such that a width of the portion of the gate structure 40G near the isolation feature 30 (or the substrate 16) is greater than a width of the portion of the gate structure 40G near the patterning layer 50. In some implementations, a width of the portion of the gate structure 40G above a top surface of the fin structure 22C is substantially the same along its height, while a width of the portion of the gate structure 40G below the top surface of the fin structures 22C decreases along its height. In conventional integrated circuit devices where a core region and an I / O region have fin structures with substantially the same critical dimensions (widths), such remaining gate layer portions cause gate-source / drain breakdown, degrading device performance.In contrast, by implementing fin CD loading between the core region 12 and the I / O region 14 as described herein (and thus increasing the spacing between the fins in the I / O region 14 relative to the spacing between the fins in the core region 12), etch loading effects during the etching process are minimized, significantly reducing a size (particularly a thickness) of the remaining gate layer portions 40' compared to conventional integrated circuit devices. The disclosed fin CD loading increases a breakdown voltage window (V. BD ) for the I / O region 14 (for example, by increasing the spacing between the fins in the I / O region 14), while maintaining a smaller spacing between the fins, which is desirable for increasing the performance of the core region 12 (for example, by providing a core fin CD that is larger than the I / O fin CD). The V BDThe I / O window for the I / O region 14 is thus increased without compromising the performance of the core region 12 and / or without compromising the gate fabrication process (particularly the polysilicon etching process). Different embodiments may have different advantages, and no particular advantage is necessarily required in any embodiment.

[0022] Referring to the Fig. 6A-6C is Fig. 6A is a plan view of the integrated circuit device 10, Fig. 6B is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 6B-6B of Fig. 6A, Fig. 6C is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 6C-6C of Fig. 6A, Fig. 6D is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 6D-6D of Fig. 6A and Fig. 6E is a fragmentary cross-sectional view of the integrated circuit device 10 taken along line 6E-6E of Fig. 6A. In the Fig. 6A-6C, after the patterning layer 50 has been removed from the gate layer 40, for example, by a resist stripping process, the gate structures 40A-40H are disposed over the fins 22A-22C. The gate structures 40A-40H extend along the y-direction (for example, substantially perpendicular to the fins 22A-22C). In the embodiment shown, the gate structures 40A-40E are disposed over the fin structure 20A and the fin structure 20B such that the gate structures 40A-40E wrap around a portion of the fins 22A and 22B; and the gate structures 40F-40H are disposed over the fin structure 20C such that the gate structures 40F-40H wrap around a portion of the fins 22C. The gate structures 40A-40H are active gate structures or dummy gate structures, depending on the design requirements of the integrated circuit device 10.“Active gate structure” generally refers to an electrically functional gate structure of the integrated circuit device 10, while “dummy gate structure” generally refers to an electrically non-functional gate structure of the integrated circuit device 10. In some implementations, a dummy gate structure mimics spatial characteristics of an active gate structure, such as spatial dimensions of the active gate structure, but is not operable in a FinFET (in other words, it does not allow current flow). In some implementations, at least one of the gate structures 40A-40E wraps channel regions of the fins 22A and 22B, thereby sandwiching them between source / drain regions of the fins 22A and 22B; and at least one of the gate structures 40F-40H wraps channel regions of the fins 22C, thereby sandwiching them between source / drain regions of the fins 22C.In such implementations, at least one of the gate structures 40A-40H engages the channel regions of the fins 22A-22C so that current can flow between the source / drain regions of the fins 22A-22C during operation. In some implementations, the gate structures 40A-40H enable a substantially uniform processing environment, enabling, for example, uniform epitaxial material growth in source / drain regions of the fins 22A-22C (for example, when forming epitaxial source / drain features), uniform etch rates in source / drain regions of the fins 22A-22C (for example, when forming source / drain recesses), and / or uniform, substantially planar surfaces (for example, by reducing (or preventing) CMP-induced dishing effects).

[0023] The integrated circuit device 10 may undergo further processing to complete manufacturing. For example, in some implementations, gate spacers are formed adjacent to the gate structures 4oA-4oH. For example, the gate spacers are disposed adjacent (e.g., along sidewalls) to the gate layer 40. The gate spacers are formed by any suitable method and include a dielectric. The dielectric may include silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (e.g., silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide). For example, in the illustrated embodiment, a dielectric layer including silicon and nitrogen, such as a silicon nitride layer, may be deposited over the substrate 16 and subsequently anisotropically etched to form the gate spacers.In some implementations, the gate spacers comprise a multi-layer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some implementations, more than one set of spacers, such as sealing spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, are formed adjacent to the gate structures 40A-40H. In such implementations, the different sets of spacers may comprise materials with different etch rates.For example, a first dielectric layer comprising silicon and oxygen (e.g., silicon oxide) may be deposited over the substrate 16 and then anisotropically etched to form a first set of spacers adjacent to the gate structures 40A-40H, and a second dielectric layer comprising silicon and nitrogen (e.g., silicon nitride) may be deposited over the substrate 16 and then anisotropically etched to form a second set of spacers adjacent to the first set of spacers.

[0024] In some implementations, source / drain features, such as heavily doped source / drain regions and / or lightly doped source / drain (LDD) features, are formed in the source / drain regions of fins 22A-22C. In some implementations, epitaxial source features and epitaxial drain features (referred to as epitaxial source / drain features) are formed in the source / drain regions of fins 22A-22C. For example, a semiconductor material is epitaxially grown on exposed portions of fins 22A-22C, thereby forming epitaxial source / drain features. An epitaxial growth process may use CVD deposition techniques (e.g., VPE and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth techniques, or combinations thereof. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of fins 22A-22C.The epitaxial source / drain features are doped with n-type dopants and / or p-type dopants. In some implementations, the epitaxial source / drain features are epitaxial layers comprising silicon and / or carbon, wherein silicon-containing epitaxial layers or silicon-carbon-containing epitaxial layers are doped with phosphorus, another n-type dopant, or combinations thereof (forming, for example, a Si:P epitaxial layer or a Si:C:P epitaxial layer). In some implementations, the epitaxial source / drain features are epitaxial layers comprising silicon and germanium, wherein the silicon-germanium-containing epitaxial layers are doped with boron, another p-type dopant, or combinations thereof (forming, for example, a Si:Ge:B epitaxial layer).In some implementations, the epitaxial source / drain features include materials and / or dopants that achieve a desired tensile and / or compressive stress in the channel regions of the fins 22A-22C. In some implementations, the epitaxial source / drain features are doped during deposition by adding impurities to a source material of the epitaxial process. In some implementations, the epitaxial source / drain features are doped by an ion implantation process following a deposition process. In some implementations, annealing processes are performed to activate dopants in the epitaxial source / drain features and / or other source / drain regions of the integrated circuit device 10 (e.g., HDD regions and / or LDD regions formed in the source / drain regions of the fins 22A-22C and / or the epitaxial source / drain features).

[0025] A gate replacement process may then be performed to replace a dummy gate stack of at least one of the gate structures 40A-40H with a gate, such as a metal gate stack. For example, an interlevel dielectric (ILD) layer may be formed over the substrate 16, for example, by a deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable processes, or combinations thereof). The ILD layer includes a dielectric, including, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, a low-k dielectric, another suitable dielectric, or combinations thereof.Example low-k dielectrics include FSG, carbon-doped silicon oxide, Black Diamond® (Applied Materials, Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, another low-k dielectric, or combinations thereof. The ILD layer may comprise a multilayer structure having multiple dielectrics. After depositing the ILD layer, a CMP process may be performed so that an upper portion of the gate structures 40A-40H is reached (exposed), such as a dummy gate electrode (e.g., a polysilicon layer) of the gate layer 40. A portion of at least one of the gate structures 40A-40H (such as the dummy gate electrode of the gate layer 40) is then removed, forming a trench (opening) that may expose a barrier layer and / or a gate dielectric.In some implementations, an etching process selectively removes the dummy gate electrode (and, in some implementations, a dummy gate dielectric). The etching process is a dry etching process, a wet etching process, or combinations thereof. A selective etching process can be tuned such that the dummy gate electrode layer has an appropriate etch rate relative to the barrier layer, the spacers, and / or the ILD layer.

[0026] A metal gate stack of at least one of the gate structures 40A-40H is then formed in the opening (trench). The metal gate stack of at least one of the gate structures 40A-40H includes a gate dielectric (e.g., a gate dielectric layer) and a gate electrode (e.g., a work function layer and a conductive bulk (or fill) layer). The gate stacks may include numerous other layers, such as capping layers, interface layers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. The gate dielectric layer includes a dielectric, such as silicon oxide, a high-k dielectric, another suitable dielectric, or combinations thereof. Examples of high-k dielectrics include hafnium dioxide (HfO 2 ,), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, hafnia-alumina (HfO 2 -Al 2 O 3), other suitable high-k dielectrics, or combinations thereof. In some implementations, the gate dielectric layer is a high-k dielectric layer. The gate electrode comprises a conductive material, such as polysilicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), cobalt (Co), TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials, or combinations thereof. In some implementations, the work function layer is a conductive layer tuned to have a desired work function (such as an n-type work function or a p-type work function), and the bulk conductive layer is a conductive layer formed over the work function layer.In some implementations, the work function layer comprises n-type work function materials, such as Ti, silver (Ag), TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, manganese (Mn), zirconium (Zr), other suitable n-type work function materials, or combinations thereof. In some implementations, the work function layer comprises a p-type work function material, such as TiN, TaN, ruthenium (Ru), Mo, Al, WN, ZrSi. 2 , MoSi 2 , TaSi 2 , NiSi 2, WN, other suitable p-type work function materials, or combinations thereof. The bulk conductive layer comprises a suitable conductive material such as Al, W, and / or Cu. In some implementations, the bulk conductive layer additionally or jointly comprises polysilicon, Ti, Ta, metal alloys, other suitable materials, or combinations thereof. The gate dielectric layer, the work function layer, and the bulk conductive layer are formed by various deposition processes, such as ALD, CVD, PVD, and / or other suitable processes. A CMP process may be performed to remove excess material (such as any excess portions of the work function layer and / or any excess portions of the metal fill layer), which planarizes the gate structures 40A-40H.It is understood that the gate structures 40A-40H comprise gate stacks configured to achieve the desired functionality according to the design requirements of the integrated circuit device 10, such that the gate structures 40A-40H comprise the same or different layers and / or materials.

[0027] In some implementations, various contacts are formed to facilitate operation of the integrated circuit device 10. For example, additional ILD layers may be formed over the substrate 16 (in the embodiment shown, over the ILD layer and the gate structures 40A-40H). The contacts may be formed in the ILD layers, such as contacts electrically coupled to the gate structures 40A-40H and contacts electrically coupled to the source / drain regions of the fin structures 20A-20C. The contacts comprise a conductive material, such as a metal. Metals include aluminum, aluminum alloy (such as aluminum / silicon / copper alloy), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, other suitable metals, or combinations thereof.The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some implementations, the ILD layers and the contacts are part of a multilayer interconnect (MLI) feature disposed over the substrate 16. The MLI feature electrically connects various components of the integrated circuit device 10 such that the various components are capable of functioning as specified by the design requirements. The MLI feature may include a combination of metal layers and ILD layers configured to form vertical interconnect features such as contacts and / or vias and / or horizontal interconnect features such as lines. The various conductive features comprise materials similar to those of the contacts.In some implementations, a damascene process and / or a dual-damascene process is used to form a multilayer copper-based interconnect structure. The integrated circuit device 10 may undergo subsequent processing to complete fabrication depending on design requirements.

[0028] Fig. 7 is a flowchart of a method 100 for manufacturing an integrated circuit device, such as the integrated circuit device 10, according to various aspects of the present disclosure. At block 102, the method 100 includes forming a first multi-fin structure having a first critical dimension in a core region and a second multi-fin structure having a second critical dimension in an input / output region. The first critical dimension is greater than the second critical dimension. In some implementations, the first multi-fin structure and the second multi-fin structure are formed as described with respect to the Fig. 1A-1C. At block 104, the method 100 includes forming a first gate structure over the first multi-fin structure and a second gate structure over the second multi-fin structure. In some implementations, the first gate structure and the second gate structure are formed as described with respect to the Fig. 2A-2C, 3A-3C, 4A-4E, 5A-5E, and 6A-6E. At block 106, the method 100 may proceed to complete the fabrication of the FinFET device. For example, in implementations where the first gate structure and / or the second gate structure comprise a dummy gate, a gate replacement process is performed to replace the one or more dummy gates with one or more metal gates. Additional steps may be provided before, during, and after the method 100, and some of the described steps may be postponed, replaced, or eliminated for additional embodiments of the method 100.

[0029] Fig. 8 is a fragmentary cross-sectional view of an integrated circuit device 200, in part or in full, according to various aspects of the present disclosure. The integrated circuit device 200 may be provided in a microprocessor, a memory, and / or other integrated circuit device. In some implementations, the integrated circuit device 200 is part of an IC chip, an SoC, or a portion thereof, including various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. Fig. Figure 8 has been simplified for clarity to better understand the inventive concepts of the present disclosure. Additional features may be added to the integrated circuit device 200, and some of the features described below may be replaced, modified, or eliminated in other embodiments of the integrated circuit device 200.

[0030] In Fig. 8, the integrated circuit device 200 includes a substrate 116 that is similar to the substrate 16 of the integrated circuit device 10 described above with reference to FIG. Fig. 1A-1C. The integrated circuit device 200 further includes a fin structure 220A, a fin structure 220B (including fins 222B), and a fin structure 220C (including fins 222C). The fin structure 220A is disposed between the fin structure 220B and the fin structure 220C. In the embodiment shown, the fin structure 220A is a dense fin structure (e.g., having three fins or more), and the fin structure 220B and the fin structure 220C are isolated fin structures (e.g., having two fins or fewer). Although the fin structures 220A-220C are multi-fin structures in the embodiment shown, the present disclosure contemplates embodiments where the fin structure 220B and / or the fin structure 220C include only one fin. The present disclosure further contemplates embodiments in which the fin structure 220A has more or fewer fins than in Fig.8. In some implementations not claimed, the fin structures 220A-220C belong to different FinFET devices of the integrated circuit device 200. In some implementations, the fin structures 220A-220C belong to the same FinFET device of the integrated circuit device 200. In some implementations, the fin structures 220A-220C belong to different regions of the integrated circuit device 200. For example, in some implementations, the fin structure 220A is arranged in an I / O region of the integrated circuit device 200 and the fin structure 220B and / or the fin structure 220C are arranged in a core region of the integrated circuit device 200.

[0031] The fin structure 220A includes interfins or interfins 222A-1 and intrafins or intrafins 222A-2, with the intrafins 222A-2 disposed between the interfins 222A-1. In the illustrated embodiment, the interfins 22A-1 are the outermost fins of the fin structure 220A, and the intrafins 222A-2 are the inner fins of the fin structure 220A. In some implementations, an intra-fin generally refers to a fin that is disposed between fins of the same fin structure (here, fin structure 220A), whereas an inter-fin generally refers to a fin that is disposed between a fin of the same fin structure (or FinFET device) and a fin of a different fin structure (or FinFET device) (here, fin structure 220B or fin structure 220C).In some implementations, an intra-fin generally refers to a fin disposed between fins that share a gate structure and / or a source / drain feature, whereas an inter-fin generally refers to a fin disposed between fins that do not share a gate structure and / or a source / drain feature.

[0032] Fin CD loading optimization is achieved for fins 222A-1 and fins 222A-2 by configuring fin structure 220A with different critical dimensions. In the illustrated embodiment, inter-fins 222A-1 have an inter-fin CD and intra-fins 222A-2 have an intra-fin CD, with the inter-fin CD being larger than the intra-fin CD. In some implementations, fin CD loading for a dense fin structure is defined as a difference between the inter-fin CD and the intra-fin CD, and fin CD loading optimizes the spacing between fins for etching processes used during gate formation when fin CD loading is greater than 0 (in other words, dense fin CD loading = inter-fin CD - intra-fin CD > 0). For example, the inter-fins 222A-1 each have a width W inter and the Intra-Fins 222A-2 each have a width w intra. If, as in the embodiment shown, the inter-fins 222A-1 have a width that is greater than a width of the intra-fins 222A-2 (in other words W inter > W intra is), a distance S 1 (distance) between the intra-fins 222A-2 less than a distance S 2 between the Inter-Finns 222A-1 and the Intra-Finns 222A-2 (in other words, S 1 < S 2 ). In some implementations, the width W inter about 1 nm to about 30 nm and the width w intra about 1 nm to about 30 nm. In some implementations, the distance S 1 about 10 nm to about 30 nm and the distance S 2 about 10 nm to about 30 nm. The inter-fins 222A-1 each have a height h inter and the Intra-Fins 222A-2 each have a height h intra In some implementations, the height h inter about 30 nm to about 150 nm and the height h intraabout 30 nm to about 150 nm. A center-to-center pitch P of the fin structure 220A generally refers to a sum of a width w of the fins (which together comprise the inter-fins 222A-1 and the intra-fins 222A-2) and the distance S between adjacent fins (in other words, P = w + S). In the embodiment shown, a center-to-center pitch P intra the fin structure 220A generally to a center-to-center distance between the intra-fins 222A-2 and a center-to-center distance P inter of the fin structure 220A generally refers to a sum of a center-to-center distance between one of the inter-fins 222A-1 and the adjacent intra-fin 222A-2. In some implementations, the center-to-center distance P intra approximately 10 nm to approximately 50 nm and the center-to-center distance P inter about 30 nm to about 600 nm. In some implementations, the center-to-center pitch P intra and the center distance P inter equal (for example P intra = Pintra ). In some implementations, the center-to-center distance P intra and the center distance P inter different. For example, in some implementations the center-to-center distance P intra greater than the center distance P inter In some implementations, the center-to-center distance P intra and / or the center distance P inter equivalent to a minimum fin center distance (P m ). In some implementations, the minimum fin pitch generally refers to a smallest fin pitch achievable by a lithography process and / or a fin fabrication process (including deposition, lithography, and / or etching processes) of a given IC technology node. In some implementations, the minimum fin pitch generally refers to a smallest fin pitch specified by design requirements for the integrated circuit device 200.

[0033] In continuation of the embodiment shown, the inter-fins 222A-1 have an adjacent inter-fin center-to-center distance (P inter-benachbart ) and the intra-fins 222A-2 have an adjacent intra-fin center-to-center distance (P intra-benachbart ) that can be configured to further optimize inter-fin spacing for etching processes used during gate formation as described above. The adjacent inter-fin pitch is a sum of a right inter-fin pitch and a left inter-fin pitch. The right pitch (P R-inter ) of an inter-fin defines a distance between a center of an inter-fin and a center of an adjacent fin located to the right of the fin, and a left center distance (P L-inter) of an inter-fin defines a distance between a center of an inter-fin and a center of a neighboring (adjacent) fin located to the left of the fin. One of the left center-to-center distance of an inter-fin and the right center-to-center distance of an inter-fin is defined between an inter-fin and an intra-fin of the same fin structure, while the other of the left center-to-center distance of an inter-fin and the right center-to-center distance of an inter-fin is defined between the inter-fin and a fin of a different fin structure. An adjacent intra-fin center-to-center distance is a sum of a right center-to-center distance of the intra-fin and a left center-to-center distance of the intra-fin. The right center-to-center distance (P R-intra ) of an intra-fin defines a distance between a center of an intra-fin and a center of an adjacent fin located to the right of the intra-fin, and a left center distance (P L-intra) of an intra-fin defines a distance between a center of an intra-fin and a center of an adjacent (adjacent) fin located to the left of the intra-fin. The left intra-fin center-to-center distance and the right intra-fin center-to-center distance are defined between fins of the same fin structure. In the embodiment shown, the inter-fins 222A-1 have an adjacent inter-fin center-to-center distance that is greater than or equal to three times a minimum fin center-to-center distance (in other words, P inter-benachbart ≥ 3P m ), and the intra-fins 222A-2 have an adjacent intra-fin center-to-center distance that is less than or equal to twice a minimum fin center-to-center distance (in other words, P intra-benachbart ≤ 2P m ). For example, the leftmost inter-fin 222A-1 of the fin structure 220A has a left center-to-center distance equal to twice the minimum fin center-to-center distance (P L-inter= 2P m ), and a right center distance equal to the minimum fin center distance (P R-inter = P m ), so that the adjacent inter-fin center-to-center distance is equal to three times the minimum fin center-to-center distance (in other words, P inter-benachbart = 2P m + P m = 3P m ). In some implementations, the left center-to-center pitch of the leftmost inter-fin 222A-1 is greater than twice the minimum fin center-to-center pitch and / or the left center-to-center pitch of the leftmost inter-fin 222A-1 is less than the minimum fin center-to-center pitch. In contrast, one of the intra-fins 222A-2 has a left center-to-center pitch equal to the minimum fin center-to-center pitch (P L-intra = P m ), and a right center distance equal to the minimum fin center distance (P R-intra = P m), so that the adjacent intra-fin center-to-center distance is equal to twice the minimum fin center-to-center distance (in other words, P intra-benachbart = P m + P m = 2P m ). In some implementations, the left center-to-center pitch and / or the right center-to-center pitch of the intra-fin 222A-2 is less than the minimum fin center-to-center pitch.

[0034] The present disclosure contemplates variations in the height, width, and / or length of the inter-fins 222A-1 and the intra-fins 222A-2 that may result from the processing and manufacturing of the integrated circuit device 200. In the embodiment shown, the inter-fins 222A-1 and the intra-fins 222A-2 have tapered widths along their respective heights, with the width W inter and the width w intraeach represent an average of the varying widths. For example, the widths of the inter-fins 222A-1 and / or the intra-fins 222A-2 decrease from lower portions of the inter-fins 222A-1 and / or the intra-fins 222A-2 to upper portions of the inter-fins 222A-1 and / or the intra-fins 222A-2 such that the average widths of the upper portions are smaller than the average widths of the lower portions. In some implementations, the widths may vary from about 5 nm to about 15 nm along the inter-fins 222A-1 and / or the intra-fins 222A-2, depending on where the widths are measured along the height of the inter-fins 222A-1 and the intra-fins 222A-2. Although the inter-fins 222A-1 and the intra-fins 222A-2 are shown as having tapered widths, in some implementations the inter-fins 222A-1 and / or the intra-fins 222A-2 have substantially the same width along their respective heights.

[0035] The present disclosure contemplates many different embodiments. An integrated circuit device according to the invention is set out in claim 1. In some implementations, the first fin structure and the second fin structure comprise fins with a tapered width.

[0036] In some implementations, the second fin structure includes an inter-fin having an inter-fin width and an intra-fin having an intra-fin width, wherein the inter-fin width is greater than the intra-fin width. In some implementations, the inter-fin has an adjacent inter-fin pitch that is greater than or equal to three times a minimum fin pitch. In some implementations, the integrated circuit device further includes a first gate structure disposed over the first fin structure and a second gate structure disposed over the second fin structure.

[0037] In another exemplary integrated circuit device, a fin structure disposed over a substrate includes intrafins disposed between interfins, the interfins having an interfin width and the intrafins having an intrafin width, the interfin width being greater than the intrafin width. The interfins may have an adjacent interfin pitch that is greater than or equal to three times a minimum fin pitch. In some embodiments, intrafins have an adjacent intrafin pitch that is less than or equal to two times the minimum fin pitch.In some implementations, the adjacent intra-fin pitch comprises a first pitch between a first intra-fin of the intra-fins and a second intra-fin of the intra-fins, and a second pitch between the first intra-fin and a third intra-fin of the intra-fins. In such implementations, the first pitch and the second pitch are equal to the minimum fin pitch. In some implementations, the integrated circuit device further comprises a gate structure disposed over the second fin structure, the gate structure traversing the second fin structure. In some implementations, the inter-fins and the intra-fins have tapered widths.In some implementations, the adjacent inter-fin pitch includes a first pitch between an inter-fin of the inter-fins and an adjacent intra-fin of the intra-fins, and a second pitch between the inter-fin and a fin located in a second region adjacent to the first region. The first pitch is equal to the minimum fin pitch. The second pitch is greater than or equal to twice the minimum fin pitch.

[0038] A method according to the invention is specified in claim 9. In some implementations, the first multi-fin structure and the second multi-fin structure are formed simultaneously. In some implementations, forming the first multi-fin structure and forming the second multi-fin structure comprises forming a patterned mask layer over a substrate, the patterned mask layer comprising first openings for defining the first multi-fin structure and second openings for defining the second multi-fin structure, and etching through the first openings and the second openings in the patterned mask layer exposed substrate. In some implementations, the first gate structure and the second gate structure comprise dummy gates, and the method further comprises replacing the dummy gates with metal gates.

Claims

[1] Integrated circuit device comprising: a substrate (16); a logic region (12) comprising a first fin structure (20A; 220B) with two fins (22A; 222B) and a third fin structure (20B; 220C) with one or two fins (22B; 222C), wherein the first fin structure (20A; 220B) and the third fin structure (20B; 220C) are included in a first FinFET; an input / output region (14) comprising a second fin structure (20C; 220A) having three or more fins (22C; 222A); wherein the fins (22A, 222B) of the first fin structure (20A; 220B) have a first width (w1), the fins (22B; 222C) of the third fin structure (20B; 220C) have a third width (w3), and the fins (22C; 222A) of the second fin structure (20C; 220A) have a second width (w2), the first width (w1) and the third width (w3) being greater than the second width (w2); wherein the first fin structure (20A; 220B), the second fin structure (20C; 220A) and the third fin structure (20B; 220C) are arranged above the substrate (16); wherein the first fin structure (20A; 220B) has a first center-to-center distance between adjacent fins, the first center-to-center distance between adjacent fins being a sum of a right center-to-center distance (P R ) a first fin of the first fin structure (20A; 220B) and a left center distance (P L ) of the first fin, with the right center distance (P R ) of the first fin defines a distance between a center of the first fin and a center of an adjacent fin which is arranged to the right of the first fin and which is a fin of the third fin structure (20B; 220C), and the left center distance (P L) the first fin defines a distance between the center of the first fin and a center of an adjacent fin which is arranged to the left of the first fin and which is a fin of the first fin structure (20A; 220B); where the left center distance (P L ) of the first fin is substantially equal to a minimum fin center-to-center distance; wherein the first center-to-center distance of adjacent fins is greater than or equal to three times the minimum fin center-to-center distance; and wherein the second fin structure (20C; 220A) has a second center-to-center distance between adjacent fins, the second center-to-center distance between adjacent fins being a sum of a right center-to-center distance (P R ) an intra-fin of the second fin structure (20C; 220A) and a left center distance (P L ) the intra-fin; and wherein the second center-to-center spacing of adjacent fins is substantially equal to twice the minimum fin center-to-center spacing. [2] The integrated circuit device of claim 1, wherein the first fin structure (20A; 220B) has a first fin pitch (S1) and fins (22C; 222A) of the second fin structure (20C; 220A) have a second fin pitch (S2), the first fin pitch (S1) being smaller than the second fin pitch (S2). [3] The integrated circuit device of any preceding claim, wherein the second fin structure (20C; 220A) comprises an inter-fin (222A-1) having an inter-fin width, the intra-fin (222A-2) having an intra-fin width, the intra-fin (222A-2) being disposed between inter-fins (222A-1), and the inter-fin width being greater than the intra-fin width. [4] An integrated circuit device according to claim 3, wherein: the inter-fin (222A-1) has an adjacent inter-fin center distance (P inter-benachbart ) which is greater than or equal to three times the minimum fin center-to-center distance, wherein the adjacent inter-fin center-to-center distance (P inter-benachbart ) is a sum of a right center distance of the inter-fin (222A-1) and a left center distance of the inter-fin (222A-1). [5] The integrated circuit device according to any one of the preceding claims, wherein the first fin structure (20A; 220B) and the second fin structure (20C; 220A) comprise fins with a tapered width. [6] Integrated circuit device according to one of the preceding claims, wherein the second fin structure (20C; 220A) has intra-fins (222A-2) comprising said intra-fin (222A-2), the intra-fins (222A-2) being arranged between two inter-fins (222A-1) of the second fin structure (20C; 220A); where the inter-fins (222A-1) have an inter-fin width (w inter ) and the intra-fins (222A-2) have an intra-fin width (w intra ), with the inter-fin width (w inter ) greater than the intra-fin width (w intra ) is; wherein the inter-fins (222A-1) have a center-to-center distance between adjacent fins (P inter-benachbart ) that is greater than or equal to three times the minimum fin center-to-center distance; and wherein the intra-fins (222A-2) have a center-to-center distance between adjacent fins (P in-tra-benachbart ) which is essentially equal to twice the minimum fin center-to-center distance. [7] The integrated circuit device of claim 6, wherein the inter-fins (222A-1) and the intra-fins (222A-2) have tapered widths. [8] Integrated circuit device according to one of claims 6 or 7, wherein the right center distance of the first intra-fin (222A-2) is a distance of the first intra-fin (222A-2) to a second intra-fin of the intra-fins (222A-2); wherein the left center-to-center distance of the first intra-fin (222A-2) is a distance of the first intra-fin (222A-2) to a third intra-fin of the intra-fins (222A-2); and wherein the right center-to-center distance of the first intra-fin (222A-2) and the left center-to-center distance of the first intra-fin (222A-2) are substantially equal to the minimum fin center-to-center distance. [9] Method comprising: Forming a first fin structure (20A; 220B) having two fins over a substrate (16) in a logic region (12), wherein the fins (22A; 222B) of the first fin structure (20A; 220B) have a first width (w1); Forming a second fin structure (20C; 220A) having three or more fins (22C; 222A) over the substrate (16) in a peripheral region (10), wherein the fins (22C; 222A) of the second fin structure (20C; 220A) have a second width (w2), and wherein the first width (w1) is greater than the second width (w2); and Forming a third fin structure (20B; 220C) having one or two fins (22B; 222C) above the substrate (16) in the logic area (12), wherein the fins (22B; 222C) of the third fin structure (20B; 220C) have a third width (w3), wherein the third width (w3) is greater than the second width (w2); Forming a first gate structure (40C) over the first fin structure (20A; 220B) and the third fin structure (20B; 220C), and forming a second gate structure (40G) over the second fin structure (20C; 220A); wherein the first fin structure (20A; 220B) and the third fin structure (20B; 220C) are included in a first FinFET; wherein the first fin structure (20A; 220B) has a first center-to-center distance between adjacent fins, the first center-to-center distance between adjacent fins being a sum of a right center-to-center distance (P R ) a first fin of the first fin structure (20A; 220B) and a left center distance (P L ) of the first fin, with the right center distance (P R ) of the first fin defines a distance between a center of the first fin and a center of an adjacent fin which is arranged to the right of the first fin and which is a fin of the third fin structure (20B; 220C), and the left center distance (P L) the first fin defines a distance between the center of the first fin and a center of an adjacent fin which is arranged to the left of the first fin and which is a fin of the first fin structure (20A; 220B); where the left center distance (P L ) of the first fin is substantially equal to a minimum fin center-to-center distance; wherein the first center-to-center distance of adjacent fins is greater than or equal to three times the minimum fin center-to-center distance; and wherein the second fin structure (20C; 220A) has a second center-to-center distance between adjacent fins, the second center-to-center distance between adjacent fins being a sum of a right center-to-center distance (P R ) an intra-fin of the second fin structure (20C; 220A) and a left center distance (P L ) the intra-fin; and wherein the second center-to-center spacing of adjacent fins is substantially equal to twice the minimum fin center-to-center spacing. [10] The method of claim 9, wherein the first fin structure (20A; 220B), the third fin structure (20B; 220C) and the second fin structure (20C; 2204) are formed simultaneously. [11] The method according to any one of claims 9 or 10, wherein forming the first fin structure (20A; 220B), the third fin structure (20B; 220C) and the second fin structure (20C; 220A) comprises: Forming a patterned mask layer over the substrate (16), wherein the patterned mask layer comprises first openings for defining the first fin structure (20A; 220B), third openings for defining the third fin structure (20B; 220C), and second openings for defining the second fin structure (20C; 220A); and Etching the substrate (16) exposed by the first openings and the second openings in the patterned mask layer. [12] The method of any one of claims 9 to 11, wherein the first gate structure (40C) and the second gate structure (40G) comprise dummy gates, and the method further comprises replacing the dummy gates with metal gates.

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