Conformal doping process for a Fin field-effect transistor

Abstract

Procedure, comprehensive: Forming a fin structure (222); Formation of a doped amorphous layer (230) over a section of the fin structure (222); and Performing a knock-on implantation process (240) to transfer a dopant from the doped amorphous layer (230) into the section of the fin structure (222) and thereby forming a doped feature (250), wherein the knock-on implantation process (240) causes a section of the doped amorphous layer (230) to become part of the fin structure (222), the process further comprising: Oxidation of a remaining section of the doped amorphous layer (230); and Removal of the oxidized section of the doped amorphous layer (230).

Description

GENERAL STATE OF THE ART

[0001] The integrated circuit (IC) industry is experiencing exponential growth. Technological advances in IC materials and design have produced generations of ICs, with each generation featuring smaller and more complex circuits than the previous generation. As ICs have evolved, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometric size (i.e., the smallest component (or lead) that can be manufactured using a manufacturing process) has decreased. This downsizing process generally provides benefits by increasing production efficiency and reducing associated costs.

[0002] However, this reduction in size has also increased the complexity of IC processing and manufacturing, and for these advances to be realized, similar developments in IC processing and manufacturing are required. For example, as fin field-effect transistor (FinFET) technologies evolve toward smaller feature sizes (such as 32 nanometers, 28 nanometers, 20 nanometers, and below), advanced doping techniques are required to provide doped features (regions) in fin structures with deeper, more uniform doping profiles without damaging the fin structures. While existing FinFET doping techniques are generally suitable for their intended purposes, they are not entirely satisfactory.

[0003] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] This disclosure is best understood by reference to the following detailed description when considered in conjunction with the accompanying figures. It is important to note that, in accordance with industry practice, various features are not drawn to scale and are used for illustrative purposes only. The dimensions of various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 is a flow diagram of a method of fabricating a fin field effect transistor (FinFET) device according to various aspects of the present disclosure. Fig. 2A-2E are fragmentary cross-sectional views of a FinFET device, in sections or in its entirety, at various stages of fabrication, such as those leading to the method of Fig. 1, according to various aspects of the present disclosure. Fig. 3A-3E are fragmentary cross-sectional views of another FinFET device, in section or in its entirety, at various stages of fabrication, such as those leading to the method of Fig. 1, according to various aspects of the present disclosure. Fig. Figure 4 is a perspective, three-dimensional view of yet another FinFET device, in section or in its entirety, at various stages of fabrication, such as those leading to Fig. 1 and Fig. 2A-2E, according to various aspects of the present disclosure. Fig. Figure 5 is a perspective, three-dimensional view of yet another FinFET device, in section or in its entirety, at various stages of fabrication, such as those leading to Fig. 1 and Fig. 3A-3E, according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0005] The present disclosure relates generally to integrated circuit devices and, more particularly, to fin field effect transistor (FinFET) devices.

[0006] The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.

[0007] Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition is for simplicity and clarity and, in itself, does not establish a relationship between the various embodiments and / or configurations discussed. Moreover, the formation of a feature on, connected to, and / or coupled to another feature in the following present disclosure may include embodiments in which the features are formed in direct contact and may also include embodiments in which additional features may be formed disposed between the features such that the features may not be in direct contact.In addition, for the convenience of this disclosure, the relationship of one feature to another feature is described in spatially relative terms, such as "lower," "upper," "horizontal," "vertical," "above," "over," "below," "beneath," "upward," "downward," "top," "bottom," etc., as well as cognate words (e.g., "horizontal," "downward," "upward," etc.). The spatially relative terms are intended to cover different orientations of the device incorporating the features.

[0008] Fig. 1 is a flow diagram of a method 100 for manufacturing an integrated circuit device according to various aspects of the present disclosure. In some implementations, as described herein, the method 100 provides an integrated circuit device including a FinFET device. At block 110, the method 100 includes forming a fin structure, for example, over a substrate. The fin structure includes a crystalline material (in other words, a material with an ordered atomic structure), such as silicon, constructed with a crystalline structure. In some implementations, the fin structure includes a channel region disposed between a source region and a drain region.

[0009] At block 120, a doped amorphous layer is formed over the fin structure. The doped amorphous layer comprises a material having a non-crystalline structure (in other words, a material with a disordered atomic structure). In some implementations, the doped amorphous layer comprises the same material as the fin structure, except that the material of the doped amorphous layer has a non-crystalline structure. For example, the fin structure comprises silicon with a crystal structure, while the doped amorphous layer comprises silicon with a non-crystalline structure, such as amorphous silicon. In some implementations, the doped amorphous layer and the fin structure comprise different materials. For example, the fin structure comprises silicon germanium with a crystal structure, and the doped amorphous layer comprises silicon with a non-crystalline structure, such as amorphous silicon.In some implementations, the doped amorphous layer has a higher dopant concentration than the fin structure. In implementations where the fin structure and the doped amorphous layer comprise the same material but different atomic structures, the material of the doped amorphous layer has a higher dopant concentration than the material of the fin structure. In some implementations, the material of the fin structure is undoped. In some implementations, the doped amorphous layer is formed over the source and drain regions of the fin structure. In these implementations, a gate structure can be formed over the channel region of the fin structure before forming the doped amorphous layer.

[0010] At block 130, a knock-on implantation process is performed to introduce dopant from the doped amorphous layer into a portion of the fin structure, thereby forming a doped feature. In some implementations, the doped feature is a lightly doped source and drain feature (or region) disposed in the source and / or drain regions of the fin structure. In some implementations, the doped feature (or region) is a doped well of the FinFET device, such as a doped well for defining an active region of the FinFET device (in these implementations, the fin structure may be undoped prior to the knock-on implantation process). The knock-on implantation process causes at least a portion of the doped amorphous layer to become part of the fin structure.In particular, the knock-on implantation process may convert at least a portion of the non-crystalline material of the doped amorphous layer into crystal material. The knock-on implantation process may thus order an atomic structure of a portion of the doped amorphous layer. In implementations where the fin structure comprises silicon and the doped amorphous layer comprises amorphous silicon, the knock-on implantation process crystallizes at least a portion of the amorphous silicon, thereby forming a doped silicon feature (region) of the fin structure that comprises a converted (or crystallized) portion of the doped amorphous layer and a doped portion of the fin structure.In implementations where the fin structure comprises silicon germanium and the doped amorphous layer comprises amorphous silicon, the knock-on implantation process crystallizes at least a portion of the amorphous silicon, thereby forming a doped feature (region) of the fin structure that includes a converted (or crystallized) portion of the doped amorphous layer (e.g., in some implementations, a silicon cap layer) and a doped portion of the fin structure.

[0011] In implementations where a portion of the doped amorphous layer becomes part of the fin structure, the method 100 may continue with removing a remaining portion of the doped amorphous layer. In these implementations, removing the remaining portion of the doped amorphous layer may include oxidizing the remaining portion of the doped amorphous layer and performing a wet etching process and / or a cleaning process to remove the oxidized remaining portion. In some implementations, prior to forming the doped amorphous layer, a trimming process is performed to reduce a dimension (such as a width) of the fin structure. In these implementations, the knock-on implantation process converts the entire doped amorphous layer into part of the fin structure (in other words, into crystal material) such that no portion of the doped amorphous layer remains.These implementations eliminate the need for a subsequent wet etching and / or cleaning process. In some implementations, the thickness of the doped amorphous layer is equal to the thickness (or width) of the fin structure, which is removed during the dicing process.

[0012] At block 140, the method 100 may proceed to complete the fabrication of the FinFET device. For example, in implementations where the gate structure includes a dummy gate, a gate replacement process is performed to replace the dummy gate with a metal gate. In implementations where the doped feature defines an active area of ​​the FinFET device, the method 100 may proceed with forming additional IC features to fabricate a functional FinFET device. Additional steps may be provided before, during, and after the method 100, and some of the described steps may be relocated, replaced, or omitted for additional embodiments of the method 100. The following discussion illustrates various embodiments of FinFET devices that may be fabricated according to the method 100.

[0013] Fig. 2A-2E are fragmentary cross-sectional views of a FinFET device 200, in sections or in its entirety, at various stages of fabrication (such as those associated with method 100) according to various aspects of the present disclosure. The FinFET device 200 may be included in a microprocessor, memory, and / or other integrated circuit device.In some implementations, the FinFET device 200 may be a portion of an integrated circuit chip, a system-on-chip (SoC), or a portion thereof that includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. Fig. 2A-2E have been simplified for clarity to better understand the inventive concept of the present disclosure. Additional features may be incorporated into FinFET device 200, and some of the features described below may be replaced, modified, or omitted in other embodiments of FinFET device 200.

[0014] In Fig. 2A, the FinFET device 200 includes a substrate (wafer) 210. The substrate 210 includes a crystalline material, which generally refers to a material having an ordered atomic structure (often referred to as a crystal structure). For example, in the illustrated embodiment, the substrate 210 includes silicon having a crystalline structure. Alternatively or additionally, the substrate 210 includes another elemental semiconductor, such as germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.Alternatively, the substrate 210 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. Semiconductor-on-insulator substrates may be fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable techniques. The substrate 210 may include various doped regions (not shown) depending on the design requirements for the FinFET device 200. In some implementations, the substrate 210 includes p-type regions (e.g., p-wells) doped with p-type dopants, such as boron, indium, another p-type dopant, or combinations thereof.In some implementations, the substrate 210 includes n-doped regions (e.g., n-wells) doped with n-type dopants, such as phosphorus, arsenic, another n-type dopant, or combinations thereof. In some implementations, the substrate 210 includes doped regions formed with a combination of p-type dopants and n-type dopants. The various doped regions may be formed directly on and / or in the substrate 210, for example, including a p-well structure, an n-well structure, a double-well structure, a raised structure, or combinations thereof. An ion implantation process, a diffusion process, and / or another suitable doping process may be performed to form the various doped regions in the substrate 210.

[0015] A fin structure 220 is formed over the substrate 210 by means of a suitable process. In Fig. 2A, the fin structure 220 includes a plurality of fins 222 extending from the substrate 210, although the present disclosure also contemplates embodiments in which the fin structure 220 includes a single fin 222 extending from the substrate 210. In some implementations, the fin structure 220 is a portion of the substrate 210 (such as a portion of a material layer of the substrate 210). For example, in the illustrated embodiment in which the substrate 210 includes a crystalline material, the fin structure 220 includes the same crystalline material, such as silicon having a crystalline structure. Alternatively, in some implementations, the fin structure 220 is defined in a material layer that, when deposited on the substrate 210, includes a semiconductor material having a crystalline structure, such as silicon germanium having a crystalline structure.In some implementations, the fin structure 220 may comprise a semiconductor layer stack (e.g., a heterostructure) including various semiconductor layers. The semiconductor layers may comprise a suitable crystalline material, such as silicon, germanium, silicon germanium, or other suitable material, or combinations thereof. The semiconductor layers may comprise the same or different materials, etch rates, atomic percentages of their constituents, weight percentages of their constituents, thicknesses, and / or configurations, depending on the design requirements for the FinFET device 200.

[0016] Each fin 222 has a height h, a width w1 defined by a pair of sidewalls, and a length l defined by a pair of sidewalls (not shown in the illustrated view). Adjacent fins 222 are separated by a gap S1, where a spacing P of the fins 222 generally refers to a sum of a width of a particular fin 222 (such as w1) and a width of a gap adjacent to the particular fin 222 (such as S1) (in other words: P = w1 + S1). In some implementations, the spacing P is a smallest spacing achievable for a given technology node between the fins 222 through a lithography process. In some implementations, the height h is about 30 nm to about 80 nm, and the width w1 is about 1 nm to about 30 nm. For example, in the illustrated embodiment, the height h is about 30 nm to about 80 nm, and the width w1 is about 2 nm to about 20 nm.In some implementations, the gap S1 measures about 10 nm to about 30 nm. In some implementations, the pitch P is about 10 nm to about 50 nm. The present disclosure also contemplates variations in the height h, width w1, and length l of the fins 222 that may result from the processing and manufacturing of the FinFET device 200. For example, although each fin 222 is illustrated as having substantially the same width w1 along the height h, in some implementations, the width w1 represents an average width of a given fin 222. In some implementations, a width of the fins 222 varies from a top portion of the fins 222 to a bottom portion of the fins 222, where the width w1 represents an average of the varying widths.In some implementations, the width tapers from the upper portion of the fins 222 to the lower portion of the fins 222 such that an average width of the upper portion is smaller than an average width of the lower portion. In some implementations, the width w1 along the fins 222 may vary from about 5 nm to about 15 nm, depending on where the width w1 is measured along the height h of the fins 222. In some implementations, the width w1 of the fins 222 varies depending on a position of the fins 222 relative to each other and / or relative to other features of the FinFET device 200. For example, the width w1 of center fins 222 (in the illustrated embodiment, the FinFET device 200 includes two center fins 222) may be greater than the width w1 of edge fins 222 (here, the leftmost fin 222 and the rightmost fin 222, which enclose the two center fins 222).Alternatively, in another example, the width w1 of the center fins 222 is smaller than the width w1 of the edge fins 222. In these two implementations, the width w1 of the edge fins 222 may represent an average width of the edge fins 222, and the width w1 of the center fins 222 may represent an average width of the center fins 222.

[0017] A combination of deposition, lithography and / or etching processes is performed to define the fins 222 extending from the substrate 210, as shown in Fig. 2A. For example, forming the fin structure 220 includes performing a lithography process to form a patterned resist layer over the substrate 210 (or a material layer disposed over the substrate 210) and performing an etching process to transfer a pattern defined in the patterned resist layer to the substrate 210 (or the material layer disposed over the substrate 210). The lithography process may include forming a resist layer on the substrate 210 (e.g., by spin coating), performing a pre-exposure heat treatment process, performing an exposure process using a mask, performing a post-exposure heat treatment process, and performing a development process. During the exposure process, the resist layer is exposed to radiant energy (such as ultraviolet (UV) light,deep UV (DUV) light or extreme UV (EUV) light), whereby the mask blocks, transmits, and / or reflects radiation to the resist layer depending on a mask structure of the mask and / or a mask type (e.g., binary mask, phase-shift mask, or EUV mask) such that an image corresponding to the mask structure is projected onto the resist layer. Since the resist layer is sensitive to radiant energy, exposed portions of the resist layer change chemically, and exposed (or unexposed) portions of the resist layer are dissolved during the development process depending on the properties of the resist layer and the properties of a developing solution used in the development process. After development, the patterned resist layer comprises a resist structure corresponding to the mask. The etching process removes portions of the substrate 210,wherein the etching process uses the patterned resist layer as an etching mask. The etching process may include a dry etching process, a wet etching process, another suitable etching process, or combinations thereof. In some implementations, a reactive ion etching (RIE) process is performed. After the etching process, the patterned resist layer is removed from the substrate 210, for example, by a resist stripping process. Alternatively, the fin structure 220 is formed by a multiple patterning process, such as a double patterning lithography (DPL) process (e.g., a lithography-etch-lithography-etch (LELE) process), a self-aligned double patterning (SADP) process, a spacer-is-dielectric (SID) process,another double patterning process or combinations thereof), a triple patterning process (e.g., a lithography-etch-lithography-etch-lithography-etch (LELELE) process, a self-aligned triple patterning (SATP) process, another triple patterning process or combinations thereof), another multi-patterning process (e.g., a self-aligned quadruple patterning (SAQP) process), or combinations thereof. In some implementations, directed self-assembly (DSA) processes are implemented while the fin structure 220 is formed. Furthermore, in some alternative implementations, the exposure process may include maskless lithography, electron beam (e-beam) writing,Implement ion beam writing and / or nanoprinting technology to structure the resist layer.

[0018] In Fig. 2B, a trimming process is performed to trim the fin structure 220 and thereby reduce a dimension of the fins 222. For example, the trimming process reduces a width of the fins 222 such that the fins 222 have a width w2 after the trimming process that is smaller than a width w1. The trimming process also increases a spacing between the fins 222 such that adjacent fins 222 are separated by a gap S2 that is larger than the gap S1. In some implementations, the trimming process reduces a width of the fins 222 from about 2 nm to about 20 nm, although the present disclosure describes the trimming process removing the fins 222 to varying degrees. For example, in some implementations where the width w1 is about 5 nm to about 30 nm, the trimming process reduces the width of the fins 222 such that the width w2 is about 2 nm to about 20 nm.In some implementations, the trimming process may facilitate formation of subsequently formed layers (e.g., by increasing the spacing between fins 222). Although not shown, it should be understood that the trimming process may also decrease the height h of fins 222. In some implementations, the trimming process is tuned (or controlled) to decrease the width w1 while minimally affecting the height h of fins 222 (e.g., the width w1 of fins 222 is decreased at a faster rate than the height h of fins 222). In some implementations, the trimming process is tuned to decrease the width w1 and the height h at approximately the same rate, such that fins 222 also have a decreased height (although not shown).Furthermore, the present disclosure also contemplates variations in the height h, width w2, and length l of the fins 222 that may result from the trimming process. For example, the width w2 may vary along the fins 222, similar to the width w1, as described above. In some implementations, the trimming process is applied to a subset of the fins 222, with some fins 222 not being trimmed by the trimming process.

[0019] The trimming process implements a suitable process for reducing the dimension of the fins 222. For example, in some implementations, the trimming process includes an etching process that can selectively etch the fins 222 relative to other features of the FinFET device 200. The etching process is a dry etching process, a wet etching process, or combinations thereof. In some implementations, a wet etching process implements an etching solution comprising ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), sulfuric acid (H2SO4), tetramethylammonium hydroxide (TMAH), another suitable wet etching solution, or combinations thereof. For example, the wet etching solution can use an NH4OH:H2O2 solution, an NH4OH:H2O2:H2O solution (known as an ammonia-peroxide mixture (APM)), or an H2SO4:H2O2 solution (known as a sulfuric peroxide mixture (SPM)).In some implementations, a dry etching process implements an etching gas comprising a fluorine-containing etching gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), an oxygen-containing gas, a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases, and / or plasmas, or combinations thereof. In some implementations, the trimming process implements an oxidation process. For example, the trimming process may expose the fins 222 to an ozone environment, thereby oxidizing a portion of the fins 222, which is subsequently removed by a cleaning process and / or an etching process, such as those described herein.By controlling the cutting process (such as cutting time, cutting process conditions, or other cutting parameters), a profile of the fins 222 can be modified to meet various design requirements for the FinFET device 200. For example, where the cutting process includes an etching process, various etching parameters, such as the etchant used, etching temperature, etching solution concentration, etching pressure, source current, RF bias voltage, RF bias current, etchant flow rate, and / or other suitable etching parameters, are modified to remove a desired amount of the fins 222 and / or achieve a desired profile of the fins 222.

[0020] In Fig. 2C, a doped amorphous layer 230 is formed over the fin structure 220. The doped amorphous layer 230 comprises a material having a non-crystalline structure (in other words, a material with a disordered atomic structure). In some implementations, the doped amorphous layer 230 and the fin structure 220 comprise the same material but with different atomic structures. For example, the doped amorphous layer 230 comprises the same material as the fin structure 210, except that the material has a non-crystalline structure. In the illustrated embodiment, in which the fin structure 220 comprises silicon with a crystal structure, the doped amorphous layer 230 comprises silicon with a non-crystalline structure, such as amorphous silicon. The doped amorphous layer 230 may thus be referred to as a doped amorphous silicon layer.Alternatively, in some implementations, the doped amorphous layer 230 and the fin structure comprise different materials with different atomic structures. For example, the fin structure 220 comprises a semiconductor material, such as silicon germanium, and the doped amorphous layer 230 comprises silicon in non-crystalline form, such as amorphous silicon. Depending on the design requirements regarding the FinFET device 200, the doped amorphous layer 230 comprises n-type dopants, p-type dopants, or combinations thereof. Where the FinFET device 200 is configured as a p-type FinFET device, the doped amorphous layer 230 comprises p-type dopants, such as boron, germanium, indium, another p-type dopant, or combinations thereof. Where the FinFET device 200 is configured as an n-FinFET device, the doped amorphous layer 230 comprises n-dopants, such as arsenic, phosphorus, another n-dopant, or combinations thereof.In some implementations, the doped amorphous layer 230 is heavily doped with a dopant having a dopant concentration in a range of about 1 × 10. 21 Dopants / cm 3 (cm -3 ) to about 4 × 10 21 cm -3 In some implementations, the doped amorphous layer 230 has a higher dopant concentration than the fin structure 220. For example, the doped amorphous layer 230 may have a dopant concentration in a range of about 1 × 10 21 cm -3 up to about 4 × 10 21 cm -3 while the fin structure 220 has a dopant concentration in a range of approximately 1 × 10 10 cm -3 up to about 1 × 10 18 cm -3 (in some implementations, the fin structure 220 is considered undoped or intrinsic at or below these doping concentrations).

[0021] The doped amorphous layer 230 encloses the fin structure 220. For example, the fins 222 include a top portion defined between sidewall portions (such as the sidewalls defining the width w2 of the fins 222), with the doped amorphous layer 230 disposed on the top portion and sidewall portions. In some implementations, the top portion is a substantially horizontal side (e.g., substantially parallel to an xy plane) of the fin structure 220, while the sidewall portions are substantially vertical sides (e.g., substantially parallel to an xz plane) of the fin structure 220. The doped amorphous layer 230 has a thickness t. In some implementations, the doped amorphous layer 230 has a thickness t that is about 1 nm to about 10 nm. For example, in the illustrated embodiment, the thickness t is about 3 nm to about 5 nm.In some implementations, a final width of the fins 222 corresponds to a defined target width (w. t ), such as a critical dimension defined by design specifications and / or an integrated circuit (IC) design layout for the FinFET device 200. In these implementations, a width w3 represents the width w2 of the fins 222 combined with the thickness t of the doped amorphous layer 230 (e.g., w3 - w2 + t), where the width w3 is substantially equal to the target width w t is (for example w3 ≈ w t ). In some implementations, the thickness t is essentially equal to a width w r the fins 222, which are removed during the cutting process (for example, t ≈ w r ). The present disclosure also contemplates variations in width w3 and thickness t resulting from processing as described herein.

[0022] The doped amorphous layer 230 is formed by a suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), spin coating, plating, another deposition method, or combinations thereof. In the illustrated embodiment, the doped amorphous layer 230 is conformally deposited over the fin structure 220 such that the thickness t is substantially uniform over exposed surfaces of the fin structure 220 and / or the substrate 210.Any suitable process (e.g., an ion implantation process, a diffusion process, an in-situ doping process, or combinations thereof) may be implemented to dope the material deposited over the fin structure 220. In some implementations, a selective epitaxial growth (SEG) process is performed to grow a semiconductor material on exposed portions of the fin structure 220, wherein dopants are introduced into the semiconductor material during the SEG process (e.g., by adding dopants to a starting material of the SEG process), thereby forming the doped amorphous layer 230. The SEG process can implement CVD deposition processes (e.g., vapor-phase epitaxy (VPE)), ultra-high vacuum CVD (UHV-CVD), LPCVD and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof.The SEG process may utilize gaseous precursors (e.g., silicon-containing gases such as SiH4 and / or germanium-containing gases such as GeH4) and / or liquid precursors that interact with a composition of the fin structure 220. For example, in the illustrated embodiment where the doped amorphous layer 230 is a doped amorphous silicon layer, the deposition process may expose the fin structure 220 (and the substrate 210) to a silicon-containing gas (e.g., a silicon hydride-containing gas such as SiH4, Si2H6, Si3H8, Si4H). 10 or combinations thereof) and adding dopants (e.g., germanium, boron, arsenic, phosphorus, or combinations thereof) to the silicon-containing gas. In some implementations, the doped amorphous layer 230 comprises materials and / or dopants that achieve a desired tensile and / or compressive stress in a channel region of the FinFET device 200.

[0023] In Fig. 2D, a knock-on implantation process 240 is performed on the doped amorphous layer 230, thereby forming a doped feature 250. The knock-on implantation process 240 bombards the doped amorphous layer 230 with ions 242, wherein the ions 242 transfer dopant from the doped amorphous layer 230 into the fin structure 220 and / or the substrate 210 (in other words, the ions 242 push dopant from the doped amorphous layer 230 into the fin structure 220 and the substrate 210). The ions 242 may include carbon, germanium, argon, nitrogen, and / or ions that do not affect the operating characteristics of the FinFET device 200. In the illustrated embodiment, the ions 242 are argon atoms. In some implementations, the ions 242 are non-doping species.The knock-on implantation process 240 may be performed at a tilt angle α, where the tilt angle α may be tuned to minimize shadowing effects while maximizing the ion depth into the doped amorphous layer 230 and / or the dopant depth into the fin structure 220 and / or the substrate 210. In some implementations, the knock-on implantation process 240 is a plasma immersion ion implantation (PIII) process (also referred to as plasma doping). In some implantations, the knock-on implantation process 240 is performed at a temperature of about 20°C to about 40°C, and in some implementations, it is performed at about room temperature (e.g., about 20°C to about 25°C). In some implantations, the knock-on implantation process 240 uses a bias voltage (also referred to as implant voltage) of about 1 kV to about 5 kV.In some implementations, bias generally refers to a DC bias applied to the substrate 210 during the knock-on implantation process 240. The knock-on implantation process 240 is achieved with much lower implant voltages than those achieved by conventional doping techniques for the fin structure 220. For example, conventional ion implantation processes typically require bias voltages of about 8 kV to about 15 kV, while other doping techniques may require bias voltages of about 20 kV to about 50 kV to ensure that dopants penetrate to sufficient depths into the fins. These high-voltage implantation processes have been observed to damage the fins, often damaging a profile of the fins.In contrast, performing the knock-on implantation process 240 on the doped amorphous layer 230 using bias voltages of less than about 5 kV can sufficiently introduce dopants into the fin structure 220 (in some implementations, dopants are introduced up to 20 nm into the fin structure 220) without damaging a profile of the fin structure 220, thereby providing improvements over conventional doping techniques. In addition, the knock-on implantation process 240 can better control dopant profiles of the fin structure 220 compared to conventional ion implantation processes, which often have less effective dopant profiles resulting from dopant scattering and dopant angle limitations of the conventional implantation processes.

[0024] By introducing a dopant into the fins 222, the knock-on implantation process 240 forms a doped portion 252 of the fins 222, while also causing at least a portion of the doped amorphous layer 230 to become part of the fin structure 220. Specifically, the knock-on implantation process 240 modifies an atomic structure of a portion of the doped amorphous layer 230 by converting (crystallizing) a portion of the non-crystalline material of the doped amorphous layer 230 into crystalline material. In the illustrated embodiment, the knock-on implantation process 240 converts the doped amorphous layer 230 into a doped layer 254 such that the doped amorphous layer 230 in its entirety becomes part of the fin structure 220, and no portion of the doped amorphous layer 230 remains. The doped feature 250 thus comprises a doped portion 252 and a doped layer 254.Where the fin structure 220 comprises silicon and the doped amorphous layer 230 comprises amorphous silicon, the knock-on implantation process 240 crystallizes the amorphous silicon (in other words, rearranges its atomic structure) such that the doped feature 250 is a doped silicon feature. Alternatively, where the fin structure 220 comprises silicon germanium (or another semiconductor material) and the doped amorphous layer 230 comprises amorphous silicon, the knock-on implantation process 240 crystallizes the amorphous silicon (in other words, rearranges its atomic structure) such that the doped feature 250 comprises a doped silicon feature and a doped feature of silicon germanium (or another semiconductor material). In some implementations, the doped layer 254 is a silicon cap layer.In some implementations, the doped feature 250 is a lightly doped source and drain (LDD) feature (or region) disposed in a source region and / or a drain region of the fin structure 220. In some implementations, the doped feature 250 is a doped well (or region) of the FinFET device 200, such as a doped well for defining an active region of the FinFET device 200. The doped feature 250 has been observed to have deeper, larger, and / or more uniform doping profiles compared to doped features formed using conventional doping techniques, such as ion implantation processes and / or knock-on implantation processes that utilize doped layers comprising materials with crystal structures. In some implementations, the doped feature 250 has a dopant concentration in a range of approximately 1 × 10 20 cm -3 up to about 5 × 10 20cm -3In some implementations, a doping concentration in the doped feature 250 is substantially uniform across a width and / or a height of the fins 222. In some implementations, the doping concentration is considered substantially uniform if the doping concentrations at a defined number of points across the width of the doped feature 250, across the height of the doped feature 250, and / or within the doped feature 250 are within ±5% of each other. In some implementations, a dopant concentration of the doped portion 252 is substantially equal to a dopant concentration of the doped layer 254.In some implementations, the doping concentration is considered to be substantially the same when the doping concentration of the doped portion 252 (such as an average doping concentration) and the doping concentration of the doped layer 254 (such as an average doping concentration) are within ±5% of each other.

[0025] Conventional doping processes for FinFETs often require removal of a material layer (such as a doped layer) after forming a doped feature, causing surface damage and / or other damage to the fin structure. By converting the doped amorphous layer 230 into part of the fin structure 220, no further processing to remove the doped amorphous layer 230 is required, and the FinFET device 200 remains as shown in Fig. 2E. Subsequent wet etching processes and / or subsequent cleaning processes may thus be omitted, which minimizes surface damage (such as surface roughness) and / or other damage to the fin structure 220. Furthermore, converting the doped amorphous layer 230 into a part of the fin structure 220 minimizes a gap S3 between the fins 222, which improves a fin merging process window (e.g., where subsequent epitaxial source and drain features are formed on the fins 222, wherein these epitaxial source and drain features merge with each other to form a merged epitaxial source and drain feature.

[0026] Fig. 3A-3E are fragmentary cross-sectional views of a FinFET device 300, in sections or in its entirety, at various stages of fabrication (such as those associated with method 100) according to various aspects of the present disclosure. In some implementations, FinFET device 300 may be a portion of an IC chip, an SoC, or a portion thereof that includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, MOSFETs, CMOSs, BJTs, LDMOSs, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. FinFET device 300 is similar in many respects to FinFET device 200. Accordingly, for clarity and simplicity, similar features are shown in Fig. 2A-2E and Fig. 3A-3E are designated by the same reference numerals. Fig. 3A-3E have been simplified for clarity to better understand the inventive concept of the present disclosure. Additional features may be incorporated into FinFET device 300, and some of the features described below may be replaced, modified, or omitted in other embodiments of FinFET device 300.

[0027] In Fig. 3A, similar to the FinFET device 200, the FinFET device 300 includes the substrate 210 and the fin structure 220 (including fins 222 extending from the substrate 210) described above with reference to Fig. 2A. In contrast to the fabrication of the FinFET device 200, no dicing process is performed on the FinFET device 300. In Fig. 3B, the fabrication of the FinFET device 300 thus proceeds with the formation of the doped amorphous layer 230 over the fin structure 220, which was described above with reference to Fig. 2C is described in detail.

[0028] In Fig. 3C, similar to the FinFET device 200, the knock-on implantation process 240 is performed on the doped amorphous layer 230, wherein the ions 242 transfer dopant from the doped amorphous layer 230 into the fin structure 220 and / or the substrate 210, as described above with reference to Fig. 2D. In contrast to the fabrication of the FinFET device 200, only a portion of the doped amorphous layer 230 becomes part of the fin structure 220 during the knock-on implantation process 240, such that the fin structure 220 includes a doped feature 350 comprising a doped portion 352 of the fins 222 and a doped layer 354 (alternatively referred to as a converted portion of the doped amorphous layer 230). For example, the knock-on implantation process 240 converts only a portion of the doped amorphous layer 230 to the doped layer 354, such that a portion of the doped amorphous layer 230 remains above the fin structure 220. In particular, the knock-on implantation process 240 modifies an atomic structure of a portion of the doped amorphous layer 230 by converting (crystallizing) a portion of the non-crystalline material of the doped amorphous layer 230 into crystal material.Where the fin structure 220 comprises silicon and the doped amorphous layer 230 comprises amorphous silicon, the knock-on implantation process 240 crystallizes the amorphous silicon (in other words, rearranges its atomic structure) such that the doped feature 350 is a doped silicon feature. Alternatively, where the fin structure 220 comprises silicon germanium (or another semiconductor material) and the doped amorphous layer 230 comprises amorphous silicon, the knock-on implantation process 240 crystallizes the amorphous silicon (in other words, rearranges its atomic structure) such that the doped feature 350 comprises a doped silicon feature and a doped feature of silicon germanium (or another semiconductor material). In some implementations, the doped layer 354 is a silicon cap layer.Further, in contrast to the FinFET device 200, the knock-on implantation process 140 partially introduces dopant into the fin structure 220 such that the FinFET device 300 includes fins 222 having a doped portion 352 and an undoped portion 356 (which, in some implementations, indicates portions of the fins 222 having a doping concentration less than a doping concentration of the doped portion 352).

[0029] After the knock-on implantation process 140, the doped amorphous layer 230 has a thickness t1, and the doped layer 354 has a thickness t2, both of which are smaller than an original thickness of the doped amorphous layer 230 (here, the thickness t). In some implementations, the thickness t1 is about 1 nm to about 7 nm, and the thickness t2 is about 1 nm to about 3 nm. In some implementations, a final width of the fins 222 corresponds to a defined target width (wt ), such as a critical dimension defined by design specifications and / or an integrated circuit (IC) design layout for the FinFET device 300. In these implementations, a width w4 represents the width w1 of the fins 222 combined with the thickness t2 of the doped layer 354 (e.g., w4 ≈ w1 + t2), where the width w4 is substantially equal to the target width w t is (for example w4 ≈ w t ). In some implementations, the knock-on implantation process 240 is tuned to ensure that a sufficient portion of the doped amorphous layer 230 is converted into the doped layer 354 such that the width w4 is substantially equal to the target width w t The present disclosure also contemplates variations in width w4, thickness t1, and thickness t2 resulting from processing as described herein.

[0030] In some implementations, the doped feature 350 is a lightly doped source and drain feature (or region) arranged in a source region and / or a drain region of the fin structure 220. In some implementations, the doped feature 350 is a doped well (or region) of the FinFET device 300, such as a doped well for defining an active region of the FinFET device 300. The doped feature 350 has been observed to have deeper, larger, and / or more uniform doping profiles compared to doped features formed using conventional doping techniques, such as ion implantation processes and / or knock-on implantation processes that utilize doped layers comprising materials with crystal structures. In some implementations, the doped feature 350 has a dopant concentration in a range of approximately 1 × 10 20 cm -3 up to about 5 × 10 20cm -3 In some implementations, a doping concentration in the doped feature 350 is substantially uniform across its thickness. In some implementations, the doping concentration is considered substantially uniform when the doping concentrations at a defined number of points across a thickness of the doped feature 350 are within ±5% of each other. In some implementations, a dopant concentration of the doped portion 352 is substantially equal to a dopant concentration of the doped layer 354. In some implementations, the doping concentration is considered substantially equal when the doping concentration of the doped portion 352 (such as an average doping concentration) and the doping concentration of the doped layer 354 (such as an averaged doping concentration) are within ±5% of each other.

[0031] Any remaining portion of the doped amorphous layer 230 is removed by a suitable process. Fig. 3D, an oxidation process is performed on the doped amorphous layer 230, thereby forming an oxidized doped amorphous layer 360. In some implementations, the oxidation process is a high-temperature oxidation process. For example, the doped amorphous layer 230 is exposed to an ozone environment at a temperature of about 800°C to about 1,000°C, thereby oxidizing the doped amorphous layer 230. In some implementations, the oxidation process is a rapid thermal oxidation (RTO) process. Subsequently, the oxidized doped amorphous layer 360 is removed by a suitable wet etching process and / or cleaning process, and the FinFET device 300 remains as shown in Fig. 3E. In some implementations, the cleaning process is an SPM cleaning process, for example, implementing an SPM wet etch solution. In these implementations, the SPM cleaning process may be performed at a temperature of about 150°C to about 200°C. By oxidizing the doped amorphous layer 230, gentler wet etching and / or cleaning processes may be implemented to remove the oxidized doped amorphous layer 360, minimizing or eliminating surface damage (such as surface roughness) and / or other damage to the fin structure 220, compared to wet etching and / or cleaning processes used in conventional doping techniques.Furthermore, converting a portion of the doped amorphous layer 230 into a part of the fin structure 220 minimizes a gap S4 between the fins 222, which improves a fin merging process window (e.g., where epitaxial source- and drain features are formed on the fins 222, wherein these epitaxial source and drain features merge with each other to form a merged epitaxial source and drain feature.

[0032] Fig. 4 is a perspective, three-dimensional view of a FinFET device 400 (e.g., in an xyz plane) after it has undergone processing as described with reference to Fig. 2A-2E to form lightly doped source and drain regions according to various aspects of the present disclosure. The FinFET device 400 may be included in a microprocessor, a memory, and / or other integrated circuit device. In some implementations, the FinFET device 400 may be a portion of an IC chip, an SoC, or a portion thereof that includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, MOSFETs, CMOSs, BJTs, LDMOSs, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. The FinFET device 400 is similar in many respects to the FinFET device 200. Accordingly, for clarity and simplicity, similar features are shown in Fig. 2A-2E and Fig. 4 are designated by the same reference numerals. Fig. Figure 4 has been simplified for clarity to better understand the inventive concept of the present disclosure. Additional features may be added to FinFET device 400, and some of the features described below may be replaced, modified, or omitted in other embodiments of FinFET device 400.

[0033] Similar to the FinFET device 200, the FinFET device 400 includes the substrate 210 and the fin structure 220, which includes fins 222 extending from the substrate 210. In Fig. 4, the fins 222 extend from the substrate 210 in a z-direction such that the fins 222 have heights defined in the z-direction (such as height h), lengths defined in an x-direction, and widths and / or spacings defined in a y-direction (such as width w1, width w2, width w3, spacing S1, spacing S2, and spacing S3). Each fin 222 includes a channel region 402, a source region 404, and a drain region 406 defined along the length of the corresponding fins 222 (here along the x-direction), with the channel region 402 being arranged between the source region 404 and the drain region 406 (generally referred to as source / drain regions).Each channel region 402 includes a top portion defined between sidewall portions of a corresponding fin 222, the top portion and sidewall portions engaging a gate structure 410 (described in detail below) such that current can flow between a corresponding source region 404 and a corresponding drain region 406 during operation of the FinFET device 400. In . Fig. 4, the gate structure 410 blocks the view of the channel regions 402 of the fins 222. In some implementations, the top surface portion is a substantially horizontal side (e.g., substantially parallel to an xy plane) of the fins 222, while the two sidewall portions are substantially vertical sides (e.g., substantially parallel to an xz plane) of the fins 222.

[0034] The fabrication of the FinFET device 400 is similar to the fabrication of the FinFET device 200 described with reference to Fig. 2A-2E. However, prior to forming the doped amorphous layer 230, isolation feature(s) 420 are formed over and / or within the substrate 210 to isolate various regions, such as various device regions, of the FinFET device 400. For example, the isolation features 420 separate and insulate the fins 222 from each other. In the illustrated embodiment, the isolation features 420 surround a portion of the fin structure 220, such as a bottom portion of the fin structure 220. The isolation features 420 comprise silicon oxide, silicon nitride, silicon oxynitride, another suitable isolation material, or combinations thereof.The isolation features 420 may include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or local oxidation of silicon (LOCOS) structures. In some implementations, the isolation features 420 include STI features that define and electrically isolate the fin structures 220 from other active device regions and / or passive device regions. For example, STI features may be formed by etching trenches in the substrate 210 (e.g., using a dry etch process and / or a wet etch process) and filling the trench with insulator material (e.g., using a chemical vapor deposition process or a spin-on-glass process).A chemical mechanical polishing (CMP) process may be performed to remove excess insulator material and / or smooth a top surface of the isolation features 420. In another example, STI features may be formed by depositing an insulator material over the substrate 210 after forming the fin structure 220 (in some implementations such that the insulator material layer fills gaps (trenches) between the fins 222) and etching back the insulator material layer to form the isolation features 420. In some implementations, the STI features include a multi-layer structure that fills the trenches. For example, the STI features include a silicon nitride layer disposed over a thermal oxide cladding layer.In another example, the STI features include a dielectric layer disposed over a doped cladding layer (such as a boron silicate glass (BSG) cladding layer or a phosphosilicate glass (PSG) cladding layer). In yet another example, the STI features include a bulk dielectric layer disposed over a dielectric cladding layer, wherein the bulk dielectric layer and the dielectric cladding layer comprise materials that depend on design requirements.

[0035] Furthermore, in these implementations, prior to forming the doped amorphous layer 230, a gate structure 410 may be formed over the fin structure 220. The gate structure 410 encloses the channel regions 402 of the fins 222 and thereby engages the fins 222 and the source regions 404 and drain regions 406 disposed therebetween. In the illustrated embodiment, the gate structure 410 engages the top and sidewall portions of the channel regions 402 such that the gate structure 410 engages three sides of the channel regions 402. The gate structure 410 includes a dummy gate stack, portions of which may be replaced with a metal gate during a gate replacement process, as described in detail below. In the illustrated embodiment, the dummy gate stack includes a gate dielectric 430 and a gate electrode 432.The gate dielectric 430 is arranged between the gate electrode 432 and the fins 222, wherein the gate dielectric 430 and the gate electrode 432 are configured to enclose the fins 222 (in particular, the channel regions 402). The gate dielectric 430 comprises a dielectric material, such as silicon oxide, a high-K dielectric material, another suitable dielectric material, or combinations thereof. Examples of a high-K material include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, a hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-K dielectric materials, or combinations thereof. The gate electrode 432 comprises a suitable dummy gate material, such as polysilicon.The dummy gate stack may include numerous other layers, such as capping layers, interlayers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In some implementations, the dummy gate stack further includes an interlayer, such as a silicon oxide layer, disposed between the gate dielectric 430 and the gate electrode 432. In some implementations, a capping layer, such as a TiN capping layer, may be disposed between the gate dielectric 430 and the gate electrode 432.

[0036] The gate structure 410 is formed by deposition processes, lithography processes, etching processes, other suitable processes, or combinations thereof. For example, a deposition process may be performed to form a gate dielectric layer over the substrate 210, in particular over the fin structures 220 and the isolation features 420, and a deposition process may be performed to form a gate electrode layer over the gate dielectric layer. In some implementations, a deposition process is performed to form an interlayer over the substrate 210 before the gate dielectric layer is formed. The deposition processes include CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof.A lithography patterning and etching process may then be performed to pattern the gate dielectric layer and the gate electrode layer (and, in some implementations, the interlayer) to form the gate dielectric 430 and the gate electrode 432. The lithography patterning processes include resist coating (e.g., spin-on coating), soft bake, mask alignment, exposure, post bake, resist development, rinsing, drying (e.g., hard bake), other suitable processes, or combinations thereof. Alternatively, the lithography exposure process is supported, implemented, or replaced by other methods, such as maskless lithography, electron beam writing, or ion beam writing. In yet another alternative, the lithography patterning process implements nanoprinting technology. The etching processes include dry etching processes, wet etching processes, other suitable etching processes, or combinations thereof.

[0037] After forming the gate structure 410, lightly doped source and drain (LDD) features 450 are formed in the source region 404 and drain region 406 of the FinFET device 400. The LDD features 450 are similar to the doped feature 250 of the FinFET device 200 described above with reference to Fig. 2A-2E. For example, a doped amorphous layer is formed over the source region 404 and the drain region 406 of the fins 222, and a knock-on implantation process is performed on the doped amorphous layer to deliver dopant from the doped amorphous layer into the source region 404 and drain region 406. The knock-on implantation process also converts the doped amorphous layer into a portion of the fins 222 such that the LDD features 450 comprise a doped portion of the fins 222 and a converted (recrystallized) doped amorphous layer. In some implementations (such as the illustrated embodiment), a fin trimming process, as described above, is performed before the isolation feature 420 and / or the gate structure 410 is / are formed.Alternatively, in some implementations, the fin trimming process is performed after the isolation feature 420 and / or the gate structure 410 is / are formed such that a width of a top portion of the fins 222 (such as a portion of the fins 222 extending above the isolation feature 420) is less than a width of a bottom portion of the fins 222. Thereafter, the FinFET device 400 may undergo subsequent manufacturing, as described below.

[0038] Fig. 5 is a perspective, three-dimensional view of a FinFET device 500 (e.g., in an xyz plane) after undergoing processing as described with reference to Fig. 3A-3E to form lightly doped source and drain regions according to various aspects of the present disclosure. The FinFET device 500 may be included in a microprocessor, a memory, and / or other integrated circuit device. In some implementations, the FinFET device 500 may be a portion of an IC chip, an SoC, or a portion thereof that includes various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, MOSFETs, CMOSs, BJTs, LDMOSs, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. The FinFET device 500 is similar in many respects to the FinFET device 300 and the FinFET device 400. Accordingly, for clarity and simplicity, similar features are shown in Fig. 3A-3E, Fig. 4 and Fig. 5 are designated by the same reference numerals. Fig. Figure 5 has been simplified for clarity to better understand the inventive concept of the present disclosure. Additional features may be added to FinFET device 500, and some of the features described below may be replaced, modified, or omitted in other embodiments of FinFET device 500.

[0039] Similar to the FinFET device 300, the FinFET device 500 includes the substrate 210 and the fin structure 220, which includes fins 222 extending from the substrate 210. In Fig. 5, the fins 222 extend from the substrate 210 in a z-direction such that the fins 222 have heights defined in the z-direction (such as height h), lengths defined in an x-direction, and widths and / or spacings defined in a y-direction (such as width w1, width w4, spacing S1, and spacing S4). Each fin 222 includes a channel region 502, a source region 504, and a drain region 506 defined along the length of the corresponding fins 222 (here along the x-direction), with the channel region 502 being disposed between the source region 504 and the drain region 506 (generally referred to as source / drain regions).Each channel region 502 includes a top portion defined between sidewall portions of a corresponding fin 222, the top portion and sidewall portions engaging the gate structure 410 (described in detail above) such that current can flow between a corresponding source region 504 and a corresponding drain region 506 during operation of the FinFET device 500. In . Fig. 5, the gate structure 410 blocks the view of the channel areas 502 of the fins 222.

[0040] The fabrication of the FinFET device 500 is similar to the fabrication of the FinFET device 300 described with reference to Fig. 3A-3E. However, prior to forming the doped amorphous layer 230, similar to the FinFET device 400, isolation feature(s) 420 are formed over and / or in the substrate 210 to isolate various regions of the FinFET device 500, as described above. Similar to the FinFET device 400, prior to forming the doped amorphous layer 230, the gate structure 410 is also formed over the fin structure 220, as described above. After forming the gate structure 410, LDD features 550 are formed in the source region 504 and drain region 506 of the FinFET device 500. The LDD features 550 are similar to the doped feature 350 of the FinFET device 300, described above with reference to Fig.3A-3E. For example, a doped amorphous layer is formed over the source region 504 and the drain region 506 of the fins 222, and a knock-on implantation process is performed on the doped amorphous layer to introduce dopant from the doped amorphous layer into a portion of the source region 504 and drain region 506. The knock-on implantation process also converts a portion of the doped amorphous layer into a portion of the fins 222, such that the LDD features 550 comprise a doped portion of the fins 222 and a converted (recrystallized) portion of the doped amorphous layer. Thereafter, any remaining doped amorphous layer is removed, for example, by an oxidation removal process. Thereafter, the FinFET device 500 may undergo further processing.

[0041] The FinFET device 400 and / or the FinFET device 500 may undergo further processing. For example, spacers may be formed adjacent to the gate structure 410 (here, gate dielectric 430 and gate electrode 432). The spacers comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or combinations thereof. In some implementations, the spacers comprise a multi-layer structure, such as a silicon nitride layer and a silicon oxide layer. The spacers are formed by a suitable process. In some implementations, the spacers comprise more than one group of spacers, such as sealing spacers, offset spacers, dummy spacers, and / or main spacers formed adjacent to the dummy gate stack.In these implementations, the different groups of spacers may comprise materials having different etch rates. For example, a silicon oxide layer may be deposited over the fin structure 220 and subsequently anisotropically etched (e.g., dry etched) to form a first spacer group adjacent to the dummy gate stack, and a silicon nitride layer may be deposited over the fin structure 220 and subsequently etched (e.g., dry etched) to form a second spacer group adjacent to the first spacer group.

[0042] A gate replacement process may then be performed to replace the dummy gate stack of gate structure 410 with a gate, such as a metal gate stack. For example, an inter-level dielectric (ILD) layer may be formed over substrate 210, for example, by a deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof). The ILD layer comprises a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, borophosphosilicate glass (BPSG), a low-K dielectric material, another suitable dielectric material, or combinations thereof.Example low-K dielectric materials include fluorinated silica glass (FSG), carbon-doped silicon oxide, Black Diamond® (Applied Materials of Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB (bis-benzocyclobutene), SiLK (Dow Chemical, Midland, Michigan), polyimide, other suitable materials, or combinations thereof. In some implementations, the ILD layer may comprise a multilayer structure including multiple dielectric materials. After deposition of the ILD layer, a CMP process may be performed such that a top portion of the gate structure 410 is reached (exposed), such as a top portion of the gate electrode 432.A portion of the gate structure 410 (such as the gate electrode 432 and, in some implementations, the gate dielectric 430) is then removed, thereby forming a trench (recess) that may expose an interlayer and / or a gate dielectric (such as the gate dielectric 430). In some implementations, an etch process selectively removes the dummy gate electrode (and, in some implementations, a dummy gate dielectric). The etch process may be a dry etch process, a wet etch process, or combinations thereof. A targeted etch process may be tuned such that the dummy gate electrode layer has an appropriate etch rate relative to the interlayer, the spacers, and / or the ILD layer.

[0043] A metal gate stack of the gate structure 410 is then formed in the recess (trench). The metal gate stack includes a gate dielectric and a gate electrode (e.g., a work function layer and a metal fill layer). The metal gate stack of the gate structure 410 may include numerous other layers, such as cap layers, interlayers, diffusion layers, barrier layers, hard mask layers, or combinations thereof. In some implementations, a gate dielectric layer is formed over the interlayer, and a gate electrode layer (such as a work function fill layer and a metal fill layer) is formed over the gate dielectric layer. The gate dielectric layer includes a dielectric material, such as silicon oxide, a high-K dielectric material, another suitable dielectric material, or combinations thereof.Examples of a high-K dielectric material include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, a hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-K dielectric materials, or combinations thereof. In some implementations, the gate dielectric layer is a high-K dielectric layer. In some implementations where an interlayer is omitted from the dummy gate stack, the gate dielectric layer may include an interlayer (such as a silicon oxide layer) and a high-K dielectric layer disposed over the interlayer. The gate electrode comprises a conductive material such as polysilicon, Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, another conductive material, or combinations thereof.In some implementations, the work function layer is a conductive layer tuned to have a desired work function (such as an n-type work function or a p-type work function), and the metal fill layer is a conductive layer formed over the work function layer. In some implementations, the work function layer comprises n-type work function materials, such as Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. In some implementations, the work function layer comprises a p-type work function material, such as TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. The metal fill layer comprises a suitable conductive material such as aluminum, tungsten or copper.The metal fill layer may also or together comprise polysilicon, titanium, tantalum, metal alloys, other suitable materials, or combinations thereof. The gate dielectric layer, the work function layer, and the metal fill layer are formed by various deposition processes, such as ALD, CVD, PVD, and / or another suitable process. In some embodiments, the work function layer and the metal fill layer may correspond to exposed surfaces in the recess. A CMP process may be performed to remove excess material (such as any excess work function layer and / or any excess metal fill layer) and thereby smooth the gate structure 410.

[0044] In some implementations, additional source / drain features are formed in fins 222, such as heavily doped source and drain (HDD) features. In some implementations, epitaxial source features and epitaxial drain features (referred to as epitaxial source / drain features) are formed over LDD features 450 and / or LDD features 550. For example, in forming LDD features 450 and / or LDD features 550, an SEG process is performed to grow a semiconductor material on exposed portions of fins 222, thereby forming epitaxial source / drain features over source region 404 (and / or source region 504) and drain region 406 (and / or drain region 506). In some implementations, the epitaxial source / drain features enclose the source region 404 (and / or source region 504) and the drain region 406 (and / or drain region 506).The SEG process may implement CVD deposition methods (e.g., VPE, UHV-CVD, LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or combinations thereof. The SEG process may utilize gaseous precursors (e.g., Si-containing gases, such as SiH4, and / or Ge-containing gases, such as GeH4) and / or liquid precursors that interact with a composition of the fins 222. Dopants may be introduced into the SEG process such that the epitaxial source / drain features are doped in situ during the SEG process. For example, the epitaxial source / drain features are doped during deposition by adding dopants to a starting material of the SEG process.In some implementations where the FinFET device 400 and / or the FinFET device 500 is / are configured as an n-type device (e.g., having an n-channel), the epitaxial source / drain features comprise silicon or silicon-carbon, wherein the silicon or silicon-carbon is doped with phosphorus, arsenic, another n-type dopant, or combinations thereof (e.g., forming Si:P epitaxial layers or Si:C:P epitaxial layers). In some implementations where the FinFET device 400 and / or the FinFET device 500 is / are configured as a p-type device (e.g., having a p-channel), the epitaxial source / drain features comprise silicon germanium (SiGe), with the SiGe layers doped with boron, another p-type dopant, or combinations thereof (e.g., forming a Si:Ge:B epitaxial layer).In some implementations, the epitaxial source / drain features include materials and / or dopants that achieve a desired tensile and / or compressive stress in the channel region 402 and / or the channel region 502, depending on the design requirements.

[0045] Various contacts may be formed to facilitate the operation of FinFET device 400 and / or FinFET device 500. For example, an ILD layer may be formed over substrate 210 (in some implementations, a second ILD layer may be formed over a first ILD layer (formed during the gate replacement process)). Contacts may then be formed in the ILD layer(s). For example, one contact is electrically coupled to gate structure 410 (in particular, the gate electrode), one contact is electrically coupled to source region 404, and one contact is electrically coupled to drain region 406. The contacts comprise a conductive material, such as metal.Metals include aluminum, an aluminum alloy (such as an aluminum / silicon / copper alloy), copper, a copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, a metal silicide, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some implementations, the ILD layer(s) and contacts (extending through the ILD layer(s), for example, are a portion of a multilayer interconnect (MLI) feature disposed over the substrate 210.The MLI feature electrically couples various components of the FinFET device 400 and / or the FinFET device 500 such that the various components are operable to function as specified by the design requirements for the FinFET device 400 and / or the FinFET device 500. The MLI feature may include a combination of metal layers and ILD layers configured to form vertical interconnect features, such as contacts and / or vias, and / or horizontal interconnect features, such as lines. The various conductive features include materials similar to the contacts. In some implementations, a damascene process and / or a dual-damascene process is / are used to form a copper-based multilayer interconnect structure.

[0046] The present disclosure contemplates many different embodiments. An example method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to deliver a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer comprises a non-crystalline form of a fin structure material. In some implementations, the fin structure comprises a crystal material, and the knock-on implantation process converts at least a portion of the doped amorphous layer to the crystal material (e.g., by crystallizing the portion of the doped amorphous layer) such that the portion of the doped amorphous layer becomes part of the fin structure.In some implementations, the fin structure comprises silicon, and the doped amorphous layer comprises amorphous silicon, such that the knock-on implantation process crystallizes at least a portion of the amorphous silicon.

[0047] In some implementations, the method further comprises performing a fin trimming process to reduce a dimension of the fin structure before forming the doped amorphous layer. In some implementations, a thickness of the doped amorphous layer is approximately equal to a thickness of the fin structure removed during the fin trimming process, and the knock-on implantation process causes the doped amorphous layer to become part of the fin structure. In some implementations, the knock-on implantation process causes a portion of the doped amorphous layer to become part of the fin structure. In these implementations, the method further comprises oxidizing a remaining portion of the doped amorphous layer and removing the oxidized portion of the doped amorphous layer.

[0048] In some implementations, the doped amorphous layer is formed on a source region and a drain region of the fin structure, and the doped feature is a lightly doped source and drain (LDD) region disposed in the source region and drain region of the fin structure. In some implementations, the method further comprises forming a gate structure over a channel region of the fin structure before forming the doped amorphous layer. In some implementations, the knock-on implantation process uses argon ions to transfer the dopant from the doped amorphous layer into the portion of the fin structure.

[0049] Another exemplary method includes forming a fin structure, forming a doped amorphous silicon layer over a portion of the fin structure, and performing a knock-on implantation process to deliver a dopant from the doped amorphous silicon layer into the portion of the fin structure, thereby forming a doped feature. In some implementations, the doped amorphous silicon layer encloses a source region and a drain region of the fin structure, and the doped feature is a lightly doped source and drain (LDD) region disposed in the source region and the drain region. In some implementations, forming the doped amorphous silicon layer includes epitaxially growing a semiconductor material over the portion of the fin structure, wherein the semiconductor material is doped in situ during the epitaxial growth.

[0050] In some implementations, the method further comprises reducing a width of the fin structure before forming the doped amorphous silicon layer. In these implementations, a thickness of the doped amorphous layer is approximately equal to an amount of the fin structure that is removed when the width of the fin structure is reduced, and the knock-on implantation process causes the doped amorphous silicon layer to become part of the fin structure. In some implementations, the knock-on implantation process causes a portion of the doped amorphous silicon layer to become part of the fin structure. In these implementations, the method further comprises oxidizing a remaining portion of the doped amorphous silicon layer and removing the oxidized portion of the doped amorphous silicon layer.

[0051] Yet another exemplary method includes forming a fin structure. The fin structure includes a channel region defined between a source region and a drain region. The fin structure further includes a material having a crystalline structure. The method further includes forming a gate structure over the channel region of the fin structure. The method further includes forming a doped layer over the source region and the drain region of the fin structure. The doped layer includes the material having a non-crystalline structure. The method further includes performing a knock-on implantation process to introduce a dopant from the doped layer into the source region and the drain region of the fin structure, wherein the knock-on implantation process converts a portion of the doped layer into the material having the crystalline structure.

[0052] In some implementations, the knock-on implantation process forms a lightly doped source and drain (LDD) region, wherein a doped portion of the fin structure and at least a portion of the doped layer form the LDD region. In some implementations, the method further comprises performing a fin trimming process to reduce a dimension of the source region and the drain region of the fin structure before forming the doped layer, wherein the entire doped layer becomes part of the LDD region. In some implementations, the method further comprises removing any remaining portion of the doped layer. In some implementations, the fin structure comprises silicon, and the doped layer comprises amorphous silicon, such that the knock-on implantation process crystallizes at least a portion of the amorphous silicon.

Claims

[1] Method comprising: Formation of a fin structure (222); Forming a doped amorphous layer (230) over a portion of the fin structure (222); and Performing a knock-on implantation process (240) to transfer a dopant from the doped amorphous layer (230) into the portion of the fin structure (222) and thereby form a doped feature (250), wherein the knock-on implantation process (240) causes a portion of the doped amorphous layer (230) to become part of the fin structure (222), the method further comprising: oxidizing a remaining portion of the doped amorphous layer (230); and Removing the oxidized portion of the doped amorphous layer (230). [2] The method of claim 1, wherein the knock-on implantation process (240) converts at least a portion of the doped amorphous layer (230) into a crystal material such that the portion of the doped amorphous layer (230) becomes part of the fin structure (222). [3] The method of claim 1 or 2, wherein the fin structure (222) comprises silicon and the doped amorphous layer (230) comprises amorphous silicon, and further wherein the knock-on implantation process (240) crystallizes at least a portion of the amorphous silicon. [4] The method of any preceding claim, further comprising performing a fin trimming process to reduce a dimension of the fin structure (222) before forming the doped amorphous layer (230). [5] The method of claim 4, wherein a thickness of the doped amorphous layer (230) is approximately equal to a thickness of the fin structure (222) removed during the fin trimming process, and further wherein the knock-on implantation process (240) causes the doped amorphous layer (230) to become part of the fin structure (222). [6] The method of any preceding claim, wherein the doped amorphous layer is formed on a source region and a drain region of the fin structure (222) and the doped feature is a lightly doped source and drain (LDD) region disposed in the source region and the drain region of the fin structure (222). [7] The method of claim 6, further comprising forming a gate structure (410) over a channel region (204) of the fin structure (222) before forming the doped amorphous layer (230). [8] The method of any preceding claim, wherein the knock-on implantation process (240) uses argon ions to transfer the dopant from the doped amorphous layer (230) into the portion of the fin structure (222). [9] Method comprising: Formation of a fin structure (222); Forming a doped amorphous silicon layer (230) over a portion of the fin structure (222); and Performing a knock-on implantation process (240) to transfer a dopant from the doped amorphous silicon layer (230) into the portion of the fin structure (222) and thereby form a doped feature (250), wherein the knock-on implantation process (240) causes a portion of the doped amorphous silicon layer (230) to become part of the fin structure (222), the method further comprising: oxidizing a remaining portion of the doped amorphous silicon layer (230); and Removing the oxidized portion of the doped amorphous silicon layer (230). [10] The method of claim 9, further comprising reducing a width of the fin structure (222) before forming the doped amorphous silicon layer (230). [11] The method of claim 10, wherein a thickness of the doped amorphous silicon layer (230) is approximately equal to an amount of the fin structure (222) that is removed when the width of the fin structure (222) is reduced, and further wherein the knock-on implantation process (240) causes the doped amorphous silicon layer (230) to become part of the fin structure (222). [12] The method of any one of the preceding claims 9 to 11, wherein the doped amorphous silicon layer (230) encloses a source region (404) and a drain region (406) of the fin structure (222) and the doped feature (250) is a lightly doped source and drain (LDD) region disposed in the source region (404) and the drain region (406). [13] The method of any one of the preceding claims 9 to 12, wherein forming the doped amorphous silicon layer (230) comprises epitaxially growing a semiconductor material over the portion of the fin structure (222), wherein the semiconductor material is doped in situ during the epitaxial growth. [14] Method comprising: Forming a fin structure (222), the fin structure (222) comprising a channel region (402) defined between a source region (404) and a drain region (406); Forming a gate structure (410) over the channel region (402) of the fin structure (222); Forming a doped layer (230) over the source region (404) and the drain region (406) of the fin structure (222), wherein the doped layer (230) comprises a material having a non-crystalline structure; and Performing a knock-on implantation process (240) to introduce a dopant from the doped layer (230) into the source region (404) and the drain region (406) of the fin structure (222), wherein the knock-on implantation process (240) converts a portion of the doped layer (230) into a material having a crystal structure, wherein the knock-on implantation process (240) causes the material having the crystal structure to become part of the fin structure (222), the method further comprising: oxidizing a remaining portion of the doped layer (230); and Removing the oxidized portion of the doped layer (230). [15] The method of claim 14, wherein the knock-on implantation process (240) forms a lightly doped source and drain (LDD) region, wherein a doped portion of the fin structure (222) and at least a portion of the doped layer (230) form the LDD region. [16] The method of claim 15, further comprising performing a fin trimming process to reduce a dimension of the source region (404) and the drain region (406) of the fin structure (222) before forming the doped layer (230), wherein the entire doped layer (230) becomes part of the LDD region. [17] The method of claim 15 or 16, further comprising removing any remaining portion of the doped layer (230). [18] The method of any one of the preceding claims 14 to 17, wherein the doped layer (230) comprises amorphous silicon, and further wherein the knock-on implantation process (240) crystallizes at least a portion of the amorphous silicon.

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