Static direct access memory with a write-assisted circuit

Abstract

Write support circuit (110), comprising: a control circuit (320) designed to receive a first and a second memory address information (112) associated with a memory write operation (116) for one or more memory cells (190), wherein the first and the second memory address information comprise a row position of the one or more memory cells (190), and a voltage generator (370) designed to provide a reference voltage (118) to one or more bit lines (BL) coupled to the one or more memory cells (190), the voltage generator (370) comprising: a first capacitive element (362), and a second capacitive element (346), wherein during the memory write operation, based on the first memory address information (112), the first capacitive element (362) is designed such that it couples the reference voltage (118) with a first negative voltage (362), and Based on the second memory address information (112), the first and second capacitive elements are designed to cumulatively couple the reference voltage (118) with a second negative voltage (346, 362) that is lower than the first negative voltage (362).

Description

STATE OF THE ART

[0001] Static random-access memory (SRAM) is a type of semiconductor memory used in computing applications that require, for example, high-speed data access. Cache memory applications, for instance, use SRAM to store frequently accessed data—such as data accessed by a central processing unit.

[0002] The SRAM cell structure and architecture enable high-speed data access. An SRAM cell comprises a bistable flip-flop structure, typically containing four to six transistors. An SRAM architecture can include one or more arrays of memory cells and supporting circuitry. Each SRAM array is arranged in rows and columns, referred to as "word lines" and "bit lines," respectively. The supporting circuitry includes addressing and driver circuitry to access each SRAM cell—via the word lines and bit lines—for various SRAM operations.

[0003] US2017 / 0117034 A1 concerns a write-assist circuit to help a storage device change logical states during a write operation.

[0004] US2014 / 0219009 A1 concerns embodiments of a memory that can enable negative gain of the data lines during writing. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The invention is defined by the subject matter of the independent claims. The dependent claims relate to corresponding embodiments. Aspects of the present disclosure are best understood from the detailed description below when read together with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be enlarged or reduced as desired for clarity of discussion. Fig. Figure 1 is a representation of a static direct access memory with a write-support circuit according to some embodiments of the present disclosure. Fig. Figure 2 is a representation of an example of a static random access memory topology. Fig. Figure 3 is a representation of a write support circuit, a column multiplexer and a write driver circuit of a static random access memory according to some embodiments of the present disclosure. Fig. Figure 4 is a representation of example signal waveforms for a write-support circuit according to some embodiments of the present disclosure. Fig. Figure 5 is a description of a method for a memory write operation according to some embodiments of the present disclosure. Fig. Figure 6 is a representation of a static random access memory with an auxiliary bit line topology and a write support circuit according to some embodiments of the present disclosure. Fig. Figure 7 is a representation of a write support circuit, a column multiplexer and a write driver circuit of a static random access memory with an auxiliary bit line topology according to some embodiments of the present disclosure. Fig. Figure 8 is a representation of a method for a memory write operation performed on a static random access memory with an auxiliary bit line topology and a write support circuit, according to some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments, or examples, for implementing various features of the present subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are merely examples and are not intended to be limiting. Furthermore, the present disclosure repeats reference numbers and / or letters in the various examples. This repetition is done for the sake of simplicity and clarity and, unless otherwise stated, does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] The following disclosure describes aspects of a static random-access memory (SRAM). In particular, the disclosure describes various embodiments related to an SRAM memory write operation. For the sake of clarity, certain SRAM circuit elements and control logic are disclosed to facilitate the description of the different embodiments. A person skilled in the art will understand that SRAMs may also include other circuit elements and control logic. These other circuit elements and control logic are within the scope of the invention and the scope of this disclosure.

[0008] Fig. Figure 1 is a representation of a static random access memory (SRAM) 100 with a write-assist circuit 110 according to some embodiments of the present disclosure. The SRAM 100 comprises a row decoder 120, a word line driver 130, a column decoder 140, a column multiplexer (MUX) 150, a write driver circuit 160, and an SRAM array 180. The SRAM array 180 comprises columns of SRAM cells 170. o up to 170 N In some embodiments, as in Fig. Figure 1 shows the write support circuit 110, the column MUX 150 and the write driver circuit 160 arranged approximately near a lower section of the SRAM array 180.

[0009] Each of the SRAM cells in the SRAM array 180 is accessed—for example, for memory read and write operations—using a memory address. Based on the memory address, the row decoder 120 selects a row of memory cells, which is then accessed via the word line driver 130. Similarly, based on the memory address, the column decoder 140 selects a column of memory cells 170. o up to 170 N , which is accessed via the write support circuit 110 and the column MUX 150, according to some embodiments of the present disclosure. In some embodiments, the write driver circuit 160 generates voltages for bit line pairs BL / BLB in columns of the memory cells 170. O up to 170 NThe notation "BL" refers to a bit line, and the notation "BLB" refers to the complement of "BL"; the bit line pair concept BL / BLB is well known in engineering. The intersection of the access row and the access column of memory cells leads to access to a single memory cell 190.

[0010] Each of the columns of memory cells 170 o up to 170 N The SRAM array comprises 190 memory cells. A person skilled in the art will understand that the 190 memory cells can be arranged in one or more arrays within the SRAM 100. In the present disclosure, a single SRAM array 180 is shown to simplify the description of the disclosed embodiments. The SRAM array 180 has a number of "M" rows and a number of "N" columns. The notation "190 OO “ refers to memory cell 190, located in row '0', column 170 ois arranged. Similarly, the notation "190" refers to MN “to a memory cell 190, located in row 'M', column 170 N is arranged.

[0011] As the average expert will understand, a memory cell can have 190 different circuit topologies. For example, a memory cell can have a "6T" circuit topology. Fig. Figure 2 is a representation of an example of a 6T circuit topology for a memory cell 190. The 6T circuit topology comprises n-channel metal-oxide-semiconductor (NMOS) pass devices 220 and 230, NMOS pulldown devices 240 and 250, and p-channel metal-oxide-semiconductor (PMOS) pullup devices 260 and 270. A voltage from the word line driver 130 controls NMOS devices 220 and 230 to transmit voltage from the bit line pair BL / BLB to a bistable flip-flop structure formed by the NMOS devices 240 and 250 and the PMOS devices 260 and 270. The voltages of the bit line pair BL / BLB can be used during a memory write operation. For example, if BL is at '1' or a logically high value (e.g., a supply voltage V), DDIf the voltage (e.g., 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, or any combination thereof) and BLB is at '0' or a logic low value (e.g., ground or 0V), the voltage applied by the word line driver 130 to the gate terminals of the NMOS pass devices 220 and 230 can be at a sufficient voltage level to transmit the logic high value of BL and the logic low value of BLB to the bistable flip-flop structure. Consequently, these logic values ​​are written (or programmed) into the bistable flip-flop structure.

[0012] Fig. Figure 3 is a representation of the write-assist circuit 110, the column MUX 150, and the write-drive circuit 160 according to some embodiments of the present disclosure. The write-assist circuit 110 comprises a control circuit 320, a voltage generator 370, and a pull-down device 380.

[0013] The control circuit 320 controls the operation of the voltage generator 370 and the pulldown device 380. During a memory write operation, for example, the control circuit 320 can supply a reference voltage – which is supplied, for example, to the write driver circuit 160. Fig. 1 is provided - with a first negative voltage via the voltage generator 370 and / or the pulldown device 380. Based on memory address information, the control circuit 320 can cumulatively couple the reference voltage with a second negative voltage, which is lower than the first negative voltage, via the voltage generator 370. As described below, the different reference voltages can couple weaker NMOS pass devices (e.g., NMOS pass devices 220 and 230) in an SRAM cell (e.g., memory cell 190 of Fig. 2) compensate.

[0014] The control circuit 320 comprises latching circuits 302 and 304, a pulse generator 306, inverter logic devices 330 to 340 and 352 to 356, and a NAND logic device 350. From the foregoing description, a person skilled in the art will recognize that the number and type of logic devices in the control circuit 320 are not limiting, and that a different number and type of logic devices can be used to implement the control circuit 320, for example, based on its operation and a desired signal propagation delay. In some embodiments, the control circuit 320 receives the following signals as inputs: a line signal 112, an NBL activation signal (NBL: negative bit line) 114, and a pulse activation signal 116.

[0015] The line signal 112 indicates the position of a memory cell 190 in the SRAM array 180 that is undergoing a memory write operation, according to some embodiments of the present disclosure. In some embodiments, the SRAM array 180 can be divided into two sections: an upper section and a lower section. For example, the SRAM array 180 can have 1024 lines - i.e., M = 1024 (2 10 ) exhibit. With reference to Fig. 1. The upper section of the SRAM array 180 can be defined by memory cells 190 in rows '0' to '511', and the lower section of the SRAM array 180 can be defined by memory cells 190 in rows '512' to '1024'. Based on the description given, a person skilled in the art will recognize that the SRAM array 180 can have a different number of rows (e.g., more or less than 1024 rows) and can be divided in different ways (e.g., into more than 2 sections, into sections with different numbers of rows, or a combination thereof).

[0016] In some embodiments, the line signal 112 can represent a most significant bit of a binary representation of a line position. For example, for the SRAM array 180 with 1024 lines, the binary representation of line '400' is [0110010000], where the most significant bit is '0'. In some embodiments, a most significant bit of '0' represents a line in the upper section of the SRAM array 180. In another example, the binary representation of line '1000' is [1111101000], where the most significant bit is '1'. In some embodiments, a most significant bit of '1' represents a line in the lower section of the SRAM array 180.

[0017] In a control circuit 320, according to some embodiments of the present disclosure, the interlocking circuit 302 receives the line signal 112, stores the line signal 112, and outputs an inverted representation of the line signal 112 (e.g., either '0' or '1'). For example, if the line signal 112 is '0' (e.g., representing a line in the upper section of the SRAM array 180), then the interlocking circuit 302 outputs '1' or a logic high value. Conversely, if the line signal 112 is '1' (e.g., representing a line in the lower section of the SRAM array 180), then the interlocking circuit 302 outputs '0' or a logic low value. The output of the interlocking circuit 302 is transmitted to the output of the inverter logic device 340 via the inverter logic devices 330 to 340.

[0018] In the control circuit 320, the interlocking circuit 304 receives the NBL activation signal 114, and the pulse generator 306 receives the pulse activation signal 116. The NBL activation signal 114 activates an NBL voltage during a memory write operation according to some embodiments of the present disclosure. The pulse activation signal 116, according to some embodiments of the present disclosure, activates the pulse generator 306 to provide a pulse signal to indicate a duration for the memory write operation.

[0019] When the NBL activation signal 114 is '0' or a logic low, the latching circuit 304 outputs a '1' or a logic high, which is provided as an input to the NAND logic device 350. When the pulse activation signal 116 is '1' or a logic high, the pulse generator 306 is activated and changes its output from '0' to '1' (e.g., from a logic low to a logic high), which is provided as another input to the NAND logic device 350. When both inputs to the NAND logic device 350 are '1' or a logic high, the output of the inverter logic device 346 is also '1' or a logic high.

[0020] The reference voltage 118 is received by the write driver circuit 160 as a reference voltage with a low voltage potential according to some embodiments of the present disclosure. In some embodiments, the write driver circuit 160 comprises level-shift devices 162 and 164, each of which receives the reference voltage 118. When either the level-shift device 162 or 164 receives a logic-low input, the level-shift device outputs a logic-high value (e.g., a supply voltage V). DD the inverter logic device outputs a voltage such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, or any combination thereof. Conversely, if a logic high input is received by either the level shifter device 162 or 164, the level shifter device outputs the reference voltage 118.

[0021] According to some embodiments of this disclosure, the reference voltage 118 can be ground (e.g., 0 V), a negative voltage (e.g., -100 mV, -200 mV, or -300 mV), or a combination thereof. In some embodiments, the reference voltage is initially pulled down to ground by the pulldown device 380. In some embodiments, the pulldown device 380 can be an NMOS transistor that, based on a voltage potential applied to the gate terminal of the NMOS transistor—e.g., the output of the inverter logic device 356 from the control circuit 320—sends ground to the reference voltage 118. For example, if the NBL activation signal 114 is at '0' or a logic low, and the pulse activation signal 116 is at '1' or a logic high, the output of the inverter logic device 356 will also be at '1' or a logic high.The gate terminal of the pulldown device 380 is activated, thereby pulling a reference voltage 118 towards ground or 0 V. As discussed above, when a logic high input is received by either the level shifter device 162 or 164, the inverter logic device outputs the reference voltage 118 or, for example, ground (e.g., 0 V).

[0022] In some embodiments, the voltage generator 370 can "pull" the reference voltage 118 from ground to a negative voltage level. According to some embodiments, the voltage generator 370 comprises an NBL initialization coupling circuit 372 and an NBL tuning coupling circuit 374. The NBL initialization coupling circuit 372 comprises inverter logic devices 358 and 360 and a capacitive element 362. The NBL tuning coupling circuit 374 comprises a NAND logic device 342, an inverter logic device 344, and a capacitive element 346. In some embodiments, the capacitive elements 362 and 364 can be a capacitor, a capacitive circuit (e.g., with one or more circuit elements configured to have capacitive or capacitor functionality), or a combination thereof.Based on the description provided, a person skilled in the art will recognize that the number and type of logic devices in the NBL initialization coupling circuit 372 and the NBL tuning coupling circuit 374 are not limiting, and that a different number and other types of logic devices may be used to implement the NBL initialization coupling circuit 372 and the NBL tuning coupling circuit 374.

[0023] When the reference voltage 118 is at ground, the output of the inverter logic device 356 is '1' or a logic high, as discussed above. The output of the inverter logic device 360 ​​in the NBL initialization coupling circuit 372 is also '1' or a logic high. At these voltages, one plate of the capacitive element 362 at a circuit node 361—that is, between the inverter logic device 360 ​​and the capacitive element 362—is at the logic high, and another plate of the capacitive element 362—e.g., a capacitor plate electrically connected to the reference voltage 118—is at ground. Therefore, a voltage potential corresponding to the logic high (e.g., a supply voltage V) is present across the capacitive element 362. DD , such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V or any combination thereof) is equivalent.

[0024] When a memory cell 190 in the upper section of the SRAM array 180 (e.g., an SRAM cell in rows '0' to '511' in an SRAM array with 1024 rows) undergoes a memory write operation, in some embodiments the row signal 112 may be '1' or a logic high, which is transmitted to an input of the NAND logic device 342 via the inverter logic devices 330 to 340. And since the other input of the NAND logic device 342 is '1' or a logic high (e.g., the logic high output of the inverter logic device 356), the output of the NAND logic device 342 is '0' or a logic low. The output from the NAND logic device 342 generates a '1' or a logic high value at an output of the inverter logic device 344. At these voltages, a plate of the capacitive element 346 is connected to a circuit node 345.Between the inverter logic device 344 and the capacitive element 346 – at the logic high value – and another plate of the capacitive element 346 – e.g., a capacitor plate electrically connected to the reference voltage 118 – is connected to ground. Therefore, a voltage potential exists across the capacitive element 346 that corresponds to the logic high value (e.g., a supply voltage V). DD , such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V or any combination thereof) is equivalent.

[0025] Fig. Figure 4 is a representation of example signal waveforms for a write-assist circuit 110 according to some embodiments of the present disclosure. As an example and not a limitation, it shows Fig. Four waveforms for the NBL activation signal 114, circuit nodes 345 and 361, and the reference voltage 118. During the memory write operation, these example waveforms assume that the pulse activation signal 116 is at a '1' or a logic high, thereby activating the pulse generator 306 and transitioning its output from a '0' to a '1' (e.g., from a logic low to a logic high). Furthermore, the example waveforms assume that a memory cell in the upper section of the SRAM array 180 is being written. Fig. 1 is subjected to a memory write operation in which the line signal 112 is at a '1' or a logically high value.

[0026] From time 0 to time t1, the NBL activation signal 114 is at '0' or a low logic value. Circuit nodes 345 and 361, on the other hand, are at '1' or a high logic value (e.g., a supply voltage V). DD , such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V or any combination thereof). Furthermore, when the NBL activation signal 114 is at '0', the output of the inverter logic device 356 is at '1' or a logic high, thus activating the pulldown device 380 and sending ground (e.g., 0V) to the reference voltage 118.

[0027] At time t1, the NBL activation signal 114 changes from '0' to '1' (e.g., from a logical low to a logical high value). With reference to Fig. 3. When the NBL activation signal 114 transitions from '0' to '1', the output of the inverter logic device 356 changes from '1' to '0' (e.g., from a logic high to a logic low value), thus deactivating the pulldown device 380. Without being pulled to ground by the pulldown device 380, the reference voltage 118 floats at a voltage level near or at ground.

[0028] At time t2, due to a transition of the NBL activation signal 114 from '0' to '1', circuit nodes 345 and 361 also transition from '1' to '0' (e.g., from a logic high value to a logic low value). With reference to Fig. 3. The delay between time t1 and time t2 can be attributed to propagation delay times, which are set by the inverter logic devices 358 and 360 in the NBL initialization coupling circuit 372 and the NAND logic device 342 and the inverter logic device 345 in the NBL tuning coupling circuit 374. As a result of a transition of the circuit nodes 345 and 361 from '1' to '0', the reference voltage 118 is capacitively coupled to a negative voltage (e.g., -100 mV, -200 mV, or -300 mV). The “depression” in the reference voltage 118 is due to an initial charge coupling effect between the capacitive elements 346 / 362 and a capacitive load associated with a bit line pair BL / BLB, which is accessed during the memory write operation.

[0029] In some embodiments, a memory cell is located in the lower section of the SRAM array 180 by Fig. The memory write operation is performed in which the line signal 112 is at a '0' or a logic high. When circuit nodes 345 and 361 transition from '1' to '0' at time t2, the reference voltage 118 is capacitively coupled to a negative voltage in this example. However, this negative voltage is higher than the negative voltage generated when the line signal 112 is at a '1' due to a lower charge coupling effect generated by capacitive element 362 (compared to the charge coupling effect generated by both capacitive elements 436 and 362 when the line signal 112 is at a '1').

[0030] In some embodiments, the size of the capacitive elements 346 and 362 can vary or be the same. According to some embodiments of the present disclosure, the size of the capacitive elements 346 and 362 can depend on a desired charge coupling ratio between the capacitive elements 346 and 362 and an associated parasitic bit line capacitance (e.g., the parasitic capacitances 2141 to 214). M in Fig. 2) depend. As an average expert would understand, based on the size of the capacitive elements 346 and 362, a desired negative voltage can be generated by the voltage generator 370. Fig. 3 will be achieved.

[0031] Based on the description provided, an average professional will recognize that the SRAM array 180 of Fig. 1 can be divided into more than two sections. For example, the SRAM array 180 can be divided into four sections, where each section is a quadrant. For the SRAM array 180 with 1024 rows, the first quadrant can be defined by memory cells 190 in rows '0' to '255', the second quadrant can be defined by memory cells 190 in rows '256' to '511', the third quadrant can be defined by memory cells 190 in rows '512' to '767', and the fourth quadrant can be defined by memory cells 190 in rows '768' to 102.4'. In some embodiments, with reference to Fig. 3 the NBL initialization coupling circuit 372 can be associated with the fourth quadrant of the memory cells 190, the NBL tuning coupling circuit 374 can be associated with the first quadrant of the memory cells 190, another NBL initialization coupling circuit can be associated with the second quadrant of the memory cells 190, and yet another NBL tuning coupling circuit can be associated with the third quadrant of the memory cells 190.

[0032] Similar to the interlocking circuit 302 associated with the NBL tuning coupling circuit 374, interlocking circuits can be associated with the NBL tuning coupling circuits for the second and third quadrants of the memory cells 190. For example, when a SRAM cell in the third quadrant undergoes a memory write operation, a bit of a binary representation of a row position associated with SRAM cells in the third quadrant can be received by the interlocking circuit for the associated NBL tuning coupling circuit. If this bit (associated, for example, with rows in the third quadrant) is a '1', then the NBL tuning coupling circuit can be activated and capacitively couple the reference voltage 118 with a negative voltage when the NBL activation signal 114 transitions from '0' to '1'.In some embodiments, the charge coupling effect on the reference voltage 118 can be generated by the capacitive element 362 in the NBL initialization coupling circuit 372 and the capacitive element in the NBL tuning coupling circuit for the third quadrant. Due to this cumulative capacitive coupling, the reference voltage 118 during the memory write operation is at a more negative voltage for memory cells in the third quadrant (e.g., -200 mV) than for memory cells in the fourth quadrant (e.g., -100 mV).

[0033] When an SRAM cell in the second quadrant undergoes a memory write operation, a bit of a binary representation of a row position associated with SRAM cells in the second quadrant can be received by the interlocking circuit for the associated NBL tuning coupling circuit. If this bit (associated, for example, with rows in the second quadrant) is a '1', then the NBL tuning coupling circuit can be activated and capacitively couple the reference voltage 118 with a negative voltage when the NBL activation signal 114 transitions from '0' to '1'. In some embodiments, if the bit is a '1', the NBL tuning circuit for the third quadrant can also be activated.Consequently, the charge coupling effect on the reference voltage 118 can be generated by the capacitive element 362 in the NBL initialization coupling circuit 372, the capacitive element in the NBL tuning coupling circuit for the third quadrant, and the capacitive element in the NBL tuning coupling circuit for the second quadrant. Due to this cumulative capacitive coupling, the reference voltage 118 during the memory write operation is at a more negative voltage for memory cells in the second quadrant (e.g., -300 mV) than for memory cells in the third quadrant (e.g., -200 mV).

[0034] When an SRAM cell in the first quadrant undergoes a memory write operation, a bit of a binary representation of a row position associated with SRAM cells in the first quadrant can also be received by the interlocking circuit 302 for the associated NBL tuning coupling circuit 374. If this bit (associated, for example, with rows in the first quadrant) is a '1', then the NBL tuning coupling circuit 374 can be activated and capacitively couple the reference voltage 118 with a negative voltage when the NBL activation signal 114 transitions from '0' to '1'. In some embodiments, if the bit is a '1', the NBL tuning circuits for the second and third quadrants can also be activated.Consequently, the charge coupling effect on the reference voltage 118 can be generated by the capacitive element 362 in the NBL initialization coupling circuit 372, the capacitive element in the NBL tuning coupling circuit for the third quadrant, the capacitive element in the NBL tuning coupling circuit for the second quadrant, and the capacitive element 346 in the NBL tuning coupling circuit 374. Due to this cumulative capacitive coupling, the reference voltage 118 during the memory write operation is at a more negative voltage for memory cells in the first quadrant (e.g., -400 mV) than for memory cells in the second quadrant (e.g., -300 mV).

[0035] One advantage of providing different negative voltages to the different sections of the SRAM array 180 includes, among other things, balancing out parasitic elements in the BL / BLB bit line pair. Fig. Figure 2 shows an example of a parasitic bitline model 210 and a memory cell 190. The parasitic bitline model 210 is presented for illustrative purposes in relation to the bitline BL. An average person will recognize, based on the present description, that the bitline BLB may exhibit a similar parasitic bitline model. A network of resistive elements 212 O up to 212 M and capacitive elements 2141 to 214 M(e.g., capacitors, capacitive circuits, or a combination thereof) represents the parasitic bitline model 210. Each resistive element 212 represents a path resistance of the bitline BL between two SRAM cells along a column of memory cells. Each capacitive element 214 represents a parasitic capacitance associated with a passgate in each SRAM cell—e.g., a parasitic capacitance associated with transistor 220 in memory cell 190—along the column of memory cells.

[0036] During a memory write operation, an addressed SRAM cell located at a greater distance from a write driver circuit – e.g., memory cell 190 – can be accessed. ON in Fig. 1- Receives a bit line voltage that differs from its intended voltage level. This can be due to a voltage difference between the voltage at the output of the write driver circuit (e.g., the write driver circuit 160 of Fig. 1) and the voltage at the bit line position associated with the addressed SRAM cell. This voltage difference can be attributed to the bit line path resistance between the write driver circuitry and the addressed SRAM cell.

[0037] With reference to Fig. 2 model the resistance elements 212 O up to 210 M the bit path resistance. If the write driver circuit outputs 0 V to the bit line BL, the voltage at an addressed memory cell 190 – which is located, for example, at a greater distance from the write driver circuit, such as in the upper section of the SRAM array 180 – can be... Fig. 1, arranged - due to the IR voltage drop (current * resistance) across the resistance elements 212 O up to 212 M...greater than 0 V. This voltage drop leads to an unintended rise in voltage at the bit line position associated with the addressed SRAM cell. This unintended voltage rise—e.g., voltage greater than 0 V—degrades the memory write operation of the SRAM cell because the bistable flip-flop structure of the SRAM cell may not be able to track its voltage level to the intended voltage—i.e., the write circuit output voltage. In other words, the unintended voltage rise can prevent the SRAM cell from changing state. Advanced process technologies further exacerbate the effects of this IR voltage drop because the parasitic bit line resistance increases when advanced process technologies reduce the physical dimensions of the bit line.Furthermore, increases in density in SRAM arrays also amplify the effects of IR voltage drop, as the bit line length increases when SRAM arrays grow.

[0038] The write support circuit - e.g., the write support circuit 110 from Fig. 1, which is described above, and the write support circuit 610 of Fig. 6, which is described below, compensates for the IR voltage drop in the bit lines. For addressed SRAM cells—especially those cells located further away from the write driver circuitry (e.g., memory cell 190)—this is particularly important. ON in Fig. 1) The write assist circuitry "pulls" the voltage level at the bit line position associated with the addressed SRAM cell closer to a predetermined voltage level. For example, if there is a 200 mV bit line IR drop between the output of the write driver circuitry and an addressed SRAM cell, the reference voltage output by the write driver circuitry can be set to, for example: (i) -300 mV, so that the bit line voltage at the addressed SRAM cell is close to or at -100 mV; (ii) -400 mV, so that the bit line voltage at the addressed SRAM cell is close to or at -200 mV; (iii) -500 mV, so that the bit line voltage at the addressed SRAM cell is close to or at -300 mV; (iv) or any other negative voltage for a desired voltage level at the addressed SRAM cell.

[0039] In addition to compensating for the IR voltage drop in the bit lines, the write-assist circuitry provides negative voltage tuning for different sections of the SRAM array, thereby reducing power consumption. For example, for SRAM cells in a lower section of the SRAM array (e.g., memory cells 190 in rows '0' to '511' of SRAM array 180 in Fig. 1) The write support circuit provides a higher negative voltage (e.g., -100 mV) to SRAM cells in the upper section of the SRAM array (e.g., memory cells 190 in rows 512 to 1024 of SRAM array 180) compared to a lower negative voltage (e.g., -200 mV) provided to SRAM cells in this section. With the higher negative voltage (i.e., a lower voltage magnitude) provided to the memory cells in the lower section of the SRAM array, less power is drawn, for example, by the write driver circuit (e.g., write driver circuit 160 of SRAM array 180). Fig. 1) included. Furthermore, as described above, the SRAM array can be divided into more than two sections (see, for example, the quadrant example described above), in which each of the more than two sections can receive a different negative voltage based on the row position of a memory cell undergoing the memory write operation. By further tuning the negative voltages based on a memory row position, power consumption can be optimized even further.

[0040] Furthermore, the write-assist circuit also compensates for process variations in the SRAM cell transistors. Referring to Fig. 2. For example, process variations can cause the PMOS pull-up devices 260 and 270 to be stronger than the NMOS pass devices 220 and 230. This process variation can cause problems during a memory write operation because the PMOS pull-up devices hinder the ability of the NMOS pass devices to disconnect an internal node—e.g., an internal node between the PMOS pull-up device and the NMOS pull-down device—from a supply voltage V. DD (e.g., 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, or any combination thereof) to pull to ground (e.g., 0V). To compensate for the weaker NMOS pass device, the write support circuitry can provide a negative voltage as a write driver circuitry output to encourage the internal node to pull to ground.

[0041] Fig. Figure 5 is a description of a method 500 for a memory write operation performed on the SRAM 100, according to some embodiments of the present disclosure. The operations described in method 500 can, for example, be performed by the write-assist circuit 110 of Fig. 1 and Fig. 3. Other operations can be performed in procedure 500. Furthermore, the operations of procedure 500 can be performed in a different order and / or vary.

[0042] In process 510, memory address information associated with the memory write operation for one or more memory cells is received. In some embodiments, the memory address information includes a row position of an SRAM cell that is subjected to the memory write operation. With reference to Fig. 3 The control circuit 320 receives the memory address information in the write support circuit 110.

[0043] In process 520, a reference voltage is provided to one or more bit lines coupled to the one or more memory cells. In some embodiments, the reference voltage can be provided by a pulldown device (e.g., the pulldown device 380 in Fig. 3) provided which initially sets the reference voltage to ground before the reference voltage is coupled to a negative voltage (as discussed below in Procedures 530 and 540).

[0044] In process 530, the reference voltage is coupled to a first negative voltage and a first capacitive element. With reference to Fig. 3 and Fig. 4. When, for example, the NBL activation signal 114 transitions from '0' to '1' (e.g., from a logic low to a logic high value), circuit node 361 transitions from '1' to '0', thereby capacitively coupling the reference voltage 118 with a negative voltage to the capacitive element 362. In some embodiments, the reference voltage is coupled with the first negative voltage after the pulldown device has been deactivated.

[0045] In process 540, the reference voltage is cumulatively coupled to the first capacitive element and a second capacitive element with a second negative voltage that is lower than the first negative voltage, based on the memory address information. With reference to Fig. 3 and Fig. 4. When, for example, the NBL activation signal 114 transitions from '0' to '1' (e.g., from a logic low to a logic high value), circuit nodes 345 and 361 transition from '1' to '0', thereby capacitively coupling the reference voltage 118 with the second negative voltage to the capacitive elements 346 and 362. In some embodiments, the reference voltage is cumulatively coupled with the second negative voltage after the pulldown device has been deactivated.

[0046] Fig. Figure 6 is a representation of an SRAM 600 with an auxiliary bit line topology and a write-assist circuit 610 according to some embodiments of the present disclosure. The SRAM 100 comprises the line decoder 120, the word line driver 130, a column decoder 640, a column multiplexer (MUX) 650, the write driver circuit 160, and an SRAM array 680. The line decoder 120, the word line driver 130, and the write driver circuit 160 are described above with reference to Fig. 1 described. In some embodiments, as in Fig. Figure 6 shows the write support circuit 610, the column MUX 650 and the write driver circuit 160 arranged approximately near a lower section of the SRAM array 680.

[0047] In some embodiments, the SRAM array comprises 680 columns of 670 SRAM cells. O up to 170 N . Each of the columns 670 O up to 670 NIt comprises 190 memory cells. In some embodiments, each column comprises 670. O up to 670 N Furthermore, a bitline pair BL / BLB (also referred to here as "a first set of bitlines") and an auxiliary bitline pair FBL / FBLB (also referred to here as "a second set of bitlines"). The bitline pair BL / BLB can be used to access memory cells 190 in a lower section of the SRAM array 680, and the auxiliary bitline pair FBL / FBLB can be used to access memory cells 190 in an upper section of the SRAM array 690. For example, for the SRAM array 680 with 1024 rows in each of the columns 670 O up to 670 NThe bit line pair BL / BLB can be coupled to the NMOS pass devices (e.g., NMOS pass devices 220 and 230) of memory cells 190 for lines '0' to '511'. The auxiliary bit line pair FBL / FBLB can be coupled to the NMOS pass devices of memory cells 190 for lines '512' to '1024'. By implementing an alternative bit line path via the auxiliary bit line pair FBL / FBLB to the memory cells 190 in the upper section of the SRAM array 180, the total parasitic resistance and total parasitic capacitance associated with the unaccessed memory cells 190 can be reduced, thereby decreasing the IR voltage drop and RC time delay to an accessed memory cell 190 in the upper section of the SRAM array 680.

[0048] The column decoder 640 can be used, according to some embodiments, to select either the bit line pair BL / BLB or the auxiliary bit line pair FBL / FBLB based on the position of the memory cell 190 in the SRAM array 680 that is subjected to a memory write operation. In some embodiments, the column decoder 640 receives an auxiliary bit line activation signal (FBL activation signal) 612, which can indicate whether the memory cell 190 is located in an upper section of the SRAM array 680 (e.g., a memory cell in rows '512' to '102.4'). If the FBL activation signal 612 is a '1' or a logic high value, in some embodiments a corresponding YSEL'[N:o] signal is selected to activate a corresponding y-selection transistor in the column MUX 650 to access a corresponding auxiliary bit line pair FBL / FBLB.If, on the other hand, the FBL activation signal 612 is a '0' or a logical low value, a corresponding YSEL[N:o] signal is selected to activate a corresponding y-selection transistor in the column MUX 650 to access a corresponding bit line pair BL / BLB.

[0049] Fig. Figure 7 is a representation of the write support circuit 610, the column MUX 650, and the write driver circuit 160 according to some embodiments of the present disclosure. The write driver circuit 160 is described above with reference to Fig. 1 and Fig. 3 described.

[0050] The write support circuit 610 comprises the control circuit 320, the voltage generator 370 and the pulldown device 380, which were described above with reference to Fig. 3 described. In the control circuit 320, the interlock 302 outputs the FBL activation signal 612. As discussed above, the interlock circuit 302 receives the line signal 112, stores the line signal 112, and outputs an inverted representation of the line signal 112 (e.g., either '0' or '1') according to some embodiments of the present disclosure. The FBL activation signal 612 is a representation of the line signal 112. For example, if the line signal 112 is a '0' (e.g., representing a line in the upper section of the SRAM array 180), then the interlock circuit 302 outputs a '1' or a logic high, and therefore the FBL activation signal 612 is also a '1' or a logic high. Conversely, if the line signal 112 is a '1' (e.g.,(representing a row in the lower section of the SRAM array 180), then the interlock circuit 302 outputs a '0' or a logical low value, and therefore the FBL activation signal is also a '0' or a logical low value.

[0051] The operation of the voltage generator 370 and the pulldown device 380 is the same as described above with reference to Fig. 3 described. To summarize, with reference to Fig. 4 (which assumes that both the line signal 112 and the pulse activation signal 116 are at a '1' or a logic high value) from time=0 to time t1, the NBL activation signal 114 is at a '0' or a logic low value. Circuit nodes 345 and 361 are again at a '1' or a logic high value (e.g., a supply voltage V). DD, such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V or any combination thereof). Furthermore, when the NBL activation signal 114 is at '0', the output of the inverter logic device 356 is at '1' or a logic high, thus activating the pulldown device 380 and sending ground (e.g., 0V) to the reference voltage 118.

[0052] At time t1, the NBL activation signal 114 changes from '0' to '1' (e.g., from a logical low to a logical high value). Referring to Fig. 7. When the NBL activation signal 114 transitions from '0' to '1', the output of the inverter logic device 356 also transitions from '1' to '0' (e.g., from a logic high to a logic low value), thus deactivating the pulldown device 380. Without being pulled to ground by the pulldown device 380, the reference voltage 118 floats at a voltage level near or at ground.

[0053] At time t2, due to a transition of the NBL activation signal 114 from '0' to '1', circuit nodes 345 and 361 transition from '1' to '0' (e.g., from a logic high value to a logic low value). With reference to Fig. 7. The delay between time t1 and time t2 can be attributed to propagation delay times, which are set by the inverter logic devices 358 and 360 in the NBL initialization coupling circuit 372 and the NAND logic device 342 and the inverter logic device 345 in the NBL tuning coupling circuit 374. As a result of a transition of the circuit nodes 345 and 361 from '1' to '0', the reference voltage 118 is capacitively coupled to a negative voltage (e.g., -100 mV, -200 mV, or -300 mV). The “depression” in the reference voltage 118 is due to an initial charge coupling effect between the capacitive elements 346 / 362 and a capacitive load associated with an auxiliary bit line pair BL / BLB, which is accessed during the memory write operation.

[0054] Since in the preceding example the line signal 112 corresponds to a '1', a memory cell in the upper section of the SRAM array 680 is assigned to it. Fig. 6 of the memory write operation is subjected to. Therefore, with reference to Fig. 7 the FBL activation signal 612 at a '0' or a logical low value. When the FBL activation signal 612 is at '0', according to some embodiments with reference to Fig. 6 accessed a memory cell in the upper section of the SRAM array 680; the column decoder 640 in turn outputs a corresponding YSEL'[N:o] signal to activate a corresponding y-selection transistor in the column MUX 650 to access a corresponding auxiliary bit line pair FBL / FBLB.

[0055] In some embodiments, a memory cell is located in the lower section of the SRAM array 680. Fig. The memory write operation is performed in step 6, during which the line signal 112 is at a '0' or a logic high. When circuit nodes 345 and 361 transition from '1' to '1' at time t2, the reference voltage 118 is capacitively coupled to a negative voltage in this example. However, this negative voltage is higher than the negative voltage generated when the line signal 112 is at a '1' due to a lower charge coupling effect produced by capacitive element 362 (compared to the charge coupling effect produced by both capacitive elements 436 and 362 when the line signal 112 is at a '1').

[0056] Since the line signal 112 corresponds to a '0', in the preceding example a memory cell in the lower section of the SRAM array 680 is used. Fig. 6 of the memory write operation is subjected to. Therefore, with reference to Fig. 7. The FBL activation signal 612 is at a '1' or a logical high value. When the FBL activation signal 612 is at '1', with reference to Fig. 6 accesses a memory cell in the lower section of the SRAM array 680; the column decoder 640 in turn outputs a corresponding YSEL'[N:o] signal to activate a corresponding y-selection transistor in the column MUX 650 to access a corresponding bit line pair BL / BLB according to some embodiments.

[0057] With reference to Fig. 7. The NBL initialization coupling circuit 372 of the voltage generator 370 can be removed, leaving the NBL tuning coupling circuit 374. Although not in Fig. As shown in Figure 7, the control logic can be implemented such that when memory cells 190 in the lower section of the SRAM array 680 are accessed during a memory write operation, the write support circuit 610 provides ground (e.g., 0 V) ​​as the reference voltage 118. Furthermore, the control logic can be implemented such that when memory cells 190 in the upper section of the SRAM array 680 are accessed during a memory write operation, the write support circuit 610 provides a negative voltage (e.g., -100 mV, -200 mV, or -300 mV) as the reference voltage 118.

[0058] As discussed above, the write-assist circuit offers many advantages, such as balancing parasitic elements in bit lines, providing negative voltage tuning for different sections of the SRAM array, and smoothing process variations in the SRAM cell transistors. These advantages are also attributed to the 610 write-assist circuit. Fig. 6 applicable.

[0059] With reference to Fig. Section 6 describes the write-assist circuit 610 and the auxiliary bitline topology of the SRAM array 680 as providing additional advantages. For example, the auxiliary bitline topology can provide a more negative voltage to memory cells located farther from the write-drive circuit 160 (e.g., in the upper section of the SRAM array 680) without affecting memory cells located closer to the write-drive circuit 160 (e.g., in the lower section of the SRAM array 680). The more negative voltage can compensate for parasitic elements in the bitlines, especially when bitlines become longer due to higher-density SRAM devices. Because of the auxiliary bitline topology, the more negative voltage does not flow through the BL / BLB bitline pairs, thus minimizing voltage disturbances for memory cells accessed via BL / BLB bitline pairs.

[0060] Based on the description provided, an average professional will recognize that the SRAM array 680 is from Fig. 6 can be divided into more than two sections. For example, the SRAM array 680 can be divided into four sections, where each section is a quadrant. For the SRAM array 680 with 1024 rows, the first quadrant can be defined by 190 memory cells in rows '0' to '255', the second quadrant can be defined by 190 memory cells in rows '256' to '511', the third quadrant can be defined by 190 memory cells in rows '512' to '767', and the fourth quadrant can be defined by 190 memory cells in rows '768' to 102.4'. In some embodiments, with reference to Fig. 7 the NBL initialization coupling circuit 372 can be associated with the fourth quadrant of the memory cells 190, the NBL tuning coupling circuit 374 can be associated with the first quadrant of the memory cells 190, another NBL initialization coupling circuit can be associated with the second quadrant of the memory cells 190, and yet another NBL tuning coupling circuit can be associated with the third quadrant of the memory cells 190.

[0061] The operation of the write-assist circuit 610 with this quadrant architecture is similar to the operation of the write-assist circuit 110 described above with respect to the quadrant example of the SRAM array 180. One difference between the two quadrant examples is that the architecture of the SRAM array 680 includes auxiliary bitline pairs FBL / FBLB. In some embodiments, the auxiliary bitline pairs FBL / FBLB can be used to access memory cells 190 in the upper section of the SRAM array 680—e.g., memory cells in the first and second quadrants. In some embodiments, the bitline pairs BL / BLB can be used to access memory cells 190 in the lower section of the SRAM array 680—e.g., memory cells in the third and fourth quadrants.

[0062] Fig. Figure 8 is a description of a method 800 for a memory write operation performed on the SRAM 600, according to some embodiments of the present disclosure. The operations described in method 800 can, for example, be performed by the write-assist circuit 610 of Fig. 6 and Fig. 7. Other operations can be performed in procedure 800. Furthermore, the operations of procedure 800 can be performed in a different order and / or vary.

[0063] In operation 810, memory address information is received that is associated with the memory write operation for one or more memory cells in an array of memory cells. In some embodiments, the memory address information includes a row position of an SRAM cell that is subjected to the memory write operation. With reference to Fig. 7 The control circuit 320 receives the memory address information in the write support circuit 610.

[0064] In process 820, a reference voltage is provided to a first set of bit lines coupled to a first set of memory cells in the array, and to a second set of bit lines coupled to a second set of memory cells in the array. In some embodiments, the reference voltage can be supplied by a pulldown device (e.g., the pulldown device 380 in Fig. 7) provided which initially sets the reference voltage to ground before the reference voltage is coupled to a negative voltage (as discussed below in Procedures 730 and 740).

[0065] In process 830, the reference voltage, with a first capacitive element, is coupled to a first negative voltage supplied to the first set of bit lines, based on the memory address information. With reference to Fig. 4 and Fig. 7, for example, when the NBL activation signal 114 transitions from '0' to '1' (e.g., from a logic low to a logic high value), circuit node 361 transitions from '1' to '0', thereby capacitively coupling the reference voltage 118 with a negative voltage to the capacitive element 362. In some embodiments, the reference voltage is coupled with the first negative voltage after the pulldown device has been deactivated.

[0066] In process 840, the reference voltage is cumulatively coupled to the first capacitive element and a second capacitive element with a second negative voltage that is lower than the first negative voltage, the second negative voltage being supplied to the second set of bit lines based on the memory address information. With reference to Fig. 4 and Fig. 7. When, for example, the NBL activation signal 114 transitions from '0' to '1' (e.g., from a logic low to a logic high value), circuit nodes 345 and 361 also transition from '1' to '0', capacitively coupling the reference voltage 118 with the second negative voltage to the capacitive elements 346 and 362. In some embodiments, the reference voltage is cumulatively coupled with the second negative voltage after the pulldown device has been deactivated.

[0067] As discussed above, the write-assist circuits disclosed here – e.g., write-assist circuit 110 of Fig. 3 and the write support circuit 610 from Fig. 7 - parasitic elements in bit lines, provide negative voltage tuning for different sections of an SRAM array, and compensate for process variations in the SRAM cell transistors. Furthermore, in an auxiliary bit line topology (e.g., SRAM 680 of Fig. 6) the write support circuit provides a more “negative” voltage to memory cells located farther away from a write support circuit (e.g. memory cells in the upper section of the SRAM array 680), without interfering with memory cells located closer to the write driver circuit (e.g. memory cells in the lower section of the SRAM array 680).

[0068] Embodiments of the present disclosure include a write-assist circuit comprising a control circuit and a voltage generator. The control circuit is configured to receive memory address information associated with a memory write operation for one or more memory cells. The voltage generator is configured to provide a reference voltage to one or more bit lines coupled to the one or more memory cells. The voltage generator comprises a first capacitive element and a second capacitive element. During the memory write operation, the first capacitive element is configured to couple the reference voltage with a first negative voltage.Based on the memory address information, the first and second capacitive elements are designed to cumulatively couple the reference voltage with a second negative voltage that is lower than the first negative voltage.

[0069] Embodiments of the present disclosure comprise a storage device. The storage device comprises an array of memory cells, a write driver circuit, and a write support circuit. The write driver circuit is configured to provide a reference voltage for a memory write operation performed on one or more memory cells in the array. The write support circuit is configured to provide the reference voltage to the write driver circuit. The write support circuit may include a control circuit and a voltage generator. The control circuit is configured to receive memory address information associated with the memory write operation performed on the one or more memory cells in the array. The voltage generator comprises a first capacitive element and a second capacitive element.Based on the memory address information, the first and second capacitive elements are designed to cumulatively couple the reference voltage with a second negative voltage that is lower than the first negative voltage.

[0070] Embodiments of the present disclosure comprise a method for a memory write operation. The method comprises the following operations: (i) receiving memory address information associated with the memory write operation for one or more memory cells; (ii) providing a reference voltage to one or more bit lines coupled to the one or more memory cells; (iii) coupling, with a first capacitive element, the reference voltage to a first negative voltage; and (iv) cumulatively coupling, with the first capacitive element and a second capacitive element, the reference voltage to a second negative voltage, which is lower than the first negative voltage, based on the memory address information.

[0071] Embodiments of the present disclosure include another write-support circuit comprising a control circuit and a voltage generator. The control circuit is configured to receive memory address information associated with a memory write operation for one or more memory cells. The voltage generator is configured to provide a reference voltage to a first set of bit lines coupled to a first set of the one or more memory cells and a second set of bit lines coupled to a second set of the one or more memory cells. The voltage generator comprises a first capacitive element and a second capacitive element.During the memory write operation, the first capacitive element is configured to couple the reference voltage with a first negative voltage applied to the first set of bit lines, based on the memory address information. Based on the memory address information, the first and second capacitive elements are configured to cumulatively couple the reference voltage with a second negative voltage, lower than the first negative voltage, which is applied to the second set of bit lines.

[0072] Embodiments of the present disclosure include another storage device. The storage device comprises an array of memory cells, a write driver, and a write-assist circuit. The write driver circuit is configured to provide a reference voltage to a first set of bit lines coupled to a first set of memory cells in the array, and to a second set of bit lines coupled to a second set of memory cells in the array. The write-assist circuit is configured to provide the reference voltage to the write driver circuit. The write-assist circuit comprises a control circuit and a voltage generator. The control circuit is configured to receive memory address information associated with a memory write operation performed on one or more memory cells in the array.The voltage generator comprises a first capacitive element and a second capacitive element. During the memory write operation, the first capacitive element is configured to couple the reference voltage with a first negative voltage applied to the first set of bit lines, based on the memory address information. Based on the memory address information, the first and second capacitive elements are configured to cumulatively couple the reference voltage with a second negative voltage, lower than the first negative voltage, which is applied to the second set of bit lines.

[0073] Embodiments of the present disclosure include another method for a memory write operation. The method comprises the following operations: (i) receiving memory address information associated with the memory write operation for one or more memory cells in an array of memory cells; (ii) providing a reference voltage to a first set of bit lines coupled to a first set of memory cells in the array and to a second set of bit lines coupled to a second set of memory cells in the array; (iii) coupling, via a first capacitive element, the reference voltage to a first negative voltage provided to the first set of bit lines based on the memory address information;and (iv) cumulative coupling, with the first capacitive element and a second capacitive element, the reference voltage with a second negative voltage which is lower than the first negative voltage, the second negative voltage being supplied to the second set of bit lines on the basis of the memory address information.

[0074] It is understood that the full description, and not the summary of the disclosure, is to be used for the interpretation of the claims. The summary of the disclosure may set forth one or more, but not all, possible embodiments of the present disclosure as envisioned by the inventor(s), and should therefore in no way limit the attached claims.

[0075] The foregoing disclosure outlines features of several embodiments so that a person skilled in the art can better understand the aspects of the present disclosure. A person skilled in the art will recognize that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same tasks and / or achieve the same advantages as the embodiments presented herein. A person skilled in the art will also understand that such equivalent embodiments do not deviate from the inventive concept and scope of the present disclosure, and that they can make various changes, substitutions, and modifications here without deviating from the inventive concept and scope of the present disclosure.

Claims

[1] Write support circuit (110) comprising: a control circuit (320) configured to receive first and second memory address information (112) associated with a memory write operation (116) for one or more memory cells (190), wherein the first and second memory address information comprises a row position of the one or more memory cells (190), and a voltage generator (370) configured to provide a reference voltage (118) to one or more bit lines (BL) coupled to the one or more memory cells (190), the voltage generator (370) comprising: a first capacitive element (362), and a second capacitive element (346), wherein during the memory write operation, based on the first memory address information (112), the first capacitive element (362) is designed to couple the reference voltage (118) to a first negative voltage (362), and based on the second memory address information (112), the first and second capacitive elements are configured to cumulatively couple the reference voltage (118) to a second negative voltage (346, 362) that is lower than the first negative voltage (362). [2] The write support circuit of claim 1, wherein the voltage generator (370) further comprises a pull-down transistor (380) configured to initially set the reference voltage (118) to ground. [3] The write support circuit of claim 2, wherein the first capacitive element (362) is configured to couple the reference voltage to the first negative voltage (362) after the pull-down transistor (380) has been deactivated. [4] The write support circuit of claim 2 or 3, wherein the first and second capacitive elements (362, 346) are configured to cumulatively couple the reference voltage (118) to the second negative voltage (362, 346) after the pull-down transistor (380) has been deactivated. [5] The write support circuit of any preceding claim, wherein each of the first and second capacitive elements (362, 346) comprises an upper capacitor plate coupled to a voltage potential (361, 345) and a lower capacitor plate coupled to a circuit node associated with the reference voltage (118), and wherein the control circuit (320) is configured to transition the voltage potential from a first value to a lower second value to cumulatively couple the reference voltage (118) to the second negative voltage (362, 346). [6] The write support circuit of claim 5, wherein the control circuit (320) is configured to switch the voltage potential coupled to the upper capacitor plate of the first and second capacitive elements based on the memory address information (112). [7] A storage device (100) comprising: an array of memory cells (180), a write driver circuit (160) configured to provide a reference voltage (118) for a memory write operation performed on one or more memory cells in the array of memory cells, and a write support circuit (110) configured to provide the reference voltage (118) to the write driver circuit (160), the write support circuit comprising: a control circuit (320) configured to receive first and second memory address information (112) associated with the memory write operation (116) performed on the one or more memory cells (190) in the array of memory cells (180), wherein the first and second memory address information comprises a row position of the one or more memory cells (190), and a voltage generator (370) comprising: a first capacitive element (362), and a second capacitive element (346), wherein during the memory write operation: wherein, based on the first memory address information (112), the first capacitive element (362) is designed to couple the reference voltage (118) to a first negative voltage, and wherein, based on the second memory address information (112), the first and second capacitive elements (362, 346) are configured to cumulatively couple the reference voltage (118) to a second negative voltage (362, 346) that is lower than the first negative voltage. [8] The memory device of claim 7, wherein each of the memory cells (190) in the array of memory cells (180) comprises a static random access memory cell. [9] The memory device of claim 7 or 8, wherein the memory address information (112) comprises a row position of a memory cell (100) in the array of memory cells that is subjected to the memory write operation, and wherein the row position is associated with a first portion of the array of memory cells or a second portion of the array of memory cells that is arranged between the first portion of the array of memory cells and the write support circuit (110). [10] The memory device of claim 9, wherein, in response to the row position being in the second portion of the array of memory cells (190), the first capacitive element (362) is configured to couple the reference voltage (118) to the first negative voltage. [11] The memory device of claim 9 or 10, wherein, in response to the row position being in the first portion of the array of memory cells, the first and second capacitive elements (362, 346) are configured to cumulatively couple the reference voltage (118) to the second negative voltage (362, 346). [12] The memory device of any one of the preceding claims 7 to 11, wherein the voltage generator (370) further comprises a pull-down transistor (380) configured to initially set the reference voltage (118) to ground. [13] The memory device of claim 12, wherein the first capacitive element (362) is configured to couple the reference voltage (118) to the first negative voltage (362) after the pull-down transistor (380) has been deactivated. [14] The memory device of claim 12, wherein the first and second capacitive elements (362, 346) are configured to cumulatively couple the reference voltage (118) to the second negative voltage (362, 346) after the pull-down transistor (380) has been deactivated. [15] The memory device of any one of the preceding claims 7 to 14, wherein each of the first and second capacitive elements (362, 346) comprises an upper capacitor plate coupled to a voltage potential (361, 345) and a lower capacitor plate coupled to a circuit node associated with the reference voltage (118), and wherein the control circuit (320) is configured to transition the voltage potential from a first value to a lower second value to cumulatively couple the reference voltage (118) to the second negative voltage. [16] A method (500) for a memory write operation, comprising: Receiving first and second memory address information (112) associated with the memory write operation for one or more memory cells (190), wherein the first and second memory address information comprises a row position of the one or more memory cells (190), Providing a reference voltage (118) to one or more bit lines coupled to the one or more memory cells (100), Coupling, with a first capacitive element (362), the reference voltage (118) to a first negative voltage (362) based on the first memory address information (112), and cumulatively coupling, with the first capacitive element and a second capacitive element (362, 346), the reference voltage (118) to a second negative voltage (362, 346) lower than the first negative voltage (362) based on the second memory address information (112). [17] The method of claim 16, wherein providing the reference voltage (118) comprises initially setting, with a pulldown transistor (380), the reference voltage to ground before coupling the reference voltage to the first and second negative voltages (362, 346). [18] The method of claim 17, wherein coupling the reference voltage (118) to the first negative voltage (362) comprises coupling the reference voltage (118) to the first negative voltage after the pull-down transistor (380) has been deactivated. [19] The method of claim 17 or 18, wherein coupling the reference voltage (118) to the second negative voltage (362, 346) comprises cumulatively coupling the reference voltage (118) to the second negative voltage (362) after the pull-down transistor (380) has been deactivated. [20] The method of any one of the preceding claims 16 to 19, wherein each of the first and second capacitive elements (362, 346) comprises an upper capacitor plate coupled to a voltage potential (361, 345) and a lower capacitor plate coupled to a circuit node associated with the reference voltage (118), and wherein coupling the reference voltage to the second negative voltage (362, 346) comprises transitioning the voltage potential from a first value to a lower second value to cumulatively couple the reference voltage (118) to the second negative voltage (362, 346).

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