Storage device that performs a hashing-based translation between a logical address and a physical address

Abstract

Storage device (1300) comprising the following: a plurality of storage devices (1310, 1311-1319); and a controller (1330) configured to translate a logical address received from a host (1100) into a physical address of the storage devices (1310, 1311-1319), where the logical address is one of a plurality of logical addresses, and the physical address is one of a plurality of physical addresses, the controller (1330) is further configured to: to manage an initial correspondence information (110a; 110b; 110c) which is linked to a correspondence relationship between the logical addresses (L1-Lr) and the physical addresses (P1-Pr); to manage a translation information (130) which has information of a minimum perfect hash (MPH) function, wherein the MPH function is generated when a size of a first memory area in the memory devices (1310, 1311-1319) reaches a reference size, where the first memory area is indicated by logical addresses managed in the first correspondence information (110a; 110b; 110c), and the MPH function is generated using the logical addresses indicating the first memory area as key values; and to manage a second correspondence information (150) which is connected with a correspondence relationship between the logical addresses used as the key values ​​and the MPH function of the translation information (130).

Description

TECHNICAL AREA

[0001] The present disclosure relates to an electronic device and more precisely to operations and configurations of a storage device which stores / outputs data. DISCUSSION OF THE STATE OF THE TECHNOLOGY

[0002] From DE 10 2015 012 621 A1, a method for managing a flash memory system is known, comprising the following: reading flash data units from a flash memory into a buffer, wherein each of the flash data units has host data units, and determining an identifier for each host data unit. The method includes selecting a set of unique identifiers from the determined identifiers based on a number of host data units that share the respective unique identifier. For each unique identifier in the set of unique identifiers, the method includes designating one of the host data units as a master data unit, mapping the logical address of the designated host data unit to a physical address.The logical addresses of the other host data units that share the unique identifier are mapped to the physical master address, and the physical addresses that were previously mapped to the newly mapped logical addresses are invalidated.

[0003] An electronic storage device includes a storage device for storing or outputting data. The storage device has multiple storage locations for storing data. Storage locations are identified and indicated based on values ​​referenced as addresses. Within the storage device, data is stored at a storage location indicated by an address, or output from a storage location indicated by an address. The electronic storage device can manage addresses appropriately to control the storage device.

[0004] In some cases, an address processed by a host device located outside the storage device may differ from an address indicating a storage location within the storage device. Therefore, the storage device may perform address translation (e.g., address mapping) between an address processed by the host device and an address on the storage device itself.

[0005] For example, the storage device can maintain an address mapping table. The address mapping table can contain information related to a mapping relationship between addresses. The storage device can translate an address processed by the host device into an address on the storage device by referencing the address mapping table.

[0006] As the capacity of a storage device increases, the size of its address mapping table also increases. The address mapping table requires a mapping of a resource (such as a buffer or cache) within the storage device. Therefore, an increase in the size of the address mapping table can decrease the management efficiency of the storage device. SUMMARY

[0007] Exemplary embodiments of the present disclosure provide a storage device configured to perform an address translation between a logical address processed by a host and a physical address of a storage device. In exemplary embodiments, the storage device can perform an address translation by using a hash function and a hashing operation instead of providing a full mapping between a logical address and a physical address.

[0008] In an exemplary embodiment, the storage device comprises storage devices and a controller. The controller can control the storage devices based on a request and a logical address received from the host. The controller can translate the logical address received from the host into a physical address of the storage devices.

[0009] In exemplary embodiments, the controller manages a first correspondence information, which is linked to a correspondence relationship between logical and physical addresses. The controller manages translation information, which contains information from a minimal perfect hash (MPH) function. The MPH function is generated by using logical addresses that indicate a memory area of ​​a reference size as key values ​​when the size of a memory area in the storage devices, indicated by logical addresses managed in the first correspondence information, reaches the reference size. The controller manages a second correspondence information, which is linked to a correspondence relationship between the logical addresses used as the key values ​​and the MPH information of the translation information.

[0010] In exemplary embodiments, the controller determines whether the received logical address is managed in one of the first correspondence pieces, which indicate a first correspondence relationship, or in the second correspondence piece, which indicates a second correspondence relationship. The first correspondence relationship has a correspondence relationship between a first plurality of logical addresses and a plurality of physical addresses. The second correspondence relationship has a correspondence relationship between a plurality of MPH functions, each of which is generated based on a group of logical addresses and a second plurality of logical addresses.If the received logical address is managed in the second correspondence information, the controller can obtain a physical address associated with the received logical address based on the received logical address and the selected MPH function that corresponds to the received logical address among the majority of MPH functions.

[0011] In exemplary embodiments, if the received logical address is managed in the first correspondence information, which indicates a correspondence relationship between a plurality of perfect hash functions, each of which is generated based on a group of logical addresses and a plurality of logical addresses, the controller can obtain a physical address of the storage devices associated with the received logical address, based on the received logical address and a perfect hash function that corresponds to the received logical address among the plurality of perfect hash functions.

[0012] In exemplary embodiments, a storage device comprises a plurality of storage devices and a controller. The controller is configured to translate a logical address received from a host into a physical address of the storage devices. The logical address is one of a plurality of logical addresses, and the physical address is one of a plurality of physical addresses. The controller is further configured to manage first correspondence information associated with a correspondence relationship between the logical and physical addresses. The controller is also configured to manage translation information containing information from a minimum perfect hash (MPH) function. The MPH function is generated when the size of a first memory area in the storage devices reaches a reference size.The first memory area is represented by logical addresses, which are managed in the first correspondence information, and the MPH function is generated using the logical addresses representing the first memory area as key values. The controller is further configured to manage a second correspondence information, which is linked to a correspondence between the logical addresses used as key values ​​and the MPH function of the translation information.

[0013] In exemplary embodiments, a storage device comprises a plurality of storage devices and a controller configured to manage the storage devices based on a request and a logical address received from a host. The controller is further configured to determine whether the received logical address is managed according to either a first correspondence information, which indicates correspondence relationships between a first plurality of logical addresses and a plurality of physical addresses, or a second correspondence information, which indicates correspondence relationships between a plurality of minimal perfect hash (MPH) functions and a second plurality of logical addresses. Each of the plurality of MPH functions is generated based on a set of logical addresses.The controller is further configured to obtain a physical address associated with the received logical address, based on the received logical address and a selected MPH function that corresponds to the received logical address from the plurality of MPH functions, when the received logical address is managed according to the second correspondence information.

[0014] In exemplary embodiments, a storage device comprises a plurality of storage devices and a controller. The controller is configured to receive a first logical address and to obtain a first physical address of the storage devices based on the first logical address and a first perfect hash function, provided the first logical address is managed according to the first correspondence information, which indicates a correspondence relationship between a plurality of perfect hash functions and a first plurality of logical addresses. The first physical address is associated with the first logical address, the first logical address is contained within the plurality of logical addresses, and the first perfect hash function is contained within the plurality of perfect hash functions.The first perfect hash function corresponds to the first logical address, and each of the plurality of perfect hash functions is generated based on a group of logical addresses.

[0015] In exemplary embodiments, a storage device comprises a plurality of storage devices and a controller. The controller is configured to translate a logical address received from a host into a physical address of the storage device. The logical address is one of a plurality of logical addresses, and the physical address is one of a plurality of physical addresses. The controller is further configured to manage the logical addresses by referencing an initial correspondence information until the size of a memory area represented by the logical addresses reaches a reference size. The initial correspondence information indicates correspondence relationships between the logical addresses and the physical addresses.The controller is further configured to manage the logical addresses by referencing a second correspondence piece of information and a translation piece of information, which contains information about a minimum perfect hash (MPH) function when the memory area reaches the reference size. The second correspondence piece of information indicates a correspondence relationship between a specific one of the logical addresses and the MPH function, and the specific one of the logical addresses is used to generate the MPH function.

[0016] According to exemplary embodiments, the amount of metadata that needs to be referenced to perform an address translation between a logical address and a physical address can be significantly reduced. Such metadata can occupy a small amount of the resources in the storage device. The available resources not occupied by the metadata can then be used to perform other operations on the storage device. Consequently, the management efficiency of the storage device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other features of the present disclosure will become clearer through a detailed description of exemplary embodiments thereof with reference to the accompanying drawings. Similar reference numerals may refer to similar elements across the accompanying drawings. Fig. Figure 1 is a block diagram illustrating an example of a configuration of an electronic device which includes a storage device according to exemplary embodiments of the present disclosure. Fig. 2 is a block diagram which is an example of a configuration of the storage device of the Fig. 1 illustrated according to exemplary embodiments of the present disclosure. Fig. 3 is a concept diagram to describe an address translation which is located in the storage device of the Fig. 2 is carried out according to exemplary embodiments of the present disclosure. Fig. Figure 4 is a table illustrating an example of information that can be referenced to perform an address translation according to exemplary embodiments of the present disclosure. Fig. 5 is a concept diagram illustrating an example of information contained in the address management information of the Fig. 3 may be included according to exemplary embodiments of the present disclosure. Fig. Figure 6 is a concept diagram describing an example of an address translation, which is performed by referencing the first correspondence information of the address management information of the Fig. 5 is carried out according to exemplary embodiments of the present disclosure. Fig. 7 and Fig. 8 are concept diagrams describing an example of a procedure for generating the translation information of the address management information of the Fig. 5 according to exemplary embodiments of the present disclosure. Fig. Figure 9 is a concept diagram describing an example of an address translation, which is achieved by referencing the second correspondence information and the translation information of the address management information. Fig. 5 is carried out according to exemplary embodiments of the present disclosure. Fig. Figure 10 is a concept diagram describing an example of a configuration of the address management information of the Fig. 5 and the storage devices of the Fig. 2 according to exemplary embodiments of the present disclosure. Fig. 11 is a flowchart that describes an example of a write operation based on the address management information of the Fig. 5 is carried out according to exemplary embodiments of the present disclosure. Fig. Figures 12 to 15 are concept diagrams describing an example of address management information configurations. Fig. 5 according to the example of the writing operation of Fig. 11 according to exemplary embodiments of the present disclosure. Fig. 16 and Fig. 17 are concept diagrams to describe an example of relationships between the translation information of the Fig. 5 and the storage devices of the Fig. 2 according to exemplary embodiments of the present disclosure. Fig. Figure 18 is a concept diagram describing an example of a configuration of the translation information of the Fig. 5 according to exemplary embodiments of the present disclosure. Fig. Figure 19 is a concept diagram to describe an example of a physical address configuration handled in exemplary embodiments of the present disclosure. Fig. 20 is a concept diagram describing an example of an address translation, which is based on the address management information of the Fig. 5 is carried out according to exemplary embodiments of the present disclosure. Fig. 21 and Fig. 22 are concept diagrams for describing examples of configurations of the first correspondence information, the address management information, the Fig. 5 according to exemplary embodiments of the present disclosure. Fig. 23 is a flowchart that describes an example of a read operation based on the address management information of the Fig. 5 is carried out according to exemplary embodiments of the present disclosure. Fig. 24 is a flowchart that describes an example of a write operation based on the address management information of the Fig. 5 is carried out according to exemplary embodiments of the present disclosure. Fig. 25 and Fig. 26 are concept diagrams for describing examples of configurations of the address management information of the Fig. 5 according to the example of the writing operation of Fig. 24 according to exemplary embodiments of the present disclosure. DETAILED DESCRIPTION OF EXAMPLE EXECUTIONS

[0018] Exemplary embodiments of the present disclosure are described in more complete below with reference to the accompanying drawings. Similar reference numerals may refer to similar elements across the accompanying drawings.

[0019] It will be understood here that the terms "first," "second," "third," etc., are used to distinguish one element from another, and that the elements are not limited by these terms. Accordingly, a "first" element in one exemplary embodiment can be described as a "second" element in another exemplary embodiment. I. Overall system configuration

[0020] Fig. Figure 1 is a block diagram illustrating an example of a configuration of an electronic device 1000 which includes a storage device according to exemplary embodiments of the present disclosure.

[0021] The electronic device 1000 can include a main processor 1101, a working memory 1200, a storage device 1300, a communication block 1400, a user interface 1500, and a bus 1600. The electronic device 1000 can be, for example, a desktop computer, a laptop computer, a tablet computer, a smartphone, a portable device, a video game console, a workstation, a server, an electric vehicle, etc.

[0022] The main processor 1101 can control the overall operation of the electronic device 1000. The main processor 1101 can process various data from arithmetic and / or logical operations. For this purpose, the main processor 1101 can incorporate a special-purpose logic circuit (for example, a field-programmable gate array (FPGA), application-specific integrated circuits (ASICs), etc.) configured to process operations. For example, the main processor 1101 can have one or more processor cores and can be implemented with a general-purpose processor, a special-purpose processor, or an application processor.

[0023] The main memory 1200 can store data used in the operation of the electronic device 1000. For example, the main memory 1200 can temporarily store data that is being processed or is to be processed by the main processor 1101. The main memory 1200 can be used as a buffer or cache for the electronic device 1000. The main memory 1200 can, for example, consist of volatile memory such as static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc., and / or non-volatile memory such as flash memory, phase-change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), etc.

[0024] The storage device 1300 can include one or more storage devices and a controller. The storage device of the storage device 1300 can store data regardless of whether power is supplied to the storage device. For example, the storage device 1300 can include non-volatile storage devices such as flash memory, PRAM, MRAM, ReRAM, FRAM, etc. Alternatively, the storage device 1300 can include storage devices such as a solid-state drive (SSD), card storage, embedded memory, etc.

[0025] The communication block 1400 can communicate with an external device / system of the electronic device 1000. For example, the communication block 1400 can have at least one of various wireless communication protocols such as Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX), Global System for Mobile Communication (GSM), Code Division Multiple Access (CDMA), Bluetooth, Near Field Communication (NFC), Wireless Fidelity (Wi-Fi), Radio Frequency Identification (RFID), etc., and / or at least one of various wired communication protocols such as Transfer Control Protocol / Internet Protocol (TCP / IP), Universal Serial Bus (USB), Firewire, etc.

[0026] The user interface 1500 can mediate communication between a user and the electronic device 1000. For example, the user interface 1500 can include input interfaces such as a keyboard, mouse, keypad, button, touch panel, touchscreen, touchpad, touchball, camera, microphone, gyroscope sensor, vibration sensor, etc. The user interface 1500 can include output interfaces such as a liquid crystal display (LCD), a light-emitting diode (LED) display, an organic LED (OLED) display, an active-matrix OLED (AMOLED) display, a loudspeaker, a motor, etc.

[0027] The 1600 bus can provide a communication path between components of the 1000 electronic device. The components of the 1000 electronic device can exchange data with each other based on a bus format of the 1600 bus. For example, the bus format can include one or more of different interface protocols such as USB, Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCIe), Mobile PCIe (M-PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), Serial Attached SCSI (SAS), Integrated Drive Electronics (IDE), Enhanced IDE (EIDE), Nonvolatile Memory Express (NVMe), Universal Flash Storage (UFS), etc.

[0028] The storage device 1300 can be implemented based on exemplary embodiments of the present disclosure. For example, the storage device 1300 can perform an address translation. In exemplary embodiments of the present disclosure, the storage device 1300 can perform the address translation based on a hash function and a hashing operation. Exemplary configurations and operations of the storage device 1300 are described with reference to the Fig. 2 to 26 are described.

[0029] It must be understood that the storage device 1300 is not limited to the storage device 1300 described herein. For example, according to exemplary embodiments of the present disclosure, the storage device 1300 can be used in any type of device, including a storage element. For example, exemplary embodiments of the present disclosure can be used in volatile memory and / or non-volatile memory contained in the working memory 1200.

[0030] Fig. Figure 2 is a block diagram, which shows an example of a configuration of the storage device 1300. Fig. 1 illustrated according to exemplary embodiments of the present disclosure.

[0031] As with reference to Fig. As described in Figure 1, the main processor 1001 can communicate with the storage device 1300 via the bus 1600. In the present disclosure, reference can be made to an object capable of accessing the storage device 1000 as a host 1100. The main processor 1101 is an example of an object capable of acting as the host 1100, but the present disclosure is not limited to this. For example, the host 1100 could be the main processor 1101, but is not limited to this.

[0032] Host 1100 can exchange DAT data with storage device 1300. Storage device 1300 can establish a storage service with host 1100 in response to a CMD command received by host 1100.

[0033] For example, host 1100 can issue a write command and write data to storage device 1300. Storage device 1300 can store the requested write data in response to the write command. Similarly, host 1100 can issue a read command to storage device 1300. Storage device 1300 can output the requested read data to host 1100 in response to the read command.

[0034] The storage device 1300 can include one or more storage devices 1310 and one controller 1330. The number of storage devices contained in the storage device 1300 can be changed or modified in various ways.

[0035] The storage device 1310 can have a plurality of storage devices. For example, the storage device 1310 can have storage devices 1311 to 1319. Each of the storage devices 1311 to 1319 can store data requested by the host 1100. For this purpose, each of the storage devices 1311 to 1319 can have a memory area(s) for storing data. For example, if each of the storage devices 1311 to 1319 has NAND-type flash memory, each of the storage devices 1311 to 1319 can have an arrangement of memory cells formed along a plurality of word lines and a plurality of bit lines. However, as described in reference to Fig. As described in 1, the type and configuration of each of the storage devices 1311 to 1319 may be changed or modified in various ways.

[0036] Each of the storage devices 1311 to 1319 can have storage locations for storing data. A storage location can be identified and indicated based on a value referenced as an address. For example, write data can be stored at a storage location indicated by an address, and read data can be output from a storage location indicated by an address. According to exemplary embodiments, a storage area can have a plurality of storage locations, each indicated by a plurality of addresses.

[0037] Host 1100 can assign an address ADDR to storage device 1300 to exchange data related to a specific storage location or area of ​​storage devices 1311 through 1319. Storage device 1300 can control storage devices 1311 through 1319 based on a request (for example, the CMD command) and the address ADDR received from host 1100.

[0038] The address ADDR, processed by host 1100, can differ from an address indicating a storage location within storage devices 1311 to 1319. For example, the address ADDR processed by host 1100 can be referenced as a logical address, and the address of storage devices 1311 to 1319 can be referenced as a physical address. Storage device 1300 can perform address translation between a logical address processed by host 1100 and a physical address of storage devices 1311 to 1319 in order to properly control the storage devices 1311 to 1319.

[0039] The controller 1330 can control the overall operation of the storage device 1300. For example, the controller 1330 can schedule operations of the storage devices 1311 to 1319 or can encode and decode signals / data to be processed in the storage device 1300. For example, the controller 1330 can control the storage devices 1311 to 1319 such that they store or output data.

[0040] The Controller 1330 can include one or more hardware components (for example, an analog circuit, a logic circuit, etc.) configured to perform functions described above and below. Additionally or alternatively, the Controller 1330 can include one or more processor cores. The functions of the Controller 1330, described above and below, can be implemented using program code or software and / or firmware, and the processor core(s) of the Controller 1330 can execute a set of instructions from the program code. The processor core(s) of the Controller 1330 can process various types of arithmetic and / or logical operations to execute the instruction set.

[0041] A buffer memory 1350 can buffer data used in an operation of the storage device 1300. For example, the buffer memory 1350 can temporarily store data that the controller 1330 needs to reference. For example, the buffer memory 1350 can temporarily store data to be stored in the storage devices 1311 to 1319 and / or data output by the storage devices 1311 to 1319. The buffer memory 1350 can, for example, be volatile memory such as SRAM, DRAM, SDRAM, etc., and / or non-volatile memory such as flash memory, PRAM, MRAM, ReRAM, FRAM, etc.

[0042] Fig. Figure 3 is a concept diagram to describe an address translation, which is located in the storage device 1300 of the Fig. 2 is carried out according to exemplary embodiments of the present disclosure.

[0043] In exemplary embodiments, the controller 1330 can perform address translation between a logical address and a physical address. The controller 1330 can translate a logical address received from the host 1100 into a physical address of the storage devices 1310. Consequently, even if a logical address provided by the host 1100 differs from a physical address indicating a specific memory location in the storage devices 1310, the controller 1330 can control the storage devices 1310 based on the translated physical address.

[0044] Controller 1330 can manage address management information 100 to perform address translation. Address management information 100 can contain metadata that is referenced to perform address translation between a logical address and a physical address. Controller 1330 can create, modify, update, and invalidate a variety of information contained in address management information 100. Additionally, controller 1330 can perform address translation based on this information.

[0045] For example, the address management information 100 can be stored in the buffer memory 1350 of the Fig. 2. Alternatively, the address management information 100 can be stored in a cache memory within the controller 1330 or in the storage devices 1310. In some cases, the address management information 100 can be distributed across at least one of the buffer memory 1350, the cache memory within the controller 1330, and / or the storage devices 1310. The controller 1330 can access a memory that stores the address management information 100 to perform the address translation.

[0046] Fig. Figure 4 is a table illustrating an example of information that can be referenced to perform an address translation according to exemplary embodiments of the present disclosure.

[0047] In exemplary embodiments, the controller 1330 can be used. Fig. 3. Manage a complete mapping table (FMT). The FMT can contain information related to a mapping relationship between logical addresses La to Lz and physical addresses Pa to Pz. The FMT can be implemented as a lookup table. The 1330 controller can translate a logical address into a physical address by referencing the FMT.

[0048] For example, the logical address La can correspond to the physical address Pa. If the controller 1330 receives the logical address La from the host 1100, the Fig. Upon receiving a request from host 1100, controller 1330 can map the logical address La to the physical address Pa. Therefore, controller 1330 can process a request received from host 1100 along with the logical address La, in conjunction with a memory location indicated by the physical address Pa.

[0049] For example, the complete mapping table FMT can be used to determine the physical addresses Pa to Pz of the storage devices 1310 of the Fig. 3. to manage completely (for example, the physical addresses Pa to Pz, which are managed in the full mapping table FMT, can completely encompass all memory areas in the storage devices 1310). In such an example, even if the controller 1330 receives any logical address from the host 1100, the controller 1330 is able to map the received logical address to a physical address corresponding to the received physical address by referring to the full mapping table FMT.This means that, in exemplary embodiments, any logical address received by the controller 1330 from the host 1100 can be mapped to a physical address corresponding to the received logical address by referring only to the complete mapping table FMT, without having to refer to any additional mapping tables other than the complete mapping table FMT.

[0050] However, if the capacity of the storage devices 1310 increases, the number of physical addresses managed in connection with the storage devices 1310 can also increase. The size of the full mapping table (FMT) can increase as the number of physical addresses increases. The full mapping table (FMT) can map a resource (for example, the buffer memory 1350, the cache memory within the controller 1330, and / or the storage devices 1310) to the storage device 1300. Fig. 2 are required. As a result, an increase in the size of the complete mapping table FMT can decrease the management efficiency of the storage device 1300. II. Example of an address translation

[0051] Fig. 5 is a concept diagram illustrating an example of information found in address management information 100 of the Fig. 3 may be included according to exemplary embodiments of the present disclosure.

[0052] As stated above with reference to Fig. As described in section 3, the controller 1330 can manage a variety of information contained in the address management information 100. The controller 1330 can translate a logical address into a physical address by referencing the address management information 100. In exemplary embodiments, the address management information 100 can include a first correspondence information 110a, a translation information 130, and a second correspondence information 150.

[0053] The first correspondence information 110a can be associated with a correspondence relationship between logical addresses L1 to Lr and physical addresses P1 to Pr. For example, the first correspondence information 110a can indicate a correspondence relationship between a specific logical address and a specific physical address (for example, the first correspondence information 110a can map a specific logical address to a specific physical address). However, unlike the complete mapping table FMT of the Fig. 4 In exemplary embodiments, the controller 1330 manages the physical addresses of the storage devices 1310. Fig. 3 in the first correspondence information 110a is not complete. For example, in exemplary embodiments, the first correspondence information 110a does not contain all of the physical addresses that exist for the storage devices 1310 (for example, the first correspondence information 110a does not contain a mapping for every physical address in the storage devices 1310).

[0054] Instead, in exemplary embodiments, the controller 1330 manages the correspondence relationship between the logical addresses L1 to Lr and the physical addresses P1 to Pr in the first correspondence information 110a until the size of a memory area, which is indicated by the logical addresses L1 to Lr managed in the first correspondence information 110a, reaches a reference size. The reference size is determined with reference to Fig. 10 will be described.

[0055] When the size of the memory area represented by the logical addresses L1 to Lr, managed in the first correspondence information 110a, reaches the reference size, the controller 1330 can manage the logical addresses L1 to Lr in conjunction with the translation information 130 and the second correspondence information 150, and can invalidate the correspondence relationship of the first correspondence information 110a. Such operations are further described with reference to the Fig. 10 to 15 will be described.

[0056] In exemplary embodiments, the translation information 130 can contain information from a minimal perfect hash (MPH) function. For example, the translation information 130 can contain information from the MPH function MPH1() to MPHm(). The MPH function refers to a hash function in which n elements of a first set are mapped to n elements of a second set without hash collision.

[0057] In exemplary embodiments, each of the MPH functions MPH1() to MPHm() ​​can be generated when the size of the memory area, indicated by the logical addresses L1 to Lr, managed in the first correspondence information 110a, reaches the reference size. Each of the MPH functions MPH1() to MPHm() ​​can be generated based on a group of logical addresses.

[0058] In exemplary embodiments, each of the MPH functions MPH1() to MPHm() ​​can be created by using logical addresses that represent a memory area of ​​the reference size as key values. A group of logical addresses can encompass a memory area of ​​the reference size. An example of an algorithm for creating an MPH function is given with reference to the Fig. 7 and Fig. 8 will be described.

[0059] The second correspondence information 150 can be linked to a correspondence relationship between logical addresses L11 to Lmr and the MPH functions MPH1() to MPHm(). A specific logical address of the second correspondence information 150 can be used as a key value to generate a specific MPH function, and the second correspondence information 150 can indicate a correspondence relationship between the specific logical address and the specific MPH function. Therefore, the second correspondence information 150 can be linked to a correspondence relationship between logical addresses used as key values ​​and MPH functions generated using these logical addresses as key values.

[0060] An address translation using the first correspondence information 110a, the translation information 130 and the second correspondence information 150 is carried out with reference to the Fig. 6 and Fig. 9 will be described.

[0061] Fig. Figure 6 is a concept diagram describing an example of an address translation, which is performed by reference to the first correspondence information 110a of the address management information 100. Fig. 5 is carried out according to exemplary embodiments of the present disclosure.

[0062] In some cases, a logical address, which is from the host 1100 of the Fig. 2 is received, managed in the first correspondence information 110a. As with reference to Fig. As described in section 5, a logical address, which is used as a key value to generate an MPH function, can be found in the second correspondence information 150 of the Fig. 5. Accordingly, a logical address that is not used as a key value to generate any MPH function can be managed in the first correspondence information 110a before the size of a memory area, indicated by logical addresses managed in the first correspondence information 110a, reaches the reference size.

[0063] If a logical address received from host 1100 is managed in the first correspondence information 110a, controller 1330 can refer to the first correspondence information 110a. Controller 1330 can obtain a physical address corresponding to the received logical address by referencing the first correspondence information 110a. Therefore, controller 1330 can perform an address translation between the received logical address and the obtained physical address.

[0064] For example, referring to Fig. 6. Controller 1330 receives a logical address L2 from host 1100. The logical address L2 can be managed in the first correspondence information 110a. Controller 1330 can obtain a physical address P2, which corresponds to the received logical address L2, by referencing the first correspondence information 110a.

[0065] For example, storage device 1311 can have memory locations indicated by physical addresses P1 to Pi, and storage device 1319 can have memory locations indicated by physical addresses Pj to Pz. Controller 1330 can process a request from host 1100 in connection with a memory location indicated by physical address P2.

[0066] The Fig. 7 and Fig. 8 are concept diagrams describing an example of a procedure for generating the translation information 130 of the address management information 100 of the Fig. 5 according to exemplary embodiments of the present invention.

[0067] As with reference to Fig. As described in section 5, in exemplary embodiments the translation information 130 can contain information about an MPH function. The MPH function refers to a hash function in which n elements of a first set are mapped to n elements (for example, to the minimum number of elements) of a second set without a hash collision (for example, perfectly mapped).

[0068] Referring to Fig. For example, three hash functions h0, h1, and h2 can be used to generate an MPH function. The hash functions h0, h1, and h2 can have any hash functions from different types. The hash functions h0, h1, and h2 can have the same type of hash function or they can have different types of hash functions.

[0069] For example, three key values ​​x, y, and z can be used to create an MPH function. The key values ​​x, y, and z can be elements belonging to a first set and can be mapped to elements of a second set by the MPH function.

[0070] For example, function values ​​h0(x), h1(x), and h2(x) can be computed by substituting the key value x into the hash functions h0, h1, and h2, respectively. The function values ​​h0(x), h1(x), and h2(x) can form a graph G1 on a function space. The key value x can correspond to any one of the function values ​​h0(x), h1(x), and h2(x) to generate an MPH function.

[0071] Similarly, function values ​​h0(y), h1(y), and h2(y), which are computed by substituting the key value y into the hash functions h0, h1, and h2, can form a graph G2 on the function space. For example, if the key value y is different from the key value "x", graph G2 cannot overlap with graph G1, even if the same hash functions h0, h1, and h2 are used. The key value y can correspond to any one of the function values ​​h0(y), h1(y), and h2(y) to generate an MPH function.

[0072] Additionally, function values ​​h0(z), h1(z), and h2(z), which are computed by substituting the key value z into the hash functions h0, h1, and h2, can form a graph G3 on the function space. For example, in some cases, graph G3 can overlap with graphs G1 and G2, even if the key value z is different from the key value x or the key value y. The key value z can correspond to any of the function values ​​h0(z), h1(z), and h2(z) to generate an MPH function.

[0073] An MPH function can be used to avoid hash collisions. Therefore, the key values ​​x, y, and z can each correspond to different function values. For example, the key value x can correspond to the function value h1(x), and the key value y can correspond to the function value h0(y). If graph G2 overlaps with graph G3, the function value h0(y) can be the same as the function value h0(z). In this case, to avoid hash collisions, the key value z cannot correspond to the function value h0(z). For example, the key value z can correspond to the function value h2(z).

[0074] In this way, to avoid hash collisions, function values ​​corresponding to the key values ​​x, y, and z can be selected differently. This means that some of the function values ​​calculated using hash functions can be chosen in such a way that function values ​​corresponding to key values ​​do not overlap.

[0075] It must be understood that the graphs G1, G2 and G3 of the Fig. 7 and the correspondence between the key value and the function value is provided as an example to facilitate a better understanding of the present disclosure, and that the present disclosure is not limited to this. For example, forms of graphs obtained by hash functions can be changed or modified in various ways on a function space, and a correspondence between a key value and a function value can be changed or modified in various ways to avoid a hash collision.

[0076] Referring to Fig. 8. Key values ​​between 0 and t can correspond to function values ​​between 0 and u. For example, as with reference to Fig. As described in section 7, the key values ​​x, y and z each correspond to the function values ​​h1(x), h0(y) and h2(z).

[0077] For example, a rank value can be assigned to each of the function values ​​depending on the magnitude of the function values. For example, ranks 0, 2, and 1 can be assigned to the function values ​​h1(x), h0(y), and h2(z), respectively, according to the order of the function values ​​h1(x), h2(z), and h0(y).

[0078] Therefore, the key value x can be mapped to the rank value 0, which corresponds to the function value h1(x). Similarly, the key value y can be mapped to the rank value 2, which corresponds to the function value h0(y), and the key value z can be mapped to the rank value 1, which corresponds to the function value h2(z).

[0079] An MPH function MPH() can be created to map the key values ​​x, y, and z to the rank values ​​0, 2, and 1, respectively. When the key values ​​x, y, and z are input into the MPH function MPH(), the function can return the rank values ​​0, 2, and 1. This MPH function MPH() can perform a mapping to the minimum number of elements without hash collisions.

[0080] The exemplary procedure, which refers to the Fig. 7 and Fig. The method described in section 8 can be used to create an MPH function in exemplary embodiments. In these exemplary embodiments, a group of logical addresses can be used as key values ​​to create an MPH function. The MPH function can be created to translate the logical addresses used as the key values ​​into physical addresses. When a key value (for example, a logical address) is input into an MPH function, the MPH function can output a value associated with a physical address corresponding to the input key value. This MPH function can be referenced to map the logical addresses used as the key values ​​to physical addresses of a memory area of ​​a reference quantity without collision.

[0081] The 1330 controller Fig. 5 can include a hardware component and / or a software component for generating an MPH function. For example, the 1330 controller can include a plurality of hash operation circuits to perform operations on the hash functions h0, h1, and h2 of the Fig. 7 and / or an additional hash function(s). For example, a processor core(s) of the controller 1330 can execute an instruction set of program code that describes operations of the hash functions h0, h1 and h2 and / or an additional hash function.

[0082] For example, the 1330 controller may incorporate a hardware circuit and / or execute an instruction set of associated program code through (a) processor core(s) to calculate and select a function value, as described in reference to Fig. 7 is described. For example, the 1330 controller may incorporate a hardware circuit and / or execute an instruction set of associated program code through (a) processor core(s) to assign a rank value and generate an MPH function, as described in reference to Fig. 8 is described.

[0083] It must be understood that the Fig. 7 and Fig. 8 are provided to facilitate a better understanding of the present disclosure, and that the present disclosure is not limited to it. For example, the number of hash functions and the number of key values ​​used to generate an MPH function can be changed or modified in various ways. Additionally, it must be understood that the Fig. 7 and Fig. Figure 8 shows a simplified example of a method for generating an MPH function. Other algorithms for generating an MPH function may be employed in exemplary embodiments. Furthermore, some exemplary embodiments are described herein using a "minimal" perfect hash function, but the present disclosure is not limited thereto. For example, some exemplary embodiments may employ other types of perfect hash function(s) to avoid hash collisions.

[0084] Fig. Figure 9 is a concept diagram describing an example of an address translation, which is achieved by referencing the second correspondence information 150 and the translation information 130 of the address management information 100. Fig. 5 is carried out according to exemplary embodiments of the present disclosure.

[0085] In some cases, a logical address, which is from the host 1100 of the Fig. 2 is received, and the second correspondence information 150 is managed. As with reference to Fig. As described in section 5, a logical address, which is used as a key value to generate an MPH function, can be managed in the second correspondence information 150.

[0086] If a logical address received from host 1100 is managed in the second correspondence information 150, controller 1330 can first reference the second correspondence information 150 (for example, before referencing the translation information 130). Controller 1330 can determine which MPH function corresponds to the received logical address by referencing the second correspondence information 150. Controller 1330 can then select an MPH function corresponding to the received logical address and obtain information about the selected MPH function by referencing the translation information 130.

[0087] The selected MPH function may have been created using the received logical address as one of its key values. Therefore, if the received logical address is input into the selected MPH function, the selected MPH function can output a value associated with a physical address corresponding to the received logical address. The 1330 controller can obtain a physical address associated with the received logical address based on the selected MPH function and the received logical address.

[0088] For example, with reference to Fig. Controller 1330 receives a logical address L12 from host 1100. The logical address L12 can be managed in the second correspondence information 150. Controller 1330 can obtain information about an MPH function MPH1, which corresponds to the received logical address L12, by referencing the second correspondence information 150 and the translation information 130.

[0089] The controller 1330 can obtain a physical address P2, which corresponds to the logical address L12, based on the MPH function MPH1 and the logical address L12. The controller 1330 can process a request from the host 1100 in conjunction with a memory location indicated by the physical address P2.

[0090] When the second correspondence information 150 and the translation information 130 are used, the 1330 controller can manage MPH functions, which are used to derive physical addresses from logical addresses. An MPH function can be used to map various logical addresses, used as key values, to several physical addresses. Therefore, the 1330 controller can manage one MPH function for logical addresses used as key values, instead of managing each and every physical address corresponding to a given logical address.

[0091] As a result, according to exemplary embodiments of the present disclosure, the amount of metadata (for example, the address management information 100) referenced to perform an address translation between a logical address and a physical address can be significantly reduced. Such metadata can occupy a small amount of resources of the storage device 1300. The increased amount of available resources not used by the metadata can be used to perform other operations of the storage device 1300, thus improving the operation of the storage device 1300.

[0092] For example, if the size of a memory area which is occupied by the metadata in a cache memory within the controller 1330 or the buffer memory 1350 of the Fig. 2 decreases, a sufficient storage area for a read cache and / or a write cache must be ensured. For example, if the size of a storage area which is defined by the metadata in the storage devices 1310 of the Fig. 2 is occupied, decreases, a sufficient storage area for thin provisioning is ensured. Therefore, the management efficiency of the storage device 1300 can be improved according to exemplary embodiments of the present disclosure. III. Reference size and initial setting

[0093] Fig. Figure 10 is a concept diagram describing an example of a configuration of address management information 100. Fig. 5 and the storage devices 1310 of the Fig. 2 according to exemplary embodiments of the present disclosure.

[0094] The storage devices 1310 can have memory areas 1310a, 1310b, 1310c, ..., 1310n. Each of the memory areas 1310a, 1310b, 1310c ..., 1310n can have a reference size R. The reference size R refers to a size of a memory area that is managed by the controller 1330 in conjunction with an address translation according to exemplary embodiments.

[0095] For example, the reference size R can correspond to a page size or a block size defined in the storage devices 1310. However, the present disclosure is not limited to this. The reference size R can correspond to another size to be sufficient for performing address translation and managing the address management information 100. For example, a manufacturer or designer of the storage device 1300 can preselect the reference size R before operating the storage device 1300, and the controller 1330 can manage the storage devices 1310 based on the selected reference size R.

[0096] The controller 1330 can manage addresses up to the reference size R in the first correspondence information 110a. For example, as above with reference to Fig. As described in section 5, the controller 1330 manages a correspondence relationship between logical addresses and physical addresses in the first correspondence information 110a until the size of a memory area, indicated by the logical addresses managed in the first correspondence information 110a, reaches the reference size R.

[0097] Controller 1330 can manage information from MPH functions in translation information 130. As above, with reference to Fig. As described in section 5, each of the MPH functions can be generated based on logical addresses that indicate a memory area of ​​the reference size R. The MPH functions can be generated to correspond to the memory areas 1310a, 1310b, 1310c, ... 1310n, which are defined with reference to the Fig. 16 and Fig. 17 will be described. Accordingly, the number of MPH functions managed in the translation information 130 can be changed depending on the number of memory areas in the storage device 1310.

[0098] Once the storage device 1300 is manufactured, the total capacity of the storage devices 1310 can be fixed. Therefore, if the reference size R is chosen to be relatively small, the number of storage areas can increase. Conversely, if the reference size R is chosen to be relatively large, the number of storage areas can decrease.

[0099] As the number of memory areas increases, the number of MPH functions managed in translation information 130 can also increase. Consequently, the amount of metadata managed in translation information 130 and the second correspondence information 150 can increase. However, since the reference size R is relatively small, the amount of metadata managed in the first correspondence information 110a can decrease.

[0100] Alternatively, if the number of memory areas decreases, the amount of metadata managed in translation information 130 and the second correspondence information 150 can decrease. However, since the reference size R is relatively large, the amount of metadata managed in the first correspondence information 110a can increase.

[0101] Therefore, the reference size R can influence the overall size of the address management information 100 and thus affect the amount of metadata and the performance of the address translation. The reference size R can be appropriately selected with regard to various factors such as a purpose, an operational rule, an operational condition or state, a required performance level, the capacity of available resources, etc., of the storage device 1300.

[0102] In an initial state (for example, immediately after the storage device 1300 has been manufactured), the address management information 100 may contain no information at all. Consequently, the first correspondence information 110a, the translation information 130, and the second correspondence information 150 may be empty. An example write operation performed in the initial state is described with reference to the Fig. 11 to 15 will be described. IV. Exemplary preceding write operation and generation of the MPH function

[0103] Fig. 11 is a flowchart that describes an example of a write operation based on the address management information 100 of the Fig. 5 according to exemplary embodiments of the present disclosure. Fig. Figures 12 to 15 are concept diagrams describing an example of address management information configurations. Fig. 5 according to the example of the writing operation of Fig. 11.

[0104] Referring to Fig. In operation S110, controller 1330 can receive a write request (for example, a write command and write data) from host 1100. Controller 1330 can receive a logical address from host 1100 along with the write request. The logical address can indicate a memory location where the write data will be stored.

[0105] In operation S120, the controller 1330 can check a logical address that was previously written to the first correspondence information 110a and the second correspondence information 150. Therefore, the controller 1330 can determine whether the logical address received in operation S110 is stored in either the first correspondence information 110a or the second correspondence information 150.

[0106] For example, in the initial state (e.g., immediately after the storage device 1300 is manufactured), the first correspondence information 110a, the translation information 130, and the second correspondence information 150 may be empty, as described with reference to Fig. 10 is described. Therefore, in the example of the Fig. 11. Controller 1330 determines that the logical address received in operation S110 is not contained in the first correspondence information 110a and the second correspondence information 150 (for example, the logical address received in operation S110 is not contained in the first correspondence information 110a or the second correspondence information 150). For example, each of the first correspondence information 110a and the second correspondence information 150, which are empty, can return a suitable value (for example, a predefined value), and controller 1330 can determine that the first correspondence information 110a and the second correspondence information 150 are empty in response to the returned value.

[0107] In operation S130, the controller 1330 can control the storage devices 1310 such that the write data is stored in a memory location indicated by a newly selected physical address. This new physical address can be selected based on various factors, such as the management state of the storage devices 1310, the operational control of the controller 1330, etc. Additionally, the controller 1330 can update the first correspondence information 110a so that the logical address received in operation S110 corresponds to the new physical address.

[0108] Referring to Fig. For example, controller 1330 can receive a logical address L11 from host 1100, and write data associated with logical address L11 can be stored in a memory location indicated by a physical address P11 (for example, a memory location contained in memory area 1310b). In this case, controller 1330 can maintain a correspondence relationship between logical address L11 and physical address P11 in the first correspondence information 110a.

[0109] Similarly, for example, controller 1330 can receive a logical address L12 from host 1100, and write data associated with logical address L12 can be stored in a memory location indicated by a physical address P23 (for example, a memory location contained in memory area 1310c). In this case, controller 1330 can maintain a correspondence relationship between logical address L12 and physical address P23 in the first correspondence information 110a.

[0110] In this way, the controller 1330 can manage a correspondence relationship between logical addresses and physical addresses in the first correspondence information 110a until the size of a memory area, indicated by the logical addresses managed in the first correspondence information 110a, reaches the reference size (for example, R in Fig. 10).

[0111] In Operation S140 of the Fig. 11. Controller 1330 can determine whether the first correspondence information 110a is full (for example, whether the size of the memory area indicated by the logical addresses managed in the first correspondence information 110a has reached the reference size).

[0112] If the first correspondence information 110a is not full, the controller 1330 can receive another write request from the host 1100 in operation S110. The first correspondence information 110a can become full if operations S110, S120, and S130 are repeated. In this case, operation S150 can be performed.

[0113] In operation S150, the controller 1330 can create an MPH function. In exemplary embodiments, an MPH function can be created using a group of logical addresses that indicate a memory area of ​​the reference size as key values.

[0114] When the MPH function is created, the controller 1330 can update the translation information 130 to manage information about the created MPH function within the translation function 130. Additionally, the controller 1330 can update the second correspondence information 150 such that the group of logical addresses used as the key values ​​corresponds to the created MPH function.

[0115] Referring to Fig. For example, the first correspondence information 110a can be completely filled. For example, the first correspondence information 110a can be filled with logical addresses L11 to L1r (for example, the logical addresses L11 to L1r can represent a memory area of ​​the reference size). The controller 1330 can create an MPH function MPH1() by using the logical addresses L11 to L1r as key values. The controller 1330 can create the MPH function MPH1() after receiving a set of logical addresses L11 to L1r.

[0116] Controller 1330 can update translation function 130 to manage information about the MPH function MPH1() within translation function 130. Controller 1330 can also update second correspondence information 150 to manage a correspondence relationship between logical addresses L11 to L1r and the MPH function MPH1() within second correspondence information 150.

[0117] For example, the MPH function MPH1() can be created to translate the logical addresses L11 to L1r into physical addresses P1 to Pr. For example, the physical addresses P1 to Pr can represent the memory area 1310a of the reference size. Data associated with the logical addresses L11 to L1r can be stored in memory area 1310a based on the MPH function MPH1().

[0118] In exemplary embodiments, a memory location indicated by a logical address of the first correspondence information 110a can differ from a memory location indicated by a logical address of the second correspondence information 150. Therefore, even if logical addresses of the first correspondence information 110a indicate a first memory area, logical addresses of the second correspondence information 150 can indicate a second memory area. Referring to the Fig. 12 and Fig. For example, 13 can indicate the logical address L11 of the first correspondence information 110a a memory location which has the physical address P11, and the logical address L11 of the second correspondence information 150 can indicate a memory location which has the physical address P1.

[0119] When the MPH function MPH1() is generated, the controller 1330 can control the memory devices 1310 such that the data associated with logical addresses L11 to L1r migrate to memory locations indicated by physical addresses P1 to Pr. For example, under the control of the controller 1330, data stored at a memory location with physical address P11 can migrate to a memory location with physical address P1.

[0120] Therefore, as with reference to Fig. As described in section 9, after the MPH function MPH1() is generated, the logical addresses L11 to L1r are each translated into the physical addresses P1 to Pr based on a correspondence relationship of the second correspondence information and information about the MPH function MPH1() of the translation information 130. The controller 1330 can obtain the physical addresses P1 to Pr each based on the MPH function MPH1() and the logical addresses L11 to L1r.

[0121] In Operation S160 of the Fig. 11. Controller 1330 can invalidate the correspondence relationship of the first correspondence information 110a in response to the MPH function that is generated. Here, the terms invalidation and invalidate refer to releasing or deleting the correspondence relationship. Referring to Fig. 13. Controller 1330 can invalidate the correspondence relationship of the first correspondence information 110a in response to the MPH function MPH1(), which is generated. Consequently, Fig. 13 with Fig. 12. Comparatively, due to the invalidation, the logical addresses L11 to L1r, which are managed in the second correspondence information 150, are not managed in the first correspondence information 110a.

[0122] If the correspondence relationship of the first correspondence information 110a is invalidated, entries of the correspondence relationship from the first correspondence information 110a can be deleted. In exemplary embodiments, data associated with addresses of the deleted entries can be deleted (or invalidated) directly from the storage devices 1310. Alternatively, in exemplary embodiments, information about the deleted entries can be temporarily stored in the buffer memory 1350 or a cache memory within the controller 1330, and then data associated with addresses of the deleted entries can be deleted (or invalidated) from the storage devices 1310 based on the temporarily stored information while an administrative operation (for example, a garbage collection operation) is being performed.

[0123] The example of the writing operation of Fig. Step 11 can, in turn, be performed in response to a subsequent writing request. Referring to Fig. For example, controller 1330 can receive a logical address L21 from host 1100 (operation S110 of the Fig. 11) The logical address L21 cannot be managed in both the first correspondence information 110a and the second correspondence information 150 (Operation S120 of the Fig. 11).

[0124] Therefore, under the control of controller 1330, write data can be stored at a memory location indicated by a physical address P21. Additionally, controller 1330 can update the first correspondence information 110a for a correspondence relationship between logical address L21 and physical address P21 (operation S130 of the Fig. 11) If the newly received logical address L21 is not managed in the second correspondence information 150, the controller 1330 can manage the newly received logical address L21 in the first correspondence information 110a.

[0125] In this way, the first correspondence information 110a can be filled with logical addresses L21 to L2r (operation S140 of the Fig. 11). For example, the logical addresses L21 to L2r can indicate a memory area of ​​the reference size.

[0126] Referring now to Fig. For example, controller 1330 can create an MPH function MPH2() based on a group of logical addresses L21 to L2r. Additionally, controller 1330 can update the translation function 130 for information about the MPH function MPH2() and can update the second correspondence information 150 for a correspondence relationship between the MPH function MPH2() and the logical addresses L21 to L2r (operation S150 of the Fig. 11). For example, the MPH function MPH2() can be created to translate the logical addresses L21 to L2r into physical addresses P (r+1) to P (2r) of the memory area 1310.

[0127] Controller 1330 can then invalidate the correspondence relationship of the first correspondence information 110a (S160 of the Fig. 11) Accordingly, Fig. 15 with Fig. 14 Comparatively, due to the invalidation, the logical addresses L21 to L2r, which are managed in the second correspondence information 150, are not managed in the first correspondence information 110a.

[0128] Logical addresses corresponding to the same MPH function can be translated into physical addresses for the same memory area. For example, the logical addresses L11 and L1r, corresponding to the MPH function MPH1(), can be translated into physical addresses P1 and Pr. The same memory area 1310a can have one memory location represented by physical address P1 and another memory location represented by physical address Pr.

[0129] Alternatively, logical addresses corresponding to different MPH functions can be translated into physical addresses for different memory areas. For example, the logical address L11, corresponding to the MPH function MPH1(), can be translated to the physical address P1, and the logical address L21, corresponding to the MPH function MPH2(), can be translated to the physical address P(r+1). The memory area 1310a, which contains the memory location indicated by the physical address P1, can be different from the memory area 1310b, which contains the memory location indicated by the physical address P(r+1).

[0130] An example of reading / writing operations performed after the writing operation of the Fig. 11 is completed, with reference to the Fig. 23 to 26 are described. V. Examples of address management information

[0131] The Fig. 16 and Fig. 17 are concept diagrams to describe an example of the relationships between the translation information 130 of the Fig. 5 and the storage devices 1310 of the Fig. 2 according to exemplary embodiments of the present disclosure.

[0132] The controller 1330 can manage memory areas 1310a, 1310b, 1310c, ... 1310n in units of a reference quantity in conjunction with the translation information 130. The translation information 130 can contain information from MPH functions MPH1() to MPHn(), each corresponding to memory areas 1310a, 1310b, 1310c, ... 1310n. The controller 1330 can determine which memory area corresponds to a specific MPH function. That is, when the controller 1330 selects the specific MPH function, it can identify a memory area that corresponds to the selected MPH function.

[0133] Referring to Fig. For example, the buffer storage tank 1350 can be used for 16. Fig. 2. Buffering information from MPH functions MPH1() to MPHn(), which are contained in the translation information 130a. In exemplary embodiments, the information from the MPH functions MPH1() to MPHn() can only be buffered at fixed locations in the buffer memory 1350. For example, information about the MPH function MPH1() can only be buffered at a specific location in the buffer memory 1350 and cannot be buffered at any other location.

[0134] Additionally, the storage locations of the memory areas 1310a, 1310b, 1310c, ... 1310n can also be fixed on the memory devices 1310. For example, memory area 1310a can only be managed at a specific memory location on the memory devices 1310 and cannot be managed at any other arbitrary memory location.

[0135] In exemplary embodiments, the controller 1330 can determine a memory area which corresponds to each of the MPH functions MPH1() to MPHn().

[0136] This determination can be made based on fixed memory locations where the information of the MPH functions MPH1() to MPHn() is buffered in the buffer memory 1350 and on fixed memory locations of the memory areas 1310a, 1310b, 1310c, ... 1310n of the storage devices 1310.

[0137] For example, a memory location where the information for the MPH function MPH1() is buffered can uniquely correspond to a memory location in memory area 1310a. In this example, if controller 1330 receives a logical address corresponding to the MPH function MPH1(), controller 1330 can translate the received logical address into a physical address in memory area 1310a. In this way, the MPH functions MPH1() through MPHn() can each correspond to the different memory areas 1310a, 1310b, 1310c, ... 1310n.

[0138] Referring to Fig. In exemplary embodiments, 17 can contain the translation information 130b of pointers T1 to Tn, each of which is associated with the MPH functions MPH1() to MPHn(). The pointers T1 to Tn can be configured to indicate memory locations of the memory areas 1310a, 1310b, 1310c, ... 1310n, which correspond to the MPH functions MPH1() to MPHn(). Consequently, the controller 1330 can determine a memory area corresponding to each of the MPH functions MPH1() to MPHn() based on the memory locations indicated by the pointers T1 to Tn.

[0139] For example, the pointer T1, which is connected to the MPH function MPH1(), can indicate a memory location in memory area 1310b. In this example, if controller 1330 receives a logical address corresponding to the MPH function MPH1(), controller 1330 can translate the received logical address into a physical address in memory area 1310b. In this way, the MPH functions MPH1() through MPHn() can correspond to the different memory areas 1310a, 1310b, 1310c, ... 1310n.

[0140] In exemplary embodiments, memory locations where the information of the MPH functions MPH1() to MPHn() is buffered in the buffer memory 1350, and memory locations of the memory areas 1310a, 1310b, 1310c, ...1310n on the storage devices 1310 can be dynamically changed without being fixed.

[0141] The Fig. 16 and Fig. Figure 17 illustrates that an MPH function corresponds to a memory area. However, the present disclosure is not limited to this. For example, in exemplary embodiments, an MPH function can be generated to correspond to a plurality of memory areas.

[0142] Fig. Figure 18 is a concept diagram to describe an example of a configuration of translation information 130. Fig. 5 according to exemplary embodiments of the present disclosure.

[0143] In exemplary embodiments, the translation information 130c can contain information on seed values ​​S1 to Sn, each associated with the MPH functions MPH1() to MPHn(). The seed values ​​S1 to Sn can be used to generate the MPH functions MPH1() to MPHn(). The information for each of the seed values ​​S1 to Sn can indicate a seed value that is used to generate a corresponding MPH function.

[0144] The MPH function can be used to avoid a hash collision. That is, exemplary implementations provide a way to avoid a hash collision by using the MPH function without using the seed values ​​S1 to Sn. However, in certain scenarios, function values ​​(or graphs similar to those found in Fig. Figure 7 illustrates the data obtained before generating the MPH function. These data points may overlap excessively, and it may be impossible to select different function values ​​for all key values. In this case, changing a seed value can lead to a change in a function value and can therefore be useful to avoid a hash collision. As a result, the translation information 130c, according to the exemplary embodiments, can contain the information of the seed values ​​S1 to Sn.

[0145] Fig. Figure 19 is a concept diagram to describe an example of a physical address configuration handled in exemplary embodiments. Fig. Figure 20 is a concept diagram describing an example of an address translation, which is based on the address management information 100 of the Fig. 5 is carried out.

[0146] For example, memory area 1310a can contain memory locations indicated by the physical addresses P1 to Pr. If memory area 1310a contains adjacent memory locations, the physical addresses P1 to Pr can be either continuous or regular.

[0147] Referring to Fig. For example, physical address P1 can be expressed as 0x000000. Physical address P2 can be expressed as 0x000010, physical address P3 as 0x000020, and physical address Pr as 0x0000F0. In this example, if memory locations are adjacent, the upper bits (UBS) of physical addresses P1 through Pr can be expressed identically as 0x0000.

[0148] Alternatively, the lower bits (LBs) of physical addresses P1 to Pr can be expressed differently. There can be an offset between the lower bits of the LBs. For example, there can be an offset of "+10" between the lower bits of the LBs of physical addresses P1 and P2, and there can be an offset of "+20" between the lower bits of the LBs of physical addresses P1 and P3.

[0149] If the upper bits (LBs) of physical addresses P1 to Pr are expressed identically, each of the physical addresses P1 to Pr can be uniquely identified based solely on the lower bits (LBs). Alternatively, if a reference address is selected, each of the physical addresses P1 to Pr can be uniquely identified based solely on an offset from the reference address. Consequently, it may be permissible to manage only the lower bits (LBs) and / or offsets instead of managing the complete values ​​of the physical addresses P1 to Pr. This can further reduce the amount of metadata referenced for address translations.

[0150] Referring to Fig. 20. Controller 1330 can obtain a physical address based on an MPH function and a logical address. For this purpose, Controller 1330 can select an MPH function MPHx(), which corresponds to a logical address, by referencing the second correspondence information 150. As referred to the Fig. 16 and Fig. As described in section 17, the controller 1330 can determine a memory area corresponding to the MPH function MPHx() when it selects the MPH function MPHx().

[0151] In exemplary embodiments, the controller 1330 can obtain a representative address of the specific memory area. Here, the representative address can be a reference address to which an offset of the Fig. 19 is applicable. For example, the representative address can be selected as a physical address of the foremost memory location of the specified memory area. However, the present disclosure is not limited to this. For example, the selection of the representative address can be changed or modified in various ways (for example, different addresses can be selected as the representative address).

[0152] Controller 1330 can obtain information about the selected MPH function MPHx() by referencing the translation information 130. Controller 1330 can input the logical address of the selected MPH function MPHx(). In exemplary embodiments, the MPH function MPHx() can be generated to output an offset for the specified logical address. In such exemplary embodiments, Controller 1330 can calculate an offset for a logical address based on the MPH function MPHx() and the logical address. In some cases, Controller 1330 can correct or calibrate the output of the MPH function MPHx() by a factor α to output a suitable offset.

[0153] The Controller 1330 can then obtain a physical address based on the calculated offset and the representative address. Therefore, the Controller 1330 can translate a logical address into a physical address. The obtained physical address can indicate a memory location that is offset from the representative address by the calculated offset in a memory area corresponding to the MPH function MPHx().

[0154] For example, with reference to the Fig. 19 and Fig. 20. Assume that controller 1330 receives a logical address which must be translated to the physical address P3. Controller 1330 can select the MPH function MPHx() corresponding to the received logical address. Controller 1330 can determine that the selected MPH function MPHx() corresponds to memory area 1310a. For example, controller 1330 can select the physical address P1 0x000000 of the leading memory location of the specified memory area 1310a as the representative address.

[0155] The Controller 1330 can input the received logical address of the selected MPH function MPHx(). In some cases, the MPH function MPHx() can directly output an offset of +20. Alternatively, the MPH function MPHx() might output a value of, for example, 2, depending on how the MPH function MPHx() is generated. In this case, the Controller 1330 can correct or calibrate the output of the MPH function MPHx() ten (10) times (for example, α=10) to calculate the offset of +20.

[0156] The 1330 controller can obtain the physical address P3 0x000020 based on the representative address 0x000000 and an offset of +20. The physical address P3 can indicate a memory location that is offset (+20) from the representative address (for example, the physical address P1 0x000000) in memory area 1310a. Therefore, the 1330 controller can translate the received logical address into the physical address P3.

[0157] The Fig. 21 and Fig. 22 are concept diagrams for describing other examples of configurations for the first correspondence information 110a, the address management information 100, and the address management information 100. Fig. 5 according to exemplary embodiments of the present disclosure.

[0158] The first correspondence information 110a, which refers to the Fig. As described in sections 5 to 20, a correspondence relationship between logical addresses and physical addresses can be directly indicated. However, the present disclosure is not limited to this. For example, according to exemplary embodiments, the configuration of the first correspondence information can be changed or modified in various ways.

[0159] Referring to Fig. In exemplary embodiments, the address management information 100 can include a first correspondence information 110b. The first correspondence information 110b can contain information from hash values ​​hP1 to hPr, which are calculated from physical addresses, instead of including information from physical addresses corresponding to the logical addresses L1 to Lr. The first correspondence information 110b can be associated with a correspondence relationship between the logical addresses L1 to Lr and the hash values ​​hP1 to hPr.

[0160] The hash values ​​hP1 to hPr can be calculated by performing an operation on a pre-selected hash function at physical addresses corresponding to the logical addresses L1 to Lr. For example, the first correspondence information 110b can be implemented in the form of a cuckoo hash table. In some cases, different logical addresses can correspond to the same hash value. In these cases, for example, controller 1330 can process a hash collision based on a cuckoo hash algorithm.

[0161] Referring to Fig. In exemplary embodiments, the address management information 100 can include a first correspondence information 110c. The first correspondence information 110c can directly contain data DAT1 to DATr, which are associated with the logical addresses L1 to Lr, instead of including information about the physical addresses corresponding to the logical addresses L1 to Lr. The first correspondence information 110c can be associated with a correspondence relationship between the logical addresses L1 to Lr and the data DAT1 to DATr.

[0162] In the example of the Fig. 22. The data DAT1 to DATr, received from host 1100, can initially be managed in the first correspondence information 110c. After an MPH function is generated, the data DAT1 to DATr can be stored in a memory area, which is indicated by a physical address obtained based on the MPH function.

[0163] The first correspondence information 110a of the Fig. 5 and the first correspondence information 110b of the Fig. 21 can accompany the migration of data when the MPH function is generated. Alternatively, the first correspondence information 110c of the Fig. 22. Do not accompany the migration of data. VI. Example following the reading operation

[0164] Fig. 23 is a flowchart that describes an example of a read operation based on the address management information 100 of the Fig. 5 is carried out according to exemplary embodiments of the present disclosure. The example of the read operation of the Fig. 23 can be illustrated by the example of the writing operation, which refers to Fig. As described in section 11, the following will be carried out.

[0165] In operation S210, controller 1330 can receive a read request (for example, a read command) from host 1100. Controller 1330 can receive a logical address from host 1100 along with the read request. This logical address can indicate a memory location from which read data will be output.

[0166] In operation S220, the controller 1330 can determine whether the logical address received in operation S210 is written to the second correspondence information 150. If the controller 1330 previously generated an MPH function based on the received logical address, the received logical address can be managed in the second correspondence information 150.

[0167] If the logical address received in operation S210 is stored in the second correspondence information 150, operation S230 can be performed. In operation S230, controller 1330 can select an MPH function corresponding to the received logical address by referencing the second correspondence information 150. Additionally, controller 1330 can obtain information about the selected MPH function by referencing the translation information 130. For example, controller 1330 can obtain an offset corresponding to the received logical address by using the selected MPH function.

[0168] In operation S240, the controller 1330 can obtain a representative address of a memory area corresponding to the selected MPH function. Additionally, the controller 1330 can obtain a physical address related to the logical address received in operation S210, based on the offset and the representative address. Therefore, the controller 1330 can translate the logical address into a physical address based on the MPH function and the logical address (refer to...). Fig. 9).

[0169] If the logical address received in operation S210 is not managed in the second correspondence information 150, operation S250 can be performed. In operation S250, the controller 1330 can determine whether the logical address received in operation S210 is written to the first correspondence information 110a. For example, if the received logical address is not referenced to create an MPH function, the received logical address can be managed in the first correspondence information 110a.

[0170] If the logical address received in operation S210 is managed in the first correspondence information 110a, operation S260 can be performed. In operation S260, the controller 1330 can obtain a physical address corresponding to the logical address received in operation S210 by referencing the first correspondence information 110a (referring to Fig. 6).

[0171] Once the physical address has been obtained in operation S240 or operation S260, operation S270 can be performed. In operation S270, the controller 1330 can control the storage devices 1310 such that read data associated with the read request is output from a memory location indicated by the physical address obtained in operation S240 or operation S260.

[0172] Referring to the Fig. 14 and Fig. 23. Controller 1330 can receive a logical address managed in either the first correspondence information 110a or the second correspondence information 150. For example, if Controller 1330 receives the logical address L11 managed in the second correspondence information 150, Controller 1330 can obtain the physical address P1 of memory area 1310a based on the MPH function MPH1(), which corresponds to the logical address L11 (refer to operations S220, S230, and S240 of the MPH function). Fig. 23). Under the control of the controller 1330, data read from a memory location can be output, which is indicated by the physical address P1.

[0173] For example, if controller 1330 receives the logical address L21, which is managed in the first correspondence information 110a, controller 1330 can obtain the physical address P21 of memory area 1310c, which corresponds to the logical address L21 (refer to operation S250 and operation S260 of the Fig. 23). Under the control of the controller 1330, data read from a memory location can be output, which is indicated by the physical address P21.

[0174] Fig. Section 23 describes that operation S220 is performed before operation S250. However, in exemplary embodiments, operation S250 can be performed before operation S220. Alternatively, operation S250 can be performed together with operation S220 (for example, in parallel with operation S220 or essentially at the same time as operation S220).

[0175] In some cases, the logical address received in operation S210 is not managed in either of the first correspondence information (110a) or the second correspondence information (150). This can occur, for example, if a read request is received for data that is not stored. In these cases, in operation S280, controller 1330 may issue an error response to host 1100. VII. Example following the writing operation

[0176] Fig. 24 is a flowchart that describes an example of a write operation based on the address management information 100 of the Fig. 5 according to exemplary embodiments of the present disclosure. Fig. 25 and Fig. 26 are concept diagrams for describing examples of address management information configurations. 100 of the Fig. 5 according to the example of the writing operation of Fig. 24 according to exemplary embodiments of the present disclosure. The example of the writing operation, which refers to Fig. The operation described in section 24 can be carried out according to the example of the writing operation, which is described with reference to Fig. 11 is described.

[0177] Referring to Fig. In operation S310, controller 1330 can receive a write request (for example, a write command and write data) from host 1100. Controller 1330 can receive a logical address from host 1100 along with the write request. In some cases, the logical address received with the write request may already have been managed in the first correspondence information 110a or the second correspondence information 150. This can occur, for example, when a write request is received to change a value from previously stored data to a new value.

[0178] In operation S320, controller 1330 can determine whether the logical address received in operation S310 has been previously written to the second correspondence information 150. If the received logical address is stored in the second correspondence information 150, operation S330 can be performed.

[0179] In operation S330, the controller 1330 can select an MPH function corresponding to the received logical address by referencing the second correspondence information 150. Additionally, the controller 1330 can obtain information about the selected MPH function by referencing the translation information 130. For example, the controller 1330 can obtain an offset corresponding to the received logical address by using the selected MPH function.

[0180] In operation S340, the controller 1330 can obtain a representative address of a memory area corresponding to the selected MPH function. Additionally, the controller 1330 can obtain a physical address related to the logical address received in operation S310, based on the offset and the representative address. Therefore, the controller 1330 can translate the logical address into a physical address based on the MPH function of the logical address (refer to...). Fig. 9).

[0181] In operation S350, the controller 1330 can invalidate a correspondence relationship of the second correspondence information 150. To change the value of previous data to a new value, the controller 1330 can release or delete a previous correspondence relationship between a logical address and an MPH function. Additionally, the controller 1330 can delete (or invalidate) data from a memory location indicated by the physical address obtained in operation S340. Data deletion can be performed immediately or during a management operation (such as a garbage collection operation).

[0182] If the logical address received in operation S310 is managed in the second correspondence information 150, operation S360 can also be performed. In operation S360, the controller 1330 can control the storage devices 1310 such that write data is stored in a memory location indicated by a newly selected physical address. Additionally, the controller 1330 can update the first correspondence information 110a so that the logical address received in operation S310 corresponds to the new physical address.

[0183] Referring to the Fig. 14 and Fig. For example, controller 1330 can receive the logical address L11 from host 1100. The logical address L11 may already have been managed in the second correspondence information 150. This can occur, for example, if a write request is received to change the value of data previously stored in connection with the logical address L11 to a new value.

[0184] Therefore, with reference to Fig. 25. Controller 1330 can obtain the preceding physical address P1, which is associated with the logical address L11, based on the MPH function MPH1(). Controller 1330 can invalidate a correspondence between the logical address L11 and the MPH function MPH1() in the second correspondence information 150. Controller 1330 can delete (or invalidate) data from a memory location indicated by the preceding physical address P1. The MPH function MPH1() can still be managed in translation information 130 for other logical addresses L12 to L1r, which are used as key values.

[0185] Additionally, the controller 1330 can control the storage device 1310 such that write data is stored in a memory location indicated by a physical address P13, which is newly selected for the logical address L11. The controller 1330 can update the first correspondence information 110a to manage a correspondence relationship between the logical address L11 and the new physical address P13.

[0186] Fig. Section 24 describes that operation S360 is performed in parallel with operation S330, operation S340, and operation S350. However, in exemplary embodiments, operation S360 can be performed sequentially to (for example, before or after) operation S330, operation S340, and / or operation S350.

[0187] If the logical address received in operation S310 is not stored in the second correspondence information 350, operation S370 can be performed. In operation S370, the controller 330 can determine whether the logical address received in operation S310 has previously been written to the first correspondence information 110a. If the received logical address is stored in the first correspondence information 110a, operation S380 can be performed.

[0188] In operation S380, the controller 1330 can obtain a physical address corresponding to the received logical address based on the first correspondence information 110a. The controller 1330 can invalidate the correspondence relationship of the first correspondence information 110a. To change the value of previously stored data to a new value, the controller 1330 can release or clear a previous correspondence relationship between a logical address and a physical address. The controller 1330 can delete (or invalidate) data from a memory location indicated by the preceding physical address.

[0189] In operation S360, the controller 1330 can control the storage devices 1310 such that write data is stored in a memory location indicated by a newly selected physical address. The controller 1330 can update the first correspondence information 110a such that the logical address received in operation S310 corresponds to the new physical address.

[0190] Referring to the Fig. 14 and Fig. For example, controller 1330 can receive the logical address L21 from host 1100, and the logical address L21 may already have been managed in the first correspondence information 110a.

[0191] Therefore, with reference to Fig. 26. The controller 1330 can obtain the preceding physical address P21, which is associated with the logical address L21, based on the first correspondence information 110a. The controller 1330 can invalidate a correspondence relationship between the logical address L21 and the physical address P21 in the first correspondence information 110a. The controller 1330 can delete (or invalidate) data from a memory location indicated by the preceding physical address P21.

[0192] Additionally, the controller 1330 can control the storage devices 1310 such that write data is stored in a memory location indicated by a physical address P12, which is newly selected for the logical address L21. The controller 1330 can update the first correspondence information 110a to manage a correspondence relationship between the logical address L21 and the new physical address P12.

[0193] Fig. Section 24 describes that operation S380 is performed before operation S360. However, in exemplary embodiments, operation S380 can be performed after operation S360. Alternatively, operation S380 can be performed together with operation S360 (for example, in parallel with operation S360 or at substantially the same time as operation S360). Additionally, it describes Fig. 24, that operation S320 is performed before operation S370. However, in exemplary embodiments, operation S370 may be performed before operation S320. Alternatively, operation S370 may be performed together with operation S320 (for example, in parallel with operation S320 or at substantially the same time as operation S320).

[0194] In some cases, the logical address received in operation S310 cannot be managed in both the first correspondence information 110a and the second correspondence information 150. This can occur, for example, if a new logical address is received that is not yet managed. Consequently, in these cases, operation S130 of the Fig. 11 will be carried out.

[0195] The above description outlines processes for translating a logical address into a physical address. According to exemplary embodiments, in some cases a physical address can be translated inversely into a logical address. For this purpose, since an MPH function provides a one-to-one correspondence, an inverse function of the MPH function can exist. For example, the 1330 controller can translate a physical address into a logical address inversely based on the inverse function of the MPH function.

Claims

[1] Storage device (1300) comprising the following: a plurality of storage devices (1310, 1311-1319); and a controller (1330) configured to translate a logical address received from a host (1100) into a physical address of the storage devices (1310, 1311-1319), where the logical address is one of a plurality of logical addresses, and the physical address is one of a plurality of physical addresses, the controller (1330) is further configured to: to manage an initial correspondence information (110a; 110b; 110c) which is linked to a correspondence relationship between the logical addresses (L1-Lr) and the physical addresses (P1-Pr); to manage a translation information (130) which has information of a minimum perfect hash (MPH) function, wherein the MPH function is generated when a size of a first memory area in the memory devices (1310, 1311-1319) reaches a reference size, where the first memory area is indicated by logical addresses managed in the first correspondence information (110a; 110b; 110c), and the MPH function is generated using the logical addresses indicating the first memory area as key values; and to manage a second correspondence information (150) which is connected with a correspondence relationship between the logical addresses used as the key values ​​and the MPH function of the translation information (130). [2] Storage device (1300) according to claim 1, wherein: the controller (1330) is further configured to map the logical addresses used as the key values ​​to physical addresses of a second memory area in the storage devices (1310, 1311-1319) by reference to the MPH function, where the size of the second memory area is equal to the reference size, and a hash collision does not occur in response to a mapping of the logical addresses used as the key values ​​to the physical addresses of the second memory area. [3] Storage device (1300) according to claim 1, wherein: If a first logical address from the logical addresses used as the key values ​​is received from the host (1100), the controller (1330) is still configured to: to obtain the information of the MPH function, which corresponds to the first logical address, by referring to the second correspondence information (150) and the translation information (130); and to obtain a first physical address among the physical addresses, which is connected to the first logical address, based on the MPH function of the first logical address. [4] Storage device (1300) according to claim 3, wherein: the controller (1330) is further configured to: to obtain a representative address of a memory area corresponding to the MPH function, based on a selection of the MPH function from the second correspondence information (150); to calculate an offset based on the MPH function and the first logical address; and to obtain the first physical address based on the offset and the representative address. [5] Storage device (1300) according to claim 4, wherein: The first physical address indicates a memory location which is separated from the representative address by the offset in the memory area according to the MPH function. [6] Storage device (1300) according to claim 1, wherein: If a first logical address among the logical addresses, which is not used as the key values, is received by the host (1100), the controller (1330) is further configured to: to obtain a first physical address among the physical addresses, which corresponds to the first logical address, by referring to the first correspondence information (110a; 110b; 110c). [7] Storage device (1300) according to claim 1, wherein: the controller (1330) is further configured to invalidate the correspondence relationship of the first correspondence information (110a; 110b; 110c) in response to the creation of the MPH function, such that logical addresses managed in the second correspondence information (150) are not managed in the first correspondence information (110a; 110b; 110c). [8] Storage device (1300) according to claim 1, wherein: the controller (1330) is further configured to manage memory areas of the storage devices (1310, 1311-1319) based on the translation information (130), and the size of each of the memory areas is equal to the reference size; and the translation information (130) also includes information from MPH functions, each corresponding to the memory areas. [9] Storage device (1300) according to claim 8, further comprising: a buffer memory configured to buffer the information of the MPH functions, wherein the controller (1330) is further configured to determine a memory area corresponding to each of the MPH functions, based on memory locations where the information of the MPH functions is buffered in the buffer memory and memory locations of the memory areas in the storage devices (1310, 1311-1319). [10] Storage device (1300) according to claim 8, wherein: the translation information (130) also includes information from pointers, each of which is associated with the MPH functions; and the controller (1330) is further configured to determine a memory area of ​​the memory devices (1310, 1311-1319) corresponding to each of the MPH functions, based on memory locations indicated by the pointers. [11] Storage device (1300) according to claim 1, wherein: the translation information (130) also includes information on a seed value which is used to generate the MPH function. [12] Storage device (1300) according to claim 1, wherein: The controller (1330) has a plurality of hash operation circuits which generate the MPH function. [13] Storage device comprising: a plurality of storage devices (1310, 1311-1319); and a controller (1330) which is configured to control the storage devices (1310, 1311-1319) based on a request and a logical address received from a host (1100), the controller (1330) is further configured to: to determine whether the received logical address is managed according to one of the first correspondence information (110a; 110b; 110c), which indicates correspondence relationships between a first plurality of logical addresses and a plurality of physical addresses, or a second correspondence information (150), which indicates correspondence relationships between a plurality of minimal perfect hash (MPH) functions and a second plurality of logical addresses, where each of the plurality of MPH functions is generated based on a group of logical addresses; and to obtain a physical address which is associated with the received logical address, based on the received logical address and a selected MPH function which corresponds to the received logical address among the majority of MPH functions, when the received logical address is managed according to the second correspondence information (150). [14] Storage device (1300) according to claim 13, wherein: The controller (1330) is further configured to invalidate a correspondence relationship between the selected MPH function and the received logical address in the second correspondence information (150) if the request includes a write request and the received logical address is managed according to the second correspondence information (150). [15] Storage device (1300) according to claim 13, wherein: if the request includes a write request and the received logical address is managed according to the first correspondence information (110a; 110b; 110c), the controller (1330) is further configured to: to obtain a physical address that corresponds to the received logical address among the majority of physical addresses by referring to the first correspondence information (110a; 110b; 110c); and to invalidate a correspondence relationship between the received logical address and the corresponding physical address in the first correspondence information (110a; 110b; 110c). [16] Storage device (1300) according to claim 13, wherein: if the request includes a write request, the controller (1330) is further configured to: to control the storage devices (1310, 1311-1319) such that write data associated with the write request is stored at a storage location of the storage devices (1310, 1311-1319) indicated by a new physical address; and to update the first correspondence information (110a; 110b; 110c) such that the received logical address corresponds to the new physical address. [17] Storage device (1300) according to claim 13, wherein: if the request includes a read request, and the received logical address is managed according to the second correspondence information (150), the controller (1330) is further configured to: to control the storage devices (1310, 1311-1319) in such a way that read data associated with the read request is output from a storage location of the storage devices (1310, 1311-1319) which is indicated by the obtained physical address. [18] Storage device (1300) according to claim 13, wherein: if the request includes a read request and the received logical address is managed according to the first correspondence information (110a; 110b; 110c), the controller (1330) is further configured to: to obtain a physical address corresponding to the received logical address by referring to the first correspondence information (110a; 110b; 110c); and to control the storage devices (1310, 1311-1319) in such a way that read data associated with the read request is output from a storage location of the storage devices (1310, 1311-1319) which is indicated by the corresponding physical address. [19] Storage device (1300) according to claim 13, wherein: If the request includes a read request and the received logical address is not managed according to one of the first correspondence information (110a; 110b; 110c) or the second correspondence information (150), the controller (1330) is further configured to issue an error response to the host (1100). [20] Storage device (1300) comprising the following: a plurality of storage devices (1310, 1311-1319); and a controller (1330) which is configured to: to receive a first logical address; and to obtain a first physical address of the storage devices (1310, 1311-1319) based on the first logical address and a first perfect hash function, if the first logical address is managed according to the first correspondence information (110a; 110b; 110c) which indicates correspondence relationships between a plurality of perfect hash functions and a first plurality of logical addresses, where the first physical address is associated with the first logical address, the first logical address is contained in the first plurality of logical addresses, and the first perfect hash function is contained in the plurality of perfect hash functions, where the first perfect hash function corresponds to the first logical address, and each of the plurality of perfect hash functions is generated based on a group of logical addresses. [21] Storage device (1300) according to claim 20, wherein: The controller (1330) is further configured to generate information of a perfect hash function according to the receipt of a group of logical addresses. [22] Storage device (1300) according to claim 21, wherein: which indicates a group of logical addresses representing a first memory area of ​​a reference quantity in the memory devices (1310, 1311-1319); and a plurality of physical addresses, which is translated from the one group of logical addresses based on the one perfect hash function, indicates a second memory area of ​​the reference size in the storage devices (1310, 1311-1319). [23] Storage device (1300) according to claim 20, wherein: the controller (1330) is further configured to: to receive a second logical address; and to obtain a second physical address of the storage devices (1310, 1311-1319) which is associated with the second logical address, based on the second logical address and a second perfect hash function, when the second logical address is managed according to the first correspondence information (110a; 110b; 110c), where the second perfect hash function is contained in the majority of perfect hash functions and the second perfect hash function corresponds to the second logical address. [24] Storage device (1300) according to claim 23, wherein: the perfect hash functions correspond to different memory areas in the storage devices (1310, 1311-1319); and a memory area which has a memory location indicated by the first physical address, different from a memory area which has a memory location indicated by the second physical address. [25] Storage device (1300) according to claim 20, wherein: the controller (1330) is further configured to: to receive a second logical address, which corresponds to the first perfect hash function; and to obtain a second physical address of the storage devices (1310, 1311-1319) based on the second logical address and the first perfect hash function, where the second physical address is linked to the second logical address.

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