ACTIVE GATE BIAS DRIVER

Abstract

The facility features: a gate driver (302; 602; 802) configured to output a turn-on voltage to activate the switch (306; 606; 806) at the gate of a switch (306; 606; 806) in response to receiving a signal to activate the switch (306; 606; 806); and an active gate bias driver (304; 604; 804) configured to actively drive a voltage at the gate of the switch (306; 606; 806) to a bias voltage in response to receiving a signal to disable the switch (306; 606; 806), where the bias voltage is lower than the turn-on voltage and higher than a ground voltage of the gate driver (302; 602; 802), wherein the active gate bias driver (304; 604; 804) is further configured to receive a reference voltage signal (VREF; VCS) and to actively drive the gate voltage at the gate of the switch (306; 606; 806) to the bias voltage according to the reference voltage signal (VREF; VCS).

Description

[0001] This disclosure generally concerns gate drivers for driving semiconductor devices.

[0002] In a switch such as a field-effect transistor (FET), a body diode provides freewheeling capability and enables reverse recovery behavior. For example, during the switch's off-interval, the diode is biased forward, and a reverse recovery charge accumulates in the switch. At the beginning of the switch's off-interval, this accumulated reverse recovery charge recombines. During a switching cycle, this recombination results in a loss of switching power from the switch.

[0003] In general, circuits and techniques for actively driving a voltage across the gate of a switch are described in such a way as to reduce the reverse recovery charge in the switch and thereby decrease the switching losses in that switch and its complementary switch. Instead of applying a ground voltage to the gate of a switch to disable it, a gate driver can actively drive the gate voltage to a bias voltage. For example, during the dead time, the gate driver can actively drive the gate voltage of the switch to a bias voltage lower than a threshold voltage to reduce the conductivity of the switch's body diode.Additionally, the gate driver can actively adjust the bias voltage by monitoring the temperature coefficient of the threshold voltage to avoid temperature-related dynamic effects such as overshoot and unwanted turn-on. This reduces the reverse recovery charge in this and its complementary switch, thereby minimizing switching losses.

[0004] LINDBERG-POULSEN, K. [et al.]: “Practical Investigation of the Gate Bias Effect on the Reverse Recovery Behavior of the Body Diode in Power MOSFETs”, 2014 International Power Electronics Conference (IPEC-Hiroshima 2014 - ECCE ASIA), 18 - 21 May 2014, pages 2842 - 2849, describes a method in which a bias voltage is applied between the gate and source of a MOSFET, which is below a turn-on voltage but higher than zero when the MOSFET is in the reverse conducting state.

[0005] One embodiment of the invention relates to a device for controlling a switch according to claim 1.

[0006] Another embodiment of the invention relates to a method for controlling a switch according to claim 7.

[0007] Another embodiment of the invention relates to a system according to claim 12.

[0008] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, subject matter, and advantages of the disclosure are apparent from the description, the drawings, and the claims. Fig. Figure 1 is a block diagram illustrating an example system having an active bias capability for reducing the blocking delay charge in a switch, according to one or more aspects of the present disclosure. Fig. Figure 2 is a flowchart illustrating operations that are demonstrated by an example system having an active gate bias capability for reducing a blocking delay charge in a switch, according to one or more aspects of the present disclosure. Fig. Figure 3 is a block diagram illustrating a first example circuit having an active gate bias capability for reducing a blocking delay charge in a switch, according to one or more aspects of the present disclosure. Fig. 4 is a diagram showing signals generated by the Fig. The 3 example circuits shown are illustrated. Fig. 5 is a flowchart that shows example operations performed by the in Fig. The 3 example circuits shown are illustrated. Fig. Figure 6 is a block diagram illustrating a second example circuit having an active gate bias capability for reducing a blocking delay charge in a switch, according to one or more aspects of the present disclosure. Fig. 7 is a flowchart that shows example operations performed by the in Fig. The example circuit shown in section 6 illustrates how it can be executed. Fig. Figure 8 is a block diagram illustrating a third example circuit having an active gate bias capability for reducing a blocking delay charge in a switch, according to one or more aspects of the present disclosure. Fig. 9 is a flowchart that shows example operations performed by the in Fig. The example circuit shown in section 8 illustrates how it can be executed. Fig. Figure 10 is a block diagram illustrating a fourth example circuit having an active gate bias capability for reducing a blocking delay charge in a switch, according to one or more aspects of the present disclosure. Fig. Figure 11 is a block diagram illustrating a fifth example circuit having an active gate bias capability for reducing a blocking delay charge in a switch, according to one or more aspects of the present disclosure. Fig. Figure 12 is a block diagram illustrating a sixth example circuit having an active gate bias capability for reducing a blocking delay charge in a switch, according to one or more aspects of the present disclosure. Fig. Figure 13 is a block diagram illustrating a seventh example circuit having an active gate bias capability for reducing a blocking delay charge in a switch, according to one or more aspects of the present disclosure. Fig. Figure 14 is a diagram illustrating the behavior of an example system having an active gate bias capability for reducing a blocking delay charge in a switch, according to one or more aspects of the present disclosure. Fig. Figure 15 is a diagram illustrating a switching energy loss according to one or more aspects of the present disclosure. Fig. Figure 16 is an example circuit for a motor application according to one or more aspects of the present disclosure. Fig. Figure 17 is a diagram showing the initial thermal behavior of the example circuit. Fig. 16 illustrated according to one or more aspects of the present revelation. Fig. Figure 18 is a diagram, a second thermal behavior of the example circuit from Fig. 16 illustrated according to one or more aspects of the present revelation.

[0009] In some applications, such as motor drives, DC-to-DC power converters, solar inverters, etc., switches can operate with switching losses that constitute a significant portion of the total losses. Such switches can be implemented in an inverter, for example, in an intelligent power module (IPM). For instance, a gate driver can alternately activate a high-side switch and a low-side switch, so that during the first part of a switching cycle, the high-side switch is activated and the low-side switch is deactivated, and during the second part of the switching cycle, the high-side switch is deactivated and the low-side switch is activated.

[0010] A gate driver can use a "dead time" to prevent the high-side and low-side switches from being activated simultaneously. For example, the gate driver disables the high-side and low-side switches during the first dead time of a switching cycle. In the example, the gate driver activates the high-side switch and deactivates the low-side switch during the first part of the switching cycle. In the example, the gate driver disables the high-side and low-side switches during the second dead time of the switching cycle. In the example, the gate driver deactivates the high-side switch and activates the low-side switch during the second part of the switching cycle. However, in such applications, recovery losses due to the accumulation of minority charge carriers during the dead time portion of switching transitions can represent a significant portion of the switching losses.For example, for an inverter that uses a dead time and operates at a bus voltage of 320 V with a motor phase current of 200 milliamperes square mean (mA). rms ) and a pulse width modulation (PWM) frequency of 20 kHz, it was found that the reverse recovery losses account for 63% of the total power loss of the inverter.

[0011] One technical aspect of the problem relates to high-voltage switches used in integrated power modules (IPMs) for very low-power (e.g., < 200 W) motor drive applications in air conditioning and pumping applications. As used here, a high-voltage switch can refer to switches designed to operate between 250 volts and 1200 volts. In these applications, the motors may spend the vast majority of their operating life running under light-load conditions at a fraction of their maximum rated load. In these applications, IPMs may operate in the 6–20 kHz frequency range. In these applications, switch turn-on losses may dominate over line losses. A major contributor to switching losses may result from the recovery losses of the switch's internal body diode.These recovery losses can occur due to the storage of minority charge carriers during a dead-time portion of the switching transitions. For example, for an inverter using these IPMs, operating at a bus voltage V. BUS = 320 V, one motor phase current I motor = 200 mA rms and operating at a PWM frequency fsw = 20 kHz, it was found that the reverse recovery losses of the conventional switch amount to 63% of the total inverter losses. Therefore, reducing the reverse recovery losses of the body diode can be very important to improve the switch's turn-on losses and the overall system efficiency.

[0012] In an effort to reduce switching losses, electron beam irradiation and platinum (Pt) implantation have been used. Even with these interventions, for example, in a 20 kHz inverter driving a fan, reverse recovery losses can account for 40% of the total losses. Additionally, some techniques may focus on controlling a body diode's reverse recovery charge using gate bias control based on a diode (e.g., diode chains, a diode and resistors, etc.). However, such techniques can bias a gate with a diode's forward voltage drop (e.g., less than 0.7 V), which is insufficient for high-voltage switches. For example, such techniques may not be suitable for high-voltage (e.g.,250-1200 V FET devices with a gate threshold of a few volts will not operate because the gate bias effect is more pronounced at gate voltages significantly higher than the diode's forward voltage drop (e.g., 0.7 V). Additionally, adding an isolated diode component to the manufacturing process of a modern high-voltage integrated circuit may require specialized isolation techniques and process steps, which can greatly increase the manufacturing cost of the resulting device. Furthermore, if a non-isolated diode is used, forward biasing it will cause a carry event, interrupting logic operation and potentially leading to latch-ups in an integrated driver circuit.Furthermore, such techniques can suffer from the effect that the gate bias level decays over time inversely proportional to the gate capacitance and diode impedance. Therefore, such techniques may only be suitable for power converters operating with very short dead times (e.g., 20 nanoseconds (ns)). Additionally, the temperature coefficient of a diode (e.g., -2.5 mV per degree Celsius) may not follow the temperature coefficient of the switch (e.g., -8.5 mV per degree Celsius), causing instabilities during high-temperature operation. A gate can be constantly biased and therefore, as the temperature increases, may exhibit sub-threshold leakage. Moreover, the aforementioned techniques typically operate at very high frequencies, for example, above 100 kHz, and lower voltage classes (e.g., < 100 V).These very high frequencies and lower voltage classes may be unsuitable for inverters used in motor drives that operate at higher voltages (e.g. 250-1200 V) and significantly longer dead times (e.g. 2 milliseconds (ms)) and frequencies typically below 100 kHz.

[0013] Instead of relying on electron beam irradiation or a diode forward voltage drop, circuits and methods are described for actively driving a switch gate, thereby reducing the reverse recovery charge in the switch. For example, a system can actively drive the voltage at the switch gate to compensate for changes in the switch's temperature or other conditions, adjusting its driving capability accordingly. In this way, the system can reduce losses that would otherwise occur in the switch.

[0014] Fig. Figure 1 is a block diagram illustrating an example system 100 having an active gate bias capability for reducing a blocking delay charge at a switch 106 according to one or more aspects of the present disclosure. Fig. Figure 1 shows the system comprising a controller 101, a gate driver 102, an active gate bias driver 104, and a switch 106. The gate drive output of the active gate bias driver 104 is electrically coupled to the gate 110 of the switch 106. The system 100 may include additional components beyond those shown. In some examples, the system 100 may be implemented as a single or multiple integrated circuit (IC) package.

[0015] Controller 101 provides instructions for enabling and disabling switch 106. In some examples, controller 101 may be a modulation (e.g., pulse-width modulation) controller. For example, controller 101 may output a high signal (e.g., logic "1") to gate driver 102 to signal an instruction to enable switch 106 during the first part of a pulse-width modulation cycle. In the same example, controller 101 may output a low signal (e.g., logic "0") to gate driver 102 to signal an instruction to disable switch 106 during the second part of the pulse-width modulation cycle. However, in some examples, the controller 101 can output a low signal (e.g., logic "0") to the gate driver 102 to signal an instruction to activate the switch 106, and a high signal (e.g.,output logically “1”) to signal an instruction to deactivate switch 106.

[0016] In some examples, controller 101 can issue an instruction to enable switch 106 using a pulse-width modulation cycle that includes a dead time. For example, controller 101 can issue an instruction to gate driver 102 to disable switch 106 and an associated high-side switch during the first part of a switching cycle. During the second part of the switching cycle, controller 101 can issue an instruction to gate driver 102 to enable the high-side switch and issue an instruction to gate driver 102 to disable switch 106. During the third part of the switching cycle, controller 101 can issue an instruction to gate driver 102 to disable both the high-side switch and switch 106.During a fourth part of the switching cycle, controller 106 can issue an instruction to gate driver 102 to disable the high-side switch and an instruction to gate driver 102 to enable switch 106. In this way, controller 101 can reduce the probability of the high-side switch and switch 106 being unintentionally enabled simultaneously.

[0017] The Controller 101 may comprise a suitable arrangement of hardware, software, firmware, or any combination thereof to perform the techniques described herein and attributed to the Controller 101. The Controller 101 may include any or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuit technology, as well as any combination of such components. If the Controller 101 includes software or firmware, the Controller may further include any hardware required to store and execute the software or firmware, such as one or more memories and one or more processors or processing units.In general, a processing unit can contain one or more microprocessors, DSPs, ASICs, FPGAs, or any other equivalent integrated or discrete logic circuit technology, as well as any combination of such components.

[0018] Switch 106 represents any conceivable switching device configured to receive a gate driver signal from a driver such as the gate driver 102 and / or the active gate bias driver 104. For example, switch 106 may be a field-effect transistor (FET). Switch 106 may also be a metal-oxide-semiconductor FET (MOSFET) used in a switching-mode power supply (SMPS). Examples of a switch may include, but are not limited to, a junction field-effect transistor (JFET), a metal-oxide-semiconductor FET (MOSFET), a dual-gate MOSFET, an insulated-gate bipolar transistor (IGBT), or any other type of FET, or any combination thereof.Examples of MOSFETs may include, but are not limited to, a p-channel MOSFET (p-MOS), an n-channel MOSFET (n-MOS), a double-diffused MOSFET (DMOS), or any other type of MOSFET, or any combination thereof. In some examples, switch 106 may incorporate a high electron mobility transistor. Additionally, in some cases, switch 106 may incorporate a gallium nitride (GaN)-based transistor. Other materials may also be used to implement switch 106. In some examples, switch 106 may be a high-voltage switch. A high-voltage switch, as used herein, may refer to a switch designed to operate between 200 volts and 1200 volts.

[0019] Switch 106 has three terminals, although in other examples, switch 106 may have additional terminals. The gate 110 of switch 106 can be electrically coupled to the active gate bias driver 104. Terminals 108A and 108B of switch 106 can be coupled to a voltage source and / or a load. During operation, switch 106 can receive a gate driver signal at gate 110 from the active gate bias driver 104, causing switch 106 to change operating states. Depending on the voltage of the gate driver signal at gate 110, switch 106 can become active (e.g., "turn on") or inactive (e.g., "turn off"). When activated, switch 106 can conduct current between terminals 108A and 108B. When deactivated, switch 106 can refrain from conducting current and block a voltage between terminals 108A and 108B of switch 106.

[0020] Gate driver 102 provides system 100 with driver capabilities for driving switch 106. For example, gate driver 102 can output a turn-on voltage that causes switch 106 to become active, or a turn-off voltage that causes switch 106 to become inactive. A turn-on voltage, as used here, can refer to a voltage that exceeds a threshold voltage for activating switch 106, and a turn-off voltage can refer to a voltage that is less than the threshold voltage for deactivating switch 106. For example, the turn-off voltage can be a system 100 ground. In some cases, the turn-off voltage can be a voltage at terminal 108B (e.g., a source of switch 106).

[0021] The gate driver 102 can be a standalone component of the system 100, or it can be part of a larger system or a component of the system 100. For example, the gate driver 102 can be a discrete component, or, in other examples, it can be part of the controller 101. In some cases, the gate driver 102 can be a high-voltage gate driver. A high-voltage gate driver, as used here, can refer to a gate driver designed to operate between 250 volts and 1200 volts.

[0022] The Gate Driver 102 may comprise a suitable arrangement of hardware, software, firmware, or any combination thereof to perform the techniques described herein and attributed to the Gate Driver 102. The Gate Driver 102 may include any or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuit technology, as well as any combination of such components. If the Gate Driver 102 includes software or firmware, it may further include any hardware required to store and execute the software or firmware, such as one or more memories and one or more processors or processing units.

[0023] The active gate bias driver 104 can be a standalone component of the system 100, or it can be part of a larger system or component of the system 100. For example, the gate bias driver 104 can be a discrete component, or in other examples, it can be part of a controller (such as a modulation controller) that controls the gate driver 102, the active gate bias driver 104, the switch 106, and other components of the system 100. In some examples, the active gate bias driver 104 can be an active high-voltage gate bias driver. An active high-voltage gate bias driver, as used herein, can refer to an active gate bias driver designed to operate between 250 volts and 1200 volts.

[0024] The active gate bias driver 104 may include a suitable arrangement of hardware, software, firmware, or any combination thereof to perform the techniques described herein and attributed to the active gate bias driver 104. The active gate bias driver 104 may include any or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuit technology, as well as any combination of such components. If the active gate bias driver 104 includes software or firmware, it may further include any hardware required to store and execute the software or firmware, such as one or more memories and one or more processors or processing units.

[0025] The active gate bias driver 104 provides the system with active gate bias driving capabilities for driving the switch 106. For example, the active gate bias driver 104 can actively drive a voltage at the gate 110 of the switch 106 to a bias voltage without exceeding a threshold voltage for activating the switch 106. A bias voltage, as used here, can refer to a voltage that is less than a threshold voltage for activating the switch 106 and greater than a ground voltage of the system 100.

[0026] Instead of applying a minimum or ground voltage to the gate 110 of switch 106 to disable the switch 106, the active gate bias driver 104 can actively drive a voltage at the gate 110 of switch 106 to a bias voltage. For example, the active gate bias driver 104 can be configured to actively drive a voltage at the gate 110 of switch 106 to a bias voltage corresponding to a reference voltage signal. Additionally or alternatively, the bias driver 104 can be configured to drive a voltage at the gate 110 of switch 106 to a bias voltage corresponding to a current flowing through switch 106 (e.g., between terminal 108A and terminal 108B). In this way, a reverse recovery charge in switch 106 is reduced, thereby minimizing losses that would otherwise occur in switch 106.

[0027] Fig. Figure 2 is a flowchart illustrating operations performed by an example system having an active gate bias capability for reducing a reverse delay charge in a switch, according to one or more aspects of the present disclosure. For example, the gate driver 102 and the active gate bias driver 104 of system 100 of Fig. 1 Operations 202-206 of Fig. 2. Execute to switch the switch 106 of system 100 from Fig. 1 to control. This is solely for illustrative purposes. Fig. 2 below in the context of system 100 of Fig. 1 described.

[0028] During operation, the gate driver 102 can output a turn-on voltage to activate switch 106 in response to receiving a signal to do so (202). For example, in response to receiving a signal (e.g., a high signal) from the controller to activate switch 106, the gate driver 102 outputs a turn-on voltage to activate switch 106.

[0029] In some examples, the gate driver 102 can optionally output a turn-off voltage to disable switch 106 in response to receiving a signal to disable switch 106 (204). For example, in response to receiving a signal (e.g., a low signal) from the controller to disable switch 106, the gate driver 102 outputs a ground voltage to disable switch 106. In any case, the active gate bias driver 104 can actively drive a voltage at the gate 110 of switch 106 to a bias voltage in response to receiving a signal to disable switch 106 (206). For example, in response to receiving a signal (e.g.,a low signal) from the controller to deactivate switch 106, a voltage at the gate 110 of switch 106 based on a temperature of switch 106, a current flowing from terminal 108A between 108B, a voltage at gate 110 or a combination thereof, actively applied to a bias voltage.

[0030] Fig. Figure 3 is a block diagram illustrating a first example circuit 300 having an active gate bias capability for reducing a blocking delay charge in a switch according to one or more aspects of the present disclosure. Fig. Figure 3 shows a gate driver 302, an active gate bias driver 304, and a switch 306. Gate driver 302 could be an example of gate driver 102 from Fig. 1. The active gate bias driver 304 could be an example of the active gate bias driver 104 from Fig. 1. Switch 306 could be an example of switch 106 from Fig. 1. For example, switch 306 can contain a gate 310, which can be an example of gate 110. Fig. 3 is used solely for explanatory purposes in the context of the Fig. 1 and Fig. 2 described.

[0031] The gate driver 302 can include a gate drive controller 320 and switching elements 322 and 324. Switching elements 322 and 324 can contain a FET, but are not limited to this. As shown, switching element 322 can be a p-channel MOSFET, although switching element 322 may be different in other examples. Similarly, switching element 324 can be an n-channel MOSFET, although switching element 324 may be different in other examples. The gate drive controller 320 can be configured to generate an initial control signal in response to receiving a signal to activate switch 306. For example, the gate drive controller 320 can be triggered by the controller 101 in response to receiving a low signal at the high-side input (e.g., HS). in) generate a first control signal (e.g., Vcc) that deactivates the switching element 322 to electronically isolate the gate 310 of switch 302 from the turn-on voltage 327. However, in response to receiving a high signal from the controller 101 at the high-side input, the gate drive controller 320 can generate a first control signal (e.g., ground) that activates the switching element 322 to create a channel that electronically connects the turn-on voltage 327 to the gate 310 of switch 306. Similarly, the gate drive controller 320 can be configured to generate a second control signal in response to receiving a signal to deactivate switch 306. For example, in response to receiving a low signal from the controller 101 at the low-side input (e.g., LSin), the gate drive controller 320 can generate a second control signal (e.g.,The gate driver 302 can generate a high-level signal (e.g., Vcc) that deactivates the switching element 324, electronically isolating the gate 310 of switch 306 from ground 328. However, in response to receiving a high signal from the controller 101 at the low-side input, the gate driver 302 can generate a second control signal (e.g., Vcc) that activates the switching element 324 to create a channel that electronically connects ground 328 to the gate 310 of the switch. In this way, the gate driver 302 can selectively connect the gate 310 of switch 306 to either the turn-on voltage 327 or ground 328.

[0032] The active gate bias driver 304 can include a timing control module 330 and an active gate bias module 331. In some examples, the timing control module 330 can be a transconductance operational amplifier. The timing control module 330 can be configured to output a signal to provide an active gate bias voltage for disabling the switch based on first and second control signals. For example, in response to receiving a first control signal from the gate drive controller 320, signaling to disable the switching element 322, and a second control signal, signaling to disable the switching element 324, the timing control module 330 can cause the gate bias module 331 to supply an active gate bias to the gate 310 of the switch 306.However, in this example, the timing control module 330, in response to receiving a first control signal from the gate drive control 320, which signals to activate the switching element 322, can cause the active gate bias module 331 to refrain from supplying an active gate bias to the gate 310 of the switch 306. Similarly, in this example, in response to receiving a second control signal from the gate drive control 320, which signals to activate the switching element 324, the timing control module 330 can cause the active gate bias module 331 to refrain from supplying an active gate bias to the gate 310 of the switch 306. In this way, the timing control module 330 can activate the gate bias module 331 during a dead-time switching operation of the switch 306.

[0033] The active gate bias module 331 can actively drive a voltage at the gate 310 of the switch 306 during various parts of a switching cycle. For example, the active gate bias module 331 can actively drive a voltage at the gate 310 of the switch 306 to a bias voltage during a dead time of the switch 306. For example, in response to receiving a first control signal from the gate drive control 320 (e.g., a low signal) signaling to deactivate the switching element 322 and a second control signal signaling to deactivate the switching element 324, the timing control module 330 can determine that the switch 306 is operating in a dead time, and in response to the determination that the switch 306 is operating in the dead time, the gate bias module 331 can cause a voltage at the gate 310 of the switch 306 to be driven to a bias voltage during the dead time of the switch 306.Additionally or alternatively, the active gate bias module 331 can actively drive a voltage at the gate 310 of switch 306 to a bias voltage during a line through a body diode of switch 306. Additionally or alternatively, the active gate bias module 331 can actively drive a voltage at the gate 310 of switch 306 to a bias voltage when switch 306 is deactivated. For example, in response to receiving a first control signal from the gate drive control 320, which signals to deactivate the switching element 322, and a second control signal, which signals to activate the switching element 324, the timing control module 330 can determine that the switch 306 is deactivated and, in response to the determination that the switch 306 is deactivated, can cause the gate bias module 331 to actively drive a voltage at the gate 310 of the switch 306 to the bias voltage during the dead time of the switch 306.

[0034] In some examples, the active gate bias module 331 can actively drive a voltage at gate 310 of switch 306 to a different bias voltage for different parts of a switching cycle. For example, the active gate bias module 331 can actively drive a voltage at gate 310 of switch 306 to a first bias voltage during a dead time of switch 306 before switch 306 is activated. In the example, the active gate bias module 331 can actively drive a voltage at gate 310 of switch 306 to a second bias voltage during a dead time of switch 306 before switch 306 is deactivated.

[0035] The active gate bias module 331 can contain a differential amplifier 332, switching elements 334 and 336. The switching elements 334 and 336 can contain a FET, but they are not limited to this. In the example of Fig. The active gate bias module 331 is configured to actively drive a bias voltage at the gate 310 of switch 306 in response to receiving a signal to deactivate switch 306. For example, in response to receiving a signal (e.g., a high signal) from the timing control module 330, switching elements 334 and 336 create an electrical channel between the output of differential amplifier 332 and the gate 310 of switch 306, thus electronically connecting differential amplifier 332 to the gate 310 of switch 306.

[0036] In the example of Fig. In Figure 3, the active gate bias driver 304 is configured to receive a reference voltage signal. For example, the differential amplifier 332 receives the reference voltage signal at a negative input terminal. In these examples, the active gate bias driver 304 is configured to actively drive the voltage at gate 310 of switch 306 to the bias voltage according to the reference voltage signal. Additionally or alternatively, in some examples, the active gate bias driver 304 is configured to receive an indication of a gate voltage at gate 310 of switch 306 and to actively drive the voltage at gate 310 of switch 306 to the bias voltage according to the indication of the gate voltage. For example, the differential amplifier 332 actively drives the voltage at gate 310 of switch 306 to the bias voltage to minimize any difference between the voltage at gate 310 and the reference voltage signal.

[0037] From the reference voltage source 326, a reference voltage signal can be generated which has a temperature coefficient corresponding to a temperature coefficient of a gate threshold (V). th ) for switch 306, exhibits, and is output. For example, the gate threshold (V) decreases th ) for switch 306 in response to switch 306 heating up. In this example, the reference voltage signal for switch 306 decreases in response to the reference voltage source 326 heating up. Similarly, the gate threshold (V) increases. th) in response to the cooling of switch 306. In this example, the reference voltage signal for switch 306 increases in response to the cooling of the reference voltage source 326. The reference voltage source 326 and switch 306 can be located in close proximity, so that a temperature change of switch 306 is translated into a corresponding temperature change of the reference voltage source 326. Additionally or alternatively, the reference voltage source 326 and switch 306 can be located in close proximity, so that a temperature change of the reference voltage source 326 is translated into a corresponding temperature change of switch 306. In this way, the active gate bias driver 304 can adjust the temperature response of switch 306 to prevent temperature-related dynamic effects such as overshoot and unwanted turn-on in switch 306, thereby reducing recovery losses of switch 306.

[0038] To further reduce power loss, the reference voltage source 326 can select an optimal gate voltage waveform during dead-time switching and / or during conduction of the body diode of switch 306 in order to minimize sub-threshold loss when a gate bias is applied. For example, the active gate bias module 331 can actively drive a voltage at the gate 310 of switch 306 to a first bias voltage during the first dead time of switch 306, before switch 306 is activated. Similarly, during the second dead time of switch 306, before switch 306 is deactivated, the active gate bias module 331 can actively drive a voltage at the gate 310 of switch 306 to a second bias voltage. In this way, the active gate bias driver 304 can reduce sub-threshold loss during the dead time while the gate bias is applied, thereby reducing recovery losses.

[0039] Fig. 4 is a diagram showing signals generated by the Fig. The 3 example circuits shown are illustrated. Fig. 4 is used for illustrative purposes only in the context of Fig. 1-3 described. In the example of Fig. 4 The gate drive control 320 outputs a first control signal 402 to a gate of the switching element 322 (e.g. a PMOS) and outputs a second control signal 404 to a gate of the switching element 324 (e.g. an NMOS). Fig. Figure 4 shows a second control signal 404, which is inverted as the second control signal 406. In the example of Fig. 4. The timing control module 330 receives the first control signal 402 and the second control signal 404 and outputs a timing control signal 408 to the switching elements 334 and 336 of the active gate bias module 331. As shown, the timing control signal 408 can signal a dead time of the switch 306. That is, the timing control signal 408 can signal part of a pulse-width modulated signal in which the switching elements 326 and 324 are deactivated. In any case, the active gate bias module 331 drives a voltage 410 at the gate 310 of the switch 306 according to the timing control signal 408. As shown, the gate bias module 331 actively drives a voltage 410 at the gate 310 of the switch 306 to a bias voltage 420 when the timing control signal 408 signals the dead time of the switch 306 (e.g., when the timing control signal 408 is high).

[0040] Fig. 5 is a flowchart that shows operations performed by the in Fig. The 3 example circuits shown are illustrated. Fig. 5 is used for illustrative purposes only in the context of Fig. Described in sections 1-4. During operation, the gate driver 302 can determine whether to activate switch 306 (502). For example, the gate driver 302 can activate switch 306 in response to a high signal at the high input (e.g., HS). in ) and a low signal at the low input (e.g., LS in The controller 101 determines whether to activate switch 306. In response to this determination, the gate driver 302 can output a turn-on voltage to activate switch 306 (520). For example, in response to receiving a signal (e.g., a high signal) from the controller to activate switch 306, the gate driver 302 outputs a turn-on voltage to activate switch 306.

[0041] However, in response to a command to disable switch 306, gate driver 302 can output a turn-off voltage to disable switch 306 (504). For example, in response to receiving a signal (e.g., a low signal) from controller 101 to disable switch 306, gate driver 302 outputs a turn-off voltage to enable switch 306. In this example, the active gate bias driver 304 can actively drive a voltage at gate 310 of switch 306 to a bias voltage corresponding to a reference voltage signal and a gate voltage at gate 310 of switch 306 (506). For example, if the timing control signal 408 signals the dead time of the switch 306, the differential amplifier 332 of the active gate bias driver 304 actively drives the voltage at the gate 310 of the switch 306 to the bias voltage in order to minimize a difference between the voltage at the gate 310 and the reference voltage signal.

[0042] Fig. Figure 6 is a block diagram illustrating a second example circuit 600 which has an active gate bias capability for reducing a blocking delay charge in a switch according to one or more aspects of the present disclosure. Fig. Figure 6 shows a gate driver 602, an active gate bias driver 604, and a switch 606. The gate driver 602 could be an example of the gate driver 102 from Fig. 1 and / or an example of the 302 gate driver from Fig. 3. For example, a gate drive controller 620 could be an example of the gate drive controller 320 from Fig. 3 act and / or the switching elements 622 and 624 may be examples of switching elements 322 and 324 respectively of Fig. 3. The active gate bias driver 604 could be an example of the active gate bias driver 104 from Fig. 1 and / or an example of the active gate bias driver 304 from Fig. 3. For example, the timing control module 630 could be an example of the timing control module 330, the active gate bias module 631 could be an example of the active gate bias module 331. The switch 606 could be an example of the switch 106 of Fig. 1. For example, switch 606 can trade a gate 610, which can be an example of gate 610. Fig. 6 is used for illustrative purposes only in the context of Fig. 1-5 described.

[0043] In the example of Fig. 6. The active gate bias driver 604 can be configured to receive an indication of a current flowing through the switch 606. For example, the active gate bias driver 604 can receive a voltage at a resistive element 652 indicating a current flowing through the switch 606. In some examples, a signal conditioning module 638 can optionally condition the voltage output by the resistive element 652. In any case, the active gate bias driver 604 can be configured to actively drive the voltage at the gate 610 of the switch 606 to the bias voltage according to the indication of the current flowing through the switch 606. For example, a differential amplifier of the active gate bias module 631 can actively drive the voltage at the gate 610 of the switch 606 to the bias voltage in order to minimize a difference between the voltage at the resistive element 652 and a reference voltage signal (e.g. Vcs).

[0044] Accordingly, instead of relying internally on a voltage reference, the active gate bias driver 604 can sense a current during a reverse delay time, controlled by an integrated active clamp, to minimize power loss during the reverse delay time. The active gate driver 604 can be configured as an active gate control loop to clamp a gate voltage at a gate 610 during a Miller-induced gate turn-on.

[0045] Fig. 7 is a flowchart that shows operations performed by the in Fig. The example circuit shown in section 6 illustrates how it can be executed. Fig. 7 is used for illustrative purposes only in the context of Fig. Described in sections 1-6. During operation, the gate driver 602 can determine whether to activate the switch 606 (702). For example, the gate driver 602 can determine to activate the switch 606 in response to receiving a high signal at the high input (e.g., HSin) and a low signal at the low input (e.g., LS). in ) activated by controller 101. In response to the instruction to activate switch 606, gate driver 602 can output a turn-on voltage to activate switch 606 (720). For example, in response to receiving a signal (e.g., a high signal) from controller 101 to activate switch 606, gate driver 602 outputs a turn-on voltage to activate switch 606.

[0046] However, in response to a signal to disable switch 606, gate driver 602 can output a turn-off voltage to disable switch 606 (704). For example, in response to receiving a signal (a low signal) from controller 101 to disable switch 606, gate driver 602 outputs a turn-off voltage to enable switch 606. In this example, the active gate bias driver 604 can actively drive a voltage at the gate 610 of switch 606 to a bias voltage corresponding to a current flowing through switch 306 (706). For example, if the timing control signal 408 indicates the dead time of the switch 606, a differential amplifier of the active gate bias driver 604 actively drives the voltage at the gate 610 of the switch 606 to the bias voltage in order to minimize a difference between the voltage at the resistive element 652 and a reference voltage signal.

[0047] Fig. Figure 8 is a block diagram illustrating a third example circuit 800, which has an active gate bias capability for reducing a blocking delay charge in a switch, according to one or more aspects of the present disclosure. Fig. Figure 8 shows a gate driver 802, an active gate bias driver 804, and a switch 806. The gate driver 802 could be an example of the gate driver 102 from Fig. 1. The gate driver 802 could be an example of the gate driver 303. For example, the gate drive controller 620 could be an example of a gate drive controller 320. Fig. 3 act and / or in the case of switching elements 822 and 824, these can be examples of switching elements 322 and 324 respectively. Fig. 3. The gate driver 802 could be an example of the gate driver 602. For example, the switching elements 822 and 824 could be examples of the switching elements 622 and 624, respectively, of Fig. 6. The active gate bias driver 804 could be an example of the active gate bias driver 104 from Fig. 1. A differential amplifier 832 could be an example of the differential amplifier 332 from Fig. 3 and / or the differential amplifier 632 of Fig. 6. The timing control module 830 could be an example of the timing control module 330, the active gate bias module 831 could be an example of the active gate bias module 331. The switch 806 could be an example of the switch 106 of Fig. 1. For example, switch 806 can be a gate, which is an example of gate 110 from Fig. 1 can act, contain. A resistive element 852 can be essentially similar to the resistive element 652 of Fig. 6. Fig. 8 is used for illustrative purposes only in the context of Fig. 1-7 described.

[0048] In the example of Fig. The active gate bias driver 804 can include a buffer module 840 and switching elements 842 and 844. The switching elements 842 and 844 can contain a FET, but are not limited to this. The buffer module 840 can be configured to store a buffered voltage corresponding to a voltage detected at the gate 810. For example, the buffer module 840 can contain one or more capacitive elements. The timing control module 830 can be configured to cause the active gate bias driver 804, when it actively drives the voltage at the gate 810 of the switch 806 to the bias voltage, to initially output a buffered voltage to the gate 810 of the switch 806. For example, the timing control module 830 can activate the switching element 844 to generate an electrical channel between the buffer module 840 and the gate 810 of the switch 806 for an initial part (less than 20%) of a dead time of a switching cycle.In some examples, the active gate bias driver 804 can be configured to modify the buffered voltage so that it corresponds to a detected voltage at the gate 810 of switch 806. In this example, the detected voltage can be detected after the initial output of the buffered voltage and before switch 806 is activated. For instance, the timing control module 830 can activate the switching element 844 in a final part (e.g., the last 20%) of the switching cycle's dead time to store a voltage detected at the gate 810 of switch 806 in the buffer module 840. In this way, to improve the response speed of a closed-loop system to an active generic disturbance (GD), a gate voltage from a previous recovery cycle can be stored in a gate voltage detection and hold circuit of the buffer module 840.During a standard gate drive period, the voltage at the gate voltage sensing and holding circuit of buffer 840 can be buffered to the active GD output. In the next recovery cycle, the active GD can quickly establish the operating point to improve speed during the lock-back delay period.

[0049] Fig. 9 is a flowchart that shows operations performed by the in Fig. The example circuit shown in section 8 illustrates how it can be executed. Fig. 9 is used for illustrative purposes only in the context of Fig. Described in sections 1-8. During operation, the gate driver 802 can determine whether to activate switch 806 (902). For example, the gate driver can activate switch 806 in response to receiving a high signal at the high input (e.g., HS). in ) and a low signal at the low input (e.g., LS inThe controller 101 determines whether to activate switch 806. In response to this determination, the gate driver 802 can output a turn-on voltage to activate switch 806 (920). For example, in response to receiving a signal (e.g., a high signal) from the controller to activate switch 806, the gate driver 802 outputs a turn-on voltage to activate switch 806.

[0050] However, in response to a signal to disable switch 806, gate driver 802 can output a turn-off voltage to disable switch 806 (904). For example, in response to receiving a signal (e.g., a low signal) from controller 101 to disable switch 806, gate driver 802 outputs a turn-off voltage to enable switch 806. In this example, the active gate bias driver 804 can actively drive a voltage at gate 810 of switch 806 to a bias voltage (906). For example, if the timing control signal 408 indicates the dead time of switch 806, the timing control module 830 can activate the switching element 844 to generate an electrical channel between the buffer module 840 and the gate 810 of switch 806 for an initial part (less than 20%) of the dead time of a switching cycle.In this example, the active gate bias driver 804 can modify the buffered voltage to match a detected voltage at the gate (906). For example, if the timing control signal 408 indicates a final part of the dead time of switch 806, the control module 830 can activate the switching element 844 to create an electrical channel between the buffer module 840 and the gate 810 of switch 806, in order to store a voltage at the gate 810 of switch 806 in the buffer module 840.

[0051] Fig. Figure 10 is a block diagram illustrating a fourth example circuit 1000, which has an active gate bias capability for reducing a blocking delay charge in a switch, according to one or more aspects of the present disclosure. Fig. Figure 10 shows a gate driver 1002, an active gate bias driver 1004, and a switch 1006. Gate driver 1002 could be an example of gate driver 102 from Fig. 1. The gate driver 1002 could be an example of the gate driver 302 from Fig. 3. For example, switching elements 1022 and 1024 could be examples of switching elements 322 and 324, respectively, of Fig. 3. The active gate bias driver 1004 could be an example of the active gate bias driver 104 from Fig. 1. Switch 1006 could be an example of switch 106 from Fig. 1. For example, switch 1006 can be a gate 1010, which is an example of gate 110 of Fig. 1 can act, contain. Fig. 10 is used for illustrative purposes only in the context of Fig. 1-9 described.

[0052] The gate driver 1002 can be configured to activate the switch 1006. For example, the gate driver 1002 can receive a signal (e.g., "LIN") that activates the switching element 1022 and deactivates the switching element 1024. In some cases, the switching element 1022 has a channel resistance of 75 to 2 kiloohms (kΩ). In the example, the diode 1060 bridges the resistive element 1062.

[0053] The gate driver can be configured to disable switch 1006. For example, the active gate bias driver 1004 can receive a signal (e.g., "HIN") that disables switch 1022 and enables switch 1024. In some cases, when switch 1024 is enabled, the active gate bias driver 1004 biases gate 1010 according to the following equation. VK=(RON,N1+R2) / (RON,N1+R2+R1)VCC

[0054] In the equation above, R ON,N1R1 is a single-resistor of the switching element 1024, R2 is a resistor of the resistive element 1064, and R2 is a resistor of the resistive element 1062. In the equation above, R2 can be chosen such that V K is approximately at an optimal gate bias (e.g., 2 volts) when switching element 1024 is activated; R2 is (significantly) larger than R P1 (i.e., a resistance of the switching element 1022), and R2 is approximately equal to R N1 (i.e., a resistance of the switching element 1024).

[0055] Fig. Figure 11 is a block diagram illustrating a fifth example circuit 1100, which has an active gate bias capability for reducing a reverse delay charge on a switch, according to one or more aspects of this disclosure. Fig. Figure 11 shows a gate driver 1102, an active gate bias driver 1104, and a switch 1106. The gate driver 1102 could be an example of the gate driver 1002 from Fig. 10 and / or the gate driver 302 from Fig. 3. For example, switching elements 1122 and 1124 could be examples of switching elements 1022 and 1024, respectively. Fig. 10. The active gate bias driver 1104 could be an example of the gate bias driver 1004 from Fig. 10. Switch 1106 could be an example of switch 1006 from Fig. 10. For example, switch 1106 can be a gate 1110, which is an example of gate 1010 of Fig. 10 can be traded, contained. Fig. 11 is used for illustrative purposes only in the context of Fig. 1-10 described.

[0056] The active gate bias driver 1104 can be used similarly to the active gate bias driver 1004 from Fig. 10. For example, the active gate bias driver 1104 can be a resistive element 1164, which is essentially similar to the resistive element 1064 of Fig. It can be 10. However, the active gate bias driver 1104, instead of as in Fig. Figure 10 shows that a resistive element 1062 is included in the active gate bias driver 1004, a second resistive element is removed, and instead the gate driver 1102 contains a resistive element 1162, which may be essentially similar to the resistive element 1062.

[0057] Fig. Figure 12 is a block diagram illustrating a sixth example circuit 1200, which has an active gate bias capability for reducing a reverse delay charge on a switch, according to one or more aspects of the present disclosure. Fig. Figure 12 shows an active gate driver 1202, an active gate bias driver 1204, and a switch 1206. Gate driver 1202 could be an example of gate driver 102 from Fig. 1 and / or an example of the 302 gate driver from Fig. 3. For example, switching elements 1222 and 1224 could be examples of switching elements 322 and 324, respectively, of Fig. 3. The active gate bias driver 1204 could be an example of the active gate bias driver 104 from Fig. 1. Switch 1206 could be an example of switch 106 from Fig. 1. For example, switch 1206 can be a gate 1210, which is an example of gate 110 of Fig. 1 can act, contain. Fig. 12 is used for illustrative purposes only in the context of Fig. 1-11 described.

[0058] The active gate bias driver 1204 can be used similarly to the active gate bias driver 1004. Fig. 10. For example, the active gate bias driver 1204 can be a resistive element 1264, which is essentially similar to the resistive element 1064 of Fig. It can be 10. However, the active gate bias driver contains 1104, instead of, as in Fig. Figure 10 shows that the active gate bias driver 1004 contains a resistive element 1062, but instead a Zener diode 1263.

[0059] Fig. Figure 13 is a block diagram illustrating a seventh example circuit 1300, which has an active gate bias capability for reducing a reverse delay charge on a switch, according to one or more aspects of the present disclosure. Fig. Figure 13 shows a gate driver 1302, an active gate bias driver 1304, and a switch 1306. Gate driver 1304 could be an example of gate driver 102 from Fig. 1 and / or an example of the gate driver 1302 from Fig. 3. For example, switching elements 1322 and 1324 could be examples of switching elements 322 and 324, respectively, of Fig. 3. The active gate bias driver 1304 could be an example of the active gate bias driver 104 from Fig. 1. Switch 1306 could be an example of switch 106 from Fig. 1. For example, switch 1306 can be a gate 1310, which is an example of gate 110 of Fig. 1 can act, contain. Fig. 13 is used for illustrative purposes only in the context of Fig. 1-12 described.

[0060] The active gate bias driver 1304 can be used similarly to the active gate bias driver 1004 from Fig. 10. For example, the active gate bias driver 1304 can be a resistive element 1364, which is essentially similar to the resistive element 1064 of Fig. It can be 10. However, the active gate bias driver contains 1304 instead of, as in Fig. Figure 10 shows that the active gate bias driver 1004 contains a resistive element 1062, but instead contains a Zener diode 1365.

[0061] Fig. Figure 14 is a diagram illustrating the behavior of an example system having an active gate bias capability for reducing the blocking delay charge of a switch, according to one or more aspects of the present disclosure. In the example of Fig. 14 can be an inverter at a bus voltage V BUS = 300 V, one motor phase current I motor = 500 mA rms work. As shown, systems that use one or more of the techniques described herein to reduce a blocking delay charge on a switch can result in a current 1402 instead of a current 1404. In the example of Fig. 14 A difference in currents 1402 and 1404 leads to a reduction in the charge level of the switch of 39%, thereby reducing the power consumption of the switch and a resulting converter compared to systems that omit one or more of the techniques described herein for reducing a blocking delay charge.

[0062] Fig. 15 is a diagram showing a switching energy loss (E on ) illustrated according to one or more aspects of this revelation. In the example of Fig. 15. A system that uses one or more of the techniques described herein to reduce a blocking delay charge in a high-voltage switch results in a voltage 1504, a current 1514, and a switching energy loss (E). on ) 1524. Additionally, as shown, a system that omits one or more of the techniques described herein for reducing the blocking delay charge on the high-voltage switch results in a voltage 1502, a current 1512 and a switching energy loss (E on) 1522. In this example, the voltages 1502 and 1504 are similar, but the currents 1512 and 1514 are different. More precisely, the current 1514 is significantly lower than the current 1512 during a time interval 1530. Therefore, the system that uses one or more of the techniques described herein to reduce the reverse recovery charge on a high-voltage switch can lead to a switching energy loss (E on ) 1524, which represents a reduction of approximately 19% in switching energy loss (E on ) 1522 for the system which omits one or more of the techniques described herein for reducing the blocking delay charge at the high-voltage switch, shall result.

[0063] Fig. 16 is an example circuit 1600 for a motor application according to one or more aspects of the present disclosure. Fig. Figure 16 showed a gate driver 1602, an active gate bias driver 1604, a switch 1606, and a motor 1650. The gate driver 1602 could be an example of the gate driver 1002 from Fig. 10 and / or the gate driver 302 from Fig. 3. The active gate bias driver 1604 could be an example of the active gate bias driver 1004 from Fig. 10. Switch 1606 could be an example of switch 1006 from Fig. 10. As shown, the switch can contain 1606 M5 1610 and M2 1612. Fig. 16 is used for illustrative purposes only in the context of Fig. 1-10 described.

[0064] In the example of Fig. The 1604 active gate bias driver can apply a gate bias mechanism to only M5 1610 of the six FETs used in the motor application. The 1604 can apply the gate bias after a logic 0 is applied to a channel. In other words, the 1604 can only bias M5 1610, the high-side FET in phase V. The 1604 applies an optimal gate bias when the HIN2 signal is LO, which occurs when M5 1610 undergoes commutation and reduces the accumulation of minority charges. The active gate bias driver 1604 can mainly apply the gate bias to influence the complementary device M2 1612, with the gate bias to obtain a lower loss in M2 1612.

[0065] Fig. Figure 17 is a diagram showing the initial thermal behavior of the example circuit 1600. Fig. 16 illustrated according to one or more aspects of the present revelation. Fig. Figure 17 shows temperatures 1702 and 1704 for a light load condition of 0.2 A rms More precisely, it shows Fig. 17 a temperature 1702 for M2 1612 as a function of time during the low load state and a temperature 1704 for M5 1610 as a function of time during the light load state. In the example of Fig. In section 17, the motor 1650 is initially operated under reference conditions without applying any bias techniques described herein. In this example, when the temperature of M2 1612 reaches a steady state at time 1702, the active gate bias driver 1604 outputs a gate bias to M5 1610. As shown, the temperatures of 1702 and 1704 rise as the switches are in the reference state. At time 1706, M2 1612 reaches a steady state, and the active gate bias driver 1604 outputs the gate bias to the high-side M5 1610. As shown, the temperature of 1702 at the low-side switch (e.g., M2 1612) drops by 1.1 degrees Celsius (°C) after time 1706, which corresponds to a reduction in the switching energy loss (ES). on ) of 9%. It is understood that the active gate bias driver 1604 in the example of Fig. 17 applies the gate bias to only one switch. However, the active gate bias driver 1604 can apply the active bias to all 6 switches, which leads to a temperature drop (e.g., more than 5 degrees Celsius (°C) during the combined heating).

[0066] Fig. Figure 18 is a diagram showing a second thermal behavior of the example circuit 1600. Fig. 16 illustrated according to one or more aspects of the present revelation. Fig. Figure 18 shows temperatures 1812 and 1814 for a full load situation of 0.45 A rms More precisely, it shows Fig. 18 the temperature 1812 for M2 1612 as a function of time during the heavy load condition, and the temperature 1814 for M5 1610 as a function of time during the heavy load condition. In the example of Fig. In section 18, the motor 1650 is initially operated under reference conditions without applying any of the active bias techniques described herein. In this example, when the temperature of M2 1612 reaches a steady state, the active gate bias driver 1604 outputs a gate bias signal to M5 1610. As shown, the temperature 1812 at the low-side switch (e.g., M2 1612) drops by 1.3 degrees Celsius (°C) after time 1816, resulting in a reduction of the switching energy loss (ES). on ) of 7%. It is understood that the active gate bias driver 1604 in the example of Fig. 18 applies the gate bias to only one switch. However, the active gate bias driver 1604 can apply the active bias to all 6 switches, which can lead to a larger temperature drop (e.g., more than 5 degrees Celsius (°C) during simultaneous heating).

[0067] In one or more examples, the described driver functions can be implemented in hardware, software, firmware, or any combination thereof. If implemented as software, the functions can be stored or transmitted as one or more instructions or code on a computer-readable medium, or executed by a hardware-based processing unit. Computer-readable media can include a computer-readable storage medium, which corresponds to a tangible medium such as a data storage medium, or communication media, which includes any medium that facilitates the transmission of a computer program from one location to another, for example, according to a communication protocol.In this way, a computer-readable medium can generally correspond to (1) a tangible, non-volatile, computer-readable storage medium, or (2) a communication medium such as a signal or carrier wave. Data storage media can be any medium accessible by one or more computers or processors to instructions, code, and / or data structures for implementing the techniques described in this disclosure. A computer program product can contain a computer-readable medium.

[0068] The techniques of this disclosure can be implemented in a wide variety of devices or apparatuses containing a wireless handset, an integrated circuit (IC), or a set of ICs (e.g., a chipset). This disclosure describes various components, modules, and units to highlight functional aspects of devices designed to perform the disclosed techniques, but they do not necessarily require implementation by different hardware units. Rather, as described above, different units can be combined within a single hardware unit or provided by a collection of interoperable hardware units, including one or more processors as described above, in conjunction with suitable software and / or firmware.

Claims

[1] Facility that features: a gate driver (302; 602; 802) configured to output a turn-on voltage to activate the switch (306; 606; 806) at the gate of a switch (306; 606; 806) in response to receiving a signal to activate the switch (306; 606; 806); and an active gate bias driver (304; 604; 804) configured to actively drive a voltage at the gate of the switch (306; 606; 806) to a bias voltage in response to receiving a signal to disable the switch (306; 606; 806), where the bias voltage is lower than the turn-on voltage and higher than a ground voltage of the gate driver (302; 602; 802), wherein the active gate bias driver (304; 604; 804) is further configured to receive a reference voltage signal (VREF; VCS) and to actively drive the gate voltage at the gate of the switch (306; 606; 806) to the bias voltage according to the reference voltage signal (VREF; VCS). [2] Device according to claim 1, wherein the reference voltage signal (VREF) is generated by a reference voltage source (326) having a temperature coefficient corresponding to a temperature coefficient of the switch (306; 606; 806). [3] Device according to one of the preceding claims, further comprising a buffer module (840) configured to: to cause the active gate bias driver (304; 604; 804), when actively driving the voltage at the gate of the switch (306; 606; 806) to the bias voltage, to initially output a buffered voltage to the gate of the switch (306; 606; 806); and to modify the buffered voltage according to a voltage detected at the gate, wherein the detected voltage is detected after the initial output of the buffered voltage and before the activation of the switch (306; 606; 806). [4] Device according to one of the preceding claims, wherein the active gate bias driver (304; 604; 804) is further configured to actively drive the gate of the switch (306; 606; 806) to the bias voltage during a dead time of the switch (306; 606; 806), during a body diode conduction of the switch (306; 606; 806) or a combination thereof. [5] Device according to any of the preceding claims, wherein the bias voltage (VREF; VCS) is a first bias voltage, wherein the active gate bias driver (304; 604; 804) is further configured to: to actively drive the voltage at the gate of the switch (306; 606; 806) to the first bias voltage during a first dead time of the switch (306; 606; 806), where the first dead time is present before the switch (306; 606; 806) is deactivated; and to actively drive the voltage at the gate of the switch (306; 606; 806) to a second bias voltage during a second dead time of the switch (306; 606; 806), the second dead time being present before the switch (306; 606; 806) is activated, where the second bias voltage differs from the first bias voltage. [6] Device according to any of the preceding claims, wherein the active gate bias driver (304; 604; 804) is a high-voltage gate driver and wherein the switch (306; 606; 806) is a high-voltage switch. [7] Method which features: Outputting a turn-on voltage to a gate of a switch (306; 606; 806) to activate the switch (306; 606; 806) in response to receiving a signal to activate the switch (306; 606; 806); Receiving a reference voltage signal (VREF; VCS); and Actively driving a voltage at the gate of the switch (306; 606; 806) to a bias voltage corresponding to the reference voltage signal in response to receiving a signal to deactivate the switch (306; 606; 806), where the bias voltage is lower than the turn-on voltage and higher than a ground voltage of the switch (306; 606; 806) [8] Method according to claim 7 wherein the reference voltage signal (VREF; VCS) is generated by a reference voltage source (326) having a temperature coefficient corresponding to a temperature coefficient of the switch (306; 606; 806). [9] Method according to any one of claims 7 to 8, further comprising: Actively driving a voltage at the gate of the switch (306; 606; 806) to the bias voltage by initially outputting a buffered voltage to the gate of the switch (306; 606; 806); Modifying the buffered voltage to match a detected voltage at the gate, where the detected voltage is detected after the initial output of the buffered voltage and before the activation of the switch (306; 606; 806). [10] Method according to any one of claims 7 to 9, further comprising: Active driving of the gate of the switch (306; 606; 806) to the bias voltage during a dead time of the switch (306; 606; 806), during a body diode conduction of the switch (306; 606; 806), or a combination thereof. [11] Method according to any one of claims 7 to 10, wherein the bias voltage is a first bias voltage, the method further comprising: Actively driving the voltage at the gate of the switch (306; 606; 806) to the first bias voltage during a first dead time of the switch (306; 606; 806), wherein the first dead time is present before the switch (306; 606; 806) is deactivated; and Actively driving the voltage at the gate of the switch (306; 606; 806) to a second bias voltage during a second dead time of the switch (306; 606; 806), wherein the second dead time is present before the switch (306; 606; 806) is activated. where the second bias voltage differs from the first bias voltage. [12] System that features: a gate driver (302; 602; 802) with a gate drive controller (320; 620; 820) designed to: in response to receiving a signal to activate a switch (306; 606; 806), to generate a first control signal, wherein the first control signal is configured to activate a first switching element (322; 622; 822), so that the gate driver (302; 602; 802) outputs a turn-on voltage to a gate of the switch (306; 606; 806) to activate the switch (306; 606; 806); and in response to receiving a signal to deactivate the switch (306; 606; 806), a second control signal is generated, wherein the second control signal is configured to deactivate a second switching element (324; 624; 824), so that the gate driver (302; 602; 802) outputs a ground voltage to the gate of the switch (306; 606; 806) to deactivate the switch (306; 606; 806); and an active gate bias driver (304; 604; 804) that features: a timing control module (330; 630; 830) configured to output a signal to provide an active gate bias voltage to disable the switch (306; 606; 806) based on the first and second control signals; and an active gate bias module (331; 631; 831) configured to receive a reference voltage (VREF; VCS) and (306; 606; 806) in response to receiving the signal to provide the active bias voltage to disable the switch (306; 606; 806), to actively drive a voltage at the gate of the switch to the bias voltage according to the reference signal (VREF; VCS), where the bias voltage is lower than the turn-on voltage and higher than the ground voltage to deactivate the switch (306; 606; 806). [13] System according to claim 12, further comprising a buffer module (840) configured to: to cause the active gate bias driver (304; 604; 804), when actively driving the voltage at the gate of the switch (306; 606; 806) to the bias voltage, to initially output a buffered voltage to the gate of the switch (306; 606; 806); and to modify the buffered voltage according to a detected voltage at the gate, wherein the detected voltage is detected after the initial output of the buffered voltage and before the activation of the switch (306; 606; 806).

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