HIGH-VOLTAGE LEVEL SHIFTING CIRCUIT AND DRIVER DEVICE

Abstract

High-voltage level shifting circuit including: • a first high-voltage-resistant NMOS transistor (T1) that is controlled by an on command; • a second high-voltage-resistant NMOS transistor (T2) that is controlled by an off command; • a first PMOS current mirror circuit (CM1) that feeds a drain current from the first high-voltage-resistant NMOS transistor (T1) into a reference side; • a second PMOS current mirror circuit (CM2) that feeds a drain current from the second high-voltage-resistant NMOS transistor (T2) into a reference side; • a first NMOS current mirror circuit (CM3) that feeds an output current of the second PMOS current mirror circuit (CM2) into a reference page; • an I / V signal conversion circuit (1) that accepts an output of the first PMOS current mirror circuit (CM1) and an output of the first NMOS current mirror circuit (CM3) to obtain an output control voltage signal; • a first PMOS transistor (PMOS10) connected in parallel to a source and a drain of a PMOS transistor of a reference side of the first PMOS current mirror circuit (CM1); and • a second PMOS transistor (PMOS11) connected in parallel to a source and a drain of a PMOS transistor of a reference side of the second PMOS current mirror circuit (CM2), • wherein a gate of the first PMOS transistor (PMOS10) is driven by a gate potential of the second PMOS current mirror circuit (CM2), and • a gate of the second PMOS transistor (PMOS11) is controlled by a gate potential of the first PMOS current mirror circuit (CM1).

Description

[0001] The present invention relates to a driving device that drives a power device such as an IGBT or a MOSFET, and a high-voltage level shift circuit used for the driving device. background

[0002] A level shift circuit is known from JP 3 838 083 B2.

[0003] Fig. Figure 9 is a diagram illustrating a conventional driver circuit. The driver circuit comprises a high-voltage level-shifting circuit 100, a transfer circuit 101, and a driver circuit 102. The high-voltage level-shifting circuit 100 includes resistors R1 and R2 and high-voltage field-effect transistors (hereafter referred to as "HNMOS transistors") T1 and T2. The transfer circuit 101 includes an RS-type flip-flop 103, NOR gates 104 and 105, NAND gates 106 and 107, I / V signal conversion circuit gates 108 and 109, and a masking signal circuit 110 consisting of an AND gate. The driver circuit 102 is connected to a power device and drives the power device by its output signal.

[0004] A signal from the high-potential side is fed into the high-voltage level-shifting circuit 100 to control an on / off operation of the power device. The high-potential signal is a pulsed signal that is fed into T1 and T2 of the high-voltage level-shifting circuit 100 and level-shifted to a high potential. The level-shifted on or off signal is transmitted from the driver circuit 102 to the power device via the transmission circuit 101.

[0005] Generally, the load of a power device controlled by a driver circuit is often an inductive load such as a motor. Under the influence of a parasitic inductance component due to an inductive load via circuit board traces or the like, the reference potential VS of the high-potential side fluctuates towards a negative value relative to the ground GND of the low-potential side at the switching time. The high-potential side signal becomes an error signal when the high-potential side reference, which is fluctuating towards the negative value, is reset to a low-potential side reference. Furthermore, this error signal can also be generated by dV / dt when the high-potential side reference potential transitions from a low potential to a high potential.

[0006] The fault signal causes a current to flow into the level-shift resistors R1 and R2, which are connected to a high-potential supply via the parasitic capacitances or parasitic diodes of T1 and T2. This causes a voltage drop and transmits the fault signal to the transmission circuit 101 in the subsequent stage, which can lead to a malfunction of the power device.

[0007] As a countermeasure for this malfunction, a logic filter arrangement is employed in a conventional driver circuit. That is, a mask signal circuit 110 is provided that generates a signal for canceling an error signal. Specifically, the mask signal circuit 110 generates a mask signal for masking these signals when both an on signal and an off signal become active, so that they are not transmitted to the RS-type flip-flop 103. This mask signal is used to mask main signals output from the NAND gates 106 and 107. At this time, if a fluctuation occurs in each of the operating ranges, an error signal may be transmitted to the transmission circuit 101 in the following stage even though the main signal and the mask signal are set to the same operating range.

[0008] Fig. 10 is a timing chart illustrating the operation of a conventional driver circuit. Here, assume a case where an on signal or an off signal, which is an output of the high-voltage level shift circuit 100, abruptly drops under the influence of dV / dt or the like, and a threshold of the NAND gate 106 or 107 is different from a threshold of the mask signal circuit 110 due to a fluctuation or the like. The threshold of the NAND gate 106 or 107 is shown by a dashed line B', and the threshold of the AND gate of the mask signal circuit 110 is shown by a dashed line A'. In this case, a range where the mask signal is active (high) is narrower than a range where the main signal becomes inactive (low) due to a disturbance. For this reason, the error signal, which is the main signal that is erroneously inactivated, is not sufficiently masked.Thus, an error signal is generated in a latch input signal, which is a set input signal of the RS-type flip-flop 103.

[0009] In contrast, a level-shifting circuit is disclosed (see, e.g., JP 2010-161753 A) which provides stable operation. In addition to an HVNMOS that generates a shift current, a current is supplied by another constant current source to ensure steady-state operation and flow into the level-shifting circuit. Summary

[0010] In the case of level shifting in a high-voltage system such as a 600-V or 1200-V system, the current involved in high-voltage level shifting must be suppressed to the utmost to reduce heating value. Therefore, there is a need for a high-voltage level shifting circuit that reduces current without the use of a separate constant current source, which would be indispensable in the prior art.

[0011] The present invention has been implemented to solve the above-described problem, and it is an object of the present invention to provide a high-voltage level shift circuit and a drive circuit capable of reducing a current while preventing transmission of an error signal.

[0012] This problem is solved by the features of the independent claim. The subclaims contain advantageous embodiments of the invention.

[0013] According to aspects of the present invention, a high-voltage level shift circuit includes: a first high-voltage withstand NMOS transistor driven by an on command; a second high-voltage withstand NMOS transistor driven by an off command; a first PMOS current mirror circuit that feeds a drain current of the first high-voltage withstand NMOS transistor to a reference side; a second PMOS current mirror circuit that feeds a drain current of the second high-voltage withstand NMOS transistor to a reference side; a first NMOS current mirror circuit that feeds an output current of the second PMOS current mirror circuit to a reference side; and an I / V signal conversion circuit that receives an output of the first PMOS current mirror circuit and an output of the first NMOS current mirror circuit to obtain an output control voltage signal.

[0014] In the present invention, the first and second PMOS current mirror circuits each feed the drain currents of the first and second high-voltage-resistant NMOS transistors into the reference side, the first NMOS current mirror circuit feeds the output current of the second PMOS current mirror circuit into the reference side, and the I / V signal conversion circuit takes the output of the first PMOS current mirror circuit and the output of the first NMOS current mirror circuit to obtain the output control voltage signal. This allows current to be reduced while preventing the transmission of an error signal.

[0015] Further details, advantages and features of the present invention will become apparent from the following description of embodiments with reference to the drawings. Short description of the drawings Fig. 1 is a diagram illustrating a high-voltage level shift circuit according to a first comparative example of the present invention. Fig. 2 is a diagram illustrating the I / V signal conversion circuit according to the first comparative example. Fig. 3 is a diagram illustrating a modification of the I / V signal conversion circuit according to the first comparative example. Fig. 4 is a diagram illustrating a modification of the high-voltage level shift circuit according to the first comparative example. Fig. 5 is a diagram illustrating a high-voltage level shift circuit according to a second comparative example. Fig. 6 is a diagram illustrating a high-voltage level shift circuit according to a third comparative example. Fig. Figure 7 is a diagram illustrating a high-voltage level-shifting circuit according to a fourth comparative example. Fig. Figure 8 is a diagram illustrating a high-voltage level-shifting circuit according to an embodiment of the present invention. Fig. Figure 9 is a diagram illustrating a conventional driver circuit. Fig. Figure 10 is a timing diagram illustrating the operation of a conventional driver circuit. Description of the comparative examples and the embodiment

[0016] A high-voltage level shift circuit and a driver circuit according to the comparative examples and the embodiment of the present invention will be described with reference to the drawings. The same components are denoted by the same reference numerals, and repeated descriptions thereof may be omitted. First comparison example

[0017] Fig. 1 is a diagram illustrating a high-voltage level shift circuit according to a first comparative example. A high-potential side signal for performing an on / off operation of a power device is input to a high-voltage level shift circuit. This high-potential side signal, which is a DC signal, is input to T1 and T2, each of which is a high-voltage withstand field-effect transistor (HNMOS), and becomes a current signal and is level-shifted to a high potential. That is, T1 is driven by an on command and outputs an on signal to control the power device to turn it on. T2 is controlled by an off command and outputs an off signal to control the power device to turn it off. The on signal and the off signal are generally referred to as "main signals."

[0018] A current mirror circuit CM1 comprises a PMOS1 and a PMOS2, which are PMOS transistors, and feeds a drain current from T1 into a reference circuit. The gate and drain of PMOS1 are connected to each other and are also connected to the gate of PMOS2. PMOS2 causes a drain current to flow according to a predefined ratio of the drain current of PMOS1.

[0019] A current mirror circuit CM2 comprises a PMOS3 and a PMOS4, which are PMOS transistors, and feeds a drain current from T2 into a reference circuit. The gate and drain of PMOS3 are connected to each other and are also connected to the gate of PMOS4. PMOS4 causes a drain current to flow according to a predefined ratio of the drain current of PMOS3.

[0020] A current mirror circuit CM3 comprises an NMOS1 and an NMOS2, which are NMOS transistors, and feeds an output current from the current mirror circuit CM2 into a reference circuit. The gate and drain of NMOS1 are connected to each other and are also connected to the drain of PMOS4.

[0021] A node between the drain of PMOS2 and the drain of NMOS2 is connected to an input of an I / V signal conversion circuit 1. The I / V signal conversion circuit 1 accepts an output of the current mirror circuit CM1 and an output of the current mirror circuit CM3 to obtain an output control voltage signal.

[0022] Next, the operation of the high-voltage level shift circuit according to the present example will be described. The on signal generated when T1 is turned on causes PMOS2 to flow a drain current at a predetermined ratio through the operation of the current mirror circuit CM1. In this case, T2 is in an off state, and no current flows through PMOS3, PMOS4, or NMOS1, and NMOS2 remains in a high-impedance state where no current is allowed to flow. Therefore, no steady-state current flows into the node between the drain of PMOS2 and the drain of NMOS2, and a voltage therebetween becomes substantially equivalent to that of a power supply. The I / V signal conversion circuit 1 outputs this as an output control voltage signal of the on signal.On the other hand, when T2 is in an on state, NMOS2 attempts to let a predefined current flow, but since PMOS2 has a high impedance, no steady current flows into the node between the drain of PMOS2 and the drain of NMOS2, and the I / V signal conversion circuit 1 outputs a control voltage signal of an off signal.

[0023] This describes the behavior when currents flow simultaneously through PMOS1 and PMOS3, even though neither T1 nor T2 receives a main signal due to a high-voltage potential transition or similar event. When currents flow through both PMOS1 and PMOS3, currents are directed through PMOS2 and NMOS2, respectively, to flow through the current mirror circuits CM1, CM2, and CM3.

[0024] In a steady state, T1 or T2 is in an on state, and the other is in an off state. For example, when T1 is in an on state, PMOS2 has a low impedance compared to NMOS2, and an input of the I / V signal conversion circuit 1 is at an H level. In this state, even if currents flow through both PMOS1 and PMOS3 due to a high-voltage potential transition or the like, the current flowing through PMOS1 is greater than the current flowing through PMOS3 by the current of a main signal. That is, the current of PMOS2 is greater than the current of NMOS2, and thus the input of the I / V signal conversion circuit 1 is maintained at an H level, and the output logic is never erroneously inverted.On the other hand, when T2 is in an on state, the current of NMOS2 is larger than the current of PMOS2, unlike the case described above, and thus the input of I / V signal conversion circuit 1 is kept at an L level and the output logic is still not erroneously inverted.

[0025] Similar effects can also be achieved when the main signal is pulse-driven. In the case of pulse-driven operation, both PMOS2 and NMOS2 have high impedances in a steady state, and the input voltage of the I / V signal conversion circuit 1 is determined depending on whether an on signal or an off signal is input to the high-voltage level shift circuit. When currents are caused to flow simultaneously through PMOS1 and PMOS3 in this state, a potential transition occurs at the input voltage of the I / V signal conversion circuit 1 due to a difference in impedance between PMOS2 and NMOS2. Therefore, compared to a circuit diagram that is independent of the difference as in the prior art, an error signal itself is attenuated, and the occurrence of erroneous output inversion is unlikely.In other words, a coupling that is a problem in the prior art and is necessary for generating a masking signal from an on-signal and an off-signal can be relaxed.

[0026] If the potential of the high-voltage supply becomes lower than the reference potential of the low-voltage side due to a switching operation or similar event in the power device, PMOS1, PMOS2, PMOS3, PMOS4, NMOS1, and NMOS2 all exhibit high impedances. Since the input voltage of the I / V signal conversion circuit 1 maintains its immediately previous state, it is still possible to prevent an erroneous output inversion. The present invention makes it possible to easily extend the signal transmission range compared to the prior art when the reference potential of the high-voltage side falls below the reference potential of the low-voltage side.

[0027] Assuming that the high-voltage side power supply is fixed, when the high-voltage side reference potential falls below the low-voltage side reference potential, a potential difference between the two ends of the high-voltage level-shift circuit, that is, a potential difference between the high-voltage side power supply and the low-voltage side reference potential, is reduced, thereby preventing sufficient currents from flowing into T1 and T2. This is because a gate-drain voltage required for a MOS transistor to allow current to flow is generally lower in the present example than a threshold of the I / V signal conversion circuit that accepts a high-voltage level-shifted main signal as a voltage signal, as is the case in the prior art.Therefore, it is possible to remove an error signal generated based on a displacement current when a high-voltage transition or the like occurs and prevent unintentional inversion of the output logic.

[0028] As described above, according to the present invention, current mirror circuits CM1 and CM2 feed the respective drain currents of T1 and T2 to the reference side, current mirror circuit CM3 feeds the output current of current mirror circuit CM2 to the reference side, and I / V signal conversion circuit 1 receives the output of current mirror circuit CM1 and the output of current mirror circuit CM3, thereby obtaining an output control voltage signal. This allows current to be reduced while preventing the transmission of an error signal.

[0029] Fig. Figure 2 is a diagram illustrating the I / V signal conversion circuit according to the first comparison example. The I / V signal conversion circuit 1 is a latch circuit in which two inverters 2 and 3 are connected in reverse parallel. Even if the high-impedance condition described above persists, this latch effect prevents the input to the I / V signal conversion circuit 1 from becoming unstable.

[0030] Fig. Figure 3 is a diagram illustrating a modification of the I / V signal conversion circuit according to the first comparison example. The I / V signal conversion circuit 1 is a Schmitt trigger circuit comprising inverters 2 and 3 and transistors 4 through 9. Since the Schmitt trigger circuit has hysteresis in an input threshold voltage, stability is increased.

[0031] Fig. 4 is a diagram illustrating a modification of the high-voltage level shift circuit according to the first comparative example. The inverter 3 on the feedback side of the I / V signal conversion circuit 1 is constructed of a three-state buffer. The inverter 3 is controlled by an AND circuit 10, which receives the drain voltages of T1 and T2 to cause the I / V signal conversion circuit 1 to perform a latch operation only when no signal is input, thereby causing high impedance. In this way, when the high-voltage level shift circuit is pulse-controlled, it is possible to prevent noise from the output when an on signal and an off signal are transmitted through the latch circuit, and to stabilize the output by latching when no signal is input. It is also possible to reduce power consumption.It is also possible to stabilize the output even when no more current is caused to flow by the DC drive. Second comparative example

[0032] Fig. Figure 5 is a diagram illustrating a high-voltage level-shifting circuit according to a second comparison example. Current mirror circuits CM4 and CM5 are added to the configuration of the first example. Current mirror circuit CM4 comprises an NMOS3 and an NMOS4, which are NMOS transistors, and feeds the output current of current mirror circuit CM1 into the reference circuit. Current mirror circuit CM5 comprises a PMOS5 and a PMOS6, which are PMOS transistors, and feeds the output current of current mirror circuit CM4 into the reference circuit. The I / V signal conversion circuit 1 receives the output of current mirror circuit CM3 and the output of current mirror circuit CM5 and generates an output control voltage signal.

[0033] When an error signal flows into PMOS1, PMOS3, and T1 and T2 (or similar components), a gate and drain potential of PMOS1 and PMOS3 is applied according to the current. At this point, if the current densities of NMOS1 and NMOS2 are reduced by increasing their size and further suppressing the current ratio between PMOS3 and PMOS4, the gate and drain potentials of NMOS1 and NMOS2 can be reduced compared to a case with high current densities. Furthermore, the gate potential and drain voltage of PMOS3 and PMOS4 can be set to allow a larger current while maintaining the current mirror ratio between the drain currents of PMOS3 and PMOS4.

[0034] In the configuration according to the first comparative example, the drain of PMOS2 is directly connected to the drain of NMOS2. Therefore, when a current generated based on the error signal flows from PMOS2 to NMOS2, the drain voltage applied to PMOS2 may increase excessively according to the current value of an error signal, and the input voltage of I / V signal conversion circuit 1 may decrease, causing the output to be erroneously inverted.

[0035] In contrast, according to the present comparison example, the current mirror circuits CM4 and CM5 are added. Thus, PMOS1 and PMOS2 can store input signals from the I / V signal conversion circuit 1 for a higher current than PMOS3 and PMOS4. Therefore, it is possible that a false current signal generated during a high-voltage potential transition or the like will flow more strongly than in the first comparison example, thereby improving the function to prevent malfunctions. Third comparative example

[0036] Fig. Figure 6 is a diagram illustrating a high-voltage level-shifting circuit according to a third comparative example. Unlike the first embodiment, the current mirror circuit CM3 is a Wilson current mirror circuit with an NMOS5, which is an NMOS transistor, added to NMOS1 and NMOS2. In the Wilson current mirror circuit, an output current is fed back into a current on the reference side. Since a gate bias is applied to NMOS1 and NMOS2 on the output side, no current flows on the reference side when no current flows on the output side.

[0037] When a DC signal is level-shifted according to the first and second comparison examples, a steady current flows through parts of the PMOS4 and NMOS1. However, according to the present comparison example, it is possible to eliminate steady currents in these parts by employing the Wilson current mirror circuit. When the high-voltage side is in a low-voltage state, a charge is built up in a capacitor connected in parallel to a high-voltage supply from a low-voltage supply. This charge is often used to supply current to the high-voltage side. The present comparison example allows for a reduction in current consumption within the high-voltage side. Fourth comparison example

[0038] Fig. 7 is a diagram illustrating a high-voltage level shift circuit according to a fourth embodiment. Current mirror circuit CM1 is a Wilson current mirror circuit including PMOS7, a PMOS transistor, added to PMOS1 and PMOS2 in addition to the configuration of the third embodiment. Current mirror circuit CM2 is also a Wilson current mirror circuit including PMOS8, a PMOS transistor, added to PMOS3 and PMOS4. T1 and T2 are supplied with a current from a high-voltage side voltage source, but this steady-state current can also be reduced in the present embodiment.For example, by adding a diode whose anode is connected to the high-voltage side power supply and whose cathode is connected to the drain of T1 and T2, it is possible to reduce the power consumption of the high-voltage side power supply while preventing excessive voltage from being applied to the high-voltage side devices. Embodiment

[0039] Fig.8 is a diagram illustrating a high-voltage level shift circuit according to an embodiment of the present invention. A PMOS10 and a PMOS11, which are PMOS transistors, are added to the configuration of the first comparative example. The PMOS10 is connected in parallel to the source and drain of PMOS1, which is a reference-side PMOS transistor of the current mirror circuit CM1. The PMOS11 is connected in parallel to the source and drain of PMOS3, which is a reference-side PMOS transistor of the current mirror circuit CM2. The gate of the PMOS10 is connected to the drain and gate of PMOS3 and is driven by a gate potential of the current mirror circuit CM2. The gate of the PMOS11 is connected to the drain and gate of PMOS1 and is driven by a gate potential of the current mirror circuit CM1.

[0040] For example, when an on signal is applied to the high-voltage level-shift circuit, the gate and drain of PMOS1 are biased, and PMOS11 is also biased. However, since no off signal is applied to T2, no current flows through PMOS11.

[0041] According to the first comparative example, when an error signal is generated due to a high-voltage potential transition or the like, a current flows through PMOS3 as an error signal, and this error signal current is canceled by PMOS2 and NMOS2 in a part connected to I / V signal conversion circuit 1. On the other hand, according to the present embodiment, a part of the error signal current flows into T2 or the like via the gate-biased PMOS11. For this reason, the error signal current transmitted to NMOS2 via PMOS3 is already reduced in a part of PMOS3. On the other hand, PMOS10 is not gate-biased until an error signal current is caused to flow into PMOS11 or PMOS3 and the entire error signal current is caused to flow into T1 or the like via PMOS1. Since an on-signal is input to T1 and PMOS1, a current continues to flow to amplify the on-signal.This means that since only the error signal current is attenuated by PMOS11, it is possible to enhance the prevention of erroneous output inversion. Note that the prevention of erroneous output inversion is also enhanced when an off signal is applied to the high-voltage level shift circuit.

[0042] In the present invention, the transmission speed of the main signal can be increased even though the logic transmission at the time of normal driving of the power device is similar to that of the first comparative example. That is, when T1 and T2 transition from an on-state to an off-state, it is necessary to charge a parasitic capacitance such as a back-gate capacitance between the drain and source of T1 and T2. However, this charging can be performed by the biased PMOS 10 and PMOS 11, thus improving the response time.

[0043] It should be noted that the PMOS10 and the PMOS11 are connected in parallel to the PMOS1 and the PMOS3 according to the present invention, but even if a similar configuration is used with respect to the other current mirror circuits such as the NMOS1 and the NMOS2, similar effects can be achieved.

[0044] As the power device driven by the driver circuit, a MOSFET made of SiC material has a higher operating speed than an IGBT or MOSFET made of Si material, and a higher dV / dt. Therefore, to prevent malfunction, it is preferable to use the high-voltage level shift circuit according to the comparative examples and the embodiment together with the driver device that drives the power device made of SiC material, such as a SiMOSFET. List of reference symbols 1 Signal conversion circuit 2 inverters 3 inverters 4 transistors 5 transistors 6 transistors 7 transistors 8 transistors 9 transistors 10 AND circuit 100 high-voltage level shift circuit 101 Transfer circuit 102 driver circuit 103 RS-type flip-flop 104 NOR gates 105 NOR gates 106 NAND gates 107 NAND gates 108 I / V signal conversion circuit gates 109 I / V signal conversion circuit gates 110 Masking signal circuit CM1 first PMOS current mirror circuit CM2 second PMOS current mirror circuit CM3 first NMOS current mirror circuit CM4 second NMOS current mirror circuit CM5 third PMOS current mirror circuit NMOS1 NMOS transistor NMOS2 NMOS transistor NMOS3 NMOS transistor NMOS4 NMOS transistor NMOS5 NMOS transistor PMOS1 PMOS transistor PMOS2 PMOS transistor PMOS3 PMOS transistor PMOS4 PMOS transistor PMOS5 PMOS transistor PMOS6 PMOS transistor PMOS7 PMOS transistor PMOS8 PMOS transistor PMOS10 first PMOS transistor PMOS11 second PMOS transistor R1 level shift resistors R2 level shift resistors T1 first high-voltage-resistant NMOS transistor T2 second high-voltage-resistant NMOS transistor

Claims

[1] High voltage level shifting circuit comprising: • a first high-voltage-resistant NMOS transistor (T1) which is controlled by an on command; • a second high-voltage-resistant NMOS transistor (T2) which is controlled by an off command; • a first PMOS current mirror circuit (CM1) which feeds a drain current of the first high-voltage-resistant NMOS transistor (T1) into a reference side; • a second PMOS current mirror circuit (CM2) which feeds a drain current of the second high-voltage-resistant NMOS transistor (T2) into a reference side; • a first NMOS current mirror circuit (CM3) which feeds an output current of the second PMOS current mirror circuit (CM2) into a reference side; • an I / V signal conversion circuit (1) receiving an output of the first PMOS current mirror circuit (CM1) and an output of the first NMOS current mirror circuit (CM3) to obtain an output control voltage signal; • a first PMOS transistor (PMOS10) connected in parallel to a source and a drain of a PMOS transistor of a reference side of the first PMOS current mirror circuit (CM1); and • a second PMOS transistor (PMOS11) connected in parallel to a source and a drain of a PMOS transistor of a reference side of the second PMOS current mirror circuit (CM2), • wherein a gate of the first PMOS transistor (PMOS10) is controlled by a gate potential of the second PMOS current mirror circuit (CM2), and • a gate of the second PMOS transistor (PMOS11) is controlled by a gate potential of the first PMOS current mirror circuit (CM1). [2] A high voltage level shift circuit according to claim 1, further comprising: • a second NMOS current mirror circuit (CM4) which feeds an output current of the first PMOS current mirror circuit (CM1) into a reference side; and • a third PMOS current mirror circuit (CM5) which feeds an output current of the second NMOS current mirror circuit (CM4) into a reference side; • wherein the I / V signal conversion circuit (1) receives an output of the first NMOS current mirror circuit (CM3) and an output of the third PMOS current mirror circuit (CM5) to obtain an output control voltage signal. [3] A high-voltage level shift circuit according to claim 1 or 2, wherein the first NMOS current mirror circuit (CM3) is a Wilson current mirror circuit in which an output current is fed back into a current of a reference side. [4] A high-voltage level shift circuit according to any one of claims 1 to 3, wherein the first and second PMOS current mirror circuits (CM1, CM2) are Wilson current mirror circuits in which an output current is fed back into a current of a reference side. [5] A high-voltage level shift circuit according to any one of claims 1 to 4, wherein the I / V signal conversion circuit (1) is a latch circuit. [6] A high-voltage level shift circuit according to claim 5, wherein the I / V signal conversion circuit (1) performs a latch operation only when no signal is input. [7] A driving device comprising the high-voltage level shift circuit according to any one of claims 1 to 6, wherein the driving device drives a power device made of a SiC material.

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