Component having a write-support circuit featuring memory-matched transistors, and a method for manufacturing them.

Abstract

Write-assist circuitry (212B, 312B, 412B) which includes the following: a first PMOS transistor (P1B) and a first NMOS transistor (N1B) connected in series between a power supply voltage (VDD, 210, 310) and a first node, with gate electrodes of the first PMOS transistor (P1B) and the first NMOS transistor (N1B) connected to a second node; a first switchable conductive path (226A, 326A, 379) between the first node and an earth voltage (VSS); a second PMOS transistor (P2B) and a second NMOS transistor (N2B) connected in series between the supply voltage (VDD, 210, 310) and a third node, with the gate electrodes of the second PMOS transistor (P2B) and the second NMOS transistor (N2B) connected to a fourth node; a second switchable conductive path (226B, 326B, 375) between the third node and the ground voltage (VSS); a third NMOS transistor (N3B) connected in series between the fourth node and a data line (BL); a first shunt (224B', 224B'', 352B) that connects the fourth node and the data line (BL); a fourth NMOS transistor (N4B) connected in series between the second node and a data bar line (BLB), and a second shunt (225B', 225B'', 354B) that connects the second node and the data bar line (BLB).

Description

STATE OF THE ART

[0001] In a typical storage system, memory cells are arranged in an array. Each memory cell (also called a cell) stores a piece of data represented by a bit. Each cell is located at the intersection of a row and a column. A specific cell is therefore accessed by selecting the row and column that intersect at that particular cell. Each cell in a column is connected to a bit line. Each input / output (I / O) circuit uses the bit line to read data from or write data to a selected cell in the column.

[0002] Typically, there are many cells in a column. Due to varying physical distances between the I / O circuitry and the cells, the bit line presents a different resistive and / or capacitive load for each cell in the column. US 2009 / 0285010 A1 describes a memory circuit with a memory matrix comprising a plurality of memory cells arranged in rows and columns. The memory circuit further comprises a plurality of first bit lines, each connected to a column of the memory matrix, and a plurality of write-assist latches, each connected to one of the plurality of first bit lines. Each of the multiple write-assist latches is configured to increase a voltage across a connecting one of the multiple first bit lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] One or more embodiments are shown as examples and are not illustrated by limitations in the figures of the accompanying drawings, where elements sharing the same reference numerals represent identical elements throughout. Unless otherwise disclosed, the drawings are not to scale. Fig. Figure 1 is a block diagram of a semiconductor component in accordance with at least one embodiment of the present disclosure. Fig. 2A is a circuit diagram of an SRAM core in accordance with at least one embodiment of the present disclosure. Fig. 2B is a circuit diagram of a WAS circuit in accordance with at least one embodiment of the present disclosure. Fig. Figure 3 is a circuit diagram of another WAS circuit in accordance with at least one embodiment of the present disclosure. Fig. Figure 3 is a circuit diagram of another WAS circuit in accordance with at least one embodiment of the present disclosure. Fig. 4B is a layout diagram of the WAS circuit of the Fig. 4A in accordance with at least one embodiment of the present disclosure. The Fig. 5A to 5H are waveforms that demonstrate improved writing margin performance using a WAS circuit, wherein the WAS circuit is in accordance with at least one embodiment of the present disclosure. Fig. Figure 6A is a graph of waveforms showing improvements in voltage level changes when accessing an SRAM memory cell, such as an SRAM memory cell 205B, in accordance with at least one embodiment of the present disclosure. The Fig. 6B to 6F are waveforms that demonstrate improved performance using a WAS circuit, corresponding to waveforms found in Fig. 6A are graphically represented, wherein the WAS circuit corresponds to at least one embodiment of the present disclosure. Fig. Figure 7 is a block diagram of another SRAM core in accordance with at least one embodiment of the present disclosure. Fig. 7B is a circuit diagram of another WAS circuit in accordance with at least one embodiment of the present disclosure. Fig. 7C is a block diagram of another SRAM core in accordance with at least one embodiment of the present disclosure. Fig. 7D is a circuit diagram of another WAS circuit in accordance with at least one embodiment of the present disclosure. Fig. 7E is a block diagram of another SRAM core in accordance with at least one embodiment of the present disclosure. Fig. 7F is a circuit diagram of another WAS circuit in accordance with at least one embodiment of the present disclosure. Fig. 7G is a block diagram of another SRAM core in accordance with at least one embodiment of the present disclosure. Fig. 7H is a circuit diagram of another WAS circuit in accordance with at least one embodiment of the present disclosure. Fig. Figure 8A is a flowchart of a method for forming a WAS circuit in accordance with some embodiments. Fig. 8B is a flowchart that represents a block of Fig. 8A shows in more detail in accordance with some embodiments. Fig. 8C is a flowchart that represents a block of Fig. 8A shows in more detail in accordance with some embodiments. Fig. Figure 8D is a flowchart of a method for operating a storage system in accordance with some embodiments. Fig. Figure 9 is a block diagram of an electronic design automation (EDA) system in accordance with at least one embodiment of the present disclosure. Fig. Figure 10 is a block diagram of a system for manufacturing an integrated circuit (IC), and of an IC manufacturing process associated therewith, in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various elements of the provided subject matter. Specific examples of components, materials, values, steps, processes, arrangements, or the like are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. Other components, values, processes, materials, arrangements, or the like are considered.The formation of a first feature over or on a second feature in the following description may, for example, include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or reference letters in the various examples. This repetition is intended for the sake of simplicity and clarity and does not itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatial reference terms such as "below," "under," "lower," "above," "above," and the like may be used here to facilitate description and to describe the relationship of a feature or characteristic to one or more other features or characteristics as illustrated in the FIGS. The spatial reference terms may be intended to include different orientations of the component during use or operation in addition to the orientation shown in the FIGS. The device may be oriented differently (rotated by 90 degrees or to other orientations), and the spatial reference descriptors used here are interpreted accordingly. Phrases such as "essentially rectangular," "essentially parallel," "essentially perpendicular," and "essentially aligned," and the like, should be understood in the context of variations resulting from manufacturing process tolerances.

[0006] According to some embodiments, in a memory system having an array of memory cells (bit cells), a write-assist circuit (WAS) is formed by modifying three bit cells (memory cells). In some embodiments, a WAS circuit is formed from a first, second, and third memory cell. In some embodiments, each of the first, second, and third memory cells has an initial standard configuration of six transistors (6T). The WAS circuit includes a buffer and a circuit for switching the buffer ON / OFF. The buffer of the WAS circuit is configured using four transistors that are present in the initial configuration of a first memory cell.In some embodiments, the circuit is configured using one transistor located in the second memory cell and one transistor located in the third memory cell. An advantage of the WAS circuit is that it mitigates the problem of resistive and / or capacitive loading of a bit line and its corresponding bit-bar line.

[0007] According to another approach, the WAS circuit is formed from transistors manufactured using a logic-matched process. Cells in a memory are formed from transistors manufactured using a memory-matched process. Logic-matched processes differ from memory-matched processes, for example, by using different doping implantation technologies. Details relating to WAS circuits configured with logic-matched transistors are disclosed in U.S. Patent No. US 7,898,875 B2, issued on March 1, 2011. Logic-matched transistors and memory-matched transistors differ in a number of ways. For example, memory-matched transistors are matched for a logic power range and low leakage currents, and consequently have high threshold voltages and low saturation currents.Logic-matched transistors are, for example, adapted for a storage power range and high saturation currents, and consequently have low threshold voltages and high leakage currents. Logic-matched transistors have a larger footprint (require more area) than storage-matched transistors. The size ratio between logic-matched and storage-matched transistors depends on the process / technology level used to manufacture the transistors. In some embodiments, the footprint (FP) ratio of a storage-matched transistor is FP . mem , to a logic-matched transistor, FP logic , FP mem / FP logic ≈ 0.6. Logic-matched transistors consume more power than memory-matched transistors.

[0008] According to some embodiments, in an SRAM memory system, the resistive and / or capacitive load of a bit line and a corresponding bit bar line is improved not only by providing a write-assisted storage (WAS) circuit for an array of SRAM cells, but also by forming the WAS circuit from reconfigured SRAM cells. The approach (mentioned above) uses logic-matched transistors to form the WAS circuit, which requires the use of a logic-matched process to form logic-matched transistors (of which the WAS circuit is made) and a separate memory-matched process to form the SRAM cells (which contain memory-matched transistors). An advantage of at least some embodiments is that the WAS circuit and the array of SRAM cells are formed using one process, namely a memory-matched process, instead of two processes as in the other approach.Another advantage of at least some embodiments is that the footprint of the WAS circuit and the array of SRAM cells is smaller than in the other approach because the WAS circuit is formed from reconfigured SRAM cells (which are formed from memory-matched transistors) instead of from logic-matched transistors as in the other approach.

[0009] Fig. Figure 1 is a block diagram of a semiconductor component 100 in accordance with at least one embodiment of the present disclosure.

[0010] In Fig. 1. The IC structure 100 includes, among other things, a memory macro 101. The memory macro includes a memory core 102 (see element 200 of Fig. 2A, discussed below). In some embodiments, the memory macro is powered partly by a logic power section (not shown) and partly by a memory power section (not shown). The logic power section provides (among other things) voltage levels suitable for logic-matched transistors. The memory power section provides (among other things) voltage levels suitable for memory-matched transistors. In some embodiments, the memory macro is a static random-access memory (SRAM) macro. In some embodiments, the macro 101 is an SRAM memory system such that the memory core 102 is an SRAM core, the SRAM memory system further comprising (among other things) addressing circuitry (not shown), timing circuitry (not shown), or the like.

[0011] In some embodiments, the circuit macro / module 101 is to be understood in the context of an analogy to the architecture hierarchy of modular programming, in which subroutines / procedures are called from a main program (or from other subroutines) to perform a given computational function. In this context, the semiconductor device 100 uses the circuit macro / module 101 to perform one or more given functions. In this context and with respect to the architecture hierarchy, the semiconductor device 100 is therefore analogous to the main program, and the circuit macro / module 101 (referred to below as Macro) 101 is analogous to subroutines / procedures. In some embodiments, Macro 101 is a soft macro. In some embodiments, Macro 101 is a hard macro. In some embodiments, Macro 101 is a soft macro described using register-transfer levels (RTLs).In some embodiments, synthesis, placement, and routing still need to be performed on macro 101, so that the soft macro can be synthesized, placed, and routed for a variety of process nodes. In some embodiments, macro 101 is a hard macro described / expressed in a binary file format (for example, Graphic Database System II (GDSII) stream format), wherein the binary file format represents planar geometric shapes, text labels, other information, and the like of one or more layout diagrams of macro 101 in hierarchical form. In some embodiments, synthesis, placement, and routing on macro 101 have been performed such that the hard macro is specific to a particular process node.

[0012] Fig. Figure 2A is a block diagram of a memory core 200 in accordance with at least one embodiment of the present disclosure. The memory core 200 of Fig. 2A is an example of a memory core 102 of the Fig. 1. In some embodiments, the memory core 200 is an SRAM memory core.

[0013] The SRAM core 200 comprises: an array 201 of SRAM cells, an array 206 of peripheral logic (PL) units; a buffer activation signal line 243A, and a write control unit 244A for generating a buffer activation signal Latch_en<202B> for the buffer activation signal line 243A. In some embodiments, the SRAM array 201 is formed by a memory-adapted process and therefore includes memory-adapted transistors. In some embodiments, the SRAM array 201 is formed by a memory-adapted process specific to SRAM, namely an SRAM-adapted process. In some embodiments, the PL array 206 is formed by a logic-adapted process and therefore includes logic-adapted transistors.

[0014] The SRAM array 201 and the PL array 206 are organized into columns. For the sake of clarity, three columns, namely columns 202A, 202B, and 202C, are shown in Fig. 2A shown. As indicated by ellipses horizontally adjacent to each of columns 202A and 20C, additional columns are contained in the SRAM arrays 201 and 206.

[0015] The SRAM array 201 includes a subarray 203A of SRAM cells and a write-assist (WAS) array 203B of WAS circuits (see discussion of Fig. 2B, below). The subarray 203A contains rows of SRAM cells. For the sake of simplicity, one row, namely row 204, is shown in Fig. 2A is shown. As indicated by the ellipses above and below line 204, subarray 203A contains additional lines.

[0016] Also to simplify the illustration in Fig. 2A and with respect to columns 202A to 202C, corresponding SRAM cells 205A, 205B and 205C are shown in row 204, corresponding WAS circuits 212A, 212B (see discussion of Fig. 2B (below) and 212C are shown in the WAS array 203B, and corresponding PL units 208A, 208B, and 208C are shown in the PL array 206. The WAS circuit 212B features a memory-matched buffer 218B and transistors N2C and N1D (see discussion of Fig. 2 B, below), so that the WAS circuit 212B has six transistors. In some embodiments, the WAS circuit 212B has five transistors. In some embodiments, the WAS circuit 212B has six transistors. In the WAS circuit 212B, transistors N2C and N1D are controlled to function as a switching unit that turns the buffer 218B ON / OFF and, more generally, turns the WAS circuit 212B ON / OFF (see again discussion of Fig. 2B, below). In some embodiments, the WAS circuit 212B includes transistor N2C but not transistor N1D. In some embodiments, the WAS circuit 212B includes transistor N1D but not transistor N2C. Cell 205A, WAS circuit 212A, and PL unit 208A are included in column 202A. Cell 205B, WAS circuit 212B, and PL unit 208B are included in column 202B. Cell 205C, WAS circuit 212C, and PL unit 208C are included in column 202C.

[0017] In some embodiments, the subarray 203A has N rows of SRAM cells, where N is a positive integer. In some embodiments, N = 512. In some embodiments, N is a positive integer other than 512. Each row of the subarray 203A is provided with a corresponding word line. Consequently, row 204 is provided with the word line WL<204A>.

[0018] In some embodiments, the SRAM cells 205A to 205C and other SRAM cells (not shown) contained in the subarray 203A correspond to instances / instantiations of a standard cell structure, wherein the standard cell structure is contained in a library of various standard cell structures. In some embodiments, such a library is contained in an electronic design automation (EDA) system (see discussion of the Fig. 9, below).

[0019] The SRAM cell 205B has a six-transistor (6T) configuration comprising memory-matched PMOS transistors P1A and P2A, and memory-matched NMOS transistors N1A, N2A, N3A, and N4A. Different interconnects for the six transistors of the SRAM cell 205B are considered in some embodiments. Configurations for the SRAM cell 205B based on a number of transistors other than six are also considered in some embodiments.

[0020] Transistors P1A-P2A and N1A-N2A are configured as a memory-adapted buffer 218A. Transistors N3A and N4A are configured as corresponding pass gates. The memory-adapted buffer 218A is connected between a power supply voltage 210 and a ground voltage. In some embodiments, the power supply voltage 210 is VDD for the memory power range. In some embodiments, the ground voltage is VSS for the memory power range. The memory-adapted buffer 218A comprises transistors P1A and N1A connected in series as a first inverter between the power supply voltage 210 and the ground voltage, and transistors P2A and N2A connected in series as a second inverter between the power supply voltage 210 and the ground voltage.Specifically, a source electrode of transistor P1A is connected to the supply voltage 210, a drain electrode of transistor P1A is connected to a segment 232A, segment 232A is connected to a drain electrode of transistor N1A, a source electrode of transistor N1A is connected to a segment 234A' (which is conductive), and segment 234A' is connected to the ground voltage. Segment 232A represents a memory node of the intermediate memory 218A, corresponding to a bit line BL. Similarly, a source electrode of transistor P2A is connected to the supply voltage 210, a drain electrode of transistor P2A is connected to a segment 230A, the segment 230A is connected to a drain electrode of transistor N2A, a source electrode of transistor N2A is connected to a segment 234A'', and the segment 234A'' is connected to the ground voltage.Segment 230A represents a storage node of the intermediate storage 218A, which corresponds to a bit-bar line (BLB).

[0021] In SRAM cell 205B, transistor N4A is connected in series between bitbar line BLB and a first node, where the first node corresponds to segment 230A. Specifically, segment 242A is connected between bitbar line BLB and a first drain / source electrode of transistor N4A, and a second drain / source electrode of transistor N4A is connected to the first node. The first node is connected to the drain electrode of transistor P2A, the drain electrode of transistor N2A, and the gate electrodes of transistors P1A and N1A. Transistor N3A is connected in series between bitbar line BL and a second node, where the second node corresponds to segment 232A. Specifically, segment 240A is connected between bitbar line BL and a first drain / source electrode of transistor N3A, and a second drain / source electrode of transistor N3A is connected to the second node.The second node is connected to the drain electrode of transistor P1A, the drain electrode of transistor N1A, and the gate electrodes of transistors P2A and N2A. The gate electrodes of transistors N3A and N4A are connected to the corresponding word line WL<204A>. Specifically, the gate electrode of transistor N3A is connected to segment 246A, and segment 246A is connected to word line WL<204A>. The gate electrode of transistor N4A is connected to segment 248A, and segment 248A is connected to word line WL<204A>. The segment of bit line BL that overlaps SRAM cell 205B has a segment 250A. The segment of bit bar line BLB that overlaps SRAM cell 205B has a segment 252A.

[0022] For the sake of brevity, a discussion of the operation of the SRAM cell 205B and, more generally, the subarray 203A, is omitted, although it does refer to the support provided by the WAS array. The operation of the WAS array 203B is discussed below (see, for example, the discussion of...). Fig. 2B).

[0023] The PL unit 208B comprises the following: PMOS transistors P11A, P12A, P13A, P14A, and P15A; NMOS transistors N11A and N12A; and inverters INV_A and INV_B. The source electrodes of transistors P11A and P12A are connected to the supply voltage 210. Transistor P13A is connected between the drain electrodes of transistors P11A and P12A such that the drain electrode of transistor P11A is connected to a first source / drain electrode of transistor P13A at a third node, and such that the drain electrode of transistor P12A is connected to a second source / drain electrode of transistor P13A at a fourth node. The third node is connected to the bit line BL. The fourth node is connected to the bit bar line BLB. One gate electrode of each of transistors P11A, P12A, and P13A is connected to a pre-charge signal line. Together, transistors P11A and P12A form a pre-charge circuit.Transistor P13A forms a balancing circuit. Transistors P14A and P15A are connected in series between bit line BL and bit bar line BLB such that the first source / drain electrode of transistor P14A is connected to bit line BL, the first source / drain electrode of transistor P15A is connected to bit bar line BLB, and the second source / drain electrodes of transistors P14A and P15A are connected to each other at a fifth node. This fifth node is connected to the power supply voltage 210. Transistors P14A and P15A form a cross-pair circuit used for a write-operation transistor N11A, which is connected in series between bit line BL and inverter INV_A. Transistor N12A is connected in series between bit bar line BBL and INV_B. Inverters INV_A and INV_B receive corresponding data, which is to be written to SRAM cell 205B.Inverters INV_A and INV_B are drivers for writing data to SRAM cell 205B. A gate electrode of each of transistors N11A and N12A is connected to a line carrying a write column select (WCS) signal wcs<202B> corresponding to column 202B. Column 202B is selected and deselected by using the wcs<202B> signal to turn the corresponding transistors N11A and N12A on and off, with transistors N11A and N12A comprising a column select switch 245. For brevity, a further discussion of the operation of PL unit 208B and, more generally, of PL array 206 is omitted.

[0024] In the context of Fig. Figure 2A shows the SRAM core 200 in a two-dimensional context, where the horizontal direction is a first direction and the vertical direction is a second direction. With respect to the vertical direction, the WAS array 203B and the PL array 206 are located on opposite sides of the subarray 203A. In some embodiments, with respect to the vertical direction, the WAS array 230B is located essentially in the center of the subarray 203A and thus, with respect to the vertical direction, closer to the PL array 206. In some embodiments, with respect to the vertical direction, there are two WAS arrays, with a first of the WAS arrays (corresponding to WAS array 203B) located on the side of the subarray 203A opposite the PL array 206, and with a second of the WAS arrays (corresponding to a copy of WAS array 203B) located in the center of the subarray 203A.In some embodiments, different orientations of the WAS array 203B are considered with respect to the vertical direction. In some embodiments, the first and second directions are different from the corresponding horizontal and vertical directions, if the second direction is already substantially perpendicular to the first direction.

[0025] Fig. 2B is a circuit diagram of a WAS circuit 212B in accordance with at least one embodiment of the present disclosure. The SRAM core 200 of the Fig. 2A is an example of an SRAM 102 core. Fig. 1. Compared to Fig. 2A, shows Fig. 2B the WAS circuit 212B in more detail.

[0026] The WAS circuit 212B has sub-circuits 220B, 220C, and 220D. It should be noted that the reference 220A is not used because the references 220B to 220D correspond more intuitively to the transistor number assignment (as used here) than references 220A to 220C.

[0027] Each of the subcircuits 220B to 220D is based on a corresponding configuration of six transistors (6T). In some embodiments, different interconnects for the six transistors of subcircuits 220B to 220D are considered. In some embodiments, configurations for subcircuits 205B based on a number of transistors other than six are considered.

[0028] In some embodiments, the sub-circuits 220B to 220D are corresponding reconfigured versions of the SRAM cell 205B. Fig. 2A. In some embodiments, subcircuits 220B to 220D correspond to reconfigured instances / instantiations of a standard cell structure, wherein the standard cell structure is contained in a library of various standard cell structures. In some embodiments, such a library is contained in an EDA system (see again the discussion of the Fig. 9, below). In some embodiments, the subcircuits 220B to 220D are correspondingly reconfigured versions of instances of another standard SRAM cell in a library of various standard cell structures.

[0029] Subcircuit 220B is a first reconfigured version of SRAM cell 205B, and therefore subcircuit 220B features the following: memory-matched PMOS transistors P1B and P2B and memory-matched NMOS transistors N1B, N2B, N3B, and N4B. Subcircuit 220C is a second reconfigured version of SRAM cell 205B, and therefore subcircuit 220C features the following: memory-matched NMOS transistors N2C and N4C. Subcircuit 220D is a third reconfigured version of SRAM cell 205B, and therefore subcircuit 220B features the following: memory-matched NMOS transistors N1D and N3D.

[0030] As part of the first reconfigured version of SRAM cell 205B, which represents subcircuit 220B, transistors P1B-P2B and N1B-N2B of subcircuit 220B are configured as a buffer 218A of subcircuit 220B, similar to transistors P1A to P2A and N1A to N2A of SRAM cell 205B, which are configured as a buffer 218A of SRAM cell 205B. Similar to buffer 218A of SRAM cell 205B, buffer 218B of subcircuit 220B is connected to the supply voltage 210. However, unlike buffer 218A of SRAM cell 205B, buffer 218B of subcircuit 220B is selectively connected to ground via a first path and a second path. The first path has a third node, where the third node corresponds to a segment 226A (which was added) and a section provided by sub-circuit 220D (as described in more detail below).The second path has a fourth node, where the fourth node corresponds to a segment 226B (which was added) and a section provided by subcircuit 220C (as described in more detail below). Since subcircuit 220B is also the first reconfigured version of SRAM cell 205B, segments 234B' and 234B'' are not used in subcircuit 220B and are consequently shown as corresponding phantom segments between the sauce electrodes of the corresponding transistors N1B and N2B and the ground voltage. In some embodiments, a phantom element, for example, phantom segment 234B' or 234B'', is a dummy structure that is present but not electrically connected to each of the source electrodes of each of transistors N1B and N2B.Therefore, if an integrated circuit containing such phantom elements were to be "peeled open," for example, by examining it under an electron microscope, such phantom elements would be present as remnants of the SRAM cell 205, resulting from the reconfiguration of the SRAM cell 205 in a subcircuit. In some embodiments, a phantom element, for example, the phantom segment 234B' or 234B'', is a structure that has been removed and is therefore no longer present.

[0031] As part of the first reconfigured version of the SRAM cell 205B, which represents sub-circuit 220B, a first drain / source electrode of transistor N3B is connected to bit line BL, a segment 224B' was added connecting the gate electrode of transistor N3B to bit line BL, and a segment 224B'' was added connecting the second drain / source electrode of transistor N3B to the second node, which corresponds to segment 232B. Together, segments 224B' and 224B'' form a shunt. As a result, transistor N3B has a "bypass" configuration, with transistor N3B connected in parallel with the series-connected segments 224B' and 224B'' between bit line BL and the second node (segment 232B). The second node (segment 232B) of the intermediate storage 218B is therefore directly connected to the bit line BL.Similarly, the first drain / source electrode of transistor N4B is connected to the bit-bar line BLB. A segment 225B' has been added, connecting the gate electrode of transistor N4B to the bit-bar line BLB. A segment 225B'' has also been added, connecting the second drain / source electrode of transistor N4B to the first node, which corresponds to segment 230B. Together, segments 225B' and 225B'' form a shunt. As a result, transistor N4B has a bypass configuration, with the series-connected segments 225B' and 225B'' between the bit-bar line BLB and the first node (segment 230B) connected in parallel. Consequently, the first node (segment 230B) of the buffer 218B is directly connected to the bit line BL.

[0032] As part of the second reconfigured version of the SRAM cell 205B, which represents subcircuit 220C, the second path (through which the buffer 218B of subcircuit 220B is selectively connected to ground) includes transistor N2C of subcircuit 220C. The source electrode of transistor N2B of buffer 218B of subcircuit 220B is connected to a first end of segment 226B. A second end of segment 226B is connected to a drain electrode of transistor N2C of subcircuit 220C. A source electrode of transistor N2C of subcircuit 220C is connected to ground. A segment 261C has been added, which connects a gate electrode of transistor N2C of subcircuit 220C to a buffer activation signal line. In some embodiments, the buffer activation signal line is a buffer activation signal line 243A of the Fig. 2A. The signal Latch_en<202B> on the buffer activation signal line is a control signal that is configured to selectively induce an ON / OFF state in transistor N2C, thereby selectively connecting the source electrode of transistor 218B of sub-circuit 220B to the ground voltage and, more generally, switching the WAS circuit 212B ON / OFF.

[0033] Also as part of the second reconfigured version of the SRAM cell 205B, which represents the sub-circuit 220C, a segment 243C was added that connects the gate electrode of transistor N4C to the ground voltage, resulting in the transistor having an "always-OFF" configuration. iThis configuration is for NMOS transistors. In the always-off configuration, an NMOS transistor is always switched off and therefore, for example, always conducts little or no current and always represents a high-resistance path. Consequently, segments 242C and 248C in subcircuit 220C are not used and are therefore shown as corresponding phantom segments. The write line WL<220B> is not used in subcircuit 220C and is therefore shown as a phantom write line. In some embodiments, transistor N4C of subcircuit 220C is not used and would therefore be shown as a phantom transistor.

[0034] Since subcircuit 220C is the second reconfigured version of SRAM cell 205B, some other components of SRAM cell 250B are not used in subcircuit 220C. Transistors P1C, P2C, N1C, and N3C are not used in subcircuit 220C and are therefore shown as phantom transistors. Segment 240C is not used in subcircuit 220C and is therefore shown as a phantom segment. Segment 246C is not used in subcircuit 220C and is therefore shown as a phantom segment. The write line WL<220C> is not used in subcircuit 220C and is therefore shown as a phantom write line. Segment 243C' is not used in subcircuit 220C and is therefore shown as a phantom segment. Segment 232C is not used in subcircuit 220C and is therefore shown as a phantom segment.

[0035] As part of the third reconfigured version of the SRAM cell 205B, which represents subcircuit 220D, the first path (through which the buffer 218B of subcircuit 220B is selectively connected to ground) includes transistor N1D of subcircuit 220D. The source electrode of transistor N1B of buffer 218B of subcircuit 220B is connected to a first end of segment 226A. A second end of segment 226A is connected to a drain electrode of transistor N1D of subcircuit 220D. A source electrode of transistor N1D of subcircuit 220D is connected to ground.A segment 269D was added, which connects a gate electrode of transistor N1D of subcircuit 220D to the signal Latch_en<202B> on the buffer activation signal line, thereby selectively connecting the source electrode of transistor N1B of buffer 218B of subcircuit 220B to the ground voltage by selectively switching transistor N1D ON / OFF. The signal Latch_en<202B> is derived from voltage levels available in the storage power range.

[0036] As integrated circuits become smaller, the bit line BL and the bit bar line BLB become progressively thinner and narrower, and their corresponding resistances increase. Unless mitigated in some way, the voltage drops between the start and end points of these bit lines will increase until they eventually become large enough to impair write speed, cause write errors, or similar problems.

[0037] During a write operation, the WAS circuit 212B supports the write operation by connecting the intermediate memory 218B of the WAS circuit 212B, which is connected in parallel with the intermediate memory 218A of the SRAM cell 205B during the write operation.

[0038] The WAS circuit 212B assists the buffer 218A of the SRAM memory cell 205B by increasing (or pulling up) voltages on the corresponding bit line BL and bit bar line BLB, thereby creating write speed differences that result from the initial voltage amplitudes at the termination / distal ends of the bit line BL and bit bar line BLB being different from the initial voltage amplitudes at the corresponding initial / proximal ends of the bit line BL and bit bar line BLB. The WAS circuit 212B is supplied by voltage levels derived from voltage levels available in the memory power range. During a write operation, the bit line BL and bit bar line BLB are set (or "developed") to opposite logic values ​​according to the new data being written to the SRAM cell 205B.In some embodiments, after voltages representing the opposite logic values ​​have settled (or been "developed"), when the signal wcs<208B> turns on transistors N11A and N12A (selecting column 202B) during a write cycle for column 202B, the signal Latch_en<202B> turns on transistors N2C and N1D (more generally switching the WAS circuit 212B ON / OFF). In some embodiments, during the write cycle for column 202B, when the pass-gate transistors N3A and N4A are switched ON / OFF, transistors N2C and N1D are switched ON / OFF accordingly.

[0039] In general, the operation of the WAS circuit 212 during a write operation causes the following pairs of current paths to be connected in parallel: a first pair of a first path, represented by the pull-up transistor P1B of the intermediate memory 218B of the WAS circuit 212B, and a second path, represented by the pull-up transistor P1A of the intermediate memory 218A and the path-gate transistor N3A of the SRAM cell 205B of the SRAM memory cell 204B, are connected in parallel between the supply voltage 210 and the bit-bar line BLB; a second pair of a third path, represented by the pull-up transistor P2B of the intermediate memory 218B of the WAS circuit 212B, and a fourth path, represented by the pull-up transistor P2A of the intermediate memory 218A and the pass-gate transistor N4A of the SRAM cell 205B of the SRAM memory cell 204B are connected in parallel between the power supply voltage 210 and the bit bar line BLB;A third pair of a fifth path, represented by the pull-down transistor N1B of the intermediate memory 218B of the WAS circuit 212B, and a sixth path, represented by the pull-down transistor N1A of the intermediate memory 218A and the pass-gate transistor N3A of the SRAM cell 205B of the SRAM memory cell 204B, are connected in parallel between the ground voltage 210 and the bit bar line BLB; and a fourth pair of a seventh path, represented by the pull-down transistor N2B of the intermediate memory 218B of the WAS circuit 212B, and an eighth path, represented by the pull-down transistor N2A of the intermediate memory 218A and the pass-gate transistor N4A of the SRAM cell 205B of the SRAM memory cell 204B, are connected between the ground voltage 210 and the Bit-bar line (BLB) connected in parallel.

[0040] The operation of the WAS circuit 212B is further explained in the context of an exemplary write operation. In the context of an SRAM write operation for a given instance of the SRAM cell 205B, located near the start ends of the corresponding bit line BL and bit bar line BLB, it is assumed, for example, that a logical state "1" stored in the data buffer 218A is to be reset by setting the bit line BL to a logical state "0" and the bit bar line BLB to "1". Since the given instance of the SRAM cell 205B is assumed to be located near the start ends of the corresponding bit line BL and bit bar line BLB, it is further assumed that the voltage on the bit line BL is 0 V and the voltage on the bit bar line is 0.9 V.In response to a binary code from a line decoder (not shown), the word line WL<204A>, coupled to the pass-gate transistors N3A and N4A of SRAM cell 205B, is acknowledged, thus selecting the buffer 218A for a write operation. After SRAM cell 205B is selected, both pass-gate transistors N3A and N4A are turned on. As a result, memory nodes 232A and 230A are connected to the bit line BL and bit bar line BLB, respectively. Furthermore, memory node 232A of buffer 218A is discharged (or pulled down) to ground by transistor N1A, so that "0" follows on the bit line BL, and thus "0" is stored at memory node 232A.A memory node 230A of the intermediate storage 218A is also charged (or pulled up) by transistor P2A to the supply voltage 210 (which in some embodiments is (again) VDD for the storage power area), so that "1" follows on the bit-bar line BLB and therefore "1" is stored at memory node 230A. As a result, the new data logic "0", which corresponds to the voltage on memory node 232A, is "temporarily" stored in SRAM cell 205B. Since the voltage on the bit-bar line BLB is initially 0.9 V, transistor P2A must pull the voltage on the bit-bar line BLB up from 0.9 V to VDD.

[0041] Continuing the example, in the context of the SRAM write operation and further assuming that the WAS circuit 212B is NOT present, consider a given instance of the SRAM cell 205B, located near the terminations of the corresponding bit line BL and bit bar line BLB. It is again assumed that a logical state "1" stored in the data buffer 218A can be reset by setting the bit line BL to a logical state "0" and the bit bar line BLB to "1".Since the given instance of SRAM cell 205B is assumed to be near the termination ends of the corresponding bit line BL and bit bar line BLB, the voltage on bit line BL is further assumed to be 0 V, and the voltage on the bit bar line is assumed to be 0.7 V, or 0.2 V lower than if the given instance of SRAM cell 205B were assumed to be near the starting ends of the corresponding bit line BL and bit bar line BLB. Since the voltage on the bit bar line BLB is initially 0.9 V, transistor P2A must pull the voltage on the bit bar line BLB from 0.7 V to VDD, which takes longer than pulling it up from 0.7 V.

[0042] Continuing with the example, BUT if the WAS circuit 212B is present, the bit bar line BLB is pulled up not only by transistor P2A of the intermediate memory 218A of the SRAM cell 205B, but also by transistor P2B of the intermediate memory 218B of the WAS circuit 212B. If the third current path, represented by transistor P2B of the intermediate storage 218B of the WAS circuit 212B, and the fourth current path, represented by the series connection of transistor P2A of intermediate storage 218A and the pass-gate transistor N4A of the SRAM cell 205B (as the second pair of connections), are connected in parallel between the supply voltage 210 and the bit-bar line BLB, this (in some embodiments) approximately doubles the current capacity available for pulling up the voltage on the bit-bar line BLB.The following is also noted in the example: the fourth pair of the seventh current path (containing transistor N2B) and the eighth (containing transistor N2A) current path is also connected in parallel with the bit-bar line BLB, but both transistors N2B and N2A are switched off; the third pair of the fifth (containing transistor N1B) and the sixth (containing transistor N1A) paths is connected to the bit-bar line BL, and both transistors, N1B and N1A, are switched on to pull the voltage on the bit-bar line BL up to the ground voltage; and the first pair of the first path (containing transistor P1B) and the second path (containing transistor P1A) is connected in parallel with the bit-bar line BL, but both transistors P1B and P1A are switched off.

[0043] Also as part of the third reconfigured version of the SRAM cell 205B, representing subcircuit 220D, a segment 241D was added that connects the gate electrode of transistor N3D to ground, resulting in transistor N3D having the always-off configuration for NMOS transistors. Consequently, segments 240D and 246D are not used in subcircuit 220D and are therefore shown as corresponding phantom segments. In some embodiments, transistor N3D of subcircuit 220D is not used and would therefore be shown as a phantom transistor.

[0044] Since subcircuit 220D is the third reconfigured version of SRAM cell 205B, some other components of SRAM cell 250B are not used in subcircuit 220D. Transistors P1D, P2D, N2D, and N4D are not used in subcircuit 220D and are therefore shown as phantom transistors. The write line WL<220D> is not used in subcircuit 220D and is therefore shown as a phantom write line. Segment 243D'' is not used in subcircuit 220D and is therefore shown as a phantom segment. Segment 230D is not used in subcircuit 220D and is therefore shown as a phantom segment.

[0045] Fig. Figure 3 is a circuit diagram of a WAS circuit 312B in accordance with at least one embodiment of the present disclosure. Compared to Fig. 2B shows Fig. 3. The WAS circuit 312B as an alternative to the WAS circuit 212B.

[0046] The WAS circuit 312B has sub-circuits 320B, 320C, and 320D. It should be noted that the reference 320A is not used because the references 320B to 320D correspond more intuitively to the transistor numbering (as used here) than references 320A to 320C.

[0047] Each of the subcircuits 320B to 320D is based on a corresponding configuration of six transistors (6T). In some embodiments, different interconnects for the six transistors of subcircuits 320B to 320D are considered. In some embodiments, configurations for subcircuits 320B to 320D based on a number of transistors other than six are considered.

[0048] In some embodiments, the sub-circuits 320B to 320D are corresponding reconfigured versions of the SRAM cell 205B. Fig. 2A. In some embodiments, subcircuits 320B to 320D correspond to reconfigured versions of instances / instantiations of a standard cell structure, wherein the standard cell structure is contained in a library of various standard cell structures. In some embodiments, such a library is contained in an EDA system (see again the discussion of the Fig. 9, below). In some embodiments, the subcircuits 320B to 320D are correspondingly reconfigured versions of instances / instantiations of another standard SRAM cell in a library of various standard cell structures.

[0049] Subcircuit 320B is a fourth reconfigured version of SRAM cell 205B, and therefore subcircuit 320B features the following: memory-matched PMOS transistors P1B and P2B and memory-matched NMOS transistors N1B, N2B, N3B, and N4B. Subcircuit 320C is a fifth reconfigured version of SRAM cell 205B, and therefore subcircuit 320C features the following: memory-matched PMOS transistors P1C and P2C and memory-matched NMOS transistors N1C, N2C, N3C, and N4C. The 320D sub-circuit is a sixth reconfigured version of the 205B SRAM cell, and therefore the 320D sub-circuit features the following: memory-matched PMOS transistors P1D and P2D and memory-matched NMOS transistors N1D, N2D, N3C and N4D.

[0050] As part of the fourth reconfigured version of the SRAM cell 205B, which represents subcircuit 320B, transistors P1B-P2B and N1B-N2B of subcircuit 220B are configured as a buffer 218B of subcircuit 220B, so too are transistors P1B-P2B and N1B-N2B of subcircuit 320B configured as a buffer 318B of subcircuit 320B. Similar to buffer 218B of SRAM cell 205B, buffer 318B of subcircuit 320A is connected to a supply voltage 310 and selectively connected to ground via a third path and a fourth path. The third path features a segment 326A (which was added), a segment 379 (which was added), and a section provided by sub-circuit 320D (as discussed in more detail below).The fourth path features a segment 326B (which was added), a segment 375 (which was added), and a section provided by subcircuit 320C (as discussed in more detail below). Since subcircuit 320B is the fourth reconfigured version of SRAM cell 205B, the 334B' and 334B'' are not used in subcircuit 320B and are therefore shown as phantoms.

[0051] Also as part of the fourth reconfigured version of SRAM cell 205B, representing subcircuit 320B, a segment 356B was added, connecting the gate electrode of transistor N3B to ground, resulting in transistor N3B having the always-off configuration for NMOS transistors. A segment 358B was added, connecting the gate electrode of transistor N4B to ground, resulting in transistor N4B having the always-off configuration for NMOS transistors. Consequently, segments 346B and 348B are not used in subcircuit 320B and are therefore shown as corresponding phantom segments. The write line WL<320D> is not used in subcircuit 320B and is therefore shown as a phantom write line. Line segments 350B and 352B are not used in sub-circuit 320B and are therefore shown as corresponding phantom segments.

[0052] Simultaneously, as part of the fourth reconfigured version of the SRAM cell 205B, which represents subcircuit 320B, a first drain / source electrode of transistor N3B is connected to the second node, with the second node corresponding to segment 332B. A first drain / source electrode of transistor N4B is connected to the first node, with the first node corresponding to segment 330B. Notwithstanding the always-off configurations of transistors N3B and N4B in subcircuit 320B, a segment 377 was added, connecting to a second drain / source electrode of transistor N3B, and a segment 385 was added, connecting to a second drain / source electrode of transistor N4B. In some embodiments, each of segments 377 and 385 is not connected to a voltage source, so they are considered "float."In some embodiments, transistors N3B and / or N4B of subcircuit 320B are not used and would therefore be shown as phantom transistors. In some embodiments, segments 377 and / or 385 are not used and would therefore be shown as corresponding phantom segments.

[0053] As part of the fifth reconfigured version of the SRAM cell 205B, which represents subcircuit 320C, a segment 360C was added that connects the gate electrode of transistor N4C to the gate electrode of transistor P2C. A segment 361C was added that connects segment 360C and the gate electrode of transistor N4C of subcircuit 320C to a buffer activation signal line. In some embodiments, the buffer activation signal line is a buffer activation signal line 243A of the Fig. 2A. The signal on the buffer activation signal line is a control signal configured to selectively induce an ON / OFF state in transistor N2C and, conversely, a corresponding OFF / ON state in transistor P2C, thereby selectively connecting the source electrode of transistor N2B of buffer 218B of subcircuit 320B to ground. A segment 326C has been added that connects the gate electrode of transistor P1C to ground 310, resulting in transistor P1C having an always-OFF configuration for PMOS transistors. In the always-OFF configuration, a PMOS transistor is always switched off and therefore, for example, always conducts little or no current and always presents a high-resistance path.A segment 363C was added, connecting the gate electrode of transistor N2C to the gate electrodes of each of transistors P1C and N1C, and thus to the supply voltage 310. Transistors N1C and N2C therefore have an "always-on" configuration for NMOS transistors, with the gate electrode of each of them connected to the supply voltage 310. In the always-on configuration, an NMOS transistor is always switched on and therefore, for example, always conducts a high, if not maximum, current and always presents a low-resistance path. Similarly, in an always-on configuration, a PMOS transistor is always switched on and therefore, for example, always conducts a high, if not maximum, current and always presents a low-resistance path.A segment 364C was added, connecting the gate electrode of transistor N3C to the supply voltage 310, resulting in transistor N3C having the always-off configuration for NMOS transistors. A segment 330C, which would otherwise connect the drain electrode of transistor P2C to the drain electrode of transistor N2C, is not used and is therefore shown as a phantom segment. A segment 332C, which would otherwise connect the drain electrode of transistor P1C to the drain electrode of transistor N1C, is not used and is therefore shown as a phantom segment. A segment 366C, which would otherwise connect the gate electrode of transistor P2C to the gate electrode of transistor N2C, is not used and is therefore shown as a phantom segment.

[0054] As part of the fifth reconfigured version of the SRAM cell 205B, which represents subcircuit 320C, the fourth path (through which the buffer 318B of subcircuit 320B is selectively connected to ground) features transistors N2C and N4C of subcircuit 320C connected in series. Transistor N4C of subcircuit 320C is connected between segment 375 and the drain electrode of transistor N2C of subcircuit 320C. The drain electrode of transistor N2C of subcircuit 320C is connected to the source electrode of transistor N4C of subcircuit 320C, and the source electrode of transistor N2C of subcircuit 320C is connected to ground.

[0055] As part of the sixth reconfigured version of the SRAM cell 205B, which represents subcircuit 320D, a segment 368D was added that connects the gate electrode of transistor N3D to the gate electrode of transistor P1D. A segment 369D was added that connects segment 368D and the gate electrode of transistor N3B of subcircuit 320D to the buffer activation signal line. In some embodiments, the buffer activation signal line is a buffer activation signal line 243A of the Fig. 2A. The signal on the buffer activation signal line is again a control signal configured to selectively induce an ON / OFF state in transistor N3D and, conversely, a corresponding OFF / ON state in transistor P1D. A segment 362D was added that connects the gate electrode of transistor P2D to the ground voltage 310, resulting in transistor P2D having the always-OFF configuration for PMOS transistors. A segment 363D was added that connects the gate electrode of transistor N1D to the gate electrodes of each of transistors P2D and N2D, and thus to the supply voltage 310. Consequently, transistors N1D and N2D have an "always-ON" configuration for NMOS transistors, with the gate electrode of each of transistors N1D and N2D connected to the supply voltage 310.A segment 346D was added, connecting the gate electrode of transistor N4D to ground voltage 310, resulting in transistor N4D having the always-off configuration for NMOS transistors. A segment 332D, which would otherwise connect the drain electrode of transistor P1D to the drain electrode of transistor N1D, is not used and is therefore shown as a phantom segment. A segment 366D, which would otherwise connect the gate electrode of transistor P1D to the gate electrode of transistor N1D, is not used and is therefore shown as a phantom segment.

[0056] As part of the fifth reconfigured version of the SRAM cell 205B, which represents subcircuit 320D, the third path (through which the buffer 318B of subcircuit 320B is selectively connected to ground) features transistors N3D and N1DC of subcircuit 320C connected in series. Transistor N3D of subcircuit 320D is connected between segment 379 and the drain electrode of transistor N1D of subcircuit 320D. The drain electrode of transistor N1D of subcircuit 320D is connected to the source electrode of transistor N3D of subcircuit 320D, and the source electrode of transistor N1D of subcircuit 320D is connected to ground.

[0057] Fig. Figure 4A is a circuit diagram of a WAS circuit 412B in accordance with at least one embodiment of the present disclosure. The WAS circuit 412B is a simplified version of the WAS circuit 312B of the Fig. 3.

[0058] In particular, the WAS circuit 412B is simplified in that it shows elements of the WAS circuit 312B that are used and omits elements that are not used. In some cases, a "mapping" of correspondences between a layout 449 of the Fig. 4B (discussed below) and the Fig. 3. Easier to distinguish by Fig. 4B (also discussed below) Fig. 4A due to the simplification that the Fig. 4A represents, is assigned. Aspects of the WAS circuit 412B are assigned with corresponding designations A to F, EN (which, for example, corresponds to the Latch_en<202B> of the Fig. 2A-2B corresponds to VDD, VSS and VSS=PIN shown. The designations A to F, EN, VDD, VSS and VSS=PIN are also shown on corresponding aspects of layout 449 of the Fig. 4B (also discussed below) shown.

[0059] Fig. 4B is a layout diagram 449 of the WAS circuit 412B in accordance with at least one embodiment of the present disclosure.

[0060] In some embodiments, a method for generating the layout diagram 449 is executed by a computer processor. An example of such a processor is a processor 902. Fig. 9 (discussed below). One example of the computer is an Electronic Design Automation (EDA) system 900 of the Fig. 9 (discussed below). In some embodiments, such a method is performed by the computer's processor. In some embodiments, the layout produced by such a method is stored on a non-volatile, computer-readable medium. An example of such a layout, as stored on a non-volatile, computer-readable medium, is Layout 907 of the Fig. 9 (discussed below).

[0061] As discussed in more detail below, a layout diagram 449 includes: a substrate 450; an active area (alternatively known as an oxide-dimensioned area or oxide-definition area) structuring 452A to 452I; MD structuring 454A to 454V; CMD structuring 456A to 456Z and 458A to 458C; PO structuring 460A to 460M; CPO structuring 462A to 462L; VDR structuring 464A to 464F; VG structuring 466A to 466L; and VD structuring 468A to 468J.

[0062] Active surface structures 452A to 452I represent active surfaces of a semiconductor device. In some embodiments, active surface structures 452A to 452I represent fins of a corresponding FinFET. MD structures 454A to 454V represent sections of a metallization layer. In some embodiments, MD 454A to 454V represent sections of a first metallization layer arranged above active surface structures 452A to 452I, where the first metallization layer is M0 or M1 depending on the metallization numbering scheme used. In some embodiments, MD structures 454A to 454V are called drain / source terminals / leads.CMD patterns 456A to 456Z and 458A to 458C represent cutting patterns arranged over sections of the corresponding MD patterns 454A to 454V, indicating that corresponding sections of the MD patterns 454A to 454V, located beneath the CMD patterns 456A to 456Z and 458A to 458C, are intended to be cut / removed. PO patterns 460A to 460M represent sections of a conductive layer arranged over corresponding active areas 452A to 452H and over corresponding CMD patterns 456A to 456Z and 458A to 458C. In some embodiments, the PO patterns 460A to 460M are designated as gate electrodes / conductors.The CPO structures 462A to 462L represent cut structures arranged over sections of corresponding PO structures 460A to 460M and indicate that any corresponding sections of PO structures 460A to 460M lying beneath CPO structures 462A to 462L are intended to be cut / removed. The VDR structures 464A to 464F represent sections of a conductive layer that connect sections of corresponding MD structures 456J, 454P, 454U, 454E, 454K, and 454V and sections of corresponding PO structures 460E, 4601, 460K, 460A, 460F, and 460L. In some embodiments, the VDR structures 464A to 464F represent vias.The VG structures 466A to 466L represent sections of a conductive layer that connect sections of corresponding VDR structures 464A to 464F and corresponding sections of PO structures 460B, 460D, 460H, 460C, 460G, 460H, 466K, and 466L. In some embodiments, the VDR structures 466A to 466F represent vias. The VD structures 468A to 468J represent sections of a conductive layer that connect sections of corresponding MD structures 454A, 454R, 454J, 454H, 454M, 454P, 454S, 454C, and 454T to corresponding sections of an overlying metallization layer (not shown). In some embodiments, the VDR structures 468A to 468J represent vias.

[0063] In Fig. 4B, active surface structurings 452A to 452I are formed as substantially rectangular shapes arranged on and / or above the substrate 450, wherein the long axes of active surfaces 450A to 450I are substantially parallel to a first direction. In some embodiments, the active surfaces 450A to 450I have shapes other than substantially rectangular. The active surface structurings 450A to 450I are arranged with respect to a first imaginary grid having parallel first reference rows / tracks that are imaginary and parallel to the first direction. Fig. 4B, the first direction is the horizontal direction. In some embodiments, the first direction is a direction other than the horizontal direction. The active surface structurings 450A to 450I are separated by gaps with respect to a second direction, the second direction being essentially perpendicular to the first direction. Fig. 4B is the second direction, the vertical direction. In some embodiments, the second direction is different from the vertical direction. With respect to the first direction, the active surface structures 452A to 452I do not overlap. With respect to the second direction, the active surface structures 452C, 452D, and 452E are aligned but not overlapping. With respect to the second direction, the active surface structures 452F and 452G are aligned but not overlapping.

[0064] In some embodiments, the active areas 452A to 452I are intended to be configured for planar FET technology. In other embodiments, the active areas 452A to 452I are intended to be configured for FinFET technology. Where the active areas 452A-452I are configured for FinFET technology and included in a layout diagram, a semiconductor device resulting from the layout diagram is a semiconductor device having instances of fins (not shown) that are arranged substantially at least parallel, if not collinear, with respect to corresponding first reference rows / tracks and are therefore substantially parallel to the horizontal direction. The fins may be structured by any suitable method.The fins can be structured, for example, using one or more photolithographic processes, including dual-structuring or multiple-structuring processes. Generally, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, allowing the creation of structures with, for example, smaller spacing than that achievable using a single direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers can be used to structure the fins.Additional details relating to the structure and manufacture of CMOS FinFET technology are disclosed in the transferred US patent No. 8 786 019, issued on June 22, 2014, which is hereby incorporated in its entirety by reference.

[0065] In Fig. 4B, MD structures 454A to 454V are formed as substantially rectangular shapes over corresponding active areas 452A to 452H, where the long axes of the MD structures 454A to 454V are substantially parallel to the second direction. With respect to the second direction, the MD structures 454A to 454V do not overlap. The MD structures 454A to 454V again represent sections of a metallization layer. In some embodiments, the MD structures 454A to 454V are again referred to as drain / source terminals / conductors. In some embodiments, the MD structures 454A to 454V have shapes other than substantially rectangular. The MD structurings 454A to 454V are set up with respect to a second imaginary grid, which has parallel second reference rows / tracks that are imaginary and parallel to the second direction.

[0066] Also in Fig. In 4B, CMD structures 456A to 456Z and 458A to 458C are formed as substantially rectangular shapes arranged over corresponding MD structures 454A to 454V. The CMD structures are again cut structures indicating that any corresponding sections of the MD structures 454A to 454V lying beneath the CMD structures 456A to 456Z and 458A to 458C are intended to be cut / removed. The CMD structures 456A to 456Z and 458A to 458C are arranged with respect to the first grid. In some embodiments, the CMD structures 456A to 456Z and 458A to 458C have shapes other than substantially rectangular.

[0067] With respect to the first direction: CMD structures 456A to 456Z and 458A to 458C are separated by gaps, and CMD structures 456A to 456Z and 458A to 458C are non-overlapping. With respect to the second direction, CMD structures 456A to 456E are aligned. With respect to the second direction, CMD structures 456A to 456E are abutting. In some embodiments, one or more of the CMD structures 456A to 456E are separated by gaps with respect to the second direction. With respect to the second direction, CMD structures 456E and 456F are aligned and separated by a gap. With respect to the second direction, CMD structures 456G to 456M are aligned. Regarding the second direction, the CMD structures 456G-456I are striking, and the CMD structures 456J to 456L are striking.In some embodiments, one or more of the CMD structures 456G to 456L are separated by gaps with respect to the second direction. With respect to the second direction: CMD structures 456I and 456J are aligned and separated by a gap, CMD structures 456L and 456M are aligned and separated by a gap, and CMD structures 456N and 456O are aligned and separated by a gap. With respect to the second direction, CMD structures 456P-456V are aligned. With respect to the second direction: CMD structures 456P-456R are abutting, and CMD structures 456S-456U are abutting. In some embodiments, one or more of the CMD structures 456P-456U are separated by gaps with respect to the second direction.With respect to the second direction: CMD structures 456R and 456S are aligned and separated by a gap, and CMD structures 456U and 456V are aligned and separated by a gap. With respect to the second direction, CMD structures 455W to 458C are aligned. With respect to the second direction: CMD structures 456W to 456Z and 458A are abutting, and CMD structures 458B to 458C are abutting. In some embodiments, one or more of the CMD structures 456W to 456U are separated by gaps with respect to the second direction. With respect to the second direction: CMD structures 4558A and 458B are aligned and separated by a gap.

[0068] In Fig. In 4B, PO structures 460A to 460M are formed as substantially rectangular shapes arranged over corresponding active surfaces 452A to 452H and over corresponding CMD structures 456A to 456Z and 458A to 458C, where the long axes of the PO structures 460A to 460M are substantially parallel to the second direction. With respect to the second direction, the PO structures 460A to 460M do not overlap. The PO structures 460A to 460M represent sections of a conductive layer. In some embodiments, the PO structures 460A to 460M are again referred to as gate electrodes / conductors. In some embodiments, the conductive layer is formed of polysilicon or the like. In some embodiments, the PO structures 460A to 460M have shapes other than substantially rectangular. The PO structures 460A to 460M are arranged in relation to the second grid.

[0069] Also in Fig. 4B, CPO structures 462A to 462L are formed as substantially rectangular shapes arranged over sections of the corresponding PO structures 460A to 460M. The CPO structures 462A to 462L are again cut structures indicating that any corresponding sections of the PO structures 460A to 460M lying beneath the CPO structures 462A to 462L are intended to be cut / removed. The CPO structures 462A to 462L are arranged with respect to the first grid. In some embodiments, the CPO structures 462A to 462L have shapes other than substantially rectangular.

[0070] With respect to the first direction: CPO structures 462A to 462L are separated by gaps, and CPO structures 462A to 462L are non-overlapping. With respect to the second direction: CPO structures 462A to 462D are aligned. With respect to the second direction, CPO structures 462A to 462B are abutting. In some embodiments, CPO structures 462A to 462B are separated by a gap with respect to the second direction. With respect to the second direction, CPO structures 462B and 462C are aligned and separated by a gap, and CPO structures 462C and 462D are aligned and separated by a gap. With respect to the second direction, CPO structures 462E to 462F are aligned and abutting. In some embodiments, the CPO structures 462E-462F are separated by a gap in the second direction.With respect to the second direction, CPO structures 462G and 462H are aligned and separated by a gap, and CPO structures 462H-462J are aligned. With respect to the second direction, CPO structures 462H to 462I are abutting. In some embodiments, CPO structures 462H-462I are separated by a gap with respect to the second direction. With respect to the second direction, CMD structures 456I and 456J are aligned and separated by a gap.

[0071] Fig. 4B represents sections of a conductive layer that connect sections of the corresponding MD structures 456J, 454P, 454U, 454E, 454K, and 454V and the PO structures 460E, 4601, 460K, 460A, 460F, and 460L. For example, the VDR structure 364A is formed over the MD structure 456J and the PO structure 460E, the VDR structure 364B is formed over the MD structure 454P and the PO structure 460I, and so on. The VDR structures 464A to 464F again represent sections of a conductive layer that connect sections of corresponding MD structures 456J, 454P, 454U, 454E, 454K and 454V and sections of corresponding PO structures 460E, 460I, 460K, 460A, 460F and 460L. In some embodiments, the VDR structures 464A to 464F again represent vias. In some embodiments, the VDR structures 464A to 464F are formed as substantially rectangular shapes.In some embodiments, the VDR structures 464A to 464F have shapes other than essentially rectangular.

[0072] In Fig. 4B represents the VG structures 466A to 466L as sections of a conductive layer, connecting sections of corresponding VDR structures 464A to 464F and corresponding sections of PO structures 460B, 460D, 460H, 460C, 460G, 460H, 466K, and 466L. For example, VG structure 466A is formed over PO structure 460B, VG structure 466B is formed over PO structure 460D, VG structure 466D is formed over VDR structure 464A, PO structure 466E is formed over VDR structure 464B, and so on. In some embodiments, the VDR structures 466A to 466L represent vias. The VG structures 466A to 466L are formed as substantially square shapes. In some embodiments, the VG structures 466A to 466L have shapes other than substantially square.

[0073] At the same time, they also pose a challenge in Fig. 4B The VD structures 468A to 468J again represent sections of a conductive layer that connect the sections of corresponding MD structures 454A, 454R, 454J, 454H, 454M, 454P, 454S, 454C, and 454T with corresponding sections of an overlying metallization layer (not shown). For example, VD structure 468A is formed over MD structure 545A, VD structure 468B is formed over MD structure 454R, and so on. In some embodiments, the VDR structures 468A to 468J again represent vias. In some embodiments, VD structures 468A to 468J are formed as substantially square shapes. In some embodiments, the VD structures 468A to 468J have shapes other than essentially square.

[0074] The Fig. 5A to 5H are waveforms 504A to 506A which exhibit improved write margin performance using a WAS circuit, wherein the WAS circuit is in accordance with at least one embodiment of the present disclosure.

[0075] In the Fig. 5A, Fig. 5C, Fig. 5E and Fig. In 5G, corresponding waveforms 504A, 504C, 504E and 504G represent a voltage BL at a node, for example node 232A. Fig. 2A, in a situation where a WAS circuit is NOT present. In the Fig. 5A, Fig. 5C, Fig. 5E and Fig. In 5G, corresponding waveforms 508A, 504C, 504E and 504G represent a voltage BLBin at a node, for example node 230A. Fig. 2A, in a situation where a WAS circuit is NOT present. In the Fig. 5A, Fig. 5C, Fig. 5E and Fig. In 5G, corresponding waveforms 506A, 5066, 506E and 506G represent a voltage BL at a node, for example node 232A. Fig. 2A, in a circumstance where a WAS circuit (in accordance with at least one embodiment of the present disclosure) is present. In the Fig. 5A, Fig. 5C, Fig. 5E and Fig. 5G, corresponding waveforms 510A, 510C, 510E and 510G represent a voltage BLBin on a node, for example node 230A, under a condition in which a WAS circuit (in accordance with at least one embodiment of the present disclosure) is present.

[0076] In the Fig. 5B, Fig. 5C, Fig. 5F and Fig. 5H, corresponding waveforms 504B, 504D, 504F and 504H represent a voltage on a bit line, for example the bit line BL in Fig. 2A, in a situation where a WAS circuit is NOT present. In the Fig. 5B, Fig. 5D, Fig. 5F and Fig. 5H, corresponding waveforms 508B, 508D, 508F and 508H represent a voltage on a bit-bar line, for example the bit-bar line BLB in Fig. 2A, in a situation where a WAS circuit is NOT present. In the Fig. 5B, Fig. 5D, Fig. 5F and Fig. 5H, corresponding waveforms 506B, 506D, 506F and 506H represent a voltage on a bit line, for example the bit line BL in Fig. 2A, in a circumstance where a WAS circuit (in accordance with at least one embodiment of the present disclosure) is present. In the Fig. 5B, Fig. 5D, Fig. 5F and Fig. 5H, corresponding waveforms 510B, 510D, 510F and 510H represent a voltage on a bit-bar line, for example the bit-bar line BLB in Fig. 2A, in a circumstance in which a WAS circuit (in accordance with at least one embodiment of the present disclosure) is present.

[0077] In Fig. 5A represents a gap 512A between waveforms 504A and 508A, indicating a write operation failure. Fig. 5B represents an interface between waveforms 506A and 510A, indicating a successful write operation. Fig. 5C represents a leftward shift (reference 514C) of waveform 510C relative to waveform 508C, thus reducing the writing time. Fig. Error 5E represents a write operation failure at interface 512E between waveforms 504E and 508E. Fig. 5E represents an interface between waveforms 506E and 510E, indicating a successful write operation. Fig. 5A and Fig. 5E demonstrates that the WAS circuit, for example the WAS circuit 212B, improves write capability even under conditions where insufficient write time (write duration) is provided. Fig. 5G represents a leftward shift (reference 514G) of waveform 506G relative to waveform 504G, thus reducing write time. It is recalled that if the WAS circuit, for example, WAS circuit 212B, is composed of memory-matched transistors instead of logic-matched transistors as in the other approach mentioned, then at least one of the following statements (A) or (B) is true: (A) the footprint of WAS circuit 212B and its corresponding array of memory cells is smaller than the footprint of the corresponding WAS circuit according to the other approach and its array of memory cells; or (B) with respect to the array of memory cells, WAS circuit 212B is physically closer than the WAS circuit according to the other approach.Given that at least one of (A) or (B) is true, it is therefore a favorable result that a shorter line connects the WAS circuit 212B to the corresponding bit line than would connect the WAS circuit of the other approach to the corresponding bit line. All other factors being equal, a shorter line connecting the WAS circuit 212B to the corresponding bit line presents less resistance through which the WAS circuit 212B must drive current, resulting in a reduction in write time, as seen in the leftward shift (reference 514C) of waveform 510C compared to waveform 508C in [reference 1]. Fig. 5C is specified, and as from the leftward shift (reference numeral 514G) of waveform 506G compared to waveform 504G in Fig. 5G is specified.

[0078] Fig. Figure 6A is a graph of waveforms 602A to 602D showing improvements in voltage level changes when accessing an SRAM memory cell, such as an SRAM memory cell 205B, in accordance with at least one embodiment of the present disclosure.

[0079] In Fig. In section 6A, waveforms 602A through 602D collectively describe SRAM memory cell 205B in the context of a write operation. Specifically, waveform 602A represents the voltage BLin. Waveform 602B represents the voltage BLBin. Waveform 602C represents a voltage on a bit-bar line BLB. Waveform 602D represents a voltage on a bit line BL. Waveform 602E represents a buffer activation signal. Element 604 specifies a restore time. Element 606 specifies a flip time. In general, flip time refers to the amount of time that elapses while one or more waveforms change / reverse their state(s). Fig. 6A refers to flip time 606, in particular, to a change in the charge state of waveform 602A and a corresponding change in the state of waveform 602B. Assuming a circumstance where waveform 602A represents a logic high state of voltage BLin, and waveform 602B represents a logic low state of voltage BLBin, flip time 606 refers to a quantity of time elapsed while waveform 602A (voltage BLin) changes from the logic high state to the logic low state, and waveform 602B (voltage BLBin) changes from the logic low state to the logic high state. In some embodiments, flip time refers to a change in a state other than the change in the state represented by element 606. Fig. 6A is specified.

[0080] The Fig. 6B to 6F are waveforms that demonstrate improved performance using a WAS circuit, corresponding to waveforms found in Fig. 6A are graphically represented, wherein the WAS circuit corresponds to at least one embodiment of the present disclosure.

[0081] In Fig. Waveforms 604B to 610B show an improvement in terms of reduced flip times (see element 606 of the Fig. 6A). Waveforms 604B to 610B are normalized such that waveforms 604B and 606B represent the power of a WAS circuit with one unit (1) of driving capability, and waveforms 608B and 610B represent the power of a WAS circuit with two units (2X) of driving capability. The WAS circuits of waveforms 604B and 608B are of a Slow-Fast-Global (SFG) type of the corresponding WAS circuits. The WAS circuits of waveforms 606B and 610B are of a Slow-Slow-Global (SGG) type of the corresponding WAS circuits.

[0082] In the Fig. Waveforms 6C-6D show corresponding waveforms 612C-616C and 612D-616D, representing an improvement with respect to reduced minimum write voltage (AC Write Vmin). Waveforms 612C and 612D represent performance under conditions where a WAS circuit is NOT present. Waveforms 614B-616C and 614D-616D are normalized such that waveforms 614C and 614D represent the performance of a WAS circuit with one unit (1X) of drive capability, and waveforms 616B and 616D represent the performance of a WAS circuit with two units (2X) of drive capability.

[0083] In the Fig. 6E-6F show corresponding waveforms 612G-616G and 612H-616H, showing an improvement in terms of reduced recovery time (see element 604 of the Fig. 6A). Waveforms 612E and 612F represent power output under conditions where a WAS circuit is NOT present. Waveforms 614E-614F and 614E-616F are normalized such that waveforms 614E and 614F represent the power output of a WAS circuit with one unit (1X) of driving capability, and waveforms 616E and 616F represent the power output of a WAS circuit with two units (2X) of driving capability.

[0084] Fig. Figure 7A is a block diagram of an SRAM core 700A in accordance with at least one embodiment of the present disclosure. Compared to Fig. 2A shows Fig. 7A presents the SRAM 700A core as an alternative to the SRAM 200 core. For the sake of brevity, similarities between the SRAM 700A and SRAM 200 cores will not be discussed. Instead, the discussion will focus on at least some of the differences between the SRAM 700A and SRAM 200 cores.

[0085] The differences between the SRAM 700A core and the SRAM 200 core include at least the following: The SRAM 700A core features the following: WAS circuits 712A to 712D (see discussion of the Fig. 7B, below); an input / output interface 742 and cell edge units 740A to 740D. In some embodiments, the PL array and the I / O unit 742 are combined as a single unit. The cell edge units 740A to 740D define the boundary of the bit cell array.

[0086] Fig. 7B is a circuit diagram of a WAS circuit 712B in accordance with at least one embodiment of the present disclosure. Compared to Fig. 2B shows Fig. Section 7A presents the WAS circuit 712B as an alternative to the WAS circuit 212B. For the sake of brevity, similarities between the WAS circuit 712B and the WAS circuit 212B are not discussed. Instead, the discussion focuses on at least some of the differences between the WAS circuit 712B and the WAS circuit 212B.

[0087] The differences between the WAS circuit 712B and the WAS circuit 212B include at least the following: While the gate electrodes of transistors NC2 and N1D in the WAS circuit 212B are connected to the buffer activation signal line, the gate electrodes of transistors N4C and N3D in the WAS circuit 712B are connected to the buffer activation signal line. Furthermore, while transistors N4C and N3D in the sub-circuit 720D have an always-off configuration, transistors N2C and N1D in the sub-circuit 720D have an always-on configuration for NMOS transistors, with the gate electrode of each of transistors N2C and N1D connected to voltage VDD.

[0088] Fig. 7C is a block diagram of an SRAM core 700C in accordance with at least one embodiment of the present disclosure. Compared to Fig. 7A shows Fig. 7C presents the SRAM 700C core as an alternative to the SRAM 700A core. For the sake of brevity, similarities between the SRAM 700C and SRAM 700A cores will not be discussed. Instead, the discussion will focus on at least some of the differences between the SRAM 700C and SRAM 700A cores.

[0089] The differences between the SRAM core 700A and the SRAM core 700C include at least the following. The SRAM core 700C features: a 744B write column decoding unit and WAS circuits 712A' to 712D' (see discussion of the Fig. 7D, below). The 744B write column decoding unit generates column-selective buffer activation signals. <o>until <3> for corresponding columns 702A' to 702D'. The activation signals en <o>until <3> are therefore provided for the corresponding WAS circuits 712A' to 712D'. In comparison to the SRAM core 700A of the Fig. 7A offers an advantage of the SRAM 700C core. Fig. 7C in that each of the WAS circuits 712A to 712D' is independently activated by corresponding activation signals. <o>until <3> can be activated / deactivated.

[0090] Fig. 7D is a circuit diagram of a WAS circuit 712B' in accordance with at least one embodiment of the present disclosure. Compared to Fig. 7B shows Fig. Section 7D presents the WAS circuit 712B' as an alternative to the WAS circuit 712B. For the sake of brevity, similarities between the WAS circuit 712B' and the WAS circuit 712B are not discussed. Instead, the discussion focuses on at least some of the differences between the WAS circuit 712B' and the WAS circuit 712B.

[0091] The differences between the WAS circuit 712B' and the WAS circuit 712B include at least the following: In the WAS circuit 712B', the gate electrode of each of transistors N4C and N3D is connected to the corresponding buffer activation signal. <1> connected. Compared to the WAS circuit 712B of the Fig. One advantage of the SRAM core 700D of the WAS circuit 712B' is that the WAS circuit 712B' can be activated by a corresponding activation signal. <11> regardless of how the WAS circuits 712A' and 712C'-712D' are activated by corresponding activation signals <o>and en <2> en <3> can be activated / deactivated.

[0092] Fig. 7E is a block diagram of an SRAM core 700E in accordance with at least one embodiment of the present disclosure. Compared to Fig. 7C shows Fig. The SRAM 700E core is presented as an alternative to the SRAM 700C core. For the sake of brevity, similarities between the SRAM 700E and SRAM 700C cores will not be discussed. Instead, the discussion will focus on at least some of the differences between the SRAM 700E and SRAM 700C cores.

[0093] The differences between the SRAM core 700E and the SRAM core 700C include at least the following. The SRAM core 700E features: a bit-write-enable bar, a BWEB signal, and WAS circuits 712A'' to 712D'' (see discussion of the Fig. 7F, below). The BWEB signal is supplied to the write column decoding unit 744C and to each of the WAS circuits 712A''-712D''.

[0094] Fig. 7F is a circuit diagram of a WAS circuit 712B'' in accordance with at least one embodiment of the present disclosure. Compared to Fig. 7D shows Fig. 7F presents the WAS circuit 712B'' as an alternative to the WAS circuit 712B'. For the sake of brevity, similarities between the WAS circuit 712B'' and the WAS circuit 712B' are not discussed. Instead, the discussion focuses on at least some of the differences between the WAS circuit 712B'' and the WAS circuit 712B'.

[0095] The differences between the WAS circuit 712B'' and the WAS circuit 712B' are at least as follows. In the WAS circuit 712B'', the gate electrode of each of transistors N2C and N1D is connected to the corresponding BWEB signal.

[0096] Fig. 7G is a block diagram of an SRAM core 700G in accordance with at least one embodiment of the present disclosure. Compared to Fig. 7E shows Fig. 7G presents the SRAM 700G core as an alternative to the SRAM 700E core. For the sake of brevity, similarities between the SRAM 700G and SRAM 700E cores will not be discussed. Instead, the discussion will focus on at least some of the differences between the SRAM 700G and SRAM 700E cores.

[0097] The differences between the SRAM 700G core and the SRAM 700E core include at least the following. The SRAM 700G core features the following: WAS shifting 712A''' to 712D''' (see discussion of the Fig. 7H, below) and write control unit 744A of the SRAM core 700A of the Fig. 7A in place of the write column decoding unit 744C of the SRAM core 700E Fig. 7E.

[0098] Fig. 7H is a circuit diagram of a WAS circuit 712B''' in accordance with at least one embodiment of the present disclosure. Compared to Fig. 7F shows Fig. 7H presents the WAS circuit 712B''' as an alternative to the WAS circuit 712B''. For the sake of brevity, similarities between the WAS circuit 712B''' and the WAS circuit 712B'' are not discussed. Instead, the discussion focuses on at least some of the differences between the WAS circuit 712B''''' and the WAS circuit 712B''.

[0099] The differences between the WAS circuit 712B'' and the WAS circuit 712B' are at least as follows. In the WAS circuit 712B''', the gate electrode of each of transistors N2C and N1D is connected to the voltage VDD. In the WAS circuit 712B'', the source electrodes of transistors P1B and P2B are also connected to the signal BWEB instead of the voltage VDD (as in the WAS circuit 712B'').

[0100] Fig. Figure 8A is a flowchart of a method 800 for forming a WAS circuit in accordance with some embodiments. Examples of the WAS circuits formed by method 800 exhibit one or more of the WAS circuit 212B of the Fig. 2B, Fig. 312B of the Fig. 3, Fig. 412B of the Fig. 4A, Fig. 712B of the Fig. 7B, Fig. 712B' the Fig. 7D, Fig. 712B'' the Fig. 7F, Fig. 712B''' the Fig. 7H or something similar.

[0101] In Fig. In diagram 8A, the flowchart of procedure 800 shows blocks 802 to 810. In block 802, an array of memory cells, for example, bit cells such as SRAM bit cells, is created using a memory-adapted process. From block 802, the process continues to block 804. In block 804, the components of the WAS circuit are created using the memory-adapted process.

[0102] Fig. 8B is a flowchart that represents block 804 of the Fig. 8A shows in more detail in accordance with some embodiments.

[0103] In Fig. Block 8B contains block 804 (which again forms components of the WAS circuit using a memory-adapted process) and blocks 820 to 824. Block 820 creates a buffer with a first and a second node. An example of this buffer is buffer 218B. Fig. 2B. An example of the first node of the buffer is therefore segment 230B of the Fig. 2B, and an example of the second node of the cache is segment 232B of the Fig. 2B. From block 820 the process continues to block 822.

[0104] At block 822, the second node is directly connected to a bit line BL. An example of such a direct connection to the bit line BL is the series-connected segments 224A'-224A'' of the Fig. 2B. From block 822, the process continues to block 824. At block 824, the first node is directly connected to a bit-bar line (BLB). An example of such a direct connection to the bit-bar line (BLB) is the series-connected segments 225A'-225A'' of the Fig. 2B.

[0105] Fig. 8C is a flowchart that represents block 804 of the Fig. 8A shows in more detail in accordance with some embodiments.

[0106] In Fig. Block 8C contains block 804 (which again forms components of the WAS circuit using a memory-adapted process) and blocks 830 to 838. Block 830 creates a buffer with a first and a second node. An example of this buffer is buffer 218B. Fig. 2B. An example of the first node of the buffer is therefore segment 226A of the Fig. 2B, and an example of the second node of the cache is segment 226B of the Fig. 2B. From block 830 the process continues to block 832.

[0107] Block 832 forms a first NMOS transistor and a second NMOS transistor. An example of the first NMOS transistor is transistor N3D of subcircuit 220D. Fig. 2B. An example of the second NMOS transistor is the N2C transistor of the 220C sub-circuit. Fig. 2B. From block 832, the sequence continues to block 834. At block 834, the first NMOS transistor is connected in series between the first node and ground. Continuing the example begun above, transistor N3D is connected in series between segment 226A and ground. From block 834, the sequence continues to block 836. At block 836, the second transistor is connected in series between the second node and ground. Continuing the example begun above, transistor N2C is connected in series between segment 226B and ground. From block 836, the sequence continues to block 838. At block 838, one gate electrode of each of the first and second transistors is connected to a buffer activation signal line. The signal on the buffer activation signal line is used to control the first and second transistors.Continuing the examples begun above, segments 269D and 361C are added, which connect the gate electrodes of corresponding transistors N1D and N2C with an intermediate storage activation signal line (in . Fig. (2B not shown) connect..

[0108] Fig. 8D is a flowchart of a method 850 for operating a storage circuit which has a WAS circuit, in accordance with some embodiments.

[0109] An example of the memory circuit controlled by procedure 850 is a memory macro 101 of the Fig. 1. Examples of WAS circuits included in the storage circuit controlled by procedure 850 feature one or more of the WAS circuits 212B of the Fig. 2B, Fig. 312B of the Fig. 3, Fig. 412B of the Fig. 4A, Fig. 712B of the Fig. 7B, Fig. 712B' the Fig. 7D, Fig. 712B'' the Fig. 7F, Fig. 712B''' the Fig. 7H or something similar.

[0110] In Fig. Figure 8A shows the flowchart of procedure 850, blocks 852 to 856. At block 852, a selected column selector switch is controlled to select a corresponding column from an array of memory cells. An example of a column selector switch is column selector switch 245. From block 852, the flow continues to block 854. At block 854, during a write cycle of a memory cell in the selected column, a corresponding WAS circuit is turned on using initial memory-matched voltage levels suitable for the memory-matched transistors in the WAS circuit. An example of the corresponding WAS circuit is WAS circuit 212B. In some embodiments, the initial memory-matched levels are derived from voltages available in the memory power range. From block 854, the flow continues to block 854.

[0111] In block 854, the voltages of the corresponding bit line (for example, BL) and bit bar line (for example, BL_Bar) are increased by using the turn-on WAS circuit. The turn-on WAS circuit is powered by secondary memory-matched voltage levels suitable for the memory-matched transistors in the WAS circuit. In some embodiments, the secondary memory-matched memory levels are derived from voltages available in the memory power range. In some embodiments, the voltages are increased such that the amplitudes of the voltages at the terminal / distal ends of the bit line and bit bar line are increased to be approximately equal to or greater than the amplitudes of the voltages at the corresponding initial / proximal ends of the bit line and bit bar line.

[0112] Fig. Figure 9 is a block diagram of an electronic design automation (EDA) system 900 in accordance with at least one embodiment of the present disclosure.

[0113] In some embodiments, the EDA system 900 features an APR system. The process of the flowcharts of the Fig. 8A to 8C, for example, is implemented using the EDA system in accordance with some embodiments.

[0114] In some embodiments, the EDA system 900 is a general-purpose computing device comprising a hardware processor 902 and a non-volatile, computer-readable storage medium 904. The storage medium 904 is, among other things, encoded with, that is, stores, computer program code 906, that is, a set of executable instructions. The execution of the instructions 906 by the hardware processor 902 constitutes (at least in part) an EDA tool that performs a section or all of, for example, the procedures of Fig. 8A to 8C in accordance with one or more embodiments (hereinafter referred to as the processes and / or methods).

[0115] The processor 902 is electrically coupled to the computer-readable storage medium 904 via a bus 908. The processor 902 is also electrically coupled to an I / O interface 910 via the bus 908. A network interface 912 is likewise electrically coupled to the processor 902 via the bus 908. The network interface 912 is connected to a network 914, enabling the processor 902 and the computer-readable storage medium 904 to communicate with external elements via the network 904. The processor 902 is configured to execute computer program code 906, which is encoded in the computer-readable storage medium 904, in order to make the system 900 usable for executing a section or all of the designated processes and / or procedures. The computer-readable storage medium 904 also includes one or more layouts 907 which are produced according to one or all of the designated processes and / or procedures.In one or more embodiments, the processor 902 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application-specific integrated circuit (ASIC) and / or a suitable processing unit.

[0116] In one or more embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). The computer-readable storage medium 904 comprises, for example, a semiconductor or solid-state memory, a magnetic tape, a removable computer disk, a random-access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and / or an optical disk. In one or more embodiments that utilize optical disks, the computer-readable storage medium 904 comprises a compact disk read-only memory (CD-ROM), a compact disk read / write disk (CD-R / W), and / or a digital video disk (DVD).

[0117] In one or more embodiments, the storage medium 904 stores the computer program code 906, which is configured to cause the system 900 (one such embodiment being (at least partially) the EDA tool) to be usable for executing a section or all of the designated processes and / or procedures. In one or more embodiments, the storage medium 904 also stores information that facilitates the execution of a section or all of the designated processes and / or procedures. In one or more embodiments, the storage medium 904 stores a library (not shown) of standard cells.

[0118] The EDA system 900 features an I / O interface 910. The I / O interface 910 is coupled to external circuitry. In one or more embodiments, the I / O interface 910 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor direction arrows for communicating information and commands to the processor 902.

[0119] The EDA system 900 again features the network interface 912. The network interface 912 includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, WCDMA, or the like, or wired network interfaces such as ETHERNET, USB, or the like. In one or more embodiments, a section or all of the designated processes and / or procedures are implemented in two or more systems 900.

[0120] The System 900 is configured to receive information via the I / O interface 910. The information received through the I / O interface 910 includes one or more instructions, data, design rules, libraries of standard cells, and / or other parameters for processing by the Processor 902. The information is transferred to the Processor 902 via the bus 908. The EDA System 900 is also configured to receive user interface (UI) information via the I / O interface 910. This information is stored on the computer-readable medium 904 as the user interface (UI) 942.

[0121] In some embodiments, a section or all of the designated processes and / or procedures are implemented as a standalone software application for execution by a processor. In some embodiments, a section or all of the designated processes and / or procedures are implemented as a software application that is part of an additional software application. In some embodiments, a section or all of the designated processes and / or procedures are implemented as a plug-in to a software application. In some embodiments, at least one of the designated processes and / or procedures is implemented as a software application that is a section of an EDA tool. In some embodiments, a section or all of the designated processes and / or procedures are implemented as a software application used by the EDA System 900.In some embodiments, a layout is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0122] In some embodiments, the processes are executed as functions of a program stored on a non-volatile, computer-readable recording medium. Examples of a non-volatile, computer-readable recording medium include, but are not limited to, an external / removable and / or internal / built-in storage unit, such as one or more optical discs, such as a DVD; magnetic disks, such as a hard disk; semiconductor memory, such as a ROM; RAM; a memory card; and the like.

[0123] Fig. 10 is a block diagram of a system for manufacturing an integrated circuit (IC), and an IC manufacturing process associated therewith, in accordance with at least one embodiment of the present disclosure.

[0124] In Fig. Figure 10 states that the IC manufacturing system 1000 comprises units, such as a design house 1020, a mask house 1040, and an IC manufacturer / fabricator (“Fab”) 1040, which interact with each other in the design, development, and manufacturing cycles and / or services related to the manufacture of an IC device 1260. The units in the system 1000 are connected by a communication network. In some embodiments, the communication network is a simple network. In other embodiments, the communication network consists of a variety of different networks, such as an intranet and the Internet. The communication network has wired and / or wireless communication channels. Each unit interacts with one or more of the units, providing and / or receiving services to one or more of the other units.In some embodiments, two or more of the Design House 1020, the Mask House 1040, and the IC-Fab 1040 are owned by a single larger company. In some embodiments, two or more of the Design House 1020, the Mask House 1040, and the IC-Fab 1040 exist in a common facility and use common resources.

[0125] Design house (or design team) 1020 creates an IC design layout 1022. IC design layout 1022 features various geometric structures designed for an IC component 1060. These geometric structures correspond to structures of metal, oxide, or semiconductor layers that form the various components of the IC device 1060 to be manufactured. The various layers are combined to form various IC features. For example, a section of IC design layout 1022 features various IC features such as an active area, a gate electrode, source electrode, and drain electrode, metal traces or vias of an interface, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer), as well as various material layers deposited onto the semiconductor substrate. Designhouse 1020 implements its own design approach to create design layout 1022.The design process includes logic design and / or physical design and / or placement and guidance. The IC design layout 1022 is presented in one or more other data files containing information about the geometric structures. The IC design layout 1022 can be expressed, for example, in a GDSII or DFII file format.

[0126] The mask house 1040 includes data preparation 1052 and mask fabrication 1044. The mask house 1040 uses the IC design layout 1022 to fabricate one or more masks, which are used to fabricate the various layers of the IC device 1060 according to the IC design layout 1022. The mask house 1040 performs mask data preparation 1052, in which the IC design layout 1022 is translated into a representative data file (RDF). The mask data preparation 1052 provides the RDF to mask fabrication 1044. Mask fabrication 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticule), or into a semiconductor wafer. The design layout is manipulated by the mask data preparation 1052 to conform to specific features of the mask writer and / or requirements of the IC-Fab 1040. Fig. Figure 10 illustrates the mask data preparation 1052 and the mask production 1044 as separate elements. In some embodiments, the mask data preparation 1052 and the mask production 1044 can be referred to together as a mask data preparation.

[0127] In some embodiments, a mask data preparation 1052 incorporates optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image defects such as those that may arise from diffraction, interference, other process effects, and the like. OPC adapts the IC design layout 1022. In some embodiments, the mask data preparation 1052 incorporates further resolution enhancement techniques (RET) such as off-axis illumination, sub-resolution support features, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as a reverse imaging problem.

[0128] In some embodiments, the mask data preparation 1052 includes a mask rule checker (MRC) that aligns the IC design layout, which has undergone processes in OPC, with a set of mask application rules that include certain geometric and / or connectivity constraints to ensure sufficient margins to accommodate variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask manufacturing 1044 that may undo some of the changes made by the OPC to comply with mask application rules.

[0129] In some embodiments, the mask data preparation 1052 includes Lithography Process Checking (LPC), which simulates the processing performed by the IC Fab 1040 to manufacture the IC fixture 1060. The LPC simulates this processing based on the IC design layout 1022 to create a simulated manufactured fixture, such as the IC fixture 1060. The processing parameters in the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), or other suitable factors, or combinations thereof.If, in some embodiments, after applying a simulated manufactured device by LPC, the simulated device is not close enough to the shape to meet the design rules, OPC and / or MRC can be repeated to further refine the IC design layout 1022.

[0130] It is clear that the above description of mask data preparation 1052 has been simplified for clarity. In some embodiments, data preparation 1052 has additional features such as a Logic Operation (LOP) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to the IC design layout 1022 during data preparation 1052 can be performed in a variety of different sequences.

[0131] Following mask data preparation 1052 and during mask fabrication 1044, a mask or a group of masks are fabricated based on the modified IC design layout. In some embodiments, an electron beam (“e-beam”) or a mechanism with multiple e-beams is used to form a structure on a mask (photomask or reticulum) based on the modified IC design layout. The mask can be implemented using various technologies. In some embodiments, the mask is formed using binary technology. In some embodiments, a mask structure has opaque and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image-sensitive material layer (for example, a photoresist) deposited on a wafer, is blocked by the opaque region and transmits through the transparent regions.In one example, a binary mask has a transparent substrate (for example, molten quartz) and an opaque material (for example, chromium) deposited in the opaque area of ​​the mask. In another example, the mask is formed using phase-shift mask technology. With phase-shift masking (PSM), various features in the structures formed on the mask are configured to create a suitable phase difference to enhance resolution and image quality. In various examples, the phase-shift mask can be a damped PSM or an alternating PSM. The mask(s) manufactured by Mask Manufacturing 1044 are used in a variety of processes.Such masks are used, for example, in an ion implantation process to form various doped areas in the semiconductor wafer, in an etching process to form various etched areas in the semiconductor wafer and / or in other suitable processes.

[0132] The IC-Fab 1040 is an IC manufacturing company that has one or more manufacturing facilities for producing a variety of different IC products. In some configurations, the IC-Fab 1040 is a semiconductor foundry. For example, there may be one manufacturing facility for the front-end manufacturing of a variety of IC products (front-end-of-line (FEOL) manufacturing), while a second manufacturing facility may provide back-end manufacturing for the interconnection and packaging of IC products (back-end-of-line (BEOL) manufacturing), and a third manufacturing facility may provide other services for the foundry business.

[0133] The IC-Fab 1040 uses the mask (or masks) manufactured by the mask house 1040 to fabricate the IC device 1060. The IC-Fab 1040 therefore uses, at least indirectly, the IC design layout 1022 to fabricate the IC device 1060. In some embodiments, semiconductor wafers 1052 are fabricated by the IC-Fab 1040 using the mask (or masks) to form the IC device 1060. The semiconductor wafer 1052 has a silicon substrate or other suitable substrate on which layers of material are formed. The semiconductor wafer further has one or more diverse doped regions, dielectric features, multilevel interconnects, and the like (formed in successive fabrication steps).

[0134] Details relating to an integrated circuit (IC) manufacturing system (for example, the System 1000 of the Fig. 10) and an IC manufacturing process that is part of it can be found, for example, in US Patent No. US 9,256,709 B2 granted on February 9, 2016, US Pre-Grant Publication No. US 2014 / 0 040 838 A1 published on October 1, 2015, US Pre-Grant Publication No. US 2015 / 0 278 429 A1 published on February 6, 2014, and US Patent No. US 7,260,442 B2 granted on August 21, 2012.

[0135] In one embodiment, the write-support circuit comprises: a first PMOS transistor and a first NMOS transistor connected in series between a power supply voltage and a first node, with the gate electrodes of the first PMOS transistor and the first NMOS transistor connected to a second node; a first switchable conductive path between the first node and a ground voltage; a second PMOS transistor and a second NMOS transistor connected in series between the power supply voltage and a third node, with the gate electrodes of the second PMOS transistor and the second NMOS transistor connected to a fourth node; a second switchable conductive path between the third node and the ground voltage; and a third NMOS transistor connected in series between the fourth node and a data line.a first shunt connecting the fourth node and the data line; a fourth NMOS transistor connected in series between the second node and a data bar line, and a second shunt connecting the second node and the data bar line.

[0136] In one embodiment, the write-support circuit comprises: a first PMOS transistor and a first NMOS transistor connected in series between a power supply voltage and a first node, wherein the gate electrodes of the first PMOS transistor and the first NMOS transistor are connected to a second node, the second node being connected to a data bar line; a first switchable conductive path between the first node and a ground voltage; a second PMOS transistor and a second NMOS transistor connected in series between the power supply voltage and a third node, wherein the gate electrodes of the second PMOS transistor and the second NMOS transistor are connected to a fourth node, the fourth node being connected to a data line; a second switchable conductive path between the third node and the ground voltage;a third NMOS transistor having a high-resistance configuration, with a first drain / source electrode connected to the fourth node; a first shunt connecting the fourth node and the data line; a fourth NMOS transistor having a high-resistance configuration, with a drain / source electrode connected to the second node, and a second shunt connecting the second node and the data bar line.

[0137] In one embodiment, the write-support circuit comprises a memory-matched buffer and memory-matched third and fourth NMOS transistors. The buffer comprises a memory-matched first PMOS transistor and a memory-matched first NMOS transistor connected in series between a power supply voltage and a first node, the first node being selectively connectable to a ground voltage; and a memory-matched second PMOS transistor and a memory-matched second NMOS transistor connected in series between the power supply voltage and the second node, the second node being selectively connectable to the ground voltage. The third NMOS transistor is connected in series between the first node and the ground voltage, and the fourth NMOS transistor is connected in series between the second node and the ground voltage.A gate electrode of each of the third and fourth transistors is connected to an intermediate storage activation signal line for controlling the storage-adapted intermediate storage.< / o> < / o> < / o> < / o>

Claims

[1] Write support circuit (212B, 312B, 412B) comprising the following: a first PMOS transistor (P1B) and a first NMOS transistor (N1B) connected in series between a power supply voltage (VDD, 210, 310) and a first node, with gate electrodes of the first PMOS transistor (P1B) and the first NMOS transistor (N1B) connected to a second node; a first switchable conductive path (226A, 326A, 379) between the first node and an earth voltage (VSS); a second PMOS transistor (P2B) and a second NMOS transistor (N2B) connected in series between the supply voltage (VDD, 210, 310) and a third node, with the gate electrodes of the second PMOS transistor (P2B) and the second NMOS transistor (N2B) connected to a fourth node; a second switchable conductive path (226B, 326B, 375) between the third node and the ground voltage (VSS); a third NMOS transistor (N3B) connected in series between the fourth node and a data line (BL); a first shunt (224B', 224B'', 352B) that connects the fourth node and the data line (BL); a fourth NMOS transistor (N4B) connected in series between the second node and a data bar line (BLB), and a second shunt (225B', 225B'', 354B) that connects the second node and the data bar line (BLB). [2] Write support circuit (212B, 312B, 412B) according to claim 1, wherein the first switchable conductive path (226A, 326A, 379) comprises: a fifth NMOS transistor (N1D) connected in series between the first node and the ground voltage (VSS), and where one gate electrode of the fifth NMOS transistor (N1D) is configured to receive a control signal (EN, Latch_en). [3] Write support circuit (212B, 312B, 412B) according to claim 2, wherein the second switchable conductive path (226B, 326B, 375) comprises: a sixth NMOS transistor (N2C) connected in series between the third node and the ground voltage (VSS), and where one gate electrode of the sixth NMOS transistor (N2C) is configured to receive the control signal (EN, Latch_en). [4] Write support circuit (212B, 312B, 412B) according to any one of the preceding claims, wherein: the first shunt (224B', 224B'', 352B) has no transistor, and the second shunt (225B', 225B'', 354B) has no transistor. [5] Write support circuit (212B, 312B, 412B) according to claim 4, wherein: a gate electrode of the third NMOS transistor (N3B) is connected to the first shunt (224B', 224B'', 352B), and a gate electrode of the fourth NMOS transistor (N4B) is connected to the second shunt (225B', 225B'', 354B). [6] Write support circuit (212B, 312B, 412B) according to any of the preceding claims, further comprising: a fifth NMOS transistor (N1D) connected in series between the first node and the ground voltage (VSS); a sixth NMOS transistor (N2C) connected in series between the third node and the ground voltage (VSS), and wherein the gate electrodes of each of the fifth NMOS transistor (N1D) and the sixth NMOS transistor (N2C) are connected to the ground voltage (VSS). [7] Write support circuit (212B, 312B, 412B) according to any one of the preceding claims, wherein: the data line (BL) is a bit line, and The Data Bar Line (BLB) is a Bit Bar Line. [8] Write support circuit (212B, 312B, 412B) comprising the following: a first PMOS transistor (P1B) and a first NMOS transistor (N1B) connected in series between a power supply voltage (VDD, 210, 310) and a first node, wherein the gate electrodes of the first PMOS transistor (P1B) and the first NMOS transistor (N1B) are connected to a second node, the second node being connected to a data bar line (BLB); a first switchable conductive path (226A, 326A, 379) between the first node and an earth voltage (VSS); a second PMOS transistor (P2B) and a second NMOS transistor (N2B) connected in series between the power supply voltage (VDD, 210, 310) and a third node, wherein the gate electrodes of the second PMOS transistor (P2B) and the second NMOS transistor (N2B) are connected to a fourth node, the fourth node being connected to a data line (BL); a second switchable conductive path (226B, 326B, 375) between the third node and the ground voltage (VSS); a third NMOS transistor (N3B) which has a high-resistance configuration and for which a first drain / source electrode is connected to the fourth node; a first shunt (224B', 224B'', 352B) that connects the fourth node and the data line (BL); a fourth NMOS transistor (N4B) which has a high-resistance configuration and for which a first drain / source electrode is connected to the second node, and a second shunt (225B', 225B'', 354B) that connects the second node and the data bar line (BLB). [9] Write support circuit (212B, 312B, 412B) according to claim 8, wherein the first switchable conductive path (226A, 326A, 379) comprises: a fifth NMOS transistor (N3D) connected in series between the first node and the fifth node; a sixth NMOS transistor (N1D) connected in series between the fifth node and the ground voltage (VSS), and where one gate electrode of the fifth NMOS transistor (N3D) is configured to receive a control signal (EN, Latch_en). [10] Write support circuit (212B, 312B, 412B) according to claim 9, wherein the first switchable conductive path (226A, 326A, 379) comprises: a gate electrode of the sixth NMOS transistor (N1D) which is connected to the power supply voltage (VDD, 210, 310). [11] Write support circuit (212B, 312B, 412B) according to claim 9 or 10, wherein the second switchable conductive path (226B, 326B, 375) comprises: a seventh NMOS transistor (N4C) connected in series between the third node and a sixth node; an eighth NMOS transistor (N2C) connected in series between the sixth node and the ground voltage (VSS), and where one gate electrode of the seventh NMOS transistor (N4C) is configured to receive the control signal (EN, Latch_en). [12] Write support circuit (212B, 312B, 412B) according to claim 11, wherein the second switchable conductive path (226B, 326B, 375) comprises: a gate electrode of the eighth NMOS transistor (N2C) which is connected to the power supply voltage (VDD, 210, 310). [13] Write support circuit (212B, 312B, 412B) according to claim 11 or 12, further comprising: a third PMOS transistor (P2C) connected in series between the supply voltage (VDD, 210, 310) and the gate electrode of the eighth NMOS transistor (N2C), and where one gate electrode of the third PMOS transistor (P2C) is configured to receive the control signal (EN, Latch_en). [14] Write support circuit (212B, 312B, 412B) according to any one of the preceding claims 9 to 13, further comprising: a third PMOS transistor (P1D) connected in series between the supply voltage (VDD, 210, 310) and the gate electrode of the sixth NMOS transistor (N1D), and where one gate electrode of the third PMOS transistor (P1D) is configured to receive the control signal (EN, Latch_en). [15] Write support circuit (212B, 312B, 412B) according to any one of the preceding claims 8 to 14, wherein: the first shunt (224B', 224B'', 352B) has no transistor, and the second shunt (225B', 225B'', 354B) has no transistor. [16] Write support circuit (212B, 312B, 412B) according to any one of the preceding claims 8 to 15, wherein: a gate electrode of each of the third NMOS transistor (N3B) and the fourth NMOS transistor (N4B) are connected to the ground voltage (VSS). [17] Write support circuit (212B, 312B, 412B) according to any one of the preceding claims 8 to 16, further comprising: a fifth NMOS transistor connected in series between the first node and a fifth node; a sixth NMOS transistor connected in series between the fifth node and the ground voltage (VSS); a seventh NMOS transistor connected in series between the third node and a sixth node; an eighth NMOS transistor connected in series between the sixth node and the ground voltage (VSS), and wherein the gate electrodes of each of the fifth NMOS transistor and the eighth NMOS transistor are connected to the ground voltage (VSS). [18] Write support circuit (212B, 312B, 412B) according to any one of the preceding claims 8 to 17, wherein: a second drain / source electrode of the third NMOS transistor is connected to a fifth node; a second drain / source electrode of the fourth NMOS transistor is connected to a sixth node, and The write-assist circuit (212B, 312B, 412B) further includes the following: a fifth NMOS transistor and a sixth NMOS transistor connected in series between the fifth node and the ground voltage (VSS), and a seventh NMOS transistor and an eighth NMOS transistor connected in series between the sixth node and the ground voltage (VSS); wherein a gate electrode of each of the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor and the eighth NMOS transistor is connected to the ground voltage (VSS). [19] Write support circuit (212B, 312B, 412B) comprising the following: a memory-adapted cache (218B, 318B) that features the following: a memory-matched first PMOS transistor (P1B) and a memory-matched first NMOS transistor (N1B) connected in series between a power supply voltage (VDD, 210, 310) and a first node, the first node being selectively connectable to a ground voltage (VSS), and a memory-matched second PMOS transistor (P2B) and a memory-matched second NMOS transistor (N2B) connected in series between the power supply voltage (VDD, 210, 310) and a first node, the second node being selectively connectable to the ground voltage (VSS); a memory-matched third NMOS transistor (N3D) connected in series between the first node and the ground voltage (VSS), and a memory-matched fourth NMOS transistor (N4C) connected in series between the second node and the ground voltage (VSS); wherein a gate electrode of each of the third and fourth transistors (N3D, N4C) is connected to an intermediate storage activation signal line (243A) for controlling the memory-adapted intermediate storage (218A, 218B, 412B). [20] Write support circuit (212B, 312B, 412B) according to claim 19, wherein: The gate electrodes of the first PMOS transistor (P1B) and the first NMOS transistor (N1B) are connected to a third node; The gate electrodes of the second PMOS transistor (P2B) and the second NMOS transistor (N2B) are connected to a fourth node; the fourth node is connected via a data line (BL), and the third node is connected to the Data Bar Line (BLB).

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