Storage system and method therefor
Patent Information
- Application Number
- DE102018110957
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2018-01-15
- Filing Date
- 2018-05-08
- Publication Date
- 2025-02-20
- Estimated Expiration
- 2038-05-08
Smart Images
Figure 00000000_0000_ABST
Abstract
Description
BACKGROUND
[0001] Embodiments of the inventive concept described herein relate to a storage system and a method thereof.
[0002] Semiconductor memories are classified into volatile memory devices, in which stored data disappears when a power supply is interrupted, and non-volatile memory devices, in which stored data is retained even when a power supply is interrupted.
[0003] A flash memory device, which is a type of non-volatile memory device, is widely used as a mass storage medium of a user device. As computer technology advances, there is a continuous need to improve the performance of a flash memory-based mass storage medium. For example, a flash memory-based mass storage medium uses a high-speed buffer memory, such as a random access memory, to compensate for a difference between the input / output speeds of a host and the storage medium. However, there is a limitation to the improvement in performance due to factors such as limited capacity of the high-speed buffer memory or limitations in the ability to guarantee the reliability of data to be stored in a flash memory.
[0004] US 2016 / 0 041 790 A1 discloses: A data storage system including: a non-volatile solid-state memory including non-volatile storage units and a temporary register; a data storage controller configured to receive a write command including a plurality of logical data segments from a host; a write buffer associated with receiving a portion of the plurality of logical data segments and accumulating a physical data segment corresponding to a write unit of the solid-state memory; a solid-state memory controller configured to transfer the accumulated data from the write buffer to the temporary storage register each time the write buffer accumulates a physical data segment.The data storage controller confirms the completion of the write command to the host after the last logical data segment has been written to the write buffer and releases the write buffer after the solid-state memory has finished receiving the accumulated data into the temporary storage register.
[0005] US 2008 / 0 209 266 A1 discloses: A memory device may include a memory cell array, a page buffer circuit, and / or control logic. The page buffer circuit may include a first and a second register and be configured to store data to be programmed into the memory cell array. The control logic may be configured to control the page buffer circuit to reload data stored in the first register to the second register in response to a reload command when a program operation fails.
[0006] US 2009 / 0 019 194 A1 relates to a storage device with a non-volatile memory.
[0007] Direct memory access. In: Wikipedia, the free encyclopedia. Processing status: April 25, 2017. URL: https: / / en.wikipedia.org / w / index.php?title=Directmemory access&oldid=777183266 concerns direct access memory. SUMMARY
[0008] Embodiments of the inventive concept are set out in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The foregoing and other objects and features will become more apparent from the following description with reference to the following drawings, in which like reference characters refer to like parts throughout the several drawings unless otherwise specified. In the drawings: Fig. 1 is a block diagram illustrating one embodiment of a user system; Fig. 2 a block diagram showing a memory controller of Fig. 1 represents; Fig. 3A and Fig. 3B are flowcharts illustrating embodiments of operating methods of the memory controller of Fig. 1 represent; Fig. 4, Fig. 5 and Fig. 6 views for describing embodiments of operating methods of the memory controller of Fig. 1 in detail; Fig. 7 and Fig. 8 views showing a structure of a storage device of Fig. 1 and a structure of a second buffer memory of Fig. 1 represent; Fig. 9 is a block diagram illustrating one embodiment of a user system; Fig. 10, Fig. 11 and Fig. 12 views for describing an operation of a memory controller of Fig. 9; Fig. 13 is a block diagram illustrating one embodiment of a user system; Fig. 14 is a flowchart showing an operation of a memory controller of Fig. 13 represents; Fig. 15 is a view for describing an operation of the memory controller of Fig. 13; Fig. 16 is a timing diagram for describing how write data is transferred to non-volatile memory devices through a plurality of channels; Fig. 17 is a view for describing a method in which the memory controller recovers write data in a programming failure situation; Fig. 18 is a timing diagram for describing an embodiment of a data transfer unit; Fig. 19 is a block diagram illustrating a configuration of an embodiment of the memory controller; and Fig. 20 is a block diagram illustrating one embodiment of a user system having a storage device. DETAILED DESCRIPTION
[0010] In the following, embodiments of the inventive concept are described in detail and clearly to such an extent that a person skilled in the art can easily implement the inventive concept.
[0011] Fig. 1 is a block diagram illustrating one embodiment of a user system 100. Referring to Fig. 1, a user system 100 may include a host device (host 110) and a storage device 120. The user system 100 may be a computer system or an information processing system, such as a computer, a notebook, a server, a workstation, a portable communications terminal, a personal digital assistant (PDA), a portable multimedia player (PMP), a smartphone, or a wearable device.
[0012] Based on a specified interface, the host 110 can store data in the storage device 120 or read data stored in the storage device 120. In one embodiment, the interface can be at least one of various communication interfaces, such as, but not limited to, a double data rate (DDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, an eMMC (embedded MMC) interface, a peripheral component interconnection (PCI) interface, a PCI Express (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial ATA interface, a parallel ATA interface, a small computer small interface (SCSI) interface, an enhanced small disk interface (ESDI) interface,an Integrated Drive Electronics interface (IDE interface), a Firewire interface, a Universal Flash Storage interface (UFS interface) and a Nonvolatile Memory Express interface (NVMe interface).
[0013] The storage device 120 may include a memory controller 121, non-volatile memory devices 122, and a second buffer memory 123. In one embodiment, the storage device 120 may be a mass storage medium of a user system 100, such as a solid-state drive (SSD), a USB memory, a hard disk drive, or a USB flash drive.
[0014] Under the control of the host 110, the memory controller 121 can store data in non-volatile memory devices 122 or read data stored in the non-volatile memory devices 122. The memory controller 121 can include a first buffer memory 121a. The first buffer memory 121a can temporarily store data to be stored in the non-volatile memory devices 122 or data to be read from the non-volatile memory devices 122. That is, the first buffer memory 121a can be used as a write buffer or a read buffer of the storage device 120.
[0015] Under the control of the memory controller 121, the non-volatile memory devices 122 can store data or output data stored therein. In one embodiment, each of the non-volatile memory devices 122 can comprise NAND flash memory. However, embodiments of the inventive concept are not limited thereto. Each of the non-volatile memory devices 122 can comprise, for example, a non-volatile memory such as a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), or a ferroelectric RAM (FRAM).
[0016] The second buffer memory 123 may store a variety of information required for the storage device 120 to operate. For example, the second buffer memory 123 may store information such as a mapping table used in a flash translation layer (FTL) of the memory controller 121. The second buffer memory 123 may be further configured to temporarily store write data to be stored in the non-volatile memory devices 122. In one embodiment, the second buffer memory 123 may be implemented with a die, chip, assembly, or module that is independent of the memory controller 121, or may be implemented with the same die, chip, assembly, or module as the memory controller 121.In one embodiment, the second buffer memory 123 may have a storage capacity greater than that of the first buffer memory 121a.
[0017] According to an embodiment of the inventive concept, the storage device may release the first buffer memory 121a used as a write buffer and transmit a write completion to the host 110 before successfully programming the write data in the non-volatile memory devices 222, so that a delay associated with a write request from the host 110 is minimized and an available capacity of the first buffer memory 121a is ensured.
[0018] For example, the storage device 120 may temporarily store write data from the host 110 in the first buffer memory 121a of the memory controller 121. The storage device 120 may release the first buffer memory 121a after transferring the write data stored in the first buffer memory 121a to the non-volatile memory devices 122 and to the second buffer memory 123, thus ensuring an available capacity of the first buffer memory 121a. In this case, there may be a need to retain the write data stored in the second buffer memory 123 until the write data has been completely and successfully programmed into the non-volatile memory devices 122.Accordingly, even if a programming failure occurs in the non-volatile memory devices 122, data reliability can be ensured because the write data is recovered using the second buffer memory 123. That is, the first buffer memory 121a according to an embodiment of the inventive concept can be used as a write buffer, and the second buffer memory 123 can be used as a backup buffer or a recording buffer. In some embodiments, the second buffer memory 123 can be a dynamic random access memory (DRAM), and an entire DRAM bandwidth of the second buffer memory 123 can be used to transfer the write data from the first buffer memory 121a to the second buffer memory 123.
[0019] During a programming operation, a conventional storage device ensures data reliability by holding data stored in a write buffer until programming of non-volatile memory devices is successfully completed, or by transmitting a write completion to a host after programming of non-volatile memory devices is successfully completed. However, if the capacity of the write buffer is insufficient, write performance may decrease, and write latency may increase because the timing at which the write completion is transmitted is delayed.
[0020] However, the storage device 120 according to an embodiment of the inventive concept can ensure the available capacity of the first buffer memory 121a used as a write buffer by releasing the write buffer in advance regardless of successful completion of programming of the non-volatile memory devices 122, and can prevent write delay by transmitting a write completion to the host 110 before successful completion of programming of the non-volatile memory devices 122. In one embodiment, the write data can be retained in the second buffer memory 123 until programming of the non-volatile memory devices 122 is successfully completed, thereby ensuring data reliability in a programming failure situation.
[0021] Accordingly, it may be possible to ensure both sufficient available write buffer space and write data reliability in a DRAM-less storage device or a storage device having a small write buffer. That is, the storage device 120 according to an embodiment of the inventive concept can provide improved reliability and performance. Operation of the storage device 120 according to an embodiment of the inventive concept will be described more fully with reference to the following drawings.
[0022] Fig. 2 is a block diagram illustrating the memory controller 121 of Fig. 1 in detail. With reference to Fig. 1 and Fig. 2, the memory controller 121 may include a first buffer memory 121a, a processor 121b, a ROM 121c, a buffer manager 121d, a host interface layer 121e, and a flash interface layer 121f.
[0023] As with reference to Fig. 1, a first buffer memory 121a may be used as a write buffer or a read buffer of the storage device 120. The first buffer memory 121a may be configured, for example, to temporarily store write data from the host 110 or to read data read from the non-volatile memory devices 122. In one embodiment, the first buffer memory 121a may comprise a static random access memory (SRAM). However, embodiments of the inventive concept may not be limited thereto. The first buffer memory 121a may comprise, for example, a random access memory such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a PRAM, an MRAM, a resistive random access memory, and an FRAM, etc.
[0024] The processor 121b may control overall operation of the memory controller 121. For example, the processor 121b may be configured to control firmware, program code, a software layer, etc., required for the memory controller 121 to operate or control various hardware elements that the memory controller 121 includes. The ROM 121c may store a variety of information required for the memory controller 121 to operate in the form of firmware. In one embodiment, the processor 121b may be configured to control firmware stored in the ROM 121c.
[0025] The buffer manager 121d may be configured to control the second buffer memory 123. The second buffer memory 123 may include, for example, a DRAM, and the buffer manager 121d may be a DRAM controller configured to write data to the second buffer memory 123 or read data stored in the second buffer memory 123. In one embodiment, the buffer manager 121d may be omitted depending on a structure of the memory controller 121 or the second buffer memory 123.
[0026] The memory controller 121 may be configured to communicate with the host 110 through the host interface layer 121e. The host interface layer 121e may include at least one of specified interfaces described with reference to Fig. 1. The memory controller 121 may be configured to communicate with the non-volatile memory devices 122 through a flash interface layer 121f.
[0027] Fig. 3A and Fig. 3B are flowcharts illustrating embodiments of operating methods of the memory controller 121 of Fig. 1. For a brief description, embodiments of the inventive concept will be described below based on a write operation of the storage device 120. However, embodiments of the inventive concept need not be limited thereto. For example, the scope of the inventive concept may be applied to various operations.
[0028] For a brief description, an operation of the memory controller 121 will be described below based on a write data unit. For example, the memory controller 121 may receive write data WRD from the host 110 and transfer the received write data WRD to the non-volatile memory devices 122. However, embodiments of the inventive concept need not be limited thereto. For example, a data transfer unit between the host 110 and the memory controller 121 may be different from a data transfer unit between the memory controller 121 and the non-volatile memory devices 122.
[0029] Hereinafter, "enabling the first buffer memory 121a or the second buffer memory 123" may refer to a state where different write data can be stored in an area of the first buffer memory 121a where write data is already stored, or in an area of the second buffer memory 123 where the write data is already stored. That is, in the case where there is the first buffer memory 121a where the write data is stored, different write data can be stored in the first buffer memory 121a (more specifically, in an area where the write data is stored, among areas of the first buffer memory 121a) where the write data is stored, or the first buffer memory 121a (or the area thereof) can be allocated so that different write data is stored.In one embodiment, the release or allocation of the buffer memory may be performed by the processor 121b of the memory controller 121 or any other separate hardware element or any other software element of the memory controller 121.
[0030] For the sake of brevity, data or information may be described below as simply being exchanged between elements. However, embodiments of the inventive concept may not be limited to this. Data transfer and data flow between elements may, for example, be established through a predefined protocol between the elements. The assumptions described above are presented merely as examples to briefly and clearly describe the scope and idea of the inventive concept, without any limitation thereto.
[0031] Referring to Fig. 1 to 3A, in operation S110, the memory controller 121 may receive write data WRD from the host 110 and store the received write data WRD in the first buffer memory 121a. As described above, for example, the first buffer memory 121a may be used as a write buffer that temporarily stores the write data WRD from the host 110. The memory controller 121 may temporarily store the write data WRD from the host 110 in the first buffer memory 121a. In one embodiment, the memory controller 121 may be configured to receive a write request (or write command) from the host 110 and to allocate the first buffer memory 121a in which the corresponding write data is stored in response to the received write request.
[0032] In operation S120, the memory controller 121 may transmit the WR completion to the host 110. For example, the memory controller 121 may store the write data WRD in the first buffer memory 121a and then transmit the WR completion associated with the above-described write request to the host 110. In one embodiment, the host 110 receiving the WR completion may recognize that a write corresponding to the issued write request has been completed and may perform other operations (e.g., another write request, a read request, or other internal operations).
[0033] In operation S130, the memory controller 121 may transmit the write data WRD to the non-volatile memory devices 122 and the second buffer memory 123. For example, the memory controller 121 may transmit the write data WRD to the non-volatile memory devices 122 such that the write data WRD stored in the first buffer memory 121a is stored in the non-volatile memory devices 122. The non-volatile memory devices 122 may perform a programming operation on the received write data WRD.
[0034] The memory controller 121 may additionally transfer the write data WRD stored in the first buffer memory 121a to the second buffer memory 123. In one embodiment, the write data WRD stored in the second buffer memory 123 may be used to recover data in a program failure situation of the non-volatile memory devices 122. In one embodiment, the first buffer memory 121a may be implemented as a dual-port memory or a multi-port memory to transfer the write data WRD from the first buffer memory 121a to the non-volatile memory devices 122 and to the second buffer memory 123 simultaneously.
[0035] In operation S140, the memory controller 121 may release the first buffer memory 121a. For example, the memory controller 121 may release the first buffer memory 121a after the write data WRD has been transferred to the non-volatile memory devices 122 and to the second buffer memory 123. In this case, since the first buffer memory 121a used as a write buffer is released, an available capacity of the first buffer memory 121a can be ensured. This may mean that the memory controller 121 receives and stores other write data from the host 110. That is, as soon as the first buffer memory 121a is released, the write delay due to a limited capacity of the write buffer can be prevented.
[0036] In operation S150, the memory controller 121 may determine whether the write data WRD is successfully programmed into the non-volatile memory devices 122. For example, the memory controller 121 may receive information about a programming result (i.e., a programming success or failure), such as a write success signal or a write failure signal, from the non-volatile memory devices 122. The memory controller 121 may determine whether the programming operation is successful based on the received information.
[0037] If it is determined that the programming operation is successful, in operation S160, the memory controller 121 may release the second buffer memory 123, for example, in response to a write success signal received from the non-volatile memory devices 122 as a confirmation of successful writing of the write data transferred to the non-volatile memory devices 122. For example, since the programming operation was successful indicates that the write data WRD was normally stored in the non-volatile memory devices 122, the second buffer memory 123 in which the write data WRD is stored may be released, thereby ensuring an available capacity of the second buffer memory 123.
[0038] In the case where the programming operation fails, in operation S170, the memory controller 121 may, for example, in response to a write fail signal received from the non-volatile memory devices 122, copy the write data WRD stored in the second buffer memory 123 to the first buffer memory 121a (or may restore the write data WRD stored in the first buffer memory 121a by using the write data WRD stored in the second buffer memory 123). For example, since the programming failure means that the write data WRD was not normally stored in the non-volatile memory devices 122, there may be a need for an additional operation of programming the write data WRD to the non-volatile memory devices 122.In this case, since the first buffer memory 121a was previously enabled in operation S140, the first buffer memory 121a may be in a state where the write data WRD is not stored therein. However, since the write data WRD is stored in the second buffer memory 123 in operation S130, the second buffer memory 123 may be in a state where the write data WRD is stored therein. Accordingly, the memory controller 121 may reprogram the write data WRD after copying the write data WRD from the second buffer memory 123 to the first buffer memory 121a (or restoring the write data WRD).
[0039] The operations S130 to S150 may be performed after the operation S170. In this case, since the write data WRD is previously stored in the second buffer memory 123, an operation of transferring the write data WRD to the second buffer memory 123 can be omitted.
[0040] Referring to Fig. 1, Fig. 2 and Fig. 3B, the memory controller 121 may next perform operation S110 to operation S160 described above with reference to Fig. 3A were described.
[0041] In the case where the programming operation S150 fails, then in an operation S180, the memory controller 121 may directly transfer the write data WRD stored in the second buffer memory 123 to the non-volatile memory devices 122.
[0042] According to the embodiment of Fig. 3A, for example, if a programming operation fails, the memory controller 121 may be configured to transfer the write data WRD stored in the second buffer memory 123 to the first buffer memory 121a, and then transfer the write data WRD from the first buffer memory 121a to the non-volatile memory devices 122. According to the embodiment of Fig. 3B, in contrast, in the case where the programming operation fails, the memory controller 121 may be configured to transfer the write data WRD from the second buffer memory 123 directly to the non-volatile memory devices 122. That is, restoring the data in the first buffer memory 121a may be omitted. Restoring the data of the first buffer memory 121a has been omitted for a brief description with respect to Fig. 3A. However, embodiments of the inventive concept need not be limited thereto. For example, restoring the data WRD in the first buffer memory 121a may be omitted, and the write data WRD may be transferred from the second buffer memory 123 directly to the non-volatile memory devices 122, as shown in Fig. 3B is shown.
[0043] As described above, according to an embodiment of the inventive concept, the storage device 120 or the memory controller 121 can release a write buffer and transfer a write completion in advance before the non-volatile memory devices 122 successfully complete a programming operation, thereby preventing a reduction in performance due to limited buffer capacity or a reduction in performance due to delayed transfer of the write completion. Furthermore, even if a programming operation fails in the non-volatile memory devices 122, data reliability can be ensured because the write data WRD is restored from a separate buffer memory (i.e., the second buffer memory 123).
[0044] Fig. 4 to 6 are views for describing an operation method of the memory controller 121 of Fig. 1 in detail. For a brief description, elements that are not necessary to describe operation of the memory controller 121 will not be repeated here. Fig. 4 is a view for describing an operation of the memory controller 121 and a data flow in the case where a programming operation is successful. Fig. 5 is a timing diagram illustrating a data flow in the case where a programming operation is successful. Fig. 6 is a view for describing an operation of the memory controller 121 and a data flow in the case where a programming operation fails.
[0045] Referring to Fig. 4 and Fig. 5, the host 110 can first transmit the write data WRD to the memory controller 121 (①). At a time t1 of Fig. 5, for example, the memory controller 121 may allocate an area in which the write data WRD is stored among areas of the first buffer memory 121a. In one embodiment, the allocation of the first buffer memory 121a may be performed in response to a write request from the host 110. The memory controller 121 may store the write data WRD in the allocated area.
[0046] After the write data WRD has been stored in the first buffer memory 121a, the memory controller 121 may transmit the WR completion to the host 110 (②). At a time t2 of Fig. 5, for example, the write data WRD may be fully transmitted from the host 110, and the memory controller 121 may transmit the WR completion to the host 110. In one embodiment, when the WR completion is received, the host 110 may detect that a write (or program) operation associated with the write data WRD has completed.
[0047] The memory controller 121 may transmit the write data WRD to the non-volatile memory devices 122 and to the second buffer memory 123 (3). For example, the memory controller 121 may transmit the write data WRD to the non-volatile memory devices 122 such that the write data WRD is stored in the non-volatile memory devices 122. The memory controller 121 may additionally transmit the write data WRD to the second buffer memory 123 such that the write data WRD is stored in the second buffer memory 123. In one embodiment, the non-volatile memory devices 122 may receive the write data WRD and perform a programming operation on the received write data WRD.
[0048] In one embodiment, operations of transferring the write data WRD to the non-volatile memory devices 122 and to the second buffer memory 123 may be performed at substantially the same time. This may mean that there is no need for additional time due to the transfer of the write data WRD to the second buffer memory 123.
[0049] The memory controller 121 may, after transmitting the write data WRD to the non-volatile memory devices 122 and to the second buffer memory 123, enable the first buffer memory 121a (4), so that the first buffer memory 121a is in an enabled operating state. Writing additional write data to the first buffer memory 121a is prohibited here before the operating state of the first buffer memory 121a is enabled, and writing additional write data to the first buffer memory 121a is permitted after the operating state of the first buffer memory 121a is enabled. At a third time t3 of Fig. 5, for example, the write data WRD may be completely transferred from the first buffer memory 121a to the non-volatile memory devices 122 and to the second buffer memory 123, and the memory controller 121 may release the first buffer memory 121a such that other write data from the host 110 is stored in the first buffer memory 121a. That is, since the first buffer memory 121a is released before the programming operation of the non-volatile memory devices 122 is successfully completed, the memory controller 121 may continue to receive other write data before the programming operation of the non-volatile memory devices 122 is successfully completed. This may mean that a write delay due to limited buffer capacity is prevented.In one embodiment, additional write data may be written to a specific area of the first buffer memory 121a even before the operating state of the first buffer memory 121a is released. For example, when the write data WRD is stored in a first area of the first buffer memory 121a, while writing additional write data to the first area of the first buffer memory 121a is prohibited before the operating state of the first area of the first buffer memory 121a is released, writing additional write data to a second area of the first buffer memory 121a is performed even before the operating state of the first area of the first buffer memory 121a is released.
[0050] The memory controller 121 may then receive information about a programming success from the non-volatile memory devices 122 (6). The memory controller 121 may release the second buffer memory 123 (6) in response to receiving information about the programming success. At the fourth time t4 of Fig. 5, for example, the memory controller 121 may receive information about the programming success from the non-volatile memory devices 122 and, in response to the received information, release the second buffer memory 123. In one embodiment, the released area of the second buffer memory 123 may be allocated to an area for storing (or backing up, recording, etc.) other write data.
[0051] A method for recovering write data in the event of a programming failure will be described next with reference to Fig. 6. For a brief description, the operation and configuration described with reference to Fig. 4 and Fig. 5 were described, not in Fig. 6 is repeated. That is, it is assumed that the memory controller 121 of Fig. 6 the operations (1) to 4, which are described with reference to Fig. 4 and Fig. 5. In the embodiment of Fig. 6, in other words, it is assumed that the first buffer memory 121a is in a state where the write data WRD is not stored therein, and the second buffer memory 123 is in a state where the write data WRD is stored therein.
[0052] Referring to Fig. 6, the memory controller 121 may receive information about a programming failure from the non-volatile memory devices 122 (5). As described above, the information about the programming failure received from the non-volatile memory devices 122 indicates that the write data WRD was not normally stored in the non-volatile memory devices 122. In this case, there may be a need to additionally perform a programming operation for the write data WRD.
[0053] The memory controller 121 can, in response to the received information (i.e., the information about the programming failure), copy the write data WRD from the second buffer memory 123 to the first buffer memory 121a (i.e., restore the write data WRD). As described above, for example, the first buffer memory 121a is in a state where the write data WRD is not stored therein, and the second buffer memory 123 is in a state where the write data WRD is stored therein. Accordingly, the memory controller 121 can restore the write data WRD by copying the write data WRD from the second buffer memory 123 to the first buffer memory 121a.
[0054] The memory controller 121 may then transfer the write data WRD of the first buffer memory 121a to the non-volatile memory devices 122 (⑦). The memory controller 121 may release the first buffer memory 121a after transferring the write data WRD to the non-volatile memory devices 122 (⑧).
[0055] In a second embodiment, the second buffer memory 123 may be enabled after a programming operation of the non-volatile memory devices 122 has been successfully performed. In other words, the write data WRD stored in the second buffer memory 123 may be retained until the write data WRD has been completely programmed into the non-volatile memory devices 122.
[0056] As described above, even if the first buffer memory 121a used as a write buffer is released before programming completion of the non-volatile memory devices 122, the memory controller 121 can ensure the reliability of the data by using the write data WRD stored in the second buffer memory 123.
[0057] Although it is not in Fig. 6, in one embodiment, in the case where the programming operation fails, the memory controller 121 may be configured to directly transfer the write data WRD from the second buffer memory 123 to the non-volatile memory devices 122. In other words, in the case where a programming operation fails, the memory controller 121 may be configured to omit copying the write data WRD to the first buffer memory 121a and to directly deliver the write data WRD to the non-volatile memory devices 122 from the second buffer memory 123.
[0058] In one embodiment, after the first buffer memory 121a has been released, the program miss may occur while new write data from the host 110 is being stored in the first buffer memory 121a. In this case, the memory controller 121 may be configured to directly transfer the write data WRD corresponding to the program miss from the second buffer memory 123 to the non-volatile memory devices 122, such that the write data WRD corresponding to the program miss is programmed first. During the operation described above, new write data may be held in the first buffer memory 121a, or the first buffer memory 121a may not be released.The memory controller 121 may alternatively perform a programming operation on the write data WRD stored in the second buffer memory 123 after first performing a programming operation on the new write data. However, embodiments of the inventive concept need not be limited thereto. For example, write data may be programmed using various schemes without departing from the scope and spirit of the inventive concept.
[0059] Fig. 7 and Fig. 8 are views showing a structure of the storage device 120 of Fig. 1 and a structure of the second buffer memory 123 of Fig. 1. With reference to Fig. 1, Fig. 7 and Fig. 8, the storage device 120 may include the memory controller 121 and the plurality of non-volatile memory devices (NVMs) 122. The memory controller 121 and the non-volatile memory devices 122 are described with reference to Fig. 1 to 6, and a detailed description of them will not be repeated here.
[0060] Referring to Fig. 7 and Fig. 8, the memory controller 121 may communicate with the non-volatile memory devices 122 through a plurality of channels CH1 to CHm, respectively. The non-volatile memory devices 122 may be distributed among a plurality of ways WAY1 to WAYn. For example, the non-volatile memory devices connected to the first channel CH1 may be included in the first to n-th ways WAY1 to WAYn, respectively. Likewise, the non-volatile memory devices connected to each of the second to m-th channels CH2 to CHm may be included in the first to n-th ways WAY1 to WAYn, respectively.
[0061] Alternatively, non-volatile memory devices included in the first way WAY1 may be connected to the plurality of channels CH1 to CHm, respectively, and non-volatile memory devices included in the ways WAY2 to WAYn may be further connected to the plurality of channels CH1 to CHm, respectively.
[0062] That is, the non-volatile memory devices 122 may each be implemented with a separate die, chip, assembly, or module and may be distinguishable for each channel or for each way.
[0063] The second buffer memory 123 can be used as a storage area with respect to each of the non-volatile memory devices 122. As in Fig. 8, for example, the second buffer memory 123 may be divided into a plurality of areas, each corresponding to the plurality of non-volatile memory devices 122. In this case, each area may be distinguishable for each channel or path of non-volatile memory devices 122 and may be configured to store write data to be stored in the corresponding non-volatile memory devices 122. The storage areas shown in Fig. 8 can be physical or logical areas.
[0064] Fig. 9 is a block diagram illustrating one embodiment of a user system 200. For the sake of brevity, a description given with reference to the preceding elements will not be repeated here. Referring to Fig. 9, the user system 200 may include a host 210 and a storage device 220. The storage device 220 may include a memory controller 221 and non-volatile memory devices 222. The memory controller 221 may include a first buffer memory 221a.
[0065] In the embodiment of Fig. 1, the storage device 120 comprises the second buffer memory 123. In the embodiment of Fig. 9, however, the host 210 includes a second buffer memory 211. In one embodiment, the storage device 220 may use the second buffer memory 211 included by the host 210 as a means for recovering write data when a programming operation fails. In one embodiment, the second buffer memory 211 may be a host buffer memory (HBM). That is, the storage device 220 may use the second buffer memory 211 (i.e., the host buffer memory) included by the host 210.
[0066] Fig. 10 to 12 are views for describing an operation of the memory controller 221 of Fig. 9. For a brief description, a detailed description of elements not necessary to describe the operation of the memory controller 221 and a description given with reference to the preceding elements will not be repeated here.
[0067] Referring to Fig. 10, the host 210 may first transfer the write data WRD to the first buffer memory 221a (1). After the write data WRD has been stored in the first buffer memory 221a, the memory controller 221 may transfer a WR completion to the host 210 (2). The operations 1 and 2 are similar to those described with reference to Fig. 4, and a description of them will not be repeated here.
[0068] The memory controller 221 can then transfer the write data WRD of the first buffer memory 221a to the non-volatile memory devices 222 and to the second buffer memory 211 (3). The operation (the write data transfer) 3 shown in Fig. 10 may differ from the operation ③ of Fig. 4. In the operation process (the write data transfer) ③ of Fig. 4, for example, the buffer manager 121d (referring to Fig. 2) transfer the write data WRD to the second buffer memory 123. However, since the second buffer memory 211 of Fig. 10 is the host buffer memory HBM, which the host 210 has in itself, can be used in the operation process (in the write data transfer) ③ of Fig. 10 the write data WRD through the host interface layer 121e (referring to Fig. 2) to the second buffer memory 211.
[0069] The memory controller 221 may then release the first buffer 221a (4), receive information about programming success from the non-volatile memory devices 222 (5), and release the second buffer 211 in response to the received information (6). In one embodiment, the release of the second buffer 211 may be performed by the host interface layer 121e.
[0070] Referring to Fig. 11, the host 210 may next transfer the write data WRD to the first buffer memory 221a (①). In this case, in contrast to the embodiment of Fig. 10, the host 210 transfers the write data WRD to the second buffer memory 211. In other words, the host 210 may store the write data WRD in the second buffer memory 211 while transferring the write data WRD to the first buffer memory 221a. In one embodiment, the host 210 may provide the memory controller 221 with information about a pointer to an address or location of the second buffer memory 211 where the write data WRD is stored.
[0071] After the write data WRD is stored in the first buffer memory 221a, the memory controller 221 may transmit the WR completion to the host 210 (2). The memory controller 221 may then transmit the write data WRD of the first buffer memory 221a to the non-volatile memory devices 222 (3). Since the write data WRD is stored in the second buffer memory 211 by the host 210, the memory controller 221 does not need to transmit the write data WRD to the second buffer memory 211.
[0072] The memory controller 221 may then perform operations 4, 5, and 6. The operations 4, 5, and 6 were described with reference to Fig. 10, and a description thereof will not be repeated here. In one embodiment, the memory controller 221 may enable the second buffer memory 211 based on the pointer information associated with the write data WRD.
[0073] As described above, the storage device 220 may use the host buffer memory HBM as a buffer memory for recovering write data when a programming operation fails. In one embodiment, the memory controller 221 of the storage device 220 may access the host buffer memory HBM through a host interface layer having a predefined interface or protocol.
[0074] In the case of Fig. 10, the write data WRD may be transferred by the memory controller 221 to the second buffer memory 211 while being transferred to the non-volatile memory devices 222. For this reason, a unit of the write data WRD to be transferred in the second buffer memory 211 may be a programming unit (for example, a unit of PGM-D, for example, 96 kB). In the embodiment described with reference to Fig. In contrast, in the embodiment described in Figure 11, the write data WRD may be transferred by the host 210 to the second buffer memory 211 while being transferred to the first buffer memory 221a. For this reason, a unit of the write data WRD to be transferred in the second buffer memory 211 may be a write data unit (i.e., a data transfer unit between the host 210 and the memory controller 221, for example, 4 kB).
[0075] In the following, a data recovery method of the storage device 220 when a programming operation fails will be described with reference to Fig. 12. For a brief description, it is assumed that the host 210 and the memory controller 221 of Fig. 12 are in a state in which the operations ①, ②, ③ and ④ of Fig. 10 or Fig. 11. That is, the first buffer memory 221a of the memory controller 221 may be in a state where the write data WRD is not stored therein, and the second buffer memory 211 of the host 210 may be in a state where the write data WRD is stored therein.
[0076] Referring to Fig. 12, the memory controller 221 may receive information about a programming miss from the non-volatile memory devices 222 (6). The memory controller 210 may, in response to the received information, copy the write data WRD from the second buffer memory of the host 210 to the first buffer memory 221a (or may restore the write data WRD) (6). In one embodiment, the memory controller 221 may copy the write data WRD to the first buffer memory 221a by accessing the second buffer memory 211 of the host 210 based on information about an area in which the write data WRD corresponding to the programming miss is stored. In one embodiment, the operation 6 may be performed by a host interface layer.In one embodiment, in the case where the write data WRD is stored in the second buffer memory 211 by the host 210, the memory controller 221 may access the second buffer memory 211 based on pointer information received from the host 210, as described above.
[0077] The memory controller 221 may then transfer the write data WRD of the first buffer memory 221a to the non-volatile memory devices 222 (⑦) and may release the first buffer memory 221a (⑧).
[0078] As described above, the storage device 220 according to an embodiment of the inventive concept can release a write buffer and transmit a write completion before a successful program completion, thereby preventing a reduction in performance due to limited buffer capacity or write delay. The storage device 220 according to an embodiment of the inventive concept can further use the second buffer memory 211 (i.e., a host buffer memory) as a means for recovering write data when a program operation fails, and the reliability of the storage device 220 can thus be improved.
[0079] Fig. 13 is a block diagram illustrating one embodiment of a user system 300. For the sake of brevity, a description given in detail with reference to the preceding elements will not be repeated here. Referring to Fig. 13, a user system 300 may include a host 310 and a storage device 320. The storage device 320 may include a memory controller 321 and non-volatile memory devices 322.
[0080] The memory controller 321 may include a first buffer 321a, a second buffer 321b, and a parity generator 321c. The first buffer 321a may be used as a write buffer or a read buffer. The first buffer 321a was described with reference to Fig. 1 to 12, and a detailed description of the same will not be repeated here.
[0081] The second buffer memory 321b may be configured to store a parity of write data to be stored in the non-volatile memory devices 322. In the embodiments described above with reference to Fig. 1 to 12, a second buffer memory may be configured to store the write data WRD itself. In the embodiment of Fig. 13, however, the second buffer memory 321b may be configured to store the parity of write data, not the write data itself. If a programming operation fails, the memory controller 321 may recover write data corresponding to the programming failure based on the parity stored in the second buffer memory 321b and the corresponding data stored in the non-volatile memory devices 322.
[0082] In one embodiment, the second buffer memory 321b may be an SRAM that the memory controller 321 has within it. The second buffer memory 321b may be physically separate from the first buffer memory 321a. The same memory may alternatively have the first and second buffer memories 321a and 321b within it, and they may be logically distinguishable from each other. In one embodiment, although not described in Fig. 13, the second buffer memory 321b may be a separate memory (for example, a DRAM) provided outside the memory controller 321.
[0083] Parity generator 321c may be configured to generate parity of one or more pieces of write data. Parity generator 321c may generate parity of one or more pieces of write data, for example, by performing a bitwise XOR operation on a default parity and one or more pieces of write data. In one embodiment, parity generator 321c may generate parity of one or more pieces of data in an on-the-fly manner.
[0084] In one embodiment, the default parity may comprise all-zero bits, the length of which is equal to that of a write data unit or a programming unit to be stored in the non-volatile memory devices 322, or may comprise data bits of a specific pattern. In one embodiment, the bitwise XOR operation for generating parity may be merely an example, and operation of the parity generator 321c may not be limited thereto.
[0085] As described above, by transmitting a write completion and releasing a write buffer before the write data is completely programmed, the storage device 320 can prevent a reduction in performance. The storage device 320 can further generate parity of one or more pieces of write data; if a programming operation fails, the storage device 320 can recover write data corresponding to the programming failure based on the generated parity and the corresponding data. The operation of the storage device 320 will be described more fully with reference to the following drawings.
[0086] Fig. 14 is a flowchart illustrating an operation of the memory controller 321 of Fig. 13. With reference to Fig. 13 and Fig. 14, the memory controller 321 may perform an operation S210 and an operation S220. The operation S210 and the operation S220 are similar to the operation S110 and the operation S120 of Fig. 3A, and a detailed description of it will not be repeated here.
[0087] In operation 230, the memory controller 321 may transfer the write data WRD to the non-volatile memory devices 322; the memory controller 321 may generate the parity PRT based on the write data WRD and may store the parity PRT in the second buffer memory 321b. For example, as described above, the memory controller 321 may transfer the write data WRD to the non-volatile memory devices 322 such that the write data WRD is stored in the non-volatile memory devices 322. The memory controller 321 may additionally generate the parity PRT based on the write data WRD and may store the parity PRT in the second buffer memory 321b.
[0088] As a detailed example, the memory controller 321 may read the parity PRT stored in the second buffer memory 321b and generate a new parity by performing a bitwise XOR operation on the read parity PRT and the write data WRD. In one embodiment, the parity PRT stored in the second buffer memory 321b may be a default parity or a parity of previous write data. That is, it is possible to restore the write data WRD by performing a bitwise XOR operation on the previous write data and a new parity. The new parity PRT thus generated is stored in the second buffer memory 321b. In one embodiment, the previous parity stored in the second buffer memory 321b may be updated to the new parity PRT.
[0089] The memory controller 321 may then perform an operation S240 to an operation S260. The operation S240 to the operation S260 may be similar to the operation S140 to the operation S160 of Fig. 3A, and a detailed description of it will not be repeated here.
[0090] If the determination result of operation S250 indicates a programming failure, in operation S270, the memory controller 321 may restore the write data WRD based on the parity PRT stored in the second buffer memory 321b. As described above, for example, the parity PRT stored in the second buffer memory 321b may be a parity associated with previous write data and the current write data WRD. That is, the current write data WRD may be restored by performing the bitwise XOR operation on the previous write data and the parity PRT. In one embodiment, to perform operation S250, the memory controller 321 may read one or more pieces of previous write data from the non-volatile memory devices 322.
[0091] After the write data WRD is retrieved, the memory controller 321 may perform the operation S230 to the operation S250.
[0092] In one embodiment, after the write data WRD is retrieved, generation of the parity PRT may be omitted in operation S230.
[0093] As described above, the storage device 320 according to an embodiment of the inventive concept may release a write buffer and transmit a write completion before a successful programming completion of the non-volatile memory devices 322, thereby preventing a reduction in performance. The storage device 320 according to an embodiment of the inventive concept may further ensure the reliability of write data by generating parity of the write data and maintaining the parity until a programming operation of the non-volatile memory devices 322 is successfully completed.
[0094] Fig. 15 is a view for describing an operation of the memory controller 321 of Fig. 13. For a brief description, elements that are not necessary to describe an operation of the memory controller 321 will not be repeated here. An operation of the memory controller 321 when a programming operation is successful will be described with reference to Fig. 15 are described.
[0095] Operation of the memory controller 321 will be further described based on write data WRD. However, this serves to describe embodiments succinctly and clearly, and embodiments of the inventive concept need not be limited thereto. For example, the memory controller 321 may be configured to transfer pieces of write data to the non-volatile memory devices 322 through a plurality of channels in an interleaved manner and to update the parity whenever each of the pieces of write data is transferred to the non-volatile memory devices 322. That is, the memory controller 321 may be configured to generate, update, and manage a single parity with respect to pieces of write data.
[0096] Referring to Fig. 15, the host 310 and the memory controller 321 can perform operations 1 and 2. The operations 1 and 2 are described with reference to Fig. 4, and a description thereof will not be repeated here. The memory controller 321 may then transfer the write data WRD to the non-volatile memory devices 322 and update the parity PRT (3).
[0097] For example, the memory controller 321 may transfer the write data WRD to the non-volatile memory devices 322. The memory controller 321 may additionally read the parity PRT from the second buffer memory 321b (3') and update the parity PRT of the second buffer memory 321b to a new parity generated based on the read parity PRT and the write data WRD (3"). In one embodiment, the previous parity PRT stored in the second buffer memory 321b may be the default parity or the parity of previous write data. In one embodiment, to ensure the reliability of the write data WRD, transferring the write data WRD, reading the parity PRT (3'), and updating the parity PRT (3") may be performed as one atomic operation.
[0098] After the transfer of the write data WRD, the reading of the parity PRT (③'), and the updating of the parity PRT (③'') are completed, the memory controller 321 may release the first buffer memory 321a.
[0099] The memory controller 321 may then receive information about programming success from the non-volatile memory devices 322 (5). The memory controller 321 may enable the second buffer memory 321b based on the received information. In one embodiment, enabling the second buffer memory 321b may include changing the corresponding parity stored in the second buffer memory 321b to the default parity. The default parity stored in the second buffer memory 321b may be used as a default parity of new write data.
[0100] In one embodiment, although not clearly shown in Fig. 15, after pieces of write data have been successfully programmed, the second buffer memory 321b may be released, or the parity stored in the second buffer memory 321b may be changed to the default parity. For example, the memory controller 321 may generate a single parity associated with pieces of write data by repeating the operations described above (transferring the write data WRD, reading the parity PRT (③'), and updating the parity PRT (③''). In this case, the memory controller 321 may be configured to release the second buffer memory 321b after all pieces of write data have been successfully programmed.In one embodiment, in the case where at least one of program operations of the pieces of write data fails, the memory controller 321 may recover write data corresponding to the programming failure based on the parity PRT and the successfully programmed write data.
[0101] Fig. 16 is a timing diagram for describing how write data is transmitted to the non-volatile memory devices through a plurality of channels. For brevity of illustration and convenience of description, a configuration for receiving write data from the host 310 and a programming operation of the non-volatile memory devices 322 are shown in Fig. 16, and only a configuration for transferring pieces of write data WRD1 to WRDn through the first to fourth channels CH1 to CH4 in the memory controller 321 is shown in Fig. 16. It is further assumed that the memory controller 321 generates a single parity PRT based on all of the first to n-th write data WRD1 to WRDn.
[0102] However, embodiments of the inventive concept may not be limited thereto. For example, storage device 320 may communicate with additional non-volatile memory devices through additional channels. Memory controller 321 may further update the parity PRT whenever all of the write data WRD1 to WRDn are transmitted through the first to fourth channels CH1 to CH4.
[0103] Referring to Fig. 13 and Fig. 15, the memory controller 321 may transmit the write data WRD1 to WRDn through the first to fourth channels CH1 to CH4 in an interleaved manner to the non-volatile memory devices 322. In one embodiment, the memory controller 321 and the non-volatile memory devices 322 may be configured with the structure (i.e., a plurality of channels and a plurality of ways) described with reference to Fig. 7 described above.
[0104] The memory controller 321 may generate the corresponding parity PRT whenever all of the write data WDR1 to WRDn are transferred to the non-volatile memory devices 322, and may release the first buffer memory 321a (in detail, an area in which the corresponding write data is stored) after the write data WRD1 to WRDn are transferred to the non-volatile memory devices 322.
[0105] For example, the memory controller 321 may transmit the first write data WRD1 through the first channel CH1 to the corresponding one of the non-volatile memory devices 322. The memory controller 321 may additionally generate the parity PRT based on the first write data WRD1 and the default parity.
[0106] The memory controller 321 may then transmit the write data WRD2 to WRDn through the first to fourth channels CH1 to CH4 in the interleaved manner to the non-volatile memory devices 322, and may update the parity PRT based on all the write data WRD2 to WRDn.
[0107] The memory controller 321 may release the first buffer memory 321a (in detail, an area in which the corresponding write data is stored) at a time when all of the write data WRD1 to WRDn have been completely transferred (or a time when the parity is updated based on all of the write data WRD1 to WRDn). That is, the first buffer memory 321a may be released at times t1 to tn, respectively, before all of the write data WRD1 to WRDn have been successfully completely programmed.
[0108] The second buffer memory 321b may be enabled after all of the first through n-th write data WRD1 through WRDn have been successfully programmed. In one embodiment, for the write data WRD1 through WRDn, "n" may correspond to "the number of channels" × "the number of ways" in the storage device 320. Alternatively, "n" may be a value defined in advance to ensure the reliability of the write data and optimize write performance.
[0109] As described above, by transmitting write completion and releasing a write buffer before the write data WRD1 to WRDn has been fully programmed, the memory controller 321 can prevent performance degradation due to a limited capacity of a write buffer and write delay. The memory controller 321 can further ensure the reliability of the write data WRD1 to WRDn by generating the parity PRT associated with the write data WRD1 to WRDn and maintaining the parity PRT until all the write data WRD1 to WRDn have been fully programmed.
[0110] Fig. 17 is a view for describing a method in which the memory controller 321 recovers write data in a program failure situation. For a brief description, elements not necessary for describing the method in which the memory controller 321 recovers write data in a program failure situation will not be repeated here.
[0111] In the embodiment of Fig. 17, it is further assumed that the memory controller 321 performs the operations ①, ②, ③ and ④ of Fig. 15 on the write data WRD1 to WRDn repeatedly. That is, it is assumed that the write data WRD1 to WRDn have been transferred to the non-volatile memory devices 322, the first buffer memory 321a has been enabled, and the second buffer memory 321 has stored the parity PRT associated with the write data WRD1 to WRDn. Further, for brevity of illustration and convenience of description, the non-volatile memory devices 322 are illustrated as one block, and it is assumed that a programming operation of the third write data WRD3 fails.
[0112] However, embodiments of the inventive concept need not be limited thereto. For example, the non-volatile memory devices 322 may each be implemented with different devices, may be partitioned in a plurality of ways, and may communicate with the memory controller 321 through a plurality of channels. Furthermore, the write data WRD1 to WRDn may each be stored in different non-volatile memory devices.
[0113] Referring to Fig. 16 and Fig. 17, as described above, the memory controller 321 may transfer the write data WRD1 to WRDn to the non-volatile memory devices 322 in an interleaved manner. In this case, the memory controller 321 may generate the parity PRT associated with the write data WRD1 to WRDn and may store the generated parity PRT in the second buffer memory 321b.
[0114] The non-volatile memory devices 322 may perform program operations on the received write data WRD1 to WRDn. According to the above assumption, the programming operation of the third write data WRD3 may fail. The memory controller 321 may receive information indicating that the programming operation of the third write data WRD3 fails. ⑤ Although Fig. 17, the memory controller 321 may receive information about programming success from all of the remaining write data WRD1, WRD2, and WRD4 to WRDn.
[0115] In response to the received information, the memory controller 321 may read the remaining write data WRD1, WRD2, and WRD4 to WRDn, except for the write data WRD3 corresponding to the programming failure, from the non-volatile memory devices 322. 6 In one embodiment, reading the write data from the non-volatile memory devices 322 may be performed after the remaining write data WRD1, WRD2, and WRD4 to WRDn, except for the write data WRD3 corresponding to the programming failure, have been successfully fully programmed.
[0116] The memory controller 321 can read the parity PRT stored in the second buffer memory 321b (6') and can restore the write data (i.e., the third data WRD3) corresponding to the program miss based on the parity PRT and the read write data WRD1, WRD2, and WRD4 to WRDn ((7)). For example, as described above, the parity generator 321c can restore the third write data WRD3 by performing a bitwise XOR operation on the parity PRT and the write data WRD1, WRD2, and WRD4 to WRDn. The restored third write data WRD3 may be stored in the first buffer memory 321a, and the memory controller 321 may transfer the restored third write data WRD3 to the non-volatile memory devices 322 such that the restored third write data WRD3 is stored in the non-volatile memory devices 322.
[0117] An embodiment of a method in which the data is restored when a programming operation of any of the write data WRD 1 to WRDn fails will be described with reference to Fig. 17. However, embodiments of the inventive concept need not be limited thereto. For example, pieces of write data may be restored in a state where program operations of pieces of write data fail by increasing the number of parities. In embodiments, the plurality of parities may be stored in the second buffer memory 321b, or some of the plurality of parities may be stored in the non-volatile memory devices 322.
[0118] As described above, according to an embodiment of the inventive concept, the storage device 320 can prevent write delay by performing write completion transfer and releasing a write buffer before pieces of write data are successfully fully programmed. Furthermore, in the case where programming operations associated with some pieces of write data fail, the storage device 320 can recover write data corresponding to a programming failure based on the remaining write data and parity. Accordingly, a storage device with improved performance and reliability is provided.
[0119] Fig. 18 is a timing diagram for describing one embodiment of a data transfer unit. In one embodiment, in order to clearly describe the scope and spirit of the inventive concept, embodiments have been described above assuming that a data transfer unit between a host 110, 210, or 310 and a memory controller 121, 221, or 321 is equal to a data transfer unit between a memory controller 121, 221, or 321 and non-volatile memory devices 122, 222, or 322. However, embodiments of the inventive concept need not be limited thereto.
[0120] A data transfer unit between a host 110, 210, or 310 and a memory controller 121, 221, or 321 may, for example, be determined depending on a predefined interface or a predefined protocol between a host 110, 210, or 310 and a memory controller 121, 221, or 321 or a file system of a host 110, 210, or 310. A data transfer unit between a memory controller 121, 221, or 321 and non-volatile memory devices 122, 222, or 322 may, for example, be determined depending on a predefined interface or a predefined protocol between the memory controller 121, 221, or 321 and the non-volatile memory devices 122, 222, or 322 or operating characteristics of the non-volatile memory devices 122, 222, or 322. This means that the data transfer units can differ from one another.
[0121] For example, the data transfer unit between a host 110, 210, or 310 and a memory controller 121, 221, or 321 may correspond to a sector unit (e.g., 4 kB), and the data transfer unit between a memory controller 121, 221, or 321 and non-volatile storage devices 122, 222, or 322 may correspond to a programming unit or a page unit (e.g., 96 kB) of non-volatile storage devices 122, 222, or 322. That is, a memory controller 121, 221, or 321 may receive pieces of write data from a host 110, 210, or 310; When the pieces of data constitute the programming unit, a memory controller 121, 221, or 321 may transfer write data of the programming unit to non-volatile memory devices 122, 222, or 322.
[0122] As a detailed example, it is assumed that pieces of write data WRD1 to WRDk constitute data of a programming unit. As in Fig. As shown in Figure 18, the pieces of write data WRD1 to WRDk may be transferred from a host 110, 210, or 310 to a first buffer memory 121a, 221a, or 321a. In this case, a memory controller 121, 221, or 321 may transfer the WR completion to a host 110, 210, or 310 whenever all of the write data WRD1 to WRDk have been transferred to a first buffer memory 121a, 221a, or 321a.
[0123] A memory controller 121, 221, or 321 may then transfer PGM-D data of a programming unit to the non-volatile memory devices 122, 222, or 322. In this case, as in the embodiments described above, the memory controller 121, 221, or 321 may transfer the PGM-D data of the programming unit to the second buffer memory 123 and 211 or may generate the corresponding parity based on the PGM-D data of the programming unit.
[0124] After the PGM-D data has been transferred to the programming unit, a memory controller 121, 221, or 321 may enable a first buffer memory 121a, 221a, or 321a. After programming into the non-volatile memory devices 122, 222, or 322 has been successfully completed, a memory controller 121, 221, or 321 may enable a second buffer memory 123 or 211.
[0125] As described above, a storage device according to an embodiment of the inventive concept can transmit a write completion to a host whenever the write data received from the host has been stored in a first buffer memory, and can release the first buffer memory whenever data of a programming unit is transferred to the non-volatile memory devices. That is, the storage device can prevent write delay by transmitting a write completion and releasing a write buffer before the write data has been successfully programmed entirely.Data reliability may be further ensured by maintaining a variety of means (e.g., data stored in a buffer memory of a storage device, write data stored in an HBM of a host, or parity associated with write data) for recovering write data until the write data has been successfully programmed in its entirety.
[0126] Fig. 19 is a block diagram illustrating a configuration of one embodiment of a memory controller 421. For the sake of brevity, a description already given in detail above with reference to the preceding elements will not be repeated here.
[0127] Referring to Fig. 19, the memory controller 421 may include a first buffer memory 421a, a processor 421b, a ROM 421c, a buffer manager 421d, a host interface layer 421e, a flash interface layer 421f, a first (host) direct memory access (HDMA) engine 421g, and a second (flash) direct memory access (FDMA) engine 421h. The first buffer memory 421a, the processor 421b, the ROM 421c, the buffer manager 421d, the host interface layer 421e, and the flash interface layer 421f were described with reference to Fig. 2, and a description of it will not be repeated here.
[0128] The memory controller 421 from Fig. 19 may further include HDMA engine 421g and FDMA engine 421h. HDMA engine 421g may be a hardware device that controls a direct memory access (DMA) operation between a host 410 and a first buffer memory 421a without intervention from processor 421b. FDMA engine 421h may be a hardware device that controls a DMA operation between the first buffer memory 421a and non-volatile memory devices 422 and a DMA operation between the first buffer memory 421a and a second buffer memory 423.
[0129] For example, a storage device may operate in a DMA mode to improve a data transfer rate. The DMA mode may refer to an operation mode in which data is transferred under control of the DMA engines 421g and 421h without intervention by the processor 421b or a core included in the memory controller 421. That is, since there is no need for control or processing by the processor 421b or the core while the data is being transferred, the data transfer rate can be improved.
[0130] In the DMA mode of operation, the HDMA engine 421g may control or manage data transfer between the host 410 and the first buffer memory 421a, and the FDMA engine 421h may control or manage data transfer between the first buffer memory 421a and the non-volatile memory devices 422 and data transfer between the first buffer memory 421a and the second buffer memory 423.
[0131] In one embodiment, a write data transfer between a host and a first buffer memory described with reference to Fig. 1 to 18, in the DMA mode. In this case, an HDMA operation associated with the write data transfer can be performed by an HDMA engine 421g without intervention of the processor 421b. A data transfer between the first buffer memory and the non-volatile memory devices and between the first buffer memory and the second buffer memory described with reference to Fig. 1 to 18 may also be performed in the DMA mode. In this case, an FDMA operation associated with the data transfer may be performed by the FDMA engine 421h without intervention by the processor 421b.
[0132] In one embodiment, although not in Fig. 19, the memory controller 421 may further include a separate DMA engine that controls or manages a DMA operation between the first buffer memory 421a and the second buffer memory 423.
[0133] The memory controller 421 according to an embodiment of the inventive concept may transmit a WR completion to the host 410 after the HDMA operation of receiving write data from the host 410 is completed, and may release the first buffer memory 421a after the FDMA operation of transferring data to the nonvolatile memory devices 422 and the second buffer memory 423 is completed. Furthermore, by releasing the second buffer memory 423 after a programming operation of the nonvolatile memory devices 422 is successfully completed, data can be normally restored even if a programming operation fails. Accordingly, a storage device with improved performance and efficiency can be provided.
[0134] Fig. 20 is a block diagram illustrating one embodiment of a user system having a storage device. Referring to Fig. 20, a user system 2000 may include a host 2100 and a storage device 2200. The host 2100 may store data in the storage device 2200 or read data stored in the storage device 2200,
[0135] The storage device 2200 may include a controller 2210, a plurality of non-volatile memory devices 2220, and a buffer memory 2230. The controller 2210 may include a processor 2211, a data domain manager circuit 2212, a write manager circuit 2213, a read manager circuit 2214, a host interface layer 2215, and a memory interface layer 2216.
[0136] The processor 2211 may include at least one processor core. The processor 2211 may execute software (SW) and / or firmware (FW) program code depending on an operation of the processor core.
[0137] The data domain manager circuit 2212 may be configured to manage a first-type task associated with the storage device 2200. For example, the data domain manager circuit 2212 may obtain information about a state of at least one of the non-volatile memory devices 2220, write data, and read data with respect to performing the first-type task. The write manager circuit 2213 and the read manager circuit 2214 may perform the first-type task to provide a variety of state information to the data domain manager circuit 2212. The data domain manager circuit 2212 may monitor states associated with operations of the controller 2210 or the non-volatile memory devices 2220 based on the obtained information.
[0138] The write manager circuit 2213 may manage the task of the first type (in particular, a write task). For example, the write manager circuit 2213 may manage a write operation for storing write data from the host 2100 to the non-volatile storage devices 2220. In one embodiment, the write manager circuit 2213 may be placed on a write path for transferring write data from the host 2100 to the non-volatile storage devices 2220.
[0139] The read manager circuit 2214 may manage a task of the first type (in particular, a read task). For example, the read manager circuit 2214 may manage a read operation for outputting read data to the exterior (e.g., the host 2100) of the controller 2210. In one embodiment, the read manager circuit 2214 may be placed on a read path for transferring read data output from the non-volatile memory devices 2220 to the exterior of the controller 2210.
[0140] In one embodiment, write manager circuit 2213 may include a buffer memory, and read manager circuit 2214 may include a separate buffer memory. The buffer(s) may be used as a write buffer or a read buffer of storage device 2200.
[0141] In one embodiment, the data domain manager circuit 2212, the write manager circuit 2213, and the read manager circuit 2214 may be implemented in hardware and may be configured to manage the first type of task. In one embodiment, the first type of task may include simple tasks, such as a data write operation and a data read operation. Alternatively, the first type of task may include a task associated with a first processing unit (e.g., a page unit).
[0142] In one embodiment, a second-type task, different from the first-type task, may be processed by software (SW) and / or firmware (FW) controlled by the processor 2211. In one embodiment, the second-type task may include maintenance tasks, such as a waste data collection operation, a wear level determination operation, a read regeneration operation, a read refresh operation, and an error correction operation, associated with the non-volatile memory devices 2220. In one embodiment, the second-type task may include a task associated with a second processing unit (e.g., a memory block unit) that is different from the first processing unit (e.g., a page unit).
[0143] In one embodiment, the first type of tasks (i.e., simple tasks), such as a data read operation and a data write operation, may be performed by a hardware circuit, and the maintenance operation may be processed by software (SW) and / or firmware (FW) executed by the processor 2211, thereby improving the overall performance of the storage device 2200.
[0144] In one embodiment, the write manager circuit 2213 and the read manager circuit 2214 may be configured based on the operating methods described with reference to Fig.1 to 19. For example, the write manager circuit 2213 may be configured to transmit a write completion to the host 2100 after receiving write data from the host 2100 and to release an internal buffer after transmitting the write data to the non-volatile storage devices 2220. The write manager circuit 2213 may further ensure the reliability of write data by transmitting the write data to the buffer memory 2230 (or an HBM of the host 2100) or by generating parity while transmitting the write data to the non-volatile storage devices 2220.
[0145] The controller 2210 may communicate with the host 2100 through a host interface layer 2215. The host interface layer 2215 may, for example, convert a command and data received from the host 2100 into a format that can be processed in the controller 2210, and vice versa. The controller 2210 may communicate with the non-volatile storage devices 2220 through the memory interface layer 2216. The memory interface layer 2216 may, for example, convert write data and relevant data into a format that can be identified in the non-volatile storage devices 2220, and vice versa.
[0146] In one embodiment, the host interface layer 2215 and the memory interface layer 2216 may include a packer for converting data or information into a format used in the controller 2210 and an unpacker (or unpacketizer).
[0147] A storage device according to an embodiment of the inventive concept can prevent a reduction in performance due to a limited capacity of a write buffer and a write delay by transmitting a write completion and releasing a write buffer before the write data is successfully fully programmed, and can ensure the reliability of the write data by maintaining the write data in a separate buffer until the write data is successfully fully programmed and restoring the write data when a programming operation fails.
[0148] Accordingly, it may be possible to provide an operating method of a memory controller having improved reliability and performance and an operating method of a user device.
[0149] The various operations of the methods described above may be performed by any suitable means capable of performing operations, such as various hardware and / or software components, circuits, and / or modules.
[0150] Software used in the disclosed systems and / or methods may comprise an ordered collection of executable instructions for implementing logical functions and may be embodied in a "processor-readable medium" for use by or in connection with an instruction execution system, an instruction execution device, or an instruction execution apparatus, for example, a single- or multi-core processor or a processor-containing system.
[0151] The blocks or steps of a method or algorithm and functions described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. When implemented in software, instructions or code for performing the functions may be stored in or carried with a tangible, non-transitory medium. A software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Claims
[1] System (100; 200; 2000) with: a non-volatile memory (122; 222; 422; 2220); a memory controller (121; 221; 421; 2210) configured to control the non-volatile memory (122; 222; 422; 2220), wherein the memory controller (121; 221; 421; 2210) comprises a first buffer memory (121a; 221a; 421a) for temporarily storing write data (WRD) received from a host device (110; 210; 410; 2100) and to be written to the non-volatile memory (122; 222; 422; 2220); and a second buffer memory (123; 211; 423) having a lower operating speed and a higher storage capacity than the first buffer memory (121a; 221a; 421a), wherein the memory controller (121; 221; 421; 2210) is configured to transfer the write data (WRD) from the first buffer memory (121a; 221a; 421a) to the second buffer memory (123; 211; 423) and to the non-volatile memory (122; 222; 422; 2220) (S130), and to release an operating state of the first buffer memory (121a; 221a; 421a) after transferring the write data (WRD) from the first buffer memory (121a; 221a; 421a) to the second buffer memory (123; 211; 423) and to the non-volatile memory (122; 222; 422; 2220) (S140), and to send a write completion signal to the host device (110; 210; 410; 2100) before successfully writing the write data (WRD) to the non-volatile memory (122; 222; 422; 2220), wherein writing of additional write data into the first buffer memory (121a; 221a; 421a) is prohibited before the operating state of the first buffer memory (121a; 221a; 421a) is released, and writing of the additional write data into the first buffer memory (121a; 221a; 421a) is permitted after the operating state of the first buffer memory (121a; 221a; 421a) is released, wherein the memory controller (121; 221; 421) is configured to transfer the write data (WRD) to the non-volatile memory (122; 222; 422) simultaneously with a transfer of the write data (WRD) to the second buffer memory (123; 221; 423) (S130). [2] The system (100; 200) of claim 1, wherein the operating state of the first buffer memory (121a; 221a; 421a) is released in response to completion of the write data (WRD) being transferred to the second buffer memory (123; 211; 423) and the non-volatile memory (122; 222; 422). [3] The system (100; 200) of claim 1, wherein the non-volatile memory (122; 222; 422) is configured to generate a write success signal when the write data (WRD) transferred from the first buffer memory (121a; 221a; 421a) has been successfully stored in the non-volatile memory (122; 222; 422), and to generate a write failure signal when the write data (WRD) transferred from the first buffer memory (121a; 221a; 421a) has been unsuccessfully stored in the non-volatile memory (122; 222; 422), and wherein the operating state of the first buffer memory (121a, 221a; 421a) is released (S140) before the non-volatile memory (122; 222; 422) generates the write success signal or the write failure signal. [4] The system (100) of claim 1, wherein the non-volatile memory (122) comprises a plurality of non-volatile memory devices (NVM), and the first buffer memory (121a) comprises a plurality of storage areas each corresponding to the plurality of non-volatile memory devices (NVM). [5] The system of claim 1, wherein the memory controller (421) comprises a first direct memory access (DMA) engine (421g) for controlling operations between the host device (410) and the first buffer memory (421a) and a second DMA engine (421h) for controlling operations between the first buffer memory (421a) and the second buffer memory (423) and between the first buffer memory (421a) and the non-volatile memory (422). [6] The system (2000) of claim 1, wherein the memory controller (2210) comprises a write manager circuit (2213) and a read manager circuit (2214), and wherein the first buffer memory is in the write manager circuit (2213) and a separate buffer memory is in the read manager circuit (2214). [7] Procedure with the following steps: temporarily storing (S110) write data (WRD) received from a host device (110; 210; 410; 2100) and to be written into a non-volatile memory (122; 222; 422; 2220) by a first buffer memory (121a; 221a; 421a) of a memory controller (121; 221; 421; 2210); Transferring (S130) the write data (WRD) from the first buffer memory (121a; 221a; 421a) to the non-volatile memory (122; 222; 422; 2220) and to a second buffer memory (123; 211; 423) having a lower operating speed and a higher storage capacity than the first buffer memory (121a; 221a; 421a) by the memory controller (121; 221; 421; 2210); and Transmitting a write completion signal to the host device (110; 210; 410; 2100) before successfully writing the write data (WRD) to the non-volatile memory (122; 222; 422; 2220) and enabling (S140) an operating state of the first buffer memory (121a, 221a, 421a) after transferring (S130) the write data (WRD) from the first buffer memory (121a; 221a; 421a) to the second buffer memory (123; 211; 423) and to the non-volatile memory (122; 222; 422; 2220) by the memory controller (121; 221; 421; 2210), wherein writing of additional write data into the first buffer memory (121a; 221a; 421a) is prohibited before the operating state of the first buffer memory (121a; 221a; 421a) is released, and writing of the additional write data into the first buffer memory (121a; 221a; 421a) is permitted after the operating state of the first buffer memory (121a; 221a; 421a) is released, with the following further step: Transferring (S130) the write data (WRD) to the non-volatile memory (122; 222; 422; 2220) simultaneously with transferring (S130) the write data (WRD) to the second buffer memory (123; 211; 423). [8] The method of claim 7, further comprising the step of: Releasing (S140) the operating state of the first buffer memory (121a; 221a; 421a) in response to completion of the write data being transferred to the second buffer memory (123; 211; 423) and the non-volatile memory (122; 222; 422; 2220). [9] The method of claim 7, further comprising the steps of: Generating a write success signal by the non-volatile memory (122; 222; 422; 2220) when the write data (WRD) transferred from the first buffer memory (121a; 221a; 421a) has been successfully stored in the non-volatile memory (122; 222; 422; 2220), and generating a write failure signal by the non-volatile memory (122; 222; 422; 2220) when the write data (WRD) transferred from the first buffer memory (121a; 221a; 421a) has not been successfully stored in the non-volatile memory (122; 222; 422; 2220), wherein the operating state of the first buffer memory (121a; 221a; 421a) is released before the non-volatile memory (122; 222; 422; 2220) generates the write success signal or the write failure signal. [10] The method of claim 9, further comprising the step of: Transmitting a write completion signal to the host device (110; 210; 410; 2100) indicating that the first buffer memory (121a; 221a; 421a) is in an enabled operating state before the non-volatile memory (122; 222; 422; 2220) generates the write success signal or the write failure signal, by the memory controller (121; 221; 421; 2210). [11] The method of claim 10, further comprising the step of: Releasing (S160) the operating state of the second buffer memory (123; 211; 423) in response to the write success signal generated by the non-volatile memory (122; 222; 422; 2220), wherein writing to the second buffer memory (123; 211; 423) is prohibited before the releasing of the operating state of the first buffer memory (121a; 221a; 421a), and wherein the second buffer memory (123; 211; 423) is configured in the released operating state to receive second write data from the first buffer memory (121a; 221a; 421a). [12] The method of claim 9, further comprising the steps of: Transferring the write data (WRD) from the second buffer memory (123; 211; 423) to the first buffer memory (121a; 221a; 421a) and then re-transferring the write data (WRD) from the first buffer memory (121a; 221a; 421a) to the non-volatile memory (122; 222; 422; 2220) when the non-volatile memory (122; 222; 422; 2220) generates the write fail signal. [13] The method of claim 9, further comprising the step of: Transferring (S180) the write data (WRD) from the second buffer memory (123; 211; 423) to the non-volatile memory (122; 222; 422; 2220) when the non-volatile memory (122; 222; 422; 2220) generates the write fail signal.
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