ROUTING DATA BLOCKS DURING THERMAL THROTTLING

Abstract

Solid State Drive (90), comprising: a control unit (100); one or more flash dies (104) comprising a plurality of triple level cell (TLC) blocks; one or more temperature sensors (106) proximate the one or more flash dies (104); and a non-transitory computer-readable storage medium containing data storing instructions that, when executed by the control unit (100), cause the control unit (100): periodically retrieve a temperature measurement from the one or more temperature sensors (106); limit operations on the one or more flash dies (104) when the temperature measurement is above a startup throttling threshold; to write to the TLC blocks in an SLC mode when the temperature reading is above the startup throttling threshold; wherein the data storing instructions further causes the control unit (100) to fold the TLC blocks written to in the SLC mode into TLC blocks in a TLC mode when the temperature measurement is below a stop throttling threshold; and wherein the data storing instructions further causes the control unit (100) to increment a program erase count of the folded TLC blocks.

Description

BACKGROUND OF REVELATIONArea of ​​Revelation

[0001] Embodiments of the present disclosure generally relate to improving the performance of SSDs in the case of thermal throttling. Description of the state of the art

[0002] Solid-state drives (SSDs) can contain multiple memory chips (e.g., in a multi-chip package) that can be read or written to in parallel. During read and write operations, SSDs consume power and generate heat. Very intensive or long-running, sustained workloads can cause an SSD to generate so much heat that it may exceed its optimal operating temperature. For example, sequential write and sequential read operations can cause the temperature of an SSD in a laptop to rapidly rise from 20°C to 80°C in approximately two minutes of operation. To prevent burnout or damage to an SSD component when the drive is at high temperatures, an SSD control unit can perform a thermal throttling operation to reduce the SSD's temperature by slowing the SSD's throughput.Reducing the throughput of an SSD allows overheated components of the SSD to cool down. Thermal throttling can involve reducing parallel processing, introducing artificial delays into operations, and other actions.

[0003] Although thermal throttling of SSDs protects the drive at high temperatures, it has a detrimental impact on drive performance. For example, thermal throttling can cause an SSD's performance to drop by 50% or more. Therefore, there is a need for improved SSDs and an improved method for operating an SSD in the event of thermal throttling.

[0004] The document US 2012 / 0 224 425 A1 relates to performing memory operations using temperature information.

[0005] The publication US 2016 / 0 320 971 A1 describes a storage system and a method for differential thermal throttling.

[0006] The document US 2014 / 0 006 688 A1 relates to solid-state drive (SSD) systems and in particular to flash controllers that adaptively program single or multi-level cells.

[0007] US 2015 / 0 213 896 A1 describes methods for operating a computer memory and a computer memory system. SUMMARY OF REVELATION

[0008] Claim 1 claims a solid state drive, claim 5 claims a method for storing data in a solid state drive (SSD), claim 9 claims a method for storing data in a solid state drive (SSD), claim 13 claims a memory storage system, and claim 16 claims a method for operating a solid state drive (SSD).

[0009] Embodiments of the present disclosure generally relate to improving the performance of SSDs in the event of thermal throttling. Embodiments of an SSD include a controller coupled to one or more flash chips, one or more temperature sensors proximate the one or more flash chips, and data storage instructions. The one or more flash chips include a plurality of TLC (Triple Level Cell) blocks. When the controller executes the data storage instructions that cause the controller to periodically retrieve a temperature reading from the one or more temperature sensors, it limits these operations on the one or more flash chips when the temperature reading is above a startup throttling threshold and writes to the TLC blocks in an SLC mode when the temperature reading is above the startup throttling threshold.

[0010] Embodiments of a method for storing data in an SSD, the SSD comprising a plurality of memory chips, include periodically retrieving a temperature of the memory chips. The memory chips comprise a plurality of multiple-bits-per-cell (MBC) blocks. Operations on the memory chips are throttled when the temperature is above a starting throttling threshold. MBC blocks are written to in a single-bit-per-cell (SBC) mode during throttling.

[0011] In other embodiments, a method for storing data in an SSD, the SSD comprising non-volatile memory, includes periodically retrieving a temperature of the non-volatile memory. The non-volatile memory includes a plurality of MBC blocks and a plurality of SBC blocks. Operations of the non-volatile memory are throttled when the temperature is above a startup throttling threshold. Scanning for one or more spare SBC blocks among the plurality of SBC blocks when the temperature reading is above the startup throttling threshold. The one or more spare SBC blocks are written with non-system data during throttling.

[0012] In yet further embodiments, a method for operating a solid-state drive (SSD), the SSD having a plurality of memory chips, includes periodically retrieving a temperature of the memory chips. Operations on the memory chips are throttled when the temperature is above a startup throttling threshold. Data is written to the blocks of the memory chips in a one-bit-per-cell (SBC) mode during throttling. The blocks written to in SBC mode are tagged with a status flag.

[0013] In other embodiments, an SSD comprises a control unit provided with non-volatile storage means for storing data. The non-volatile storage means can store data in a high-performance, low-capacity mode and in a low-performance, high-capacity mode. A temperature sensor is located near the non-volatile storage means. Memory storage data, when executed by the control unit, causes the control unit to periodically retrieve a temperature reading from the temperature sensor, throttle operations on the non-volatile storage means when the temperature reading is above a startup throttling threshold, and write to the non-volatile storage means to store data in a high-performance, low-capacity mode when the temperature reading is above the startup throttling threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] For a more detailed understanding of the above-noted features of the present disclosure, a more particular description of the disclosure, briefly summarized above, may be made with reference to embodiments, some of which are illustrated in the accompanying drawings. It is to be understood, however, that the accompanying drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. Fig. 1 is a schematic diagram of one embodiment of an SSD. Fig. 2 is a schematic diagram of an example of a two-dimensional memory array. Fig. 3 is a schematic diagram of an example of a three-dimensional memory array. Fig. 4A-4D are schematic representations of a memory cell storing a different number of bits. Fig. Figure 5 is a schematic diagram of an embodiment of an SSD with improved performance in the case of thermal throttling. Fig. 6 is a flowchart illustrating one embodiment of improved performance of an SSD device in the case of thermal throttling. Fig. 7 is an embodiment of a block allocation table.

[0015] For ease of understanding, identical reference numerals have been used where possible to designate identical elements common to the figures. It is contemplated that elements disclosed in one embodiment may be advantageously used in other embodiments without specific reference. DETAILED DESCRIPTION

[0016] Reference is made below to embodiments of the disclosure. However, it is to be understood that the disclosure is not limited to the specific embodiments described. Rather, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the disclosure. Although embodiments of the disclosure may achieve advantages over other possible solutions and / or over the prior art, the disclosure is not limited by whether or not a particular advantage is achieved by a given embodiment. Thus, the following aspects, features, embodiments, and advantages are illustrative only and are not to be considered elements or limitations of the appended claims, except where expressly recited in the claim(s).Similarly, reference to "the disclosure" is not intended to generalize any inventive subject matter disclosed herein and is not to be construed as an element or limitation of the appended claims, except where expressly recited in the claim(s).

[0017] Fig. 1 is a schematic representation of one embodiment of an SSD 90 suitable for implementing the present invention. The SSD 90 operates with a host 80 through a host interface 110. The SSD 90 and the host 80 may be coupled via a connection (e.g., a communication path), such as a bus or a wireless connection. The SSD may be used as an embedded storage drive, an enterprise storage drive, a client storage device, a cloud storage drive, or in other applications. The SSD 90 may be directly coupled to the host 80 or may be indirectly coupled to the host 80 via a network. For example, the network may be a data center storage system network, an enterprise storage system network, a storage area network, a cloud storage network, a local area network (LAN), a wide area network (WAN), the Internet, and / or another network.

[0018] The SSD 90 may be in the form of removable storage, such as a memory card, or may be in the form of an embedded storage system. The SSD 90 may be a removable mass storage device, such as, but not limited to, handheld devices, a removable storage device, such as a memory card (e.g., a Secure Digital (SD) card, a Micro Secure Digital (Micro SD) card, or a MultiMedia Card (MMC), or a Universal Serial Bus (USB) device. The SSD 90 may take the form of an embedded mass storage device, such as an eSD / eMMC embedded flash drive embedded in the host 80.

[0019] The host 80 may include a wide range of devices, such as computer servers, network-attached storage (NAS) units, desktop computers, notebook (i.e., laptop) computers, tablet computers (i.e., "smart" pads), set-top boxes, mobile phones (i.e., smart phones), televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, and vehicle applications (i.e., mapping, autonomous driving). In certain embodiments, the host 80 includes any device having a processing unit or any form of hardware capable of processing data, including a general-purpose processing unit (such as a central processing unit (CPU)), dedicated hardware (such as an application-specific integration circuit (ASIC)), configurable hardware such as a field-programmable gate array (FPGA), or any other form of processing unit configured by software instructions, microcode, or firmware.

[0020] The host 80 interacts with the SSD 90 through the host interface 110. In certain embodiments, the host 80 and the SSD 90 operate according to Nonvolatile Memory Express (NVMe), Universal Flash Storage (UFS), Serial Advanced Technology Attachment (SATA), Serially Attached SCSI (SAS), Advanced Technology Attachment (ATA), Parallel-ATA (PATA), Fibre Channel Arbitrated Loop (FCAL), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI-Express (PCIe), and other suitable protocols.

[0021] The SSD 90 includes a non-volatile memory (NVM) 102 controlled by a controller 100. The NVM 102 includes one or more arrays of non-volatile memory cells. The NVM 102 may be configured for long-term data storage of information and may retain information across power cycles. The non-volatile memory may include one or more storage devices. Examples of non-volatile memory devices include flash memory, phase-change memory, ReRAM memory, MRAM memory, electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and other solid-state memories. The non-volatile memory device may also have various configurations. For example, flash memory devices may be configured in a NAND or NOR configuration.

[0022] The NVM 102 may include one or a plurality of NAND flash memory chips 104. The NVM 102 may include one or a plurality of temperature sensors 106 proximate the one or a plurality of chips 104. For example, each die 104 may have a dedicated temperature sensor 106 for measuring the operating temperature of an individual die 104. Alternatively, two or more chips 104 may share a temperature sensor 106 for measuring the operating temperature of the group of chips 104.

[0023] The control unit 100 also includes a processor 120, a read-only memory (ROM) 122, a volatile memory 130, and additional components not shown. The control unit 100 manages operations of the SSD 90, such as writing to and reading from the NVM 102. The processor 120 may be one or more processors or may be a multi-core processor. The control unit 100 also includes a volatile memory 130 or cache buffer(s) for short-term storage or temporary storage during operation of the SSD 90. The volatile memory 130 does not retain stored data when it is powered off. Examples of volatile memory include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and other forms of volatile memory.

[0024] The control unit 100 executes instructions (hereinafter referred to as "instructions") executable by computer-readable program code (e.g., software or firmware). The instructions can be executed by various components of the control unit 100, such as the processor 120, logic gates, switches, application-specific integration circuits (ASICs), programmable logic controllers, embedded microcontrollers, and other components of the control unit 100.

[0025] The instructions are stored in a non-transitory computer-readable storage medium. In certain embodiments, the instructions are stored in a non-transitory computer-readable storage medium of the SSD 90, such as in ROM 122 or NVM 102. Instructions stored in the SSD 90 can be executed without additional input or instructions from the host 80 and can enable high input / output per second operations of the SSD 90 because the SSD 90 does not have to wait to receive additional commands from the host 80 in addition to normal read, write, and / or erase commands from the host 80. Execution of instructions stored in the SSD 90 is seamless to the host 80. In other embodiments, the instructions are stored in a non-transitory computer-readable storage medium of the host 80.The stored instructions, such as those stored in SSD 90 or host 80, can be loaded, in whole or in part, into the volatile memory 130 of control unit 100 for execution by the control unit. Control unit 100 is configured with hardware and instructions to perform the various functions described herein and shown in the figures.

[0026] The SSD 90 may further include a flash translation layer 140. The flash translation layer 140 may be stored in the NVM 120 and loaded or partially loaded into the volatile memory 130. The flash translation layer may include a logical-to-physical (or virtual-to-physical) data address / container / sector translation mapping 142. The host device 80 may reference a unit of data using a logical data address, and the controller 110 may use the mapping 142 to command writing data to and reading data from the NVM 102. The flash translation layer 140 may include garbage collection tables 144 to move valid data from a selected block with invalid data to an open block or a partially filled block and to erase the selected block.The flash translation layer 140 may include a wear leveling counter 146 to record the number of program erase cycles of a block to balance the usage of the blocks of the NVM 102. The flash translation layer 140 may include a free block list that lists the blocks that are open or available for programming.

[0027] The NVM 102 may include multiple memory cells configured to be accessible as a group or individually accessible. For example, flash memory devices in a NAND configuration typically include memory cells connected in series. A NAND memory array may be configured such that the array consists of multiple memory strings, where a string consists of multiple memory cells that share a single bit line and are accessed as a group. Alternatively, memory elements may be configured such that each element can be accessed individually, as in a NOR design. Memory designs other than NAND or NOR memory designs are possible.

[0028] The memory cells may be arranged in two or three dimensions, such as a two-dimensional memory array or a three-dimensional memory array. Fig. 2 is a schematic diagram of an example of a two-dimensional memory array 210, such as a 2D or planar NAND memory array. The memory array 210 includes a set of NAND strings 250. Each NAND string 250 includes a memory cell 260A, 260B, 260D through 260N. Each NAND string 250 includes a select gate-drain (SGD) transistor 220 and a select gate-source (SGS) transistor 230. The memory array 210 includes multiple pages 290. Page 290 is accessed by the control gates of the cells of the page, which are commonly connected to a word line 260, and each cell can be accessed via bit lines 280. A source line 285 is also provided. In other embodiments, the memory cells may be arranged in other configurations.

[0029] Fig. Figure 3 is a schematic diagram of an example of a three-dimensional memory array 310, such as a 3D or vertical NAND memory array or a BiCS2 cell array, as shown. The memory array 310 consists of a plurality of pages 390. Each page 390 includes a set of NAND strings 350 (four NAND strings are shown). Each set of NAND strings 350 is commonly connected to a global bit line 380. Each NAND string 350 includes a drain selected gate transistor 320, a plurality of memory cells 360A, 360B, 360N, and a source selected gate transistor (SGS) 330. A row of memory cells is commonly connected to a word line 370. A source line 385 is also present.

[0030] The memory cells 260, 360, which are Fig. 2 and Fig. 3 consist of a transistor having a charge storage element for storing a given amount of charge representing a memory state. Fig. 4A-4D are schematic representations of a memory cell, such as the memory cells 260, 360 of Fig. 2 and Fig. 3, which store a different number of bits. Fig. Figure 4A is a schematic diagram 410 of a memory cell operating as a single-level cell (SLC) memory cell to store one bit per cell. The SLC memory cell can operate with two threshold voltage distribution states, representing an erased state 412 and a programmed state 414. Fig. Figure 4B is a schematic diagram 420 of a memory cell operating as a multi-level cell (MLC) or X2 cell that stores 2 bits per cell. The MLC memory cell can operate with four threshold voltage states, representing an erased state 422 and three programmed states 424. Fig. Figure 4C is a schematic diagram 430 of a memory cell operating as a triple-level cell (TLC) or X3 cell, storing 3 bits per cell. The TLC memory cell can operate with eight threshold voltage states, representing an erased state 432 and seven programmed states 434. Fig. Figure 4D is a schematic diagram 440 of a memory cell operating as a quadruple-level memory cell (QLC) or X4 cell, storing 4 bits per cell. The QLC memory cell can operate with seven threshold voltage states, representing an erased state 442 and fifteen programmed states 444.

[0031] The blocks of chips 104 of SSD 90 can be organized to store a single bit per cell (referred to herein as one-bit-per-cell or SBC) or to store multiple bits per cell (referred to herein as multiple-bit-per-cell or MBC). SBC blocks include blocks configured to store one bit per cell, such as SLC blocks. MBC blocks include blocks configured to store two or more bits per cell, such as MLC blocks, TLC blocks, or QLC blocks. For example, BiCS3 flash dies can be designed as 1,350 TLC blocks and 64 SLC blocks. SBC blocks can be used to store system data, which may include, but is not limited to, BIOS, firmware, flash translation layer, and mapping tables. MBC blocks can be used to store non-system data. SBC blocks can be reserved for system data, allowing system data to be stored in more durable memory and read more quickly.

[0032] Fig. Figure 5 is a schematic diagram of an embodiment of an SSD 500 with enhanced performance in the case of thermal throttling. The system 500 is described with reference to the SSD 90 of Fig. 1, but other SSDs are possible. System 500 includes subsystem 510, subsystem 520, subsystem 530, and subsystem 540, but other subsystems and configurations are possible.

[0033] The subsystem 510 comprises a firmware and hardware layer, such as a control unit 100 of Fig. 1, which is connected or coupled to subsystem 520, subsystem 530, and subsystem 540. Subsystem 520 includes a NAND layer of one or a plurality of chips of NAND flash memory cells, such as dies 104 of Fig. 1. Each bare chip 104 can have a temperature sensor, such as the temperature sensor 106 of Fig. 1, or two or more dies 104 may share a temperature sensor. Each die 104 includes a plurality of blocks, such as blocks 295 of Fig. 2 and / or blocks 395 of Fig. 3. Each block can be operated in such a way that the memory cells store a certain number of bits per cell, as in Fig. 4A-4D. Subsystem 520 may include a plurality of MBC blocks and a plurality of SBC blocks.

[0034] Subsystem 510 accesses the temperature sensor of the NAND flash chips of subsystem 520. If subsystem 510 detects that a temperature reading from the temperature sensor is above a startup throttling threshold, subsystem 510 implements a thermal throttling operation by limiting operations on the flash chips. During thermal throttling, subsystem 510 may perform write operations of non-system data to spare SBC blocks, less than the total number of designed SBC blocks. In certain embodiments, a certain number of SBC blocks are not used to store non-system data during thermal throttling, allowing system data to be stored in SBC blocks when necessary. If SBC blocks are unavailable during thermal throttling, subsystem 510 then selects MBC blocks and performs writes to those MBC blocks in an SBC mode.For example, the control unit can select a TLC block and program the selected TLC block in an SLC mode.

[0035] By writing to an SBC block during thermal throttling or writing to an MBC block in SBC mode during thermal throttling, less heat is generated when writing in SBC mode compared to MBC mode. For example, writing a page of a block in SLC mode generates less heat than writing a page of a block in TLC mode. Additionally, writing to blocks in SBC mode is faster compared to writing in MBC mode. For example, writing a page of a block in SLC mode is faster compared to writing a page of a block in TLC mode. Due to the lower heat generated and / or faster programming, subsystem 520 may require less time to reduce its temperature below a stop thermal throttling threshold and may return to normal operation more quickly.Additionally, during thermal throttling, faster writing in an SBC mode compared to an MBC mode reduces the impact on performance caused by thermal throttling.

[0036] The subsystem 530 has a block allocation table, such as a block allocation table 700 of Fig. 7. As in Fig. 7, the block allocation table 700 may include block addresses / ranges 710 corresponding to a logical block address (LBA) and / or a physical block address (PBA). The subsystem 510 may use the block allocation table 700 to include a remapping status flag 730. The remapping status flag 730 may indicate the SBC blocks that will be written to during thermal throttling or the MBC blocks that will be written to in an SBC mode during thermal throttling. For example, the subsystem 510 may use the block allocation table in subsystem 530 to provide a status flag to the TLC blocks that will be written to in an SLC mode during thermal throttling. The block allocation table may be stored in subsystem 520 and loaded into the volatile memory of the subsystem 510.

[0037] Subsystem 510 may use the block mapping table during read operations of MBC blocks that store data in an SBC mode to decode the stored data in an SBC mode. Subsystem 510 may use the block mapping table to identify the SBC blocks that store non-system data to be folded into MBC blocks to maintain the capacity to store system data. Subsystem 510 may use the block mapping table to identify MBC blocks that store data in an SBC mode to be folded into MBC blocks in an MBC mode to maintain the storage capacity of the SSD.

[0038] Subsystem 540 may include a firmware layer containing instructions that, after thermal throttling is completed or when subsystem 510 detects that a temperature reading from the temperature sensor is below a stop thermal throttling threshold, the SLB blocks storing non-system data may be folded into MBC blocks to maintain the capacity to store system data, and / or MBC blocks storing data in an SBC mode may be folded into MBC blocks in an MBC mode to maintain the storage capacity of the SSD. Subsystem 540 may also include a firmware layer containing instructions to forward increment a program erase cycle counter of the folded blocks, such as forward incrementing the wear leveling counter 146 of Fig. 1.

[0039] Fig. 6 is a flowchart 600 illustrating one embodiment of storing data in an SSD device in the case of thermal throttling. The flowchart 600 is described with reference to the SSD 90 of Fig. 1, however, other SSDs are possible. One or more blocks of flowchart 600 may be performed by control unit 100 executing computer-readable program code (e.g., software or firmware) executable instructions stored in SSD 90 or host 80. Flowchart 600 is described with reference to MBC blocks of TLC blocks, however, other MBC blocks may be used, such as MLC blocks and / or QLC blocks.

[0040] In process 610, a controller periodically retrieves a temperature of the NAND chip(s) by receiving a temperature reading from temperature sensor 106. For example, the controller may retrieve the temperature of the NAND chips every 1 second or at any suitable interval. Each chip may include a temperature sensor, such as temperature sensor 106 of Fig. One, or two or more chips can share a temperature sensor.

[0041] In process 620, the controller determines whether the temperature reading is above a start throttling threshold or whether the temperature reading is below a stop throttling threshold. If the temperature reading is above a start throttling threshold (such as 80°C or more), control proceeds to process 625, where thermal throttling is started. If the temperature is below a stop throttling threshold (such as 75°C or less), the controller proceeds to process 648, where thermal throttling is stopped. A start throttling threshold and a stop throttling threshold can be set to any suitable temperature(s). In other embodiments, a start throttling threshold and a stop throttling threshold can be approximately the same temperature.

[0042] In process 625, operations on the NAND chips 104 are throttled to prevent or reduce damage to the NAND chips and other components of the SSD 90. Throttling may include limiting the number of active operations on the NAND chips, such as limiting the number of active read, write, and / or erase operations on the blocks of the NAND chips.

[0043] In process 630, the control unit scans a free SLC block pool, such as a free block list 148 of Fig. 1, available SLC spare blocks to store non-system data. A certain number of SBC blocks are not used to store non-system data during thermal throttling, so that system data can be stored in SBC blocks when necessary. In certain embodiments, the available SLC spare blocks are fewer than the total available SBC blocks.

[0044] In process 632, the controller determines from process 630 whether or not there are available SLC blocks. If there are available spare SLC blocks, the controller proceeds to process 634. If there are no available SLC blocks, the controller proceeds to process 636.

[0045] In process 634, the controller reroutes pending or received host writes destined for one or more TLC blocks to one or more available SLC spare blocks. The controller may use the mapping table, such as mapping table 700 of Fig. 7, update with a remapping status character to indicate the SLC spare blocks being written to during thermal throttling.

[0046] In process 636, the control unit routes pending or received host writes to TLC blocks and writes to the TLC blocks in an SLC mode. The control unit may use the mapping table, such as the mapping table 700 of Fig. 7, update with a remap status character to indicate the TLC blocks being written to in an SLC mode during thermal throttling.

[0047] If the temperature in process 620 is below a stop throttling threshold (such as 75°C or less), the controller proceeds to process 648, where thermal throttling is stopped. After thermal throttling is stopped, the SSD 90 operates at normal or full system power. The controller then proceeds to process 650.

[0048] If, in process 650, SSD 90 is not thermally throttled, the controller scans for blocks marked with a remap status flag from process 634 and / or process 636. If a remap status flag is present, the controller proceeds to process 660.

[0049] In process 660, the control unit folds or marks blocks to be folded into TLC blocks in a TLC mode. For example, SLC blocks written to in process 634 may be folded into TLC blocks in a TLC mode to maintain the capacity to store system data. TLC blocks written to in an SLC mode in process 636 may be folded into TLC blocks in a TLC mode to maintain the storage capacity of the SSD. A program erase cycle counter of the folded blocks may be forward incremented, such as forward incrementing the wear leveling counter 146 of Fig. 1. After the blocks are folded into TLC blocks, the remapping status flags of the folded blocks are removed or reset from the mapping table.

[0050] As shown in flowchart 600, at the end of process 634, process 636, process 650 if there are no blocks with a remap status flag, and process 660, the controller returns to process 610. It will be appreciated that in other embodiments, polling the temperature of the NAND chips occurs periodically to start and / or stop thermal throttling and does not need to wait for the end of any processes of flowchart 600.

[0051] Fig. 7 is an embodiment of a block allocation table 700 used in an SSD 500 of Fig. 5 and in the flowchart 600 of Fig. 6 can be used. The table 700 includes block addresses 710 and remapping status characters 730. The block addresses 710 may correspond to logical block addresses (LBA) and / or physical block addresses (PBA). The remapping status character 730 may indicate the SBC blocks being written to during thermal throttling and / or the MBC blocks being written to in an SBC mode during thermal throttling. The remapping status character entry may consume as little as one memory bit. The remapping status character may be an entry "1" and a non-remapping status character as an entry "0." Alternatively, the remapping status character may be an entry "0" and a non-remapping status character as an entry "1." Remapping status characters 730 may be used by a controller in read operations of MBC blocks written to in an SBC mode.The remapping status flag 730 may be used by a controller to fold blocks being written to in an SBC mode to MBC blocks in an MBC mode, or to mark them to be folded.

[0052] The block allocation table 700 may be used by a flash translation layer or may be included in a flash translation layer, such as the flash translation layer 140 of Fig. 1. For example, in one embodiment, the block mapping table may be included in a logical block address to physical block address mapping of the flash translation layer. In another embodiment, the block mapping table may be included in a garbage collection module to fold blocks during garbage collection.

[0053] In certain embodiments, an SSD operates with less heat generated during programming and improved performance during thermal throttling. In certain aspects, an SSD under thermal throttling has improved performance through faster programming of data blocks during thermal throttling, such as programming in SLC mode instead of TLC mode.

[0054] In certain embodiments, programming in an SBC mode generates less heat than programming in an MBC mode. For example, programming a memory cell in an HBC mode may require multiple passes or multiple programming cycles to reach the final program state, resulting in more heat being generated. For example, the approximate amount of current I CC, which is consumed on average by a TLC block in a TLC mode, approximately 40 milliamperes, while the approximate amount of current I CC , which is consumed on average by an SLC block in SLC mode, is approximately 20 milliamperes. Assuming the same voltage V CC TLC blocks in TLC mode consume approximately twice the amount of power during operation and must dissipate approximately twice the amount of heat on a per-block basis compared to SLC blocks in SLC mode.

[0055] Because less heat is generated by programming in an SBC mode during thermal throttling rather than programming in an MBC mode, an SSD may cool more quickly below a stop-throttling threshold temperature and may have a reduced time under thermal throttling (i.e., it emerges from thermal throttling more quickly). Although an SSD operates under thermal throttling, in certain embodiments, less degradation of the SSD's performance and less heating of the SSD are achieved by programming in an SBC mode, such as programming SBC spare blocks and / or programming MBC blocks in an SBC mode.

[0056] In certain embodiments, a capacity of an SSD is maintained by folding the blocks written to in an SBC mode during thermal throttling into MBC blocks in an MBC mode when the SSD is not thermally throttled. For example, folding spare SLC blocks written to during thermal throttling and / or folding TLC blocks written to in an SLC mode into TLC blocks when the SSD is not thermally throttled.

[0057] In certain embodiments of a NAND Flash BiCS chip, a BiCS chip cools approximately 1°C / s under thermal throttling and programming in SBC mode. Therefore, depending on the memory chip, if a start thermal threshold is 80°C and a stop thermal throttling threshold is 75°C, in certain embodiments, the time to exit thermal throttling by programming in SBC mode is approximately 5 seconds to fully resume unthrottled performance.

[0058] In certain embodiments, programming in an SBC mode during thermal throttling provides a lower bit error rate. Decoding cells programmed in an SBC mode may be less complicated than decoding cells programmed in an MBC mode. Cells programmed in an SBC mode may be less affected by cross-temperature variations, in which the threshold voltage of a programmed cell shifts from a different write and read temperature, than cells programmed in an MBC mode.

[0059] In certain embodiments, a larger data size can be programmed in SBC mode than when programming in MBC mode when the SSD is thermally throttled. For example, programming one page in an SLC block may take approximately 170 microseconds, while programming one page in TLC mode may take approximately 1000 microseconds. Therefore, five or more pages of an SLC block can be programmed in the time required to program one page of a TLC block.

[0060] In certain embodiments, an improved method and SSD for storing data under thermal throttling require no design changes to the host. In certain embodiments, an improved method and SSD for storing data under thermal throttling are seamless to the host in that host data writes are written in an SBC or MBC mode without instructions from the host as to which mode to use.

[0061] Embodiments of the present disclosure in Fig.2-6 were described with reference to NAND flash memory cells. Embodiments of the present disclosure are applicable to any non-volatile memory capable of operating in an SBC mode and an MBC mode, such as NOR flash memory cells, resistive random access memory (ReRAM), and phase-change memory (PCM). Memory cells operating in an SBC mode may have higher performance (such as faster programming and / or better longevity) but lower capacity than memory cells operating in an MBC mode. Embodiments of the present disclosure include writing to non-volatile memory in a high-power, low-capacity mode during thermal throttling and in a low-power, high-capacity mode outside of thermal throttling.Embodiments of the present disclosure include folding data stored in a high power, low capacity mode into a low power, high capacity mode outside of thermal throttling.

Claims

[1] Solid State Drive (90), comprising: a control unit (100); one or more flash dies (104) comprising a plurality of triple level cell (TLC) blocks; one or more temperature sensors (106) proximate the one or more flash dies (104); and a non-transitory computer-readable storage medium containing data storing instructions that, when executed by the control unit (100), cause the control unit (100): periodically retrieve a temperature measurement from the one or more temperature sensors (106); limit operations on the one or more flash dies (104) when the temperature measurement is above a startup throttling threshold; to write to the TLC blocks in an SLC mode when the temperature reading is above the startup throttling threshold; wherein the data storing instructions further causes the control unit (100) to fold the TLC blocks written to in the SLC mode into TLC blocks in a TLC mode when the temperature measurement is below a stop throttling threshold; and wherein the data storing instructions further causes the control unit (100) to increment a program erase count of the folded TLC blocks. [2] The solid state drive (90) of claim 1, further comprising a mapping table, wherein the data storing instructions further causes the control unit (100) to provide the TLC blocks in the mapping table with a status flag to which the SLC mode is written. [3] The solid state drive (90) of claim 1, wherein the one or more flash dies (104) further comprise a plurality of single level cell (SLC) blocks, and wherein the data storing instructions further causes the controller (100) to scan for one or more spare SLC blocks from the plurality of SLC blocks when the temperature measurement is above the startup throttling threshold. [4] The solid state drive (90) of claim 3, wherein the data storing instructions further causes the controller (100) to write to the one or more spare SLC blocks prior to writing to the TLC blocks when the temperature measurement is above the startup throttling threshold. [5] A method for storing data in a solid state drive (SSD) (90), the SSD (90) comprising a plurality of memory dies, the memory dies comprising a plurality of multiple bits per cell (MBC) blocks, the method comprising: periodically retrieving a temperature of the memory die; Throttling the memory die when the temperature is above a startup throttling threshold; Writing to the MBC blocks in a one-bit-per-cell (SBC) mode during throttling; Folding the MBC blocks written to in SBC mode into MBC blocks in an MBC mode when the temperature is below a stop throttling threshold; and Incrementing a program erase count of the folded MBC blocks. [6] The method of claim 5, further comprising providing the MBC blocks with a status flag to be written to in SBC mode. [7] The method of claim 5, wherein the plurality of memory dies further comprises a plurality of SBC blocks, the method further comprising scanning for one or more spare SBC blocks from the plurality of SBC blocks during throttling. [8] The method of claim 7, further comprising writing to the SBC spare blocks before writing to the MBC blocks during throttling. [9] A method for storing data in a solid state drive (SDD) (90), the SSD (90) comprising non-volatile memory, the non-volatile memory comprising a plurality of multiple bits per cell (MBC) blocks and a plurality of one bit per cell (SBC) blocks, the method comprising: periodically retrieving a temperature of the non-volatile memory; Throttling non-volatile memory when the temperature is above a startup throttling threshold; scanning for one or more spare SBC blocks from the plurality of SLC blocks if the temperature reading is above the startup throttling threshold; Writing to the one or more SBC spare blocks with non-system data during throttling; Folding spare SBC blocks that are written with non-system data during throttling into MBC blocks when the temperature reading is below a stop throttling threshold; and Incrementing a program erase count of folded SBC blocks with non-system data. [10] The method of claim 9, wherein writing to the one or more SBC spare blocks comprises rerouting the writing to MBC blocks to the one or more SBC spare blocks. [11] The method of claim 9, further comprising providing SBC spare blocks with a status flag to be written with non-system data during throttling. [12] The method of claim 9, wherein the MBC blocks are TLC blocks and the SBC blocks are SLC blocks. [13] Memory storage system, comprising: a control unit means; a non-volatile storage means for storing data, wherein the non-volatile storage means can store data in a high power, low capacity mode and in a low power, high capacity mode; a temperature sensor (106) near the non-volatile storage medium; and a non-transitory computer-readable storage medium containing data storing instructions that, when executed by the control unit means, cause the control unit means to: periodically retrieve a temperature measurement value from the temperature sensor (106); throttle operations on the non-volatile storage medium when the temperature measurement is above a startup throttle threshold; write to the non-volatile storage means to store data in a high performance, low capacity mode when the temperature measurement is above the startup throttling threshold; wherein the data storing instructions further causes the controller means to fold data stored in the high power, low capacity mode into the low power, high capacity mode when the temperature measurement is below a stop throttling threshold; and wherein the data storing instructions further causes the control unit means to increment a program erase count of the folded data. [14] The memory storage system of claim 13, wherein the blocks operating in the high power, low capacity mode generate less heat than the blocks operating in the low power, high capacity mode. [15] The memory storage system of claim 13, wherein the data storing instructions further causes the controller means to write data faster in the high power, low capacity mode than in the low power, high capacity mode. [16] A method of operating a solid state drive (SSD) (90), the SSD (90) having a plurality of memory dies, the memory dies having a plurality of blocks, the method comprising: periodically retrieving a temperature of the memory die; Throttling the memory die when the temperature is above a startup throttling threshold; Writing data to the blocks in a one-bit-per-cell (SBC) mode during throttling; Assigning a status character to the blocks written to in SBC mode; Folding the blocks being written to in SBC mode into blocks in a multiple-bits-per-cell (MBC) mode when the temperature is below a stop throttling threshold; and Increasing a program erase count of the folded blocks. [17] The method of claim 16, further comprising decoding the written data in a read operation by determining whether the blocks have been flagged in SBC mode. [18] The method of claim 16, wherein folding the blocks comprises determining whether the blocks have been flagged in SBC mode.

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