Thin-film transistor with a two-dimensional semiconductor and display device with this thin-film transistor

Abstract

Thin film transistor (100) comprising: a gate electrode (110) arranged on a substrate (101); a semiconductor layer (120) overlapping at least a portion of the gate electrode (110), the semiconductor layer (120) being insulated from the gate electrode (110); a gate insulation film (150) disposed between the gate electrode (110) and the semiconductor layer (120); a source electrode (130) connected to the semiconductor layer (120), and a drain electrode (140) connected to the semiconductor layer (120), wherein the drain electrode (140) is spaced from the source electrode (130), wherein the semiconductor layer (120) comprises: a first layer (121) comprising an oxide semiconductor; and a second layer (122) overlapping the first layer (121), and wherein an energy band gap of the first layer (121) is larger than an energy band gap of the second layer (122), wherein the second layer (122) comprises a two-dimensional semiconductor, wherein the two-dimensional semiconductor is a monolayer or a stack of multiple monolayers, and wherein the second layer (122) is a channel layer.

Description

BACKGROUND OF THE INVENTIONField of the InventionThe present invention relates to a thin film transistor including a two-dimensional semiconductor and a display device including the thin film transistor.BackgroundIn the field of electronic equipment, a transistor has been widely used as a switching device or a driving device. In particular, a thin film transistor has been widely used as a switching device of a display device such as a liquid crystal display device or an organic light emitting display device because the thin film transistor can be fabricated on a glass substrate or a plastic substrate.Based on a material constituting an active layer, the thin film transistor may be classified as an amorphous silicon thin film transistor in which amorphous silicon is used as the active layer, a polycrystalline silicon thin film transistor in which polycrystalline silicon is used as the active layer, or an oxide semiconductor thin film transistor in which an oxide semiconductor is used as the active layer.An amorphous silicon thin film transistor (a-Si TFT) has advantages in that the manufacturing time is short and the manufacturing cost is low because the amorphous silicon is deposited within a short time to form the active layer. However, the amorphous silicon thin film transistor has disadvantages that the amorphous silicon thin film transistor has low mobility, whereby the current driving capability of the amorphous silicon thin film transistor is not good, and that the threshold voltage of the amorphous silicon thin film transistor is changed, whereby the use of the amorphous silicon thin film transistor in an active matrix organic light emitting device (AMOLED) is restricted.The polycrystalline silicon thin film transistor (poly-Si TFT) is formed by depositing and crystallizing amorphous silicon. Since the process for crystallizing amorphous silicon is required to produce the thin film transistor with polycrystalline silicon, the number of processes is increased, with the result that the production cost is increased. In addition, since the crystallization process is carried out at a high process temperature, it is difficult to apply the thin film transistor with polycrystalline silicon to a large-sized device. Moreover, because of its polycrystalline characteristics, it is difficult to ensure the uniformity of the polycrystalline silicon thin film transistor.For the oxide semiconductor thin film transistor (oxide semiconductor TFT), an oxide constituting the active layer can be deposited at a relatively low temperature, mobility of the oxide semiconductor thin film transistor is high, and a change in resistance of the oxide depending on the oxygen content is large, whereby desired physical properties of the oxide semiconductor thin film transistor are easily obtained. In addition, the oxide semiconductor thin film transistor is advantageous in realizing a transparent display device because the oxide semiconductor is transparent due to the characteristics of the oxide. However, in the case where the amount of oxide in the oxide semiconductor is insufficient due to contact between the oxide semiconductor and an insulating layer or a passivation layer, the reliability of the oxide semiconductor is reduced.In recent years, the demand for a thin film transistor which has excellent current characteristics, is small-sized, and is flexible has been increasing. For this purpose, research has been conducted for semiconductors other than silicon-based semiconductors or oxide semiconductors.[Prior Art]Thin film transistors are already known from the following patent documents 001-008:Patent Document 001: Korean Patent Publication No. KR 10 2016 0 038 675 A entitled "SEMICONDUCTOR DEVICE AND CHANNEL STRUCTURE THEREOF";Patent Document 002: Korean Patent Publication No. KR 10 2015 0 029 035 A with the title "THIN-FILM TRANSISTOR";Patent Document 003: US 2011 / 0 156 020 A1Patent Document 004: US 2009 / 0 224 238 A1Patent Document 005: US 2011 / 0 140 100 A1Patent Document 006: US 2009 / 0 180 045 A1Patent Document 007: JP 2017-79 313 APatent Document 008: US 2015 / 0 179 815 A1Of these, Patent Document 003 describes a transistor having a semiconductor insertion layer. The semiconductor insert layer is arranged between a channel layer and a source electrode and serves to increase the potential barrier between the channel layer and the source electrode. Patent Document 004 is directed to a transistor having a channel layer. The source electrode and the drain electrode contact the ends of the channel layer, respectively. The gate electrode is spaced from the channel layer and separated therefrom by an insulating layer. Further, between the channel layer and the insulating layer, there is provided a plug layer whose electron work function is different from that of the channel layer. Patent Document 005 discloses a thin film transistor including an oxide semiconductor layer including a first region, a second region, and a third region. The three regions are designed such that a trough-shaped potential is formed. Patent Document 006 relates to a display device including a substrate, a gate electrode disposed on the substrate, a first semiconductor structure separated from the gate electrode by a gate insulating film, and a second semiconductor structure formed on the first semiconductor structure. In this arrangement, the first semiconductor structure has a first energy band gap that is smaller than the second energy band gap of the second semiconductor structure. Patent Document 007 discloses a device including a metal film; a first transition metal dichalcogenide that is a semiconductor electrically connected to the metal film; and a second transition metal dichalcogenide that is a metal disposed at the boundary between the metal film and the first transition metal dichalcogenide. Patent Document 008 also describes a thin film transistor having a well-shaped potential, similar to the thin film transistor of Patent Document 005.SUMMARY OF THE INVENTIONThe present invention has been made in view of the above problems, and it is an object of the present invention to provide a thin film transistor including a two-dimensional semiconductor, being thin and preferably flexible, and exhibiting excellent electrical characteristics.It is another object of the present invention to provide a thin film transistor including a two-dimensional semiconductor and an oxide semiconductor, exhibiting excellent reliability, and preventing deterioration of electrical characteristics occurring under the conditions of the manufacturing process, thereby excellent process tolerance of the thin film transistor.It is another object of the present invention to provide a display device including the above-described thin film transistor.According to one aspect of the present invention, the above and other objects are achieved by the thin film transistor having the features of claim 1. The thin film transistor includes, among other things, a gate electrode disposed on a substrate, a semiconductor layer disposed to overlap at least a portion of the gate electrode in the state isolated from the gate electrode, a gate insulating film disposed between the gate electrode and the semiconductor layer, a source electrode connected to the semiconductor layer, and a drain electrode connected to the semiconductor layer in the state spaced from the source electrode, the semiconductor layer including a first layer including an oxide semiconductor and a second layer disposed to overlap with the first layer, and wherein an energy bandgap of the first layer is greater than an energy bandgap of the second layer.Preferably, the second layer completely overlaps the first semiconductor layer. Moreover, the second layer has the same size or area as the first layer.The thin film transistor may further include a gate insulating film disposed between the gate electrode and the semiconductor layer, wherein the gate electrode may be disposed to be closer to the substrate than the gate insulating film-based semiconductor layer.The thin film transistor may further include a gate insulating film disposed between the gate electrode and the semiconductor layer, wherein the semiconductor layer may be disposed to be closer to the substrate than the gate electrode based on the gate insulating film.The second layer may be disposed to be closer to the gate electrode than the first layer based on the gate electrode.The first layer may have an energy band gap of 3.0 eV or more.The first layer may contain gallium (Ga) and at least one metal element other than gallium, and the content of gallium may be 1.5 times or more the content of each of the at least one metal elements based on the number of atoms.The two-dimensional semiconductor may be at least one of a transition metal dichalcogenide, single layer CdTe, GaS, GaSe, GaS 1-x Se x, CdI 2, PbI 2, K 2 Al 4( Si 6 Al 2 O 28)( OH, F) 4 and Mg6(Si8O28)(OH)4.The transition metal dichalcogenide may include at least one of molybdenum disulfide (MoS 2), molybdenum diselenide (MoSe 2), molybdenum ditelluride (MoTe 2), tungsten disulfide (WS 2), tungsten diselenide (WSe 2), tungsten ditelluride (WTe 2), niobium disulfide (NbS 2), niobium diselenide (NbSe 2), niobium ditelluride (NbTe 2), tantalum disulfide (TaS 2), The following may be mentioned as examples: tantalum diselenide (TaSe 2), tantalum diselenide (TaTe 2), hafnium disulfide (HfS 2), hafnium diselenide (HfSe 2), hafnium diselenide (HfTe 2), titanium disulfide (TiS 2), titanium diselenide (TiSe 2) and titanium diselenide (TiTe 2).The second layer may be a channel layer.The second layer may have an energy band gap in the range of 1.0 to 1.5 eV.The second layer may have a structure in which a plurality of layers each made of a two-dimensional semiconductor are stacked.The second layer may have a thickness in the range of 1.5 to 5 nm.The semiconductor layer may further include a third layer disposed between the first layer and the second layer, the third layer being made of a two-dimensional semiconductor.An energy band gap of the third layer may be smaller than the energy band gap of the first layer and larger than the energy band gap of the second layer.The third layer may have an energy band gap in the range of 1.6 to 2.5 eV.The third layer may be composed of a single layer made of the two-dimensional semiconductor.The second layer may have a thickness in the range of 0.5 to 1.4 nm.The third layer may include any one of molybdenum disulfide (MoS 2) and tungsten disulfide (WS 2).Preferably, the thickness of the first layer may be in the range of 10 to 50 nm.According to another aspect of the present invention, there is provided a display device including a substrate, a thin film transistor disposed on the substrate, and a first electrode connected to the thin film transistor, the thin film transistor including a gate electrode disposed on the substrate, a semiconductor layer disposed to overlap at least a portion of the gate electrode in the state of being insulated from the gate electrode, a gate insulating film disposed between the gate electrode and the semiconductor layer, a source electrode connected to the semiconductor layer, and a drain electrode connected to the semiconductor layer in the state of being spaced apart from the source electrode, the semiconductor layer including a first layer, including an oxide semiconductor and a second layer disposed to overlap with the first layer in a plan view, wherein the second layer includes a two-dimensional semiconductor, and wherein an energy band gap of the first layer is larger than an energy band gap of the second layer.Preferably, the display device can be a flexible display device.BRIEF DESCRIPTION OF THE DRAWINGSThe above and other objects, features and other advantages of the present invention will become apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which: FIG. 1 is a cross-sectional view of a thin film transistor according to an embodiment of the present invention; FIG. 2 is a schematic perspective view showing the structure of a two-dimensional semiconductor; FIG. 3 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention; FIG. 4 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention; FIG. 5 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention; FIG. 6 is a diagram of an energy band gap; FIG. 7 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention; FIG. 8 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention; FIG. 9 is a schematic cross-sectional view of a display device according to another embodiment of the present invention; FIG. 10 is a schematic cross-sectional view of a display device according to another embodiment of the present invention; and FIGS. 11 to 16 are views showing the results of measurement of the threshold voltage of a thin film transistor according to Comparative Examples and Examples.DETAILED DESCRIPTION OF THE INVENTIONAdvantages and features of the present invention and implementation methods thereof will be made apparent by the following embodiments described with reference to the accompanying drawings. The present invention may, however, be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Further, the present invention is defined only by the scope of the claims.The shapes, sizes, proportions, angles, and numbers disclosed in the drawings for describing the embodiments of the present invention are merely examples, and thus the present invention is not limited to the details illustrated. Like reference numerals refer to like elements throughout. In the following description, when it is determined that the detailed description of the relevant known function or configuration unnecessarily obscures the important point of the present invention, the detailed description is omitted.In the case where "include", "have", and "contain" described in the present specification are used, another part may also be present unless "only" is used. The terms in the singular form may include plural forms unless indicated to the contrary.In interpreting an element, the element is construed to include an error region, although no explicit description thereof is provided.In describing a positional relationship, for example, when the order of the positions is described as "on", "above", "below", and "next", there may be included the case where no contact exists therebetween unless "immediately" or "directly" is used. If it is mentioned that a first element is positioned "on" a second element, this does not mean that the first element is actually positioned above the second element in the figure. The upper part and the lower part of an object concerned may be interchanged depending on the orientation of the object. Thus, the case where the first element is positioned "on" a second element includes both the case where the first element is positioned "below" the second element and the case where the first element is positioned "above" the second element in the figure or in an actual configuration. When one layer is laminated on another layer in a cross-sectional view, it says that the two layers overlap each other.In describing a temporal relationship, for example, when the temporal order is described as "after", "after", "next", and "before", a case that is not continuous may be included unless "immediately" or "directly" is used.It is to be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the present invention.It is understood that the term "at least one" includes all combinations belonging to any element. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first, second, and third elements as well as each element among the first, second, and third elements.Features of various embodiments of the present invention may be partially or wholly coupled or combined with each other and may cooperate and be technically driven in various ways as those skilled in the art can sufficiently understand. The embodiments of the present invention may be carried out independently of each other or may be carried out together in a relationship of dependency.Hereinafter, a thin film transistor and a display device including the same according to embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same or similar elements are denoted by the same reference numerals even though they are depicted in different drawings.FIG. 1 is a schematic cross-sectional view of a thin film transistor 100 according to an embodiment of the present invention.The thin film transistor 100 according to the embodiment of the present invention includes a gate electrode 110 disposed on a substrate 101, a semiconductor layer 120 disposed to overlap at least a portion of the gate electrode 110 in the state of being insulated from the gate electrode 110, a gate insulating film 150 disposed between the gate electrode 110 and the semiconductor layer 120, a source electrode 130 connected to the semiconductor layer 120, and a drain electrode connected to the semiconductor layer 120 in a state of being spaced apart from the source electrode 130. The semiconductor layer 120 includes a first layer 121 including an oxide semiconductor and a second layer 122 that overlaps the first layer 121 in a plan view and that includes a two-dimensional semiconductor. Here, an energy band gap of the first layer 121 is larger than an energy band gap of the second layer 122.The structure of the thin film transistor 100 will be described in detail below.Glass or plastic may be used as the substrate 101. Transparent resin showing flexibility, such as polyimide, may be used as the resin.In the case where polyimide is used as the substrate 101, heat-resistant polyimide that resists high temperatures may be used in consideration of the fact that a high-temperature deposition process is performed on the substrate 101. In this case, processes such as deposition and etching may be performed in the state where the polyimide substrate is disposed on a support substrate made of high-resistivity material such as glass to form the thin film transistor 100.A buffer layer 160 may be disposed on the substrate 101.The buffer layer 160 may include at least one of a silicon oxide and a silicon nitride. The buffer layer 160 exhibits a high insulation property, high moisture and oxygen barrier properties, and a planar property. The buffer layer 160 protects the semiconductor layer 120. The buffer layer 160 may be formed to have a single layer, or multiple layers made of different materials may be stacked to form the buffer layer 160. The buffer layer 160 disposed on the substrate 101 may also be referred to as a passivation layer. The buffer layer 160 may be omitted.The gate electrode 110 is disposed on the substrate 101. The gate electrode 110 may include at least one of an aluminum-based metal such as (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 110 may have a structure of multiple thin films including at least two conductive thin films having different physical properties.The gate insulating film 150 is disposed on the gate electrode 110. The gate insulating film 150 serves as an insulating film between the semiconductor layer 120 and the gate electrode 110.The gate insulating film 150 may include at least one of a silicon oxide and a silicon nitride. The gate insulating film may include an aluminum oxide (Al 2 O 3) or a hafnium oxide (HfO x).The gate insulating film 150 may have a single-layer film structure or a multi-layer film structure. For example, any one of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, and a hafnium oxide layer may individually form the gate insulating film 150. Alternatively, the silicon oxide layer, the silicon nitride layer, the aluminum oxide layer, and the hafnium oxide layer may be stacked to form the gate insulating film 150.The semiconductor layer 120 is disposed on the gate insulating film 150. The semiconductor layer 120 is insulated from the gate electrode 110 and overlaps at least a portion of the gate electrode 110. The structure of the semiconductor layer 120 will be described in detail later.The source electrode 130 is disposed to be connected to the semiconductor layer 120. The drain electrode 140 is connected to the semiconductor layer 120, the drain electrode 140 being spaced apart from the source electrode 130. Referring to FIG. 1, the source electrode 130 and the drain electrode 140 are disposed on the gate insulating film 150 and overlap at least a portion of the semiconductor layer 120. Each of the source electrode 130 and the drain electrode 140 is in direct contact with the semiconductor layer 120 with a distance between the source electrode 130 and the drain electrode 140. Thus, both the source electrode 130 and the drain electrode 140 overlap the semiconductor layer 120 at different positions of the semiconductor layer 120.Each of the source electrode 130 and the drain electrode 140 may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and an alloy thereof. Each of the source electrode 130 and the drain electrode 140 may be formed to include a single layer made of a metal or an alloy of metals, or may be formed to include multiple layers, such as two or more layers.The structure in which the gate electrode 110 is disposed below the semiconductor layer 120 as shown in FIG. 1 is referred to as a gate-below structure. Here, the semiconductor layer 120, the gate electrode 110, the source electrode 130, and the drain electrode 140 form the thin film transistor 100.The structure of the semiconductor layer 120 will be described in detail below.A semiconductor layer 120 according to an embodiment of the present invention includes a first layer 121 including an oxide semiconductor and a second layer 122 overlapping with the first layer 121. In a plan view, there is preferably a full or complete overlap between the first layer 121 and the second layer 122. The second layer 122 includes a two-dimensional semiconductor. In the present invention, "the second layer 122 overlaps with the first layer 121 in a plan view" means that the second layer 122 is laminated or disposed on the first layer 121 in a cross-sectional view, or that the first layer 121 is laminated or disposed on the second layer 122 in a cross-sectional view. Sometimes, "the second layer 122 overlaps with the first layer in a plan view" is expressed as "the second layer 122 overlaps with the first layer 121 in a cross-sectional view.".According to an embodiment of the present invention, the second layer 122 is arranged to be closer to the gate electrode 110 than the first layer based on the gate electrode 110. Referring to FIG. 1, the gate electrode 110, the second layer 122, and the first layer 121 are sequentially arranged. That is, the first layer 121 is disposed on the second layer 122 on the basis of the figure.The first layer 121 includes an oxide semiconductor. Specifically, the first layer 121 may be made of an oxide semiconductor. The first layer 121 may also be referred to as an oxide semiconductor layer. The first layer 121 containing an oxide semiconductor serves as a support layer for supporting the second layer 122, and protects the second layer 122.The first layer 121 includes gallium (Ga). For example, the first layer 121 may be made of a gallium-based (Ga-based) oxide semiconductor. The gallium-based (Ga-based) oxide semiconductor exhibits high resistance to gases such as oxygen and high process stability. Consequently, the first layer 121 formed of a gallium-based (Ga-based) oxide semiconductor can effectively support and protect the second layer 122. According to an embodiment of the present invention, the first layer 121 contains only gallium (Ga) as a metal element. However, the present invention is not limited thereto. The first layer 121 may further include (a) metal(s) other than gallium (Ga). For example, the first layer 121 may further include at least one of indium (In), zinc (Zn), and tin (Sn). For example, the first layer 121 may include an InGaZnO (IGZO)-based oxide semiconductor, an InGaZnSnO (IGZTO)-based oxide semiconductor, a GaZnSnO (GZTO)-based oxide semiconductor, an InGaO (IGO)-based oxide semiconductor, an InSnZnO (ITZO)-based oxide semiconductor, or an InSnO (ITO)-based oxide semiconductor.In the case where the first layer 121 further includes metal elements other than gallium (Ga), the content of gallium (Ga) of the first layer 121 may be 1.5 times or more the content of each of the other metal elements based on the number of atoms. For example, in the case where the first layer 121 contains gallium (Ga) and a first metal element, the content of gallium (Ga) is 1.5 times or more the content of the first metal element based on the number of atoms. In this case, the content of gallium (Ga) may be 60% or more of the total content of the metal elements included in the first layer 121 based on the number of atoms. In addition, in the case where the first layer 121 contains gallium (Ga), a first metal element, and a second metal element, the content of gallium (Ga) is 1.5 times or more the content of the first metal element based on the number of atoms, and is 1.5 times or more the content of the second metal element based on the number of atoms. The same applies to the case where the first layer 121 further includes three or more metal elements in addition to gallium (Ga).According to an embodiment of the present invention, the first layer 121 has an energy band gap of 3.0 eV or more. In particular, the first layer 121 may have an energy band gap in the range of 3.0 to 4.0 eV.It is not easy to form a first layer 121 having an energy band gap of less than 3.0 eV using an oxide semiconductor containing a relatively large amount of gallium. In the case where the first layer 121 has an energy band gap of less than 3.0 eV, the stability of the first layer 121 is reduced, whereby the function of the first layer 121 as the layer for supporting the second layer 122 may be deteriorated. Thus, the first layer 121 is configured to have an energy band gap of 3.0 eV or more. In addition, the first layer 121 may have an energy band gap of 4.0 eV or less in consideration of manufacturing ease and material properties. However, the present invention is not limited thereto. The first layer 121 may have an energy band gap of more than 4.0 eV.According to an embodiment of the present invention, the first layer 121 may have a thickness in the range of 10 to 50 nm. In the case where the thickness of the first layer 121 is less than 10 nm, the stability of the first layer 121 is reduced and the first layer 121 cannot sufficiently support the second layer 122. On the other hand, in a case where the thickness of the first layer 121 is greater than 50 nm, it is difficult to provide a thin film transistor 100.The second layer 122 includes a two-dimensional semiconductor.The two-dimensional semiconductor has a thickness measured in units of an atomic layer or an atomic diameter, and is generally formed in a planar shape. In a layer (e.g., an in-plane layer) of the two-dimensional semiconductor, atoms are bonded to each other via covalent bonding, whereby the atoms have a high bonding force. However, the bonding force between layers is less than the bonding force within each layer. The two-dimensional semiconductor may be insulated in the form of a single layer or mechanically laminated in the form of a thin film having a plurality of stacked layers.According to an embodiment of the present invention, the two-dimensional semiconductor is defined as a semiconductor consisting of 2D layered materials in which atoms are bonded to each other in covalent bond in a layer while the atoms are not chemically bonded across layers, and the bond between the layers is Van der Waals bond.The two-dimensional semiconductor may include at least one of a transition metal dichalcogenide, GaS, GaSe, GaS 1-x Se x, CdI 2, PbI 2, K 2 Al 4( Si 6 Al 2 O 28)( OH,F) 4, Mg6(Si8O28)(OH)4, and single-layer CdTe.FIG. 2 is a schematic perspective view showing the structure of the two-dimensional semiconductor. Specifically, FIG. 2 illustrates a two-dimensional semiconductor expressed by the general formula MX 2. Here, M indicates a Group IVB, Group VB, or Group VIB transition metal in the periodic table of the elements, and X indicates a chalcogen element such as sulfur (S), selenium (Se), or tellurium (Te).For example, a two-dimensional transition metal dichalcogenide (TMD) is expressed as a two-dimensional semiconductor by the general formula MX 2. The ultra-thin layer of the two-dimensional transition metal dichalcogenide containing one monolayer or a plurality of stacked monolayers exhibits an excellent transport property. Such layered materials exhibit various electrical properties. For example, the layered materials have an indirect band gap in a base type multilayer structure and have a direct band gap in a thin film structure.According to an embodiment of the present invention, a transition metal dichalcogenide may be used as the two-dimensional semiconductor. For example, the transition metal dichalcogenide may include at least one of molybdenum disulfide (MoS 2), molybdenum diselenide (MoSe 2), molybdenum diselenide (MoTe 2), tungsten disulfide (WS 2), tungsten diselenide (WSe 2), tungsten diselenide (WTe 2), niobium disulfide (NbS 2), niobium diselenide (NbSe 2), niobium diselenide (NbTe 2), tantalum disulfide (TaS 2), The following may be mentioned as examples: tantalum diselenide (TaSe 2), tantalum diselenide (TaTe 2), hafnium disulfide (HfS 2), hafnium diselenide (HfSe 2), hafnium diselenide (HfTe 2), titanium disulfide (TiS 2), titanium diselenide (TiSe 2) and titanium diselenide (TiTe 2).According to an embodiment of the present invention, the second layer 122 may include at least one of molybdenum ditelluride (MoTe 2), molybdenum diselenide (MoSe 2), tungsten diselenide (WSe 2) and tungsten ditelluride (WTe 2). In the case where the second layer 122 is formed to have a structure in which two or more layers of the two-dimensional semiconductor are stacked, the second layer 122 may have an energy band gap in the range of 1.0 to 1.5 eV.According to an embodiment of the present invention, a channel region of the thin film transistor 100 may be formed in the second layer 122 of the semiconductor layer 120. That is, in the thin film transistor 100 of FIG. 1, the second layer 122 is a channel layer. In the case where the second layer serves as a channel layer, when the second layer 122 made of a two-dimensional semiconductor is disposed to be closer to the gate electrode than the first layer 121 made of an oxide semiconductor, the second layer 122 can serve more effectively than the channel layer and can be more effectively protected by the first layer 121. However, the present invention is not limited thereto. The channel layer may be formed in the first layer 121.The second layer 122 has an energy band gap in the range of 1.0 to 1.5 eV. The second layer 122 having the above-defined energy band gap may effectively serve as a channel layer. In the case where the energy band gap of the second layer 122 is less than 1.0 eV, the second layer 122 may be difficult to serve as a semiconductor layer due to its high conductivity. On the other hand, in the case where the energy band gap of the second layer 122 is greater than 1.5 eV, the mobility of the second layer 122 may be reduced.The second layer 122 may have a structure in which a plurality of layers each made of a two-dimensional semiconductor are stacked. For example, as shown in FIG. 2, a plurality of layers each made of a two-dimensional semiconductor having the composition MX 2 (hereinafter referred to as "two-dimensional semiconductor layers") may be stacked to form the second layer 122. The two-dimensional semiconductor layers forming the second layer 122 may be coupled to each other by van der Waals force.More specifically, the second layer 122 may have a structure in which two to ten layers each made of a two-dimensional semiconductor are stacked. For example, two two two-dimensional layers may be stacked to form the second layer 122. Alternatively, three or more two-dimensional layers may be stacked to form the second layer 122.In the case where a plurality of two-dimensional semiconductor layers are stacked, the energy band gap of the second layer 122 may be reduced. Specifically, a stack formed by stacking a plurality of two-dimensional semiconductor layers has an energy band gap smaller than the energy band gap of a single two-dimensional semiconductor layer. As the number of two-dimensional semiconductor layers stacked increases, the energy band gap of the second layer 122 is reduced. Consequently, the second layer 122, which is a stack formed by stacking a plurality of two-dimensional semiconductor layers, can have an excellent channel property.According to an embodiment of the present invention, the second layer 122 may have a thickness of 1.5 to 5 nm, for example. It is not easy that the second layer 122 formed by stacking a plurality of two-dimensional semiconductor layers has a thickness of less than 1.5 nm. On the other hand, since the energy band gap of the second layer 122 is no longer substantially reduced even when the thickness of the second layer 122 is more than 5 nm, it is not necessary that the thickness of the second layer 122 exceeds 5 nm in consideration of the process of thinning a device and the cost for manufacturing the device. However, the present invention is not limited thereto. The thickness of the second layer 122 may exceed 5 nm.The semiconductor layer 120 according to the embodiment of the present invention including a first layer 121 made of an oxide semiconductor and a second layer 122 made of a two-dimensional semiconductor may have excellent mobility, small thickness, and transparency. The thin film transistor 100 according to the embodiment of the present invention including the semiconductor layer 120 may exhibit excellent current characteristics, flexibility, and transparency.In addition, the semiconductor layer 120 according to the embodiment of the present invention may form a short channel having a channel length of 4 μm or less. Here, the channel length may be defined as the distance between the source electrode 130 and the drain electrode 140. Therefore, in the case where the semiconductor layer 120 according to the embodiment of the present invention is used, the area of the thin film transistor 100 can be reduced. Consequently, the thin film transistor 100 can be used to fabricate an ultra-high density or ultra-high resolution display device.Specifically, the thin film transistor 100 according to the embodiment of the present invention can be applied to a large-area display device or a high-resolution display device, so that the display device exhibits excellent display property and flexibility. In addition, a substrate 101 exhibiting flexibility may be used to fabricate a flexible display device.According to an embodiment of the present invention, the second layer 122 made of a two-dimensional semiconductor is supported and protected by the first layer 121 made of an oxide semiconductor. As a result, damage to the second layer 122 is prevented during the manufacture of the semiconductor layer 120 or during the use of the display device, whereby the second layer 122 can maintain the inherent characteristics of the two-dimensional semiconductor. Accordingly, as compared with the case where the semiconductor layer is formed using only the two-dimensional semiconductor, the region where materials for the passivation film or the insulating film are selected can be widened, and the region where process temperatures such as those of deposition or heat treatment are selected can also be widened. According to the present invention, therefore, process reliability and stability can be improved.FIG. 3 is a cross-sectional view of a thin film transistor 200 according to another embodiment of the present invention. Hereinafter, description of the components already described above will be omitted to avoid duplication of the description.In comparison with the thin film transistor 100 shown in FIG. 1, the thin film transistor 200 shown in FIG. 3 further includes an etch stop 180 disposed on the semiconductor layer 120. The etch stop 180 may at least partially overlap with the semiconductor layer 120 and the gate electrode. The etch stop 180 may be made of an insulating material such as silicon oxide. The etch stop 180 may protect a channel region of the semiconductor layer 120. Thus, the semiconductor layer 120 according to the embodiment of the present invention may be applied to a thin film transistor 200 having an etch stopper structure.FIG. 4 is a cross-sectional view of a thin film transistor 300 according to another embodiment of the present invention.The thin film transistor 300 shown in FIG. 4 includes a buffer layer 160 disposed on a substrate 101, a semiconductor layer 120 disposed on the buffer layer 160, and a gate electrode 110 disposed to overlap with at least a portion of the semiconductor layer 120. The gate electrode 110 is insulated from the semiconductor layer 120, a gate insulating film 150 disposed between the gate electrode 100 and the semiconductor layer 120, an interlayer insulating film 170 disposed on the gate insulating film 110, a source electrode 130 connected to the semiconductor layer 120, and a drain electrode 140 connected to the semiconductor layer 120, the drain electrode 140 being spaced apart from the source electrode 130.Although not shown, a light blocking layer (not shown) may be disposed between the substrate 101 and the buffer layer 160 or on the buffer layer 160. The light blocking layer protects the semiconductor layer 120 from light.The semiconductor layer 120 includes a first layer 121 including an oxide semiconductor and a second layer 122 that overlaps the first layer 121 in a plan view and that includes a two-dimensional semiconductor. The second layer 122 is disposed to be closer to the gate electrode 110 than the first layer 121 is on the basis of the gate electrode 110. Referring to FIG. 4, the semiconductor layer 120 has a structure in which the second layer 122 is disposed on the first layer 121. The second layer 122 is a channel layer including a channel region.The second layer 122 of the semiconductor layer 120 may have a structure in which a plurality of layers each of which is made of a two-dimensional semiconductor are stacked. For example, as shown in FIG. 2, multiple layers each of which is made of a two-dimensional semiconductor having the composition MX 2 (i.e., "two-dimensional semiconductor layers") may be stacked to form the second layer 122.The gate insulating film 150 is disposed on the semiconductor layer 120, and the gate electrode 110 is disposed on the gate insulating film 150. The gate electrode 110 is insulated from the semiconductor layer 120 by the gate insulating film 150.The interlayer insulating film 170 is disposed on the gate electrode 110. The interlayer insulating film 170 is made of an insulating material. Specifically, the interlayer insulating film 170 may be made of an organic material, an inorganic material, or a stack including an organic material layer and an inorganic material layer.The source electrode 130 and the drain electrode 140 are disposed on the interlayer insulating film 170. The source electrode 130 and the drain electrode 140 are connected to the semiconductor layer 120 with both being spaced apart from each other. Referring to FIG. 4, the source electrode 130 and the drain electrode 140 are connected to the semiconductor layer 120 via contact holes formed by the interlayer insulating film 170.The structure in which the gate electrode 110 is disposed above the semiconductor layer 120 as shown in FIG. 4 is referred to as an upper gate structure. The semiconductor layer 120, the gate electrode 110, the source electrode 130, and the drain electrode 140 form the thin film transistor 300.FIG. 5 is a cross-sectional view of a thin film transistor 400 according to another embodiment of the present invention. The thin film transistor 400 shown in FIG. 5 further includes a third layer 123 provided in the semiconductor layer 120 as compared to the thin film transistor 100 shown in FIG. 1.Specifically, the semiconductor layer 120 of the thin film transistor 400 according to the embodiment of the present invention further includes a third layer 123 that is disposed between the first layer 121 and the second layer 122 and that is made of a two-dimensional semiconductor. Referring to FIG. 5, the semiconductor layer 120 includes a second layer 122, a third layer 123, and a first layer 121 sequentially stacked.The third layer 123 serves as an intermediate layer between the first layer 121 made of an oxide semiconductor and the second layer 122 made of a two-dimensional semiconductor. In addition, the third layer 123 serves to increase the bonding force between the first layer 121, which is a support layer, and the second layer 122, which is a channel layer.In the case where the first layer 121 made of an oxide semiconductor and the second layer 122 made of a two-dimensional semiconductor are directly in contact with each other, interaction may occur at the interface between the first layer 121 and the second layer 122. As a result, the second layer 122 may be partially damaged, atoms may move between the first layer 121 and the second layer 122, or chemical coupling may occur between the first layer 121 and the second layer 122. In this case, the two-dimensional semiconductor constituting the second layer 122 may be damaged. In addition, the energy band gap of the second layer 122 may be increased, whereby the function of the second layer 122 as a channel layer may be reduced. In particular, the second layer 122 may be damaged due to the contact of the second layer 122 with the first layer 121 because the difference in energy band gap between the first layer 121 and the second layer 122 is large.In addition, in the case where the first layer 121 and the second layer 122 are in direct contact with each other, under some severe conditions, the first layer 121 and the second layer 122 may be delaminated from each other, whereby the reliability of the semiconductor layer 120 may be reduced.The third layer 123 may be disposed between the first layer 121 and the second layer 122 to prevent direct contact between the first layer 121 and the second layer 122, and at the same time to allow the first layer 121 and the second layer 122 to more stably couple with each other.For example, the third layer 123 is in contact with the first layer 121 to interact with the first layer 121. As a result, the third layer 123 and the first layer 121 may be stably coupled to each other. In addition, the third layer 123 may be stably bonded to the second layer 122, because the third layer 123 is made of a two-dimensional semiconductor, in the same manner as the second layer 122. The third layer 123 and the second layer 122 may be bonded to each other by a van der Waals force.Meanwhile, even in the case where the structure of the two-dimensional semiconductor constituting the third layer 123 is partially damaged due to the contact of the third layer 123 with the first layer 121, the driving characteristics of the semiconductor layer 120 and the thin film transistor 400 are not deteriorated because the second layer 122 serving as a channel layer is independently provided.According to another embodiment of the present invention, the energy band gap of the third layer 123 is constructed to be smaller than the energy band gap of the first layer 121 and larger than the energy band gap of the second layer 122, so that the third layer 123 is disposed between the first layer 121 and the second layer 122 to be stably coupled to the first layer 121 and the second layer 122.The third layer 123 may have an energy band gap of 1.6 to 2.5 eV, for example, in consideration of the energy band gap of the first layer 121 and the energy band gap of the second layer 122. As described earlier, the first layer 121 has an energy band gap in the range of 3.0 to 4.0 eV and the second layer 122 has an energy band gap in the range of 1.0 to 1.5 eV.FIG. 6 is a diagram of the energy band gap. Referring to FIG. 6, a sudden change in energy band gap between the first layer 121 and the second layer 122 is prevented because the third layer 123 is disposed between the first layer 121 and the second layer 122. As a result, the first layer 121, the third layer 123, and the second layer 122 can be stably coupled to each other, and damage to the second layer 122, which is a channel layer, due to the first layer 121, which is a support layer, can be prevented, whereby the thin film transistor 400 can exhibit excellent driving characteristics.The third layer 123 is made of a layer made of a two-dimensional semiconductor (i.e., a two-dimensional semiconductor layer). For example, the third layer may be composed of a single layer made of a two-dimensional semiconductor. That is, the third layer 123 may be composed of a single two-dimensional semiconductor layer.A single two-dimensional semiconductor layer has an energy band gap larger than the energy band gap of a stack formed by stacking a plurality of two-dimensional semiconductor layers. Therefore, in the case where the third layer 123 is composed of a single two-dimensional semiconductor layer, the third layer 123 may have an energy band gap equivalent to a value between the energy band gap of the first layer 121 and the energy band gap of the second layer 122. That is, in the case where the third layer 123 is composed of a single two-dimensional semiconductor layer, the third layer 123 may have an energy band gap in the range of 1.6 to 2.5 eV.The third layer 123 may have a thickness in the range of 0.5 to 1.4 nm. It is not easy to form a two-dimensional semiconductor layer having a thickness of less than 0.5 nm. It is also not easy for a single two-dimensional semiconductor layer to have a thickness of more than 1.4 nm.The third layer 123 may include any one of molybdenum disulfide (MoS 2) and tungsten disulfide (WS 2). A single-layer two-dimensional semiconductor layer made of molybdenum disulfide (MoS 2) and a single-layer two-dimensional semiconductor layer made of tungsten disulfide (WS 2) can be used as the third layer 123, because each of the above-mentioned single-layer two-dimensional semiconductor layers may have an energy band gap in the range of 1.6 to 2.5 eV.FIG. 7 is a cross-sectional view of a thin film transistor 500 according to another embodiment of the present invention.In comparison with the thin film transistor 400 shown in FIG. 5, the thin film transistor 500 shown in FIG. 7 further includes an etch stop 180 disposed on the semiconductor layer 120. In particular, the etch stop 180 is arranged on the first layer 121 of the semiconductor layer 120. The etch stop 180 may be made of an insulating material such as silicon oxide. The etch stop 180 may protect a channel region of the semiconductor layer 120.FIG. 8 is a cross-sectional view of a thin film transistor 600 according to another embodiment of the present invention.The thin film transistor 600 shown in FIG. 8 further includes a third layer 123 provided in the semiconductor layer 120, unlike the thin film transistor 300 shown in FIG. 4. In particular, the thin film transistor 600 of FIG. 8 further includes a third layer 123 that is disposed between a first layer 121 and a second layer 122 of the semiconductor layer 120 and that is made of a two-dimensional semiconductor. Referring to FIG. 8, the semiconductor layer 120 includes a first layer 121, a third layer 123, and a second layer 122 which are sequentially stacked.The third layer 123 serves as an intermediate layer between the first layer 121 made of an oxide semiconductor and the second layer 122 made of a two-dimensional semiconductor. In addition, the third layer 123 serves to increase the coupling force between the first layer 121, which is a support layer, and the second layer 122, which is a channel layer.FIG. 9 is a schematic cross-sectional view of a display device 700 according to another embodiment of the present invention.The display device 700 according to the embodiment of the present invention includes a substrate 101, a thin film transistor 400, and an organic light emitting device 270 connected to the thin film transistor 400.Although the display device 700 including the thin film transistor 400 of FIG. 5 is shown in FIG. 9, the thin film transistors 100, 200, 300, 500, and 600 shown in FIGS. 1, 3, 4, 7, and 8 may be applied to the display device 700 of FIG. 9 in addition to the thin film transistor 400 of FIG. 5.Referring to FIG. 9, the display device 700 according to the embodiment of the present invention includes a substrate 101, a thin film transistor 400 disposed on the substrate 101, and a first electrode 271 connected to the thin film transistor 400. In addition, the display device 700 includes an organic layer 272 disposed on the first electrode 271 and a second electrode 273 disposed on the organic layer 272.In particular, the substrate 101 may be made of glass or plastic. For a flexible display device, transparent resin exhibiting flexibility, such as polyimide, may be used as the substrate 101.A buffer layer 160 may be disposed on the substrate 101. The buffer layer 160 may be omitted.The thin film transistor 400 is disposed on the buffer layer 160 disposed on the substrate 101. The thin film transistor 400 includes a gate electrode 110 disposed on the substrate 101, a semiconductor layer 120 disposed to overlap at least a portion of the gate electrode 110 in the state of being insulated from the gate electrode 110, a gate insulating film 150 disposed between the gate electrode 110 and the semiconductor layer 120, a source electrode 130 connected to the semiconductor layer 120, and a drain electrode connected to the semiconductor layer 120 in a state of being spaced apart from the source electrode 130.The semiconductor layer 120 includes a second layer 122, a third layer 123, and a first layer 121 that are sequentially stacked. The first layer 121 is an oxide semiconductor layer made of an oxide semiconductor. The first layer 121 serves as a support. The second layer 122 includes a two-dimensional semiconductor and serves as a channel layer. The second layer 122 may have a structure in which two to ten layers each made of a two-dimensional semiconductor are stacked. The third layer 123 serves as an intermediate layer between the first layer 121 and the second layer 122. The third layer 123 may be made of a single layer made of a two-dimensional semiconductor. The energy band gap of the third layer 123 is smaller than the energy band gap of the first layer 121 and larger than the energy band gap of the second layer 122.A passivation film 190 is disposed on the thin film transistor 400 to protect the thin film transistor 400 and level the upper part of the substrate 101. The passivation film 190 may be made of an organic insulating material exhibiting photosensitivity, such as an acrylic resin. However, the present invention is not limited thereto.The first electrode 271 is disposed on the passivation film 190. The first electrode 271 is connected to the drain electrode 140 of the thin film transistor 400 via a contact hole formed by the passivation film 190.A well layer 250 is disposed on the first electrode 271 and the passivation film 190 to define a pixel region or a light emitting region. For example, the well layer 250 may be arranged at the interface between pixels in a matrix manner, such that the pixel region may be defined by the well layer 250.The organic layer 272 is disposed on the first electrode 271. The organic layer 272 may be disposed on the well layer 250. That is, the organic layer 272 may not be divided for each pixel, but may be continuous between adjacent pixels.The organic layer 272 includes an organic light emitting layer. The organic layer 272 may include a single organic light emitting layer or two or more organic light emitting layers stacked in the vertical direction. The organic layer 272 may emit any of red, green, and blue light. Alternatively, the organic layer 272 may emit white light.The second electrode 273 is disposed on the organic layer 272.The first electrode 271, the organic layer 272, and the second electrode 273 are stacked to form the organic light emitting device 270. The organic light emitting device 270 may serve as a light amount adjustment layer in the display device 700.Although not shown, in the case where the organic layer 272 emits white light, each pixel may include a color filter for filtering the white light emitted from the organic layer 272 for each wavelength. The color filter is formed on a light propagation path. In a so-called bottom emission type structure in which light emitted from the organic layer 272 propagates to the substrate 101 disposed below the organic layer 272, the color filter is disposed below the organic layer 272. In a so-called top emission type structure in which light emitted from the organic layer 272 propagates to the second electrode 273 disposed above the organic layer 272, the color filter is disposed above the organic layer 272.FIG. 10 is a schematic cross-sectional view of a display device 800 according to another embodiment of the present invention.Referring to FIG. 10, the display device 800 according to the embodiment of the present invention includes a substrate 101, a thin film transistor 400 disposed on the substrate 101, and a first electrode 381 connected to the thin film transistor 400. In addition, the display device 800 includes a liquid crystal layer 382 disposed on the first electrode 381 and a second electrode 383 disposed on the liquid crystal layer 382.The liquid crystal layer 382 serves as a light amount adjustment layer. As described above, the display device 800 shown in FIG. 10 is a liquid crystal display device including a liquid crystal layer 382.Specifically, the display device 800 of FIG. 10 includes a substrate 101, a thin film transistor 400, a passivation film 190, a first electrode 381, a liquid crystal layer 382, a second electrode 383, a blocking layer 320, color filters 341 and 342, a light blocking unit 350, and a counter substrate 102.The substrate 101 may be made of glass or plastic.The thin film transistor 400 is disposed on the substrate.Referring to FIG. 10, a buffer layer 160 is disposed on the substrate 101, a gate electrode 110 is disposed on the buffer layer 160, a gate insulating film 150 is disposed on the gate electrode 110, a semiconductor layer 120 is disposed on the gate insulating film 150, a source electrode 130 and a drain electrode 140 are disposed on the semiconductor layer 120, and the passivation film 190 is disposed on the source electrode 130 and the drain electrode 140.FIG. 10 shows a thin film transistor 400 having a bottom gate structure in which the gate electrode 110 is disposed below the semiconductor layer 120. However, the present invention is not limited thereto. Alternatively, a thin film transistor having an upper gate structure in which the gate electrode 110 is disposed above the semiconductor layer 120 may be used. In addition, the thin film transistors 100, 200, 300, 500, and 600 shown in FIGS. 1, 3, 4, 7, and 8 may be applied to the display device 800 of FIG. 10, in addition to the thin film transistor 400 of FIG. 5.The passivation film 190 is disposed on the thin film transistor 400 to level the upper part of the substrate 101. The passivation film 190 may be made of an organic insulating material exhibiting photosensitivity, such as an acrylic resin. However, the present invention is not limited thereto.The first electrode 381 is disposed on the passivation film 190. The first electrode 381 is connected to the drain electrode 140 of the thin film transistor 400 via a contact hole CH formed through the passivation film 190.The counter substrate 102 is disposed to be opposite to the substrate 101.The light blocking unit 350 is disposed on the counter substrate 102. The light blocking unit 350 has a plurality of openings therein. The openings are arranged to correspond to the first electrodes 381, which are pixel electrodes. The light blocking unit 350 blocks passage of light through the remaining portion thereof outside the openings. The light blocking unit 350 is not essential and thus may be omitted.The color filters 341 and 342 are disposed on the counter substrate 102 and selectively block the wavelength of light incident from a backlight unit (not shown). Specifically, the color filters 341 and 342 may be disposed in the openings defined by the light blocking unit 350.Each of the color filters 341 and 342 may express any one of red, green, and blue. Each of the color filters 341 and 342 may express a color other than red, green, or blue.The blocking layer 320 may be disposed on the color filters 341 and 342 and the light blocking unit 350. The barrier layer 320 may be omitted.The second electrode 383 is disposed on the barrier layer 320. For example, the second electrode 383 may be disposed in front of the counter substrate 102. The second electrode 383 may be made of a transparent conductive material such as ITO or IZO.The first electrode 381 and the second electrode 383 are disposed so as to be opposed to each other, and the liquid crystal layer 382 is disposed between the first electrode 381 and the second electrode 383. The second electrode 383 applies an electric field to the liquid crystal layer 382 together with the first electrode 381.Assuming that the surfaces of the substrate 101 and the counter substrate 102 facing each other between the first substrate 101 and the counter substrate 102 are defined as upper surfaces of the substrate 101 and the counter substrate 102, and the surfaces of the substrate 101 and the counter substrate 102 facing the upper surfaces thereof are defined as lower surfaces of the substrate 101 and the counter substrate 102, a polarizing plate may be disposed on each of the lower surfaces of the substrate 101 and the counter substrate 102.Hereinafter, the present invention will be described in more detail with reference to Examples, Comparative Examples and Experimental Examples. FIGS. 11 to 16 are views showing the results of measurement of the threshold voltage V th of a thin film transistor according to Comparative Examples and Examples.[Example 1]A gate electrode 110 made of an alloy of Mo and Ti and having a thickness of 100 nm was formed on a substrate 101 made of glass, a gate insulating film 150 made of a silicon oxide was formed on the gate electrode 110, and a semiconductor layer 120 was formed on the gate insulating film 150. Specifically, a second layer 122, which is a two-dimensional semiconductor layer made of molybdenum ditelluride (MoTe 2) and having a two-layered structure, was formed on the gate electrode 110, a third layer 123, which is a two-dimensional semiconductor layer made of molybdenum disulfide (MoS 2) and having a single-layered structure, was formed on the second layer 122, and a first layer 121, which is an oxide semiconductor layer containing indium (In), gallium (Ga), and zinc (Zn) in a ratio of 1:1.5:1 and having a thickness of 30 nm, was formed on the third layer 123, thereby forming the semiconductor layer 120. Thereafter, a source electrode 130 having a thickness of 100 nm and a drain electrode 140 having a thickness of 100 nm were formed using an alloy of Mo and Ti. The thin film transistor having the structure shown in FIG. 5 as the result of being fabricated as described above is referred to as Example 1.[Comparative Example 1]A thin film transistor was fabricated in the same manner as in Example 1 except that a semiconductor layer consisting of only a second layer 122, which is a two-dimensional semiconductor consisting of molybdenum ditelluride (MoTe 2) and having a two-layered structure, was formed. The thin film transistor fabricated as described above is referred to as Comparative Example 1.[Measurement of Threshold Voltage]The threshold voltage V th of the thin film transistors according to Example 1 and Comparative Example 1 was measured. To measure the threshold voltage V th the drain current I ds was measured while applying a gate voltage V gs in the range of -20 V to +20 V. A voltage of 10 V and a voltage of 0.1 V were applied across the source electrode 130 and the drain electrode 140. FIGS. 11 and 12 show the results of measurement of the threshold voltage V th of the thin film transistor according to Comparative Example 1 and Example 1.In FIG. 11, A1 indicates the result of measurement of the threshold voltage V th of the thin film transistor according to Comparative Example 1 when a voltage of 10 V was applied across the source electrode 130 and the drain electrode 140, and B1 indicates the result of measurement of the threshold voltage V th of the thin film transistor according to Comparative Example 1 when a voltage of 0.1 V was applied across the source electrode 130 and the drain electrode 140. Referring to FIG. 11, it can be seen that a change ΔV th of the threshold voltage is about 2.87 V and that the slope of a graph of the drain current I ds is not steep in a region of the threshold voltage V th whereby the driving characteristics of the thin film transistor according to Comparative Example 1 are not good.In FIG. 12, A 2 indicates the result of measurement of the threshold voltage V th of the thin film transistor according to Example 1 when a voltage of 10 V was applied across the source electrode 130 and the drain electrode 140, and B 2 indicates the result of measurement of the threshold voltage V th of the thin film transistor according to Example 1 when a voltage of 0.1 V was applied across the source electrode 130 and the drain electrode 140. Referring to FIG. 12, it can be seen that a change ΔV th of the threshold voltage is 0.12 V, which is very small, and that the slope of a graph of the drain current I ds in a region of the threshold voltage V th is very steep, whereby the driving characteristics of the thin film transistor according to Example 1 are excellent.[Examples 2 and 3 and Comparative Examples 2 and 3]A passivation layer made of SiO 2 was formed on each of the thin film transistors made in Example 1 and Comparative Example 1. Specifically, a passivation layer made of SiO 2 was formed by plasma deposition using He / N 2 O / SiH 4- gases. At this time, plasma deposition was carried out under conditions in which energy (kW / m 2) and pressure per unit area were applied as shown in Table 1 below to form a passivation layer on the thin film transistor according to Example 1 and Comparative Example 1, thereby producing the thin film transistors according to Examples 2 and 3 and Comparative Examples 2 and 3. A passivation layer made of SiO 2 may be used as a protection layer, a gate insulating film, or an interlayer insulating film. [Table 1] Table 1] [Table 1] Table 1]Thin-film transistor on which plasma deposition is to be performedExample 1Example 1Comparative Example 1Comparative Example 1Applied energy (kW / m 2)0,71,00,71,0Pressure (T)1,51,21,51,2Thereafter, the threshold voltages V th of the thin film transistor according to Examples 2 and 3 and Comparative Examples 2 and 3 were measured. To measure the threshold voltage V th the drain current I ds was measured while applying a gate voltage V gs in the range of -20 V to +20 V. A voltage of 10 V and a voltage of 0.1 V were applied across the source electrode 130 and the drain electrode 140. FIG. 13 shows the result of measurement of the threshold voltage V th of the thin film transistor according to Comparative Example 2, FIG. 14 shows the result of measurement of the threshold voltage V th of the thin film transistor according to Example 2, FIG. 15 shows the result of measurement of the threshold voltage V th of the thin film transistor according to Comparative Example 3, and FIG. 16 shows the result of measurement of the threshold voltage V th of the thin film transistor according to Example 3.In FIG. 13, A 3 indicates the result of measurement of the threshold voltage V th of the thin film transistor according to Comparative Example 2 when a voltage of 10 V was applied across the source electrode 130 and the drain electrode 140, and B 3 indicates the result of measurement of the threshold voltage V th of the thin film transistor according to Comparative Example 2 when a voltage of 0.1 V was applied across the source electrode 130 and the drain electrode 140. Referring to FIG. 13, it can be seen that a change ΔV th of the threshold voltage is -4.55 V indicating a large distribution of the threshold voltage, and that the slope of a graph of the drain current I ds in a region of the threshold voltage V th is smooth, whereby the driving characteristics of the thin film transistor according to Comparative Example 2 are not good.In addition, as compared with the result of measurement of the threshold voltage V th of the thin film transistor according to Comparative Example 1 (see FIG. 11 ), it can be seen that the distribution of the threshold voltage was increased in the thin film transistor according to Comparative Example 2. Based on this result, it can be seen that the driving characteristics of the thin film transistor have been greatly reduced in the course of forming the passivation layer.In FIG. 14, A 4 indicates the result of measurement of the threshold voltage V th of the thin film transistor according to Example 2 when a voltage of 10 V was applied across the source electrode 130 and the drain electrode 140, and B 4 indicates the result of measurement of the threshold voltage V th of the thin film transistor according to Example 2 when a voltage of 0.1 V was applied across the source electrode 130 and the drain electrode 140. Referring to FIG. 14, it can be seen that a change ΔV th of the threshold voltage is 0.29 V, which is very small, and that the slope of a graph of the drain current I ds in a region of the threshold voltage V th is very steep, whereby the driving characteristics of the thin film transistor according to Example 2 are excellent.In addition, as compared with the result of measurement of the threshold voltage V th of the thin film transistor according to Example 1 (see FIG. 12 ), it can be seen that the driving characteristics of the thin film transistor according to Example 2 were not greatly reduced. Based on this result, it can be seen that in the case where the third layer 123 is disposed on the second layer 122 made of a two-dimensional semiconductor and the first layer 121 made of an oxide semiconductor is formed on the third layer 123, the driving characteristics of the thin film transistor according to Example 2 are not greatly reduced even when the passivation layer is formed on the semiconductor layer 120 by plasma treatment.In FIG. 15, A5 indicates the result of measurement of the threshold voltage V th of the thin film transistor according to Comparative Example 3 when a voltage of 10 V was applied across the source electrode 130 and the drain electrode 140, and B5 indicates the result of measurement of the threshold voltage V th of the thin film transistor according to Comparative Example 3 when a voltage of 0.1 V was applied across the source electrode 130 and the drain electrode 140. Referring to FIG. 15, it can be seen that a change ΔV th of the threshold voltage is -10.68 V indicating a large distribution of the threshold voltage, and it is difficult to use the thin film transistor according to Comparative Example 3 as a switching device.In addition, as compared with the result of measurement of the threshold voltage V th of the thin film transistor according to Comparative Example 1 (see FIG. 11 ), the driving characteristics of the thin film transistor according to Comparative Example 3 were greatly deteriorated. Consequently, it can be seen that the reliability of the thin film transistor has been greatly reduced in the course of forming the passivation layer.In FIG. 16, A6 indicates the result of measurement of the threshold voltage V th of the thin film transistor according to Example 3 when a voltage of 10 V was applied across the source electrode 130 and the drain electrode 140, and B6 indicates the result of measurement of the threshold voltage V th of the thin film transistor according to Example 3 when a voltage of 0.1 V was applied across the source electrode 130 and the drain electrode 140. Referring to FIG. 16, it can be seen that a change ΔV th of the threshold voltage is -1.59 V, which is very small, and that the slope of a graph of the drain current I ds in a region of the threshold voltage V th is very steep, whereby the driving characteristics of the thin film transistor according to Example 3 are excellent.In addition, as compared with the result of measurement of the threshold voltage V th of the thin film transistor according to Example 1 (see FIG. 12 ), it can be seen that the driving characteristics of the thin film transistor according to Example 3 were not greatly reduced. Based on this result, it can be seen that the reliability of a thin film transistor according to an embodiment of the present invention is not reduced even when the passivation layer is formed on the semiconductor layer 120 by plasma treatment.As can be seen from the above description, a thin film transistor according to an embodiment of the present invention includes a semiconductor layer formed by stacking an oxide semiconductor and a two-dimensional semiconductor. Consequently, the thin film transistor is thin, preferably flexible, and exhibits excellent electrical characteristics. According to an embodiment of the present invention, the thin film transistor exhibits excellent reliability because the oxide semiconductor carries the two-dimensional semiconductor. In addition, the deterioration of electrical characteristics due to the manufacturing process conditions is avoided. A thin film transistor according to another embodiment of the present invention is thin and flexible, whereby the thin film transistor is applicable to a thin film display device and a flexible display device.

Claims

A thin film transistor (100) comprising: a gate electrode (110) disposed on a substrate (101); a semiconductor layer (120) overlapping at least a portion of the gate electrode (110), the semiconductor layer (120) being insulated from the gate electrode (110); a gate insulating film (150) disposed between the gate electrode (110) and the semiconductor layer (120); a source electrode (130) connected to the semiconductor layer (120); and a drain electrode (140) connected to the semiconductor layer (120), the drain electrode (140) being spaced apart from the source electrode (130), the semiconductor layer (120) comprising: a first layer (121) comprising an oxide semiconductor; and a second layer (122) overlapped with the first layer (121), and wherein an energy band gap of the first layer (121) is larger than an energy band gap of the second layer (122), wherein the second layer (122) comprises a two-dimensional semiconductor, wherein the two-dimensional semiconductor is a monolayer or a stack of multiple monolayers, and wherein the second layer (122) is a channel layer.The thin film transistor of claim 1, wherein the gate electrode (110) is disposed closer to the substrate (101) than the semiconductor layer (120), or the semiconductor layer (120) is disposed closer to the substrate (101) than the gate electrode (110).The thin film transistor of any preceding claim, wherein the second layer (122) is disposed closer to the gate electrode (110) than the first layer (121).The thin film transistor according to any preceding claim, wherein the first layer (121) has an energy band gap of 3.0 eV or greater.The thin film transistor according to any one of the preceding claims, wherein the first layer (121) comprises gallium (Ga) and at least one metal element other than gallium, and / or a content of gallium in the first layer (121) is 1.5 times or more a content of each of the at least one metal elements other than gallium based on the number of atoms.The thin film transistor of any preceding claim, wherein the semiconductor of the second layer (122) comprises at least one of a transition metal dichalcogenide, GaS, GaSe, GaS 1-x Se x, CdI 2, PbI 2, K 2 Al 4( Si 6 Al 2 O 28)( OH,F) 4, Mg6(Si8O28)(OH)4, and single layer CdTe.The thin film transistor according to claim 6, wherein the transition metal dichalcogenide is at least one of molybdenum disulfide (MoS 2), molybdenum diselenide (MoSe 2), molybdenum diselenide (MoTe 2), tungsten disulfide (WS 2), tungsten diselenide (WSe 2), tungsten diselenide (WTe 2), niobium disulfide (NbS 2), niobium diselenide (NbSe 2), niobium diselenide (NbTe 2), tantalum disulfide (TaS 2), The compound of the invention may be selected from the group consisting of tantalum diselenide (TaSe 2), tantalum diselenide (TaTe 2), hafnium disulfide (HfS 2), hafnium diselenide (HfSe 2), hafnium diselenide (HfTe 2), titanium disulfide (TiS 2), titanium diselenide (TiSe 2) and titanium diselenide (TiTe 2).The thin film transistor according to any one of the preceding claims, wherein the second layer (122) has an energy band gap in the range of 1.0 to 1.5 eV; and / or the second layer (122) has a structure in which a plurality of layers each made of the semiconductor of the second layer (122) are stacked; and / or the second layer (122) has a thickness in the range of 1.5 to 5 nm.The thin film transistor of any preceding claim, wherein the semiconductor layer (120) further comprises a third layer (123) disposed between the first layer (121) and the second layer (122).The thin film transistor of claim 9, wherein an energy band gap of the third layer (123) is smaller than the energy band gap of the first layer (121) and larger than the energy band gap of the second layer (122).The thin film transistor of claim 9 or 10, wherein the third layer (123) has an energy band gap in the range of 1.6 to 2.5 eV; and / or the third layer (123) consists of a single layer; and / or the third layer (123) has a thickness in the range of 0.4 to 1.4 nm; and / or the third layer (123) comprises one of molybdenum disulfide (MoS 2) and tungsten disulfide (WS 2).The thin film transistor according to any one of the preceding claims, wherein the thickness of the first layer (121) is in the range of 10 to 50 nm.The thin film transistor according to any preceding claim, wherein the third layer (123) is made of a two-dimensional semiconductor.A display device, comprising: a substrate (101); a thin film transistor (400) disposed on the substrate (101); and a first electrode (271) connected to the thin film transistor (400) according to any one of the preceding claims.The display device of claim 14, wherein the display device is a flexible display device.

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