Semiconductor device containing a transition material in a trench, and manufacturing method

Abstract

Semiconductor device (100) comprising: a SiC semiconductor body (102); a gate dielectric (104) and a gate electrode (106); a first trench (108) extending from a first surface (110) of the SiC semiconductor body (102) into the SiC semiconductor body (102); a transition material (112) in the first trench (108), wherein the transition material (112) and the semiconductor body (102) form a diode; and a drift region (138) of a first conductivity type and a first current propagation region (140) of the first conductivity type, which is arranged between a body region (122) of a second conductivity type and the drift region (138), wherein a doping concentration of the first current propagation region (140) is greater than a doping concentration of the drift region (138).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices, particularly silicon carbide (SiC) semiconductor devices and manufacturing methods therefor. BACKGROUND

[0002] Semiconductor devices containing field-effect transistor cells contain pn junctions between a drift zone and body regions of the field-effect transistor cells. For example, reference is made to the disclosure content of the documents US 2017 / 0 077 299 A1, US 2017 / 0 345 818 A1, and US 2017 / 0 200 787 A1. The pn junctions form an intrinsic body diode. In a forward-biased mode of the semiconductor device, the body diode is forward-biased, and a bipolar current of electrons and holes passes through the drift zone and the body regions. The forward voltage drop across the body diode and electrical losses induced by the body diode result from parameters, e.g., dimensions of doped regions and dopant concentrations in doped regions, which are typically selected with regard to the desired properties of the field-effect transistor cells.

[0003] There is a need to improve silicon carbide-based semiconductor devices. SUMMARY

[0004] The invention is defined in the independent patent claims. Further developments are the subject of the dependent patent claims.

[0005] One example of the present disclosure relates to a semiconductor device including a SiC semiconductor body, a gate dielectric, and a gate electrode. The semiconductor device further includes a first trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body, and a junction material in the first trench, wherein the junction material and the semiconductor body form a diode.

[0006] Another example of the present disclosure relates to a semiconductor device including a SiC semiconductor body and a trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body. The semiconductor device further includes a gate dielectric adjacent to a first sidewall and a bottom of the trench, and a junction material adjacent to a second sidewall of the trench and adjacent to the bottom of the trench, wherein the junction material and the semiconductor body form a diode.

[0007] Another example of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing a SiC semiconductor body. The method further includes forming a gate dielectric and a gate electrode. Furthermore, the method includes forming a first trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body. Furthermore, the method includes forming a junction material in the first trench, wherein the junction material and the semiconductor body form a diode.

[0008] Another example of the present disclosure relates to a method of manufacturing a semiconductor device. The method includes providing a SiC semiconductor body. The method further includes forming a trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body. Furthermore, the method includes forming a gate dielectric adjacent to a first sidewall and adjacent to a bottom of the trench. The method further includes forming a junction material adjacent to a second sidewall of the trench and adjacent to the bottom of the trench, wherein the junction material and the semiconductor body form a diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the semiconductor device and method of fabricating a semiconductor device and, together with the description, serve to explain the principles of the embodiments. Additional embodiments are described in the following detailed description and claims. Fig. 1A and Fig. 1B illustrate schematic cross-sectional views of an embodiment of a semiconductor device including a diode formed from a junction material in a trench, the semiconductor device further comprising a trench gate electrode ( Fig. 1A) or a planar gate electrode ( Fig. 1B). Fig. 2A and Fig. 2B illustrate schematic cross-sectional views of embodiments of the transition material in the trench. Fig. 3 to 6 are schematic cross-sectional views to illustrate further embodiments of a semiconductor device. Fig. 7 is a schematic plan view to illustrate an embodiment of a semiconductor device having semiconductor stripes. Fig. 8A and Fig. 8B are schematic cross-sectional views to illustrate embodiments of a semiconductor device. Fig. 9 and Fig. 10 are schematic process flow diagrams to illustrate embodiments of manufacturing methods for a semiconductor device. DETAILED DESCRIPTION

[0010] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, for purposes of illustration, specific embodiments in which a semiconductor device may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one embodiment may be used in or in connection with other embodiments to arrive at yet another embodiment. It is intended that the present disclosure encompass such modifications and changes. The examples are described using specific language that should not be construed as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. Corresponding elements are designated by the same reference numerals in the various drawings unless otherwise noted.

[0011] The terms "have," "contain," "comprise," "have," and similar terms are open-ended terms. These terms indicate the presence of the identified structures, elements, or characteristics, but do not preclude the presence of additional elements or characteristics. The indefinite and definite articles are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0012] The term "electrically connected" describes a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or a highly doped semiconductor. The term "electrically coupled" encompasses the possibility that one or more intermediate elements suitable for signal transmission and / or power transmission may be present between the electrically coupled elements, for example, elements that can be controlled to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state.

[0013] The figures illustrate relative doping concentrations by indicating “-” or “+” next to the doping type “n” or “p”. For example, “n -” a doping concentration that is lower than the doping concentration of an “n” doping region, while an “n + "-doping region has a higher doping concentration than an "n"-doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n"-doping regions can have the same or different absolute doping concentrations.

[0014] Two adjacent doping regions of the same conductivity type and with different dopant concentrations form a unipolar junction, e.g., an (n / n+) junction or a (p / p+) junction, along an interface between the two doping regions. In a unipolar junction, a dopant concentration profile orthogonal to the unipolar junction may exhibit a step or inflection point at which the dopant concentration profile changes from concave to convex or vice versa.

[0015] Ranges specified for physical dimensions include the boundary values. For example, a range for a parameter y from a to b is written as a ≤ y ≤ b. A parameter y with a value of at least c is written as c ≤ y, and a parameter y with a value of at most d is written as y ≤ d.

[0016] A safe operating area (SOA) defines the voltage and current conditions under which a semiconductor device can be expected to operate without self-damage. The SOA is defined by published maximum values ​​for device parameters such as maximum continuous load current, maximum gate voltage, and others.

[0017] IGFETs (Insulated Gate Field Effect Transistors) are voltage-controlled devices that include MOSFETs (Metal Oxide Semiconductor FETs) and other FETs with gate electrodes based on doped semiconductor material and / or with gate dielectrics that are not or not exclusively based on an oxide.

[0018] According to one embodiment, a semiconductor device may include a silicon carbide (SiC) semiconductor body. The semiconductor device may further include a gate dielectric and a gate electrode. The semiconductor device may further include a first trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body. The semiconductor device may further include a junction material in the first trench. The junction material and the semiconductor body may form a diode.

[0019] The SiC semiconductor body can consist of a hexagonal phase of silicon carbide, e.g. 4H-SiC. <0001> The crystal axis may be inclined by an offset angle α relative to a surface normal to the first surface. The <11-20> crystal axis may be inclined by the offset angle α relative to the horizontal plane. The <1-100> crystal axis may be orthogonal to the cross-sectional plane. The offset angle α may range from 2° to 8°. For example, the offset angle α may be 4°.

[0020] The gate dielectric and the gate electrode may define a gate structure. The gate dielectric may include or consist of a layer or a combination of layers, e.g., a stack of dielectric layers, for example, oxide layers such as thermal oxide layers or deposited oxide layers, e.g., LPCVD (low pressure chemical vapor deposition) oxides using tetraethyl orthosilicate (TEOS) as a precursor, PECVD (plasma enhanced chemical vapor deposition) oxides, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSP), borophosphosilicate glass (BPSG), nitride layers, high-k dielectric layers, and / or low-k dielectric layers.

[0021] The gate electrode may contain or consist of one or a combination of electrode materials, for example doped semiconductor material such as doped polycrystalline silicon, metal or metal compounds.

[0022] According to one embodiment, the gate structure may be a planar gate structure. A planar gate structure is a gate structure with the gate dielectric and the gate electrode arranged on the first surface of the SiC semiconductor body. A current flow direction through the channel of a planar gate structure may be a lateral direction parallel to the first surface.

[0023] According to another embodiment, the gate structure may be a trench gate structure. A trench gate structure is a gate structure comprising the gate dielectric and the gate electrode arranged in a gate trench extending into the SiC semiconductor body. A current flow direction through the channel may deviate from the lateral direction (so-called "vertical channel") and may correspond to a direction perpendicular to the first surface or a direction parallel to a sidewall slope of the gate trench. Such a vertical channel is also possible at least in places in the case of a planar gate structure.

[0024] The transition material in the first trench may be a material or a combination of materials that forms a diode with the SiC semiconductor body adjacent to the transition material.

[0025] According to one embodiment, the diode may be a Schottky diode, and the junction material may be any metal or combination of metals that forms a Schottky barrier with the SiC semiconductor body. Examples of metals or metal combinations that form a Schottky junction with n-type SiC include, but are not limited to, Ti, TiN, Ti / TiN, Mo, MoN, and WN.

[0026] According to another embodiment, the diode may be, for example, a unipolar or a bipolar junction diode such as an nn + -junction diode or a pp +The junction can be a junction diode or a pn junction diode. The junction can be a homojunction in the case of a junction material made of SiC or a heterojunction in the case of a junction material other than SiC. A unipolar or bipolar heterojunction diode can, for example, be formed between the SiC semiconductor body and a junction material made of polycrystalline silicon.

[0027] According to yet another embodiment, the diode may be, for example, a combination of a Schottky diode and a unipolar or bipolar junction diode such as an nn + -junction diode or a pp + -junction diode or a pn junction diode. The unipolar or bipolar junction diode can, for example, be formed by a first region of the first trench, and the Schottky diode can be formed by a second region of the first trench.

[0028] The diode may have a lower forward voltage drop than an intrinsic bipolar body diode of the semiconductor device. For example, the forward voltage drop of the intrinsic bipolar diode in silicon carbide may be between 2.5 V and 3 V, and the forward voltage drop across the diode in the first trench may be less than 2 V, e.g., less than 1.5 V.

[0029] The diode in the first trench can reduce turn-on losses, reverse recovery losses, and thermal stress in the semiconductor device. DC / DC converters that use the semiconductor device as a power switch in a rectification stage, for example, can achieve higher efficiency. Since the diode in the first trench can bypass the internal body diode for the entire SOA, bipolar degradation can be effectively reduced or avoided.

[0030] According to one embodiment, the semiconductor device may further comprise a second trench extending from the first surface of the SiC semiconductor body into the SiC semiconductor body. The gate dielectric and the gate electrode may be arranged in the second trench. Thus, in this embodiment, a gate structure comprising the gate dielectric and the gate electrode is a trench gate structure.

[0031] The vertical extension of the gate structure may be in a range from 0.3 µm to 5 µm, e.g., in a range from 0.5 µm to 2 µm. Sidewalls of the second trench may be vertical or may taper with increasing distance from the first surface. The width of the gate structures in the plane of the first surface may be in a range from 500 nm to 5 µm, e.g., in a range from 1 µm to 3 µm.

[0032] The second trench may taper with increasing distance from the first surface. For example, a taper angle of the second trench with respect to the vertical direction may be equal to the offset angle α or may deviate from the offset angle α by no more than ±1 degree, such that at least one first mesa sidewall of two opposite longitudinal mesa sidewalls is formed by a main crystal plane with a high charge carrier mobility, e.g., a {11-20} crystal plane. A second mesa sidewall opposite the first mesa sidewall may be inclined to a main crystal plane by twice the offset angle α, e.g., by 4 degrees or more, for example, by about 8 degrees. A taper and dimensions of the second trench may, for example, correspond to the first trench.

[0033] According to one embodiment, a first width of the first trench at the first surface may correspond to a second width of the second trench at the first surface, and a first depth of the first trench with respect to the first surface may correspond to a second depth of the second trench with respect to the first surface. For example, the first and second trenches may be formed using a common lithography mask, for example, with identical widths of mask openings for forming the first and second trenches. The first and second trenches may also differ, for example, in terms of width and / or depth.

[0034] According to one embodiment, the semiconductor device may further comprise a source region of a first conductivity type adjacent to the gate dielectric at a first sidewall of the second trench. Consequently, a channel (e.g., a MOS channel) may be confined to the first sidewall with respect to opposing first and second sidewalls of the second trench. The source region may also adjoin the gate dielectric at opposing first and second walls of the second trench, respectively. As a result, a channel (e.g., a MOS channel) may be formed not only on the first sidewall of the second trench, but also on the second sidewall of the second trench.

[0035] According to one embodiment, the semiconductor device may further comprise a body region of a second conductivity type bordering the first sidewall of the second trench. The semiconductor device may further comprise a first shield region of the second conductivity type bordering the bottom of the second trench and bordering the second sidewall of the second trench. The first shield region may, for example, extend from the bottom of the second sidewall up to the first surface. The first shield region may, for example, be electrically connected via a contact on the first surface. The first shield region may also be formed below the bottom of the second trench and may border (e.g., only border) the bottom of the second trench. The first shield region may, for example, be electrically connected at the bottom of the second trench.The presence of the first shielding region can reduce the effective electric field at the bottom of the second trench.

[0036] According to one embodiment, the gate dielectric and the gate electrode may be part of a planar gate electrode structure arranged on the first surface of the SiC semiconductor body. This allows a channel current to flow, for example, at least at locations along a lateral direction parallel to the first surface. This may enable a simplified manufacturing process that avoids etching gate trenches.

[0037] According to one embodiment, the junction material comprises at least one of: i) a metal or ii) a doped polycrystalline silicon. The junction material may at least partially fill the first trench. The diode may be a Schottky diode formed by a Schottky junction between the semiconductor body and the metal that at least partially fills the first trench. Exemplary metals or metal combinations forming a Schottky junction with n-type SiC include, for example, Ti, TiN, Ti / TiN, Mo, MoN, WN, among others. The junction material may also be doped polycrystalline silicon, and the corresponding diode may, for example, be a unipolar or a bipolar junction diode such as an nn + -Heterojunction diode or a pp +-heterojunction diode or a pn-heterojunction diode. According to yet another embodiment, the diode may, for example, be a combination of a Schottky diode and a unipolar or bipolar junction diode such as an nn + -junction diode or a pp +-junction diode or a pn-junction diode. A doping concentration of the junction material may, for example, vary along the vertical direction. The junction material may also contain a plurality of different metals forming a plurality of parallel-connected Schottky junction diodes. The different metals may, for example, be arranged in different regions of the first trench. The junction material may also contain i) a semiconductor or a combination of semiconductors and ii) a metal or a combination of metals in different regions of the first trench, thereby forming i1) a Schottky diode and i2) a unipolar or bipolar junction diode, such as an nn + -junction diode or a pp + -junction diode or a pn junction diode connected in parallel, or any combination thereof.

[0038] According to one embodiment, the first trench and the second trench may be arranged in a transistor cell array of the semiconductor device. The transistor cell array may, for example, be surrounded or partially surrounded by an edge termination structure. The first trench, which is part of the diode, may, for example, be arranged between transistor cells, e.g., between two second trenches.

[0039] According to one embodiment, a plurality of the first trenches may be irregularly distributed across the transistor cell array. If a region of a part of or the entire transistor cell array at the first surface is divided into n equal sub-regions, where n is an integer between 4 and 100, a distribution of the first trenches is considered irregular if a percentage of a region of the first trenches at the first surface differs by more than 10% among the n sub-regions. An irregular distribution of the first trenches may, for example, enable an improvement in switching characteristics of the semiconductor device.

[0040] According to another embodiment, the plurality of first trenches are regularly (in other words: uniformly) distributed across the transistor cell array. If a region of a part of or the entire transistor cell array at the first surface is divided into n equal sub-regions, where n is an integer between 4 and 100, a distribution of the first trenches is considered regular if a percentage of a region of the first trenches at the first surface differs by less than 10% among the n sub-regions.

[0041] According to one embodiment, the gate electrode and the first trench may be strip-shaped, extending parallel along a first lateral direction. For example, the gate electrode and the first trench may extend from one lateral end of a transistor cell array to an opposite lateral end of the transistor cell array.

[0042] According to one embodiment, the semiconductor device may further comprise a second shielding region of the second conductivity type, which borders the bottom of the first trench. The first shielding region and the second shielding region may, for example, be formed at least partially or entirely by means of a common ion implantation process. In other words, one and the same ion implantation mask may, for example, be used to form the first and second shielding regions.

[0043] According to one embodiment, a doping concentration profile of the first shielding region along a vertical extension (dimension) between a bottom of the second trench and a bottom of the first shielding region may correspond to a doping concentration profile of the second shielding region along the vertical extension, at least between a bottom of the first trench and a bottom of the second shielding region. For example, the doping concentration profile of the first shielding region below the bottom of the second trench may correspond to the doping concentration profile of the second shielding region below the bottom of the first trench. This may make it possible to reduce the manufacturing effort of the diode if the first and second trenches are formed together using a common etching process and if at least a part of the first and second shielding regions is formed together using a common ion implantation process.Additionally or alternatively, the first shielding region and the second shielding region may have the same doping concentration profile along at least one lateral direction.

[0044] According to one embodiment, the first and second shielding regions may differ in at least one of a doping concentration profile along the vertical direction and a dimension along the vertical direction. For example, the first shielding region may extend from below a bottom of the second trench upwards to the first surface, and the second shielding region may extend from below a bottom of the first trench upwards to a vertical position below the first surface. In other words, the second shielding region may, for example, be buried below the first surface. The second shielding region may, for example, be electrically coupled to the transition material in the first trench.

[0045] According to one embodiment, the semiconductor device may further comprise a drift region of the first conductivity type. Optionally, the semiconductor device may comprise a first current spreading region of the first conductivity type arranged between the body region and the drift region. The first current spreading region may border the first sidewall of the second trench and the bottom of the second trench. A doping concentration of the first current spreading region may be higher than a doping concentration of the drift region. The first current spreading region may enable a reduction of the on-state resistance by providing a low-ohmic current path for a load current leaving a channel region and directed into the drift region toward a drain contact at a second surface of the SiC semiconductor body opposite the first surface.

[0046] According to one embodiment, the first current propagation region can be arranged between the first and second shielding regions, respectively. The first current propagation region and the body region can form a pn junction. The first current propagation region can, for example, also be located at a vertical distance from the body region.

[0047] According to one embodiment, the semiconductor device may further comprise a second current spreading region of the first conductivity type adjacent to the bottom of the first trench. A doping concentration of the second current spreading region may, for example, be higher than a doping concentration of the drift region.

[0048] According to one embodiment, the first and second current spreading regions may differ in at least one of a doping concentration profile along the vertical direction and a dimension along the vertical direction. This may, for example, enable separate optimization of the electrical shielding behavior around i) the diode in the first trench by the second current spreading region and ii) the gate structure in the second trench by the first current spreading region.

[0049] According to one embodiment, a semiconductor device may include a SiC semiconductor body. The semiconductor device may further include a trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body. The semiconductor device may further include a gate dielectric adjacent to a first sidewall and a bottom of the trench. The semiconductor device may further include a junction material adjacent to a second sidewall of the trench and adjacent to the bottom of the trench. The junction material and the semiconductor body may form a diode. The embodiment may enable a compact design of a gate structure and a diode by integrating the gate structure and the diode within a single trench and by utilizing opposite sidewalls of the trench for different functions, e.g., a MOSFET channel on the first sidewall and a diode on the second sidewall.Details regarding the SiC semiconductor body, the gate dielectric, the gate electrode, the junction material, and the diode described with respect to the above embodiments are intended to apply equally to this embodiment. In this respect, the trench may correspond to the first trench described herein.

[0050] According to one embodiment, the semiconductor device may further comprise a gate electrode in the trench and a dielectric in the trench. The dielectric may provide electrical insulation between the gate electrode and the junction material in the trench. The dielectric may include or consist of a layer or a combination of layers, e.g., a layer stack of dielectric layers, for example, oxide layers such as thermal oxide layers or deposited oxide layers, e.g., LPCVD (low pressure chemical vapor deposition) oxides using tetraethyl orthosilicate (TEOS) as precursor, PECVD (plasma enhanced chemical vapor deposition) oxides, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSP), borophosphosilicate glass (BPSG), nitride layers, high-k dielectric layers, or low-k dielectric layers.

[0051] According to one embodiment, the semiconductor device may further comprise a shielding region of a second conductivity type adjacent to a bottom of the trench. The shielding region may further border at least a portion of a second sidewall of the trench. The presence of the shielding region may, for example, reduce the effective electric field at a bottom of the second trench. In some embodiments, the shielding region may correspond to and / or have the same or similar features as the second shielding region described herein. According to one embodiment, a current spreading region may, for example, laterally border the shielding region.

[0052] According to one embodiment, a method for manufacturing a semiconductor device may include providing a SiC semiconductor body. The method may further include forming a gate dielectric and a gate electrode. Moreover, the method may include forming a first trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body. The method may further include forming a junction material in the first trench, wherein the junction material and the semiconductor body form a diode. Details regarding the SiC semiconductor body, the gate dielectric, the gate electrode, the junction material, and the diode described with respect to the above embodiments are intended to apply equally to this embodiment.

[0053] According to another embodiment, a method for manufacturing a semiconductor device may include providing a SiC semiconductor body. Furthermore, the method may include forming a trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body. The method may further include forming a gate dielectric adjacent to a first sidewall and adjacent to a bottom of the trench. The method may further include forming a junction material adjacent to a second sidewall of the trench and adjacent to the bottom of the trench. The junction material and the semiconductor body may form a diode. Details regarding the SiC semiconductor body, the gate dielectric, the gate electrode, the junction material, and the diode described with respect to the above embodiments are intended to apply equally to this embodiment.

[0054] The embodiments described above can be combined in any way.

[0055] The embodiments described above are further illustrated with reference to exemplary figures described below.

[0056] Referring to the schematic cross-sectional views of the Fig. 1A and Fig. 1B, a semiconductor device 100 comprises a silicon carbide, SiC, semiconductor body 102. The semiconductor device 100 further comprises a gate dielectric 104 and a gate electrode 106 forming a gate structure. The semiconductor device further comprises a first trench 108 extending from a first surface 110 of the SiC semiconductor body 102 into the SiC semiconductor body 102. The semiconductor device 100 further comprises a junction material 112 in the first trench 108. The junction material 112 and the semiconductor body 102 form a diode. Details regarding the SiC semiconductor body, the gate dielectric, the gate electrode, the junction material, and the diode described with respect to the above embodiments shall be referred to in Fig. 1A and Fig. 1B are equally applicable.

[0057] In the Fig. 1A, the gate structure is a trench gate structure. In other words, the gate dielectric 104 and the gate electrode 106 are arranged in a second trench 114 extending from the first surface 110 of the SiC semiconductor body 102 into the SiC semiconductor body 102. A first width w1 of the first trench 108 at the first surface 110 may correspond to a second width w2 of the second trench 114 at the first surface 110. A first depth d1 of the first trench 108 with respect to the first surface 110 may also correspond to a second depth d2 of the second trench 114 with respect to the first surface 110. According to other embodiments, the first and second widths w1, w2 may also differ from each other. Likewise, the first and second depths d1, d2 may also differ from each other.

[0058] In the Fig. In the exemplary embodiment illustrated in FIG. 1B, the gate structure is a planar gate structure. In other words, the gate dielectric 104 and the gate electrode 106 are arranged on the first surface 110 of the SiC semiconductor body 102.

[0059] Referring to the schematic cross-sectional view of Fig. 2A, the transition material 112 in the first trench 108 may comprise a combination of materials 1121, 1122 in the form of a layer stack lining sidewalls and a bottom of the first trench 108. Although the Fig. 2A is a dual layer, the number of stacked layers may be greater than two, for example, three, four, or even greater.

[0060] Referring to the schematic cross-sectional view of Fig. 2B, the transition material 112 in the first trench 108 may comprise a combination of materials 1121, 1122 stacked along a vertical direction. Although the Fig. 2B comprises two materials, the number of stacked materials may be greater than two, for example, three, four, or even greater. Consequently, a parallel connection of any combination of different diodes, e.g., a Schottky junction diode, an nn + -junction diode, a pp + -junction diode or a pn junction diode.

[0061] The transition material 112 may, for example, partially or completely fill the first trench 108.

[0062] Referring to the schematic cross-sectional view of Fig. 3, the semiconductor device 100 further comprises a source region 116 of a first conductivity type, which borders the gate dielectric 104 at a first sidewall 118 of the second trench 114. The source region 116 may optionally also border the gate dielectric 104 at an opposite second sidewall 120 of the second trench 114. This optional arrangement of the source region 116 is shown in Fig. 3 by a dashed line. The semiconductor device 100 further includes a body region 122 of a second conductivity type, which borders the first sidewall 118 of the second trench 114. The semiconductor device further includes a first shield region 124 of the second conductivity type, which borders a bottom 126 of the second trench 114 and borders the second sidewall 120 of the second trench 114. The semiconductor device 100 further includes a second shield region 128 of the second conductivity type, which borders a bottom 130 of the first trench 108.

[0063] In the Fig. 3, the diode is formed only on a first sidewall 132 of the first trench 108.

[0064] Details regarding the SiC semiconductor body, the gate dielectric, the gate electrode, the junction material, the diode, the first and second shielding regions described with respect to the above embodiments shall be referred to in Fig. 3 illustrated exemplary embodiment equally applies.

[0065] In the schematic Fig. In the exemplary embodiment illustrated in Figure 4, the diode is formed not only on the first sidewall 132 of the first trench 108, but also on a second sidewall 134 of the first trench 108. The diode on the second sidewall 134 may be formed by the transition material 112 and a diode region 136 of the second conductivity type adjacent to the transition material 112 on the second sidewall 134. The diode region 136 may be formed, for example, by means of one or more ion implantation processes. A dose of the one or more ion implantation processes for forming the diode region 136 may be appropriately adjusted, for example, to enable counter-doping. A lateral distance l between lateral ends of the source region 116 and the body region 122 may be appropriately adjusted, for example, to avoid a short circuit between the source and drain.The semiconductor device further includes a drift region 138 of the first conductivity type and a first current spreading region 140 of the first conductivity type arranged between the body region 122 and a drift region 138. The first current spreading region 140 may border the first sidewall 118 of the second trench 114 and the bottom 126 of the second trench 114. The semiconductor device 100 further includes a second current spreading region 142 of the first conductivity type bordering the bottom 130 of the first trench 108.

[0066] Details regarding the first SiC semiconductor body, the gate dielectric, the gate electrode, the junction material, the diode, the first and second shielding regions and the first and second current spreading regions described above with respect to the embodiments shall be referred to in Fig. The embodiment illustrated in Figure 4 applies equally.

[0067] A compact design of transistor cells and the diode is described with reference to the schematic cross-sectional view of Fig. 5. The second shielding region 128 is omitted from the second sidewall 134 of the first trench 108 and borders the bottom 130 of the first trench. Therefore, the diode is formed on both the first and second sidewalls 132, 134 of the first trench 108.

[0068] Another compact design of transistor cells and the diode is described with reference to the schematic cross-sectional view of Fig. 6. The semiconductor device 100 includes a trench 144 extending from the first surface 110 of the SiC semiconductor body 102 into the SiC semiconductor body 102. The gate dielectric 104 borders a first sidewall 146 and a bottom 148 of the trench 144. The semiconductor device 100 further includes the junction material 112 bordering a second sidewall 150 of the trench 144 and bordering the bottom 148 of the trench 144. The junction material 112 and the semiconductor body 102 form a diode. The junction material 112 and the gate electrode 106 are electrically isolated by an interlayer dielectric 152 in the trench 144. A shielding region 153 of the second conductivity type borders the bottom 148 of the trench 144.

[0069] Details regarding the SiC semiconductor body, the gate dielectric, the gate electrode, the junction material, the shielding region and the diode described above with respect to the embodiments shall be referred to in Fig. The embodiment illustrated in Figure 6 applies equally.

[0070] Referring to the schematic plan view of Fig. 7, selected regions of an embodiment of the semiconductor device 100 are illustrated. Semiconductor stripes 154 of the second conductivity type, e.g., buried semiconductor stripes 154 or semiconductor stripes bordering the first surface 110, may run parallel along a lateral direction that is different from an extension direction of the first trench 108, e.g., perpendicular to the extension direction of the first trench 108. The semiconductor stripes 154 may, for example, enable an improvement of an electrical connection to the second shielding region 128. The semiconductor stripes 154 may, for example, have a bottom at the same vertical distance from the first surface as the second shielding region 128.

[0071] Referring to the schematic cross-sectional view of the Fig. 8A and Fig. 8B, a highly doped semiconductor region 156 of the second conductivity type may be formed on the first surface 110, overlapping both the body region 116 and the diode region 136. The highly doped semiconductor region 156 of the second conductivity type may improve electrical connection of the body region 112 via the first surface 110 and may further suppress a short circuit between the source and drain.

[0072] Fig. 9 is a schematic flow diagram to illustrate a method 1000 for manufacturing a semiconductor device.

[0073] It will be appreciated that while the method 1000 is illustrated and described below as a series of steps or events, the illustrated order of such steps or events is not to be interpreted in a limiting sense. For example, some steps may occur in different orders and / or concurrently with other steps or events apart from those illustrated and / or described herein. Furthermore, not all steps may be required to practice one or more aspects of embodiments of the disclosure herein. One or more of the steps illustrated herein may also be divided into one or more separate substeps and / or phases.

[0074] Process feature F10 includes providing a SiC semiconductor body.

[0075] Process feature F11 includes forming a gate dielectric and a gate electrode.

[0076] Process feature F12 includes forming a first trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body.

[0077] Process feature F13 includes forming a junction material in the first trench, wherein the junction material and the semiconductor body form a diode.

[0078] In at least some embodiments of the method 1000, the following features (if applicable) apply alone or in combination: (i) forming at least one of the body region, the first shielding region, the second shielding region, the source region, the diode region, the first current spreading region, the second current spreading region, the highly doped semiconductor region comprises at least one masked or unmasked ion implantation process; (ii) forming the first trench is carried out after step (i); (iii) forming the second trench is carried out together with or after forming the first trench; (iv) the gate dielectric and the gate electrode are formed in the first trench and in the second trench; (v) the gate dielectric and the gate electrode are removed from the second trench; (vi) the transition material is formed in the second trench after performing (ii) to (v); (vii) the gate electrode and the junction material are formed by a co-deposition process of polycrystalline silicon.

[0079] Fig. 10 is a schematic flow diagram to illustrate a method 2000 for manufacturing a semiconductor device.

[0080] It will be appreciated that while the method 2000 is illustrated and described below as a series of steps or events, the illustrated order of such steps or events is not to be interpreted in a limiting sense. For example, some steps may occur in different orders and / or concurrently with other steps or events apart from those illustrated and / or described herein. Furthermore, not all steps may be required to practice one or more aspects of embodiments of the disclosure herein. One or more of the steps illustrated herein may also be divided into one or more separate substeps and / or phases.

[0081] Process feature F20 includes providing a SiC semiconductor body.

[0082] Process feature F21 includes forming a trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body.

[0083] Process feature F22 includes forming a gate dielectric adjacent to a first sidewall and a bottom of the trench.

[0084] Process feature F23 includes forming a junction material adjacent to a second sidewall of the trench and adjacent to the bottom of the trench, wherein the junction material and the semiconductor body form a diode.

[0085] In at least some embodiments of the method 2000, the following features (if applicable) apply alone or in combination: (i) forming at least one of the body region, the shield region, the source region comprises at least one masked or unmasked ion implantation process; (ii) forming the first trench is carried out according to (i); (iii) the gate dielectric and the gate electrode are formed in the trench; (iv) the gate dielectric and the gate electrode are removed from a part of the trench by means of a masked etching process; (v) the transition material is formed in the part of the trench after carrying out (iv).

Claims

[1] A semiconductor device (100) comprising: a SiC semiconductor body (102); a gate dielectric (104) and a gate electrode (106); a first trench (108) extending from a first surface (110) of the SiC semiconductor body (102) into the SiC semiconductor body (102); a transition material (112) in the first trench (108), wherein the transition material (112) and the semiconductor body (102) form a diode; and a drift region (138) of a first conductivity type and a first current spreading region (140) of the first conductivity type arranged between a body region (122) of a second conductivity type and the drift region (138), wherein a doping concentration of the first current spreading region (140) is greater than a doping concentration of the drift region (138). [2] The semiconductor device (100) of claim 1, further comprising a second trench (114) extending from the first surface (110) of the SiC semiconductor body (102) into the SiC semiconductor body (102), wherein the gate dielectric (104) and the gate electrode (106) are disposed in the second trench (114). [3] The semiconductor device (100) of claim 2, wherein a first width (w1) of the first trench (108) at the first surface (110) corresponds to a second width (w2) of the second trench (114) at the first surface (110), and a first depth (d1) of the first trench (108) with respect to the first surface (110) corresponds to a second depth (d2) of the second trench (114) with respect to the first surface (110). [4] The semiconductor device (100) of claim 2 or 3, further comprising a source region (116) of a first conductivity type adjacent to the gate dielectric (104) at a first sidewall (118) of the second trench (114) or adjacent to the gate dielectric (104) at opposite first and sidewalls (118, 120) of the second trench (114). [5] The semiconductor device (100) of any one of claims 2 to 4, further comprising a body region (122) of a second conductivity type adjacent to the first sidewall (118) of the second trench (114), and a first shield region (124) of the second conductivity type adjacent to the bottom (126) of the second trench (114) and adjacent to the second sidewall (120) of the second trench (114). [6] The semiconductor device (100) of claim 1, wherein the gate dielectric (104) and the gate electrode (106) are part of a planar gate electrode structure arranged on the first surface (110) of the SiC semiconductor body (102). [7] Semiconductor device (100) according to one of the preceding claims, wherein the transition material (112) contains at least one of i) a metal or ii) a doped polycrystalline silicon, and wherein the transition material (112) at least partially fills the first trench (108). [8] Semiconductor device (100) according to one of the preceding claims, wherein the first trench (108) and the second trench (114) are arranged in a transistor cell array of the semiconductor device (100). [9] A semiconductor device (100) according to any one of the preceding claims, wherein a plurality of the first trenches (104) are irregularly distributed over the transistor cell array. [10] A semiconductor device (100) according to any one of the preceding claims, wherein the gate electrode (106) and the first trench (108) are strip-shaped and extend parallel along a first lateral direction. [11] The semiconductor device (100) of any preceding claim, further comprising a second shielding region (128) of the second conductivity type adjacent to a bottom (130) of the first trench (108). [12] The semiconductor device (100) of claim 11, wherein a doping concentration profile of the first shielding region (124) along a vertical extent between the bottom (126) of the second trench (114) and a bottom of the first shielding region (124) corresponds to a doping concentration profile of the second shielding region (128) along the vertical extent. [13] The semiconductor device (100) according to any one of the preceding claims, wherein the first and second shielding regions (124, 125) differ in at least one of a doping concentration profile along the vertical direction and a dimension along the vertical direction. [14] The semiconductor device (100) of claim 12, further comprising a second current spreading region (142) of the first conductivity type adjacent to the bottom (130) of the first trench (108), and wherein a doping concentration of the second current spreading region (142) is higher than a doping concentration of the drift region (138). [15] The semiconductor device (100) of claim 14, wherein the first and second current spreading regions (140, 142) differ in at least one of a doping concentration profile along the vertical direction and a dimension along the vertical direction. [16] A semiconductor device (100) comprising: a SiC semiconductor body (102); a trench (144) extending from a first surface (110) of the SiC semiconductor body (102) into the SiC semiconductor body (102); a gate dielectric (104) adjacent to a first sidewall (146) and a bottom (148) of the trench (144); and a transition material (112) adjacent to a second sidewall (150) of the trench (144) and adjacent to the bottom (148) of the trench (144), wherein the transition material (112) and the semiconductor body (102) form a diode. [17] The semiconductor device (100) of claim 16, further comprising a gate electrode (106) in the trench (144) and a dielectric (152) in the trench (144), wherein the dielectric (152) provides electrical insulation between the gate electrode (106) and the junction material (112) in the trench (144). [18] The semiconductor device (100) of any one of claims 16 to 17, further comprising a shield region (153) of a second conductivity type adjacent to the bottom (148) of the trench (144). [19] A method of manufacturing a semiconductor device, the method comprising: Providing a SiC semiconductor body (F10); Forming a gate dielectric and a gate electrode (F11); Forming a first trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body (F12); Forming a transition material in the first trench, wherein the transition material and the semiconductor body form a diode (F13); and Forming a drift region (138) of a first conductivity type and a first current spreading region (140) of the first conductivity type, which is arranged between a body region (122) of a second conductivity type and the drift region (138), wherein a doping concentration of the first current spreading region (140) is greater than a doping concentration of the drift region (138). [20] A method of manufacturing a semiconductor device, the method comprising: Providing a SiC semiconductor body (F20); Forming a trench extending from a first surface of the SiC semiconductor body into the SiC semiconductor body (F21); Forming a gate dielectric adjacent to a first sidewall and adjacent to a bottom of the trench (F22); and Forming a transition material adjacent to a second sidewall of the trench and adjacent to the bottom of the trench, wherein the transition material and the semiconductor body form a diode (F23).

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