Digital-to-analog converter with improved linearity

Abstract

A digital-to-analog converter (DAC) circuit (300) for reducing gain mismatch errors and comprising an input for receiving a stream of digital input words, each digital input word being divided into a digital MSB (most significant bit) subword and a digital LSB (least significant bit) subword, the circuit comprising: a digital noise shaper circuit (304) for receiving a representation of the LSB subword, the digital noise shaper circuit (304) being configured to output a modulated LSB subword; an LSB DAC circuit (306) for receiving and converting a combination of a representation of the LSB subword and the modulated LSB subword and for generating a first analog output; an MSB DAC circuit (302) for receiving and converting a combination of a representation of the digital MSB subword and the modulated LSB subword and for generating a second analog output, wherein each of the first analog output and the second analog output are combined to produce an analog output representing the stream of digital input words.

Description

FIELD OF DISCLOSUREThe present disclosure relates generally to the field of data converter circuits and systems, and more particularly to digital-to-analog converters.GENERAL STATE OF THE ARTElectronic systems may include analog-to-digital (A / D) converters (ADCs). Converting analog signals to digital quantities allows processors in electronic systems to perform signal processing functions for the systems. The performance of the ADC circuits may depend on ambient conditions such as temperature and variations that may occur during manufacture.SUMMARY OF THE DISCLOSUREThe present document describes techniques for maintaining linear performance of analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits. A higher accuracy ADC circuit (e.g., where the number of bits of the ADC circuit is twelve or greater) may require multiple calibration during its lifetime to avoid bit weighting errors. The inventors herein have recognized a need for improved calibration of ADCs.In some aspects, the present disclosure relates to a digital-to-analog converter (DAC) circuit for reducing gain mismatch errors and having an input for receiving a stream of digital input words, each digital input word divided into a most significant bit (MSB) subword and a least significant bit (LSB) subword. The circuit includes: a digital noise shaper circuit for receiving a representation of the LSB subword, the digital noise shaper configured to output a modulated LSB subword; an LSB DAC circuit for receiving and converting a combination of a representation of the LSB subword and the modulated LSB subword and generating a first analog output; an MSB DAC circuit for receiving and converting a combination of a representation of the MSB digital subword and the modulated LSB subword and generating a second analog output, wherein each of the first analog output and the second analog output are combined to generate an analog output representing the stream of input digital words.In some aspects, this disclosure relates to a method of operating a digital-to-analog converter circuit to reduce gain mismatch errors. The method comprises: receiving a stream of digital input words, each digital input word being divided into a most significant bit (MSB) subword and a least significant bit (LSB) subword; noise shaping a representation of the LSB subword to generate a modulated LSB subword; receiving and converting a combination of a representation of the LSB subword and the modulated LSB subword and generating a first analog output; receiving and converting a combination of a representation of the MSB digital subword and the LSB modulated subword and generating a second analog output, and combining each of the first analog output and the second analog output to generate an analog output representing the stream of input digital words.In some aspects, the present disclosure relates to an integrated circuit device including an analog-to-digital converter circuit including a digital-to-analog converter (DAC) circuit. The DAC circuit comprises: a segmenting circuit having an input for receiving a stream of input digital words, each input digital word comprising an MSB digital subword and an LSB digital subword, the segmenting circuit comprising: a digital noise shaper circuit having an input for receiving a representation of the LSB subword, the digital noise shaper being configured to output a modulated LSB subword, the modulated LSB subword having a word length less than the LSB subword; an LSB circuit for receiving the LSB digital subword and the LSB modulated subword, the LSB circuit to subtract the LSB modulated subword from the corresponding LSB digital subword to generate a first digital output, the LSB circuit comprising an LSB encoder circuit; an MSB circuit for receiving the MSB digital subword and the LSB modulated subword, the MSB circuit to add the LSB modulated subword and the MSB digital subword to generate a second digital output, the MSB circuit comprising an MSB encoder circuit. The DAC circuit includes: an LSB DAC circuit for receiving and converting a representation of the first digital output and generating a first analog output using an LSB DAC circuit output; an MSB DAC circuit for receiving and converting a representation of the second digital output and generating a second analog output using an MSB DAC circuit output, the LSB DAC circuit and the MSB DAC circuit generating the first and second analog output, respectively, in proportion to the relative bit weights of the LSB and MSB digital subwords, the LSB DAC circuit output coupled to the MSB DAC circuit output for combining each of the first analog output and the second analog output to generate an analog output representing the stream of digital input words.This overview is intended to provide an overview of the subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is an example of a portion of a digital-to-analog converter that uses scrambling to frequency shape analog mismatch errors. FIG. 2 is a block diagram of a digital-to-analog converter that uses bit splitting techniques. FIG. 3 is a conceptual diagram illustrating an example of an existing DAC circuit for noise shaping an error resulting from a gain mismatch between multiple DACs in the DAC circuit. FIG. 4 is a conceptual diagram illustrating an example of a DAC circuit for noise shaping an error resulting from a gain mismatch between multiple DACs in the DAC circuit using various techniques of this disclosure. FIG. 5 is a functional block diagram of an example of an N-bit successive approximation register (SAR) ADC circuit that can implement various techniques of this disclosure. FIG. 6 is a block diagram of an example of a DAC circuit for implementing various techniques of this disclosure. FIG. 7 is a block diagram of another example of a DAC circuit for implementing various techniques of this disclosure. FIG. 8 is a block diagram of another example of a DAC circuit for implementing various techniques of this disclosure. FIG. 9 is a block diagram of another example of a DAC circuit for implementing various techniques of this disclosure. FIG. 10A is a conceptual diagram illustrating a standard first order error feedback delta-sigma modulator. FIG. 10B shows the example of the delta-sigma modulator of FIG. 9 having the terminology presented in FIG. 10A. FIGS. 11 and 12 are conceptual diagrams illustrating other examples of delta-sigma modulators that could be used to implement various techniques of this disclosure. FIG. 13 is a block diagram of another example of a DAC circuit for implementing various techniques of this disclosure. Fig. 14 shows an example of a delta-sigma modulator circuit which controls the three clusters in Fig. 13. FIG. 15 is a conceptual diagram showing an example of a DAC circuit for noise shaping an error resulting from a gain mismatch between the three DACs in FIG. 13. FIG. 16 illustrates the delta-sigma modulator configuration of FIG. 14 including a dual register technique in accordance with this disclosure. FIG. 17 illustrates the delta-sigma modulator configuration of FIG. 14 including the addition of dither, in accordance with this disclosure. FIG. 18 shows an example of a code-selected register circuit for reducing tone generation in accordance with this disclosure. FIG. 19 is a flow chart showing an example of a method of operating a digital-to-analog converter circuit in an integrated circuit device to reduce gain mismatch errors.In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. Like numerals having different letter suffixes may represent different cases of similar components. The drawings illustrate generally, by way of example, but not limitation, various embodiments discussed in the present document.DETAILED DESCRIPTIONFIG. 1 is an example of a portion of an existing digital-to-analog converter that uses scrambling to frequency shape analog mismatch errors. The DAC circuit 100 of FIG. 1 may include a thermometer encoder circuit 102 for receiving and encoding an N-bit, e.g., 10-bit, input signal. Thermometer encoder circuit 102 may convert the N binary weighted bits to balanced bits, where M is 2 N. The balanced bits may be passed through a scrambler 104 and then applied to a digital-to-analog converter (DAC) 106 having balanced analog elements that sum the outputs of the scrambler 104 to form an analog signal 108. The analog elements may be switched capacitors that provide packets of charge, switched currents, or switched voltages that are summed with resistors. The DAC 106 may be followed by an analog low pass filter that may remove the out-of-band noise generated by a non-illustrated digital modulator.It may be desirable to use a large number of bits to increase resolution. This may cause the required circuit area and power consumption to increase, which is not practical in the converter system of FIG. 1. For example, the 10-bit DAC circuit 100 of FIG. 1 would require a 1024-level scrambler (2 N, where N=10).The number of analog elements and swap cells may be reduced using two or more DACs instead of a single DAC with 2 N levels. Each DAC may have its own thermometer encoder and the analog weights for each DAC may be different as shown in the example of FIG. 2.FIG. 2 is a block diagram of a digital-to-analog converter circuit that uses bit splitting techniques. In the DAC circuit 109 of FIG. 2, an N-bit word may be split into most significant bits (MSBs), least significant bits (LSBs), sub-LSBs, sub-sub-LSBs, etc.For example, in FIG. 2, a 10-bit word may be split into the four (4) MSBs B1-B4, three (3) LSBs B5-B7, and three sub-LSBs B8-B10.The four MSBs B1-B4 may be converted by thermometer encoder 110 into 15 balanced bits, which are sent through scrambler 112 and drive 16-level DAC 114. The three LSBs B5-B7 may be converted by thermometer encoder 116 into 7 balanced bits which pass through scrambler 118 and drive an 8-level DAC 120. The three sub-LSBs B8-B10 may be converted by thermometer encoder 122 into 7 balanced bits that pass through scrambler 124 and drive an 8-level DAC 126.The analog outputs of the DACs 114, 120, and 126 may be summed at 128. The output of DAC 114 has bit weights of K, the output of DAC 120 has bit weights of K / 16, and the output of DAC 126 has bit weights of K / 128. The output at 128 is an analog value equal to the 10-bit digital input word. Only 32 analog elements are required (16+8+8) as compared to 1024 elements required in the converter of Figure 1.For purposes of this disclosure, each associated thermometer encoder, scrambler, and DAC may be referred to as a "cluster.". FIG. 2 shows three (3) clusters, where "cluster 1" is associated with the four MSBs B1-B4, "cluster 2" is associated with the three LSBs B5-B7, and "cluster 3" is associated with the three LSBs B8-B10.As mentioned above, the techniques of FIG. 2 may advantageously reduce the number of analog elements and swapper cells by using multiple DACs instead of a single DAC with 2 N levels, thereby reducing hardware costs. In addition, each of the DACs 114, 120, 126 may be linearized because, on average, each element in the DACs 114, 120, 126 has the same utilization due to the use of the scrambler. Any mismatches between elements of a DAC, e.g., resistive elements, capacitor elements, current source elements, can be overcome because the elements are used to the same extent on average.Although any errors in the DACs 114, 120, 126 are modulated into noise due to the use of the scramblers, errors resulting from gain mismatches between the three DACs are not fixed and therefore generate tones. For example, if the average weight of the elements in DAC 2 120 is different than the average weight of the elements in DAC 1 114, then there is a gain mismatch between those two DACs.The gain mismatch between DACs may cause a nonlinearity error depending on the input signal. If the DACs are perfect and there is no gain mismatch, there is no error when the outputs of the DACs are combined. However, if there is a gain mismatch when the outputs of the DACs are combined, this mismatch error can cause significant distortion and harmonics.FIG. 3 is a conceptual diagram showing an example of an existing DAC circuit 200 for noise shaping an error resulting from a gain mismatch between multiple DACs in the DAC circuit. Described in more detail below, the delta-sigma modulator outputs the input signal plus shaped quantization noise. The LSB DAC is driven by the difference between the output of the delta-sigma modulator and the input signal, which is equal to the shaped quantization noise. The benefit of using the shaped quantization noise to drive the LSB DAC is that it is signal independent and does not exhibit nonlinearity. It is also shaped so that there is little noise content at low frequencies, e.g. the frequencies of interest.More specifically, a digital input word comprising "A", MSBs, and LSBs may be applied to an input 202 of a segmentation circuit 204 comprising a digital noise shaper circuit 200, e.g., a delta-sigma modulator or a PWM modulator. The input digital words A are applied to the digital noise shaper 206, which reduces the word length of the input words A and generates the noise shaped partial digital words B. The error introduced by the word length reduction is noise shaped rather than white. A second digital subword C is generated by subtracting subword B from input word A in subtracter 208. Delta-sigma modulator 206 and subtractor 208 divide digital input word A into subwords B and C and segment them, respectively.Subword C is equal to A-B and B+C=A. The digital subword B is MSB aligned with the digital input word A in subtractor 208, with the two low order bits of subword B input to subtractor 208 set to a logic zero. Since subword B tracks with input word A, subword C is small and has fewer bits than the original input word A. Since input words A are noise shaped, subwords B and C are noise shaped. The subwords B and C are both noise shaped and have smaller word lengths than the input word A, and their sum is equal to the original input word A.Subword B is received by MSB DAC 210 and subword C is received by LSB DAC 212. The subword B is equal to A plus the noise transfer function (NTF) of the digital noise shaper 206 (H) multiplied by its quantization error (E) so that B = A + HE. When C = A-B, C = A - (A+HE)= -HE. In this manner, the MSB DAC 210 of FIG. 3 receives the input A plus the quantization noise HE, and the LSB DAC 212 receives the negative quantization noise or HE. The MSB DAC output is coupled to the LSB DAC output to combine its analog outputs at 214 and generate an analog output representing the stream of digital input words A.Additional information regarding the circuit of Figure 3 can be found in US 5 977 899 A.However, the inventors herein have recognized that gain errors between the MSB DAC and the LSB DAC in FIG. 3 (or analogously between DAC 1, DAC 2, and DAC 3 of FIG. 2 ) may not be repaired using the techniques of FIG. 2. Using various techniques, this disclosure handles DAC element ratio errors between clusters, e.g., cluster 1, cluster 2, and cluster 3 of FIG. 2, of a DAC circuit.FIG. 4 is a conceptual diagram illustrating an example of a DAC circuit 300 for noise shaping an error resulting from a gain mismatch between multiple DACs in the DAC circuit using various techniques of this disclosure. Described in more detail below, in FIG. 4, the MSB input is provided to the main or MSB DAC circuit 302. The LSBs are noise shaped, e.g., delta sigma modulated, by a noise shaper circuit 304, which is then added to the MSB DAC circuit 302. As such, the MSB DAC circuit 302 is driven by D 1, which includes the MSBs and the LSBs, and where the LSBs include shaped noise. The LSB DAC circuit 306 is driven by D2, which is the difference between the output of the delta-sigma modulator (LSBs plus shaped noise) and the input to the delta-sigma modulator (LSB), which is equal to the negative shaped quantization noise. When correctly modulated, the signal D2 does not have a signal component. It has a DC average value which is small or even zero.If there is no gain mismatch between the elements in the MSB DAC circuit 302 and the elements in the LSB DAC circuit 306, then no error occurs at the analog output 308 where the analog outputs of the MSB DAC circuit 302 and the LSB DAC circuit 306 are combined.The DAC circuit 300 of FIG. 4 includes a segmentation circuit 310 having inputs 312, 314 for receiving a stream of input digital words including MSBs (MSB digital subwords) and LSBs (LSB digital subwords). The segmentation circuit 310 further comprises the digital noise shaper 304, e.g. the delta-sigma modulator, having an input for receiving a representation of the LSB subword "LSB" and outputting a digital modulated LSB subword "S1b", wherein the modulated digital LSB subword has a smaller word length than the LSB subword, e.g. a bit. In FIG. 4, the modulated LSB subword output of the digital noise shaper 304 may be, for example, a single bit "S1b" having both the LSB signal spectrum and any noise shaped quantization error.Segmentation circuit 310 may include MSB circuit 316 and LSB circuit 318. As seen in FIG. 4, the LSB circuit 318 may receive the LSB digital subword ("LSB") and the LSB modulated subword ("S 1 b"), and may subtract the LSB modulated subword ("S 1 b") from the corresponding LSB digital subword ("LSB") to generate a first digital output ("D 2"), D2=LS-S. The LSB circuit 318 may include an LSB encoder circuit, e.g., a thermometer encoder circuit 116, such as shown in FIG. 2. In some examples, the LSB circuit 318 may include a subtractor circuit coupled to the thermometer encoder circuit, or the thermometer encoder circuit itself may perform the functionality of the subtractor circuit. In some examples, the LSB circuit 318 may include a scrambler, e.g., a barrel shifter, such as shown at 112 in FIG. 2.The MSB circuit 316 of FIG. 4 may receive the MSB digital subword ("MSB") and a representation, e.g., inverted version, of the modulated LSB subword ("S1") and may add the modulated LSB subword ("S1") to the corresponding MSB digital subword (MSB) to generate a second digital output (D1), D1=MS+S. The MSB circuit 316 may include an MSB encoder circuit, e.g., a thermometer encoder circuit 110, such as shown in FIG. 2. In some examples, the MSB circuit 316 may include an adder circuit coupled to the thermometer encoder circuit, or the thermometer encoder circuit may perform the functionality of the adder circuit. In some examples, the MSB circuit 316 may include a scrambler, e.g., a barrel shifter, such as shown at 118 in FIG. 2.The DAC circuit 300 of FIG. 4 may include the LSB DAC circuit 306 and the MSB DAC circuit 302. The LSB DAC circuit 306 may receive and convert a representation of the first digital output, generate LSB DAC code D 2, and generate a first analog output 320 using an LSB DAC circuit output. The MSB DAC circuit 302 may receive and convert a representation of the second digital output, generate MSB DAC code D 1, and generate a second analog output 322 using an MSB DAC circuit output. The combined code is D1+D2=(MSB+S1b)+(LSB+S1)=MSB+LSB.The LSB DAC circuit 306 and the MSB DAC circuit 302 may generate the first and second analog outputs 320 and 322, respectively, in proportion to the relative bit weights of the LSB and MSB digital subwords. The output of the LSB DAC circuit 306 may be coupled to the output of the MSB DAC circuit 302 to combine each of the first analog output and the second analog output to generate an analog DAC output at 308 representing the stream of digital input words.The DAC techniques shown in FIG. 4 and described in more detail below may be used with any type of analog-to-digital converter, including, but not limited to, SAR ADCs, pipelined ADCs, and delta-sigma ADCs.FIG. 5 is a functional block diagram of an example of an N-bit successive approximation register (SAR) ADC circuit that can implement various techniques of this disclosure. The SAR ADC circuit 400 may include a sampling circuit 402, a digital-to-analog converter (DAC) circuit 404 (e.g., a capacitor DAC, a resistor DAC, a current source DAC), a comparator circuit 406, and SAR logic control circuitry 408.The DAC circuit 404 may implement the DAC techniques described above with respect to FIG. 4 and as described in the course of this disclosure. The DAC circuit 404 may include at least N weighted circuit components, such as in which the weight (e.g., capacitance value) of a particular weighted circuit component relative to that of one or more other weighted circuit components may be predetermined, where N is a positive integer. In certain examples, N is sixteen and the weighted circuit components include sixteen capacitors (e.g., with the sixteen capacitors including different multiples of a given unit capacitor to obtain the weight relative to each other). The sampling circuit 205 may sample an input voltage at an input to the ADC circuit and may hold a sampled voltage for comparison with another voltage using the weighted circuit components.An output voltage (Vdaco) of the DAC circuit 404 may be compared to the sampled and held voltage, such as using a comparator circuit 406. The bit values of the DAC circuit 404 may be adjusted, such as based on the output of the comparator circuit 406. The conversion may begin with the DAC set to the midscale in one example. The comparator 406 may determine whether the DAC output is greater or less than the sampled input voltage and the comparison result may be stored as a one or zero for that bit of the DAC. The conversion then proceeds to the next bit value until all bits of the digital value are determined. An iteration of changing the DAC output and comparing the voltage to the input voltage may be referred to as a bit trial or bit determination.The SAR logic circuitry 408 may control ADC operation, such as during bit trials (charge balancing of a reference charge stored on the bit trial capacitors with respect to the sampled charge stored on the sampling capacitors). The SAR logic circuitry 408 initiates a sample of the input voltage, initiates the first conversion of the sampled input voltage to a first set of bit values, such as using a first set of bit trials, and initiates a second conversion of the sampled input voltage to a second set of bit values, such as using a second set of bit trials.The logic circuitry may include a state machine or other digital engine 410 for performing functions such as advancing the ADC through various operating states and performing the described computations. Logic circuitry 408 may determine the final N-bit digital value for the sampled input, and the final N-bit digital value may be made available at output Dout.It should be noted that although the techniques of this disclosure are described with respect to a SAR ADC, e.g., the SAR ADC 400 of FIG. 5, the techniques are not limited to SAR ADCs. Rather, the techniques may also be applied to delta-sigma ADCs, pipeline ADCs, pipeline SAR ADCs, as well as other ADCs.FIG. 6 is a block diagram of an example of a DAC circuit 500 for implementing various techniques of this disclosure. The DAC circuit 500 may implement the techniques described above with respect to FIG. 4. The DAC circuit 500 of FIG. 6 includes a segmentation circuit 502 that includes two clusters 504 and 506. Cluster 504 may include an MSB circuit 508 including thermometer encoder circuit 510 and scrambler circuit 512, and an MSB DAC circuit 514, e.g., capacitor DAC, resistor DAC, current source DAC. The three MSBs B1-B3 and the modulation bit "s1b" may be converted by the thermometer encoder 510 into 8 balanced codes, which pass through the scrambler 512 and drive the 8-level MSB DAC 514. Each of the 8 lines shown control a single DAC element, e.g., capacitor, resistor, current source, in the MSB DAC circuit 514. Bits B1, B2, B3 control 7 elements, and modulation bit "s1b" controls one element.Cluster 506 may include an LSB circuit 516 including a thermometer encoder circuit 518, a scrambler circuit 520, and an LSB DAC circuit 522, e.g., a capacitor DAC. The two LSBs B4-B5 and the modulation bit "s1" may be converted by the thermometer encoder circuit 518 into 4 balanced bits which pass through the scrambler circuit 520 and drive the 4-level LSB DAC circuit 522. Each of the 7 lines shown controls a single DAC element, e.g., a capacitor, a resistor, a current source, in the LSB DAC circuit 522. Bits B4, B5 control 3 elements, and modulation bit "s1" controls 4 elements. Any error at which the LSB DAC circuit 522 is dependent on the codes B 4, B 5 as mentioned above (when B 4, B 5 are active). The modulation bits "s 1" and "s 1 b" may also be referred to as "selection signals".Before moving to further details of FIG. 6, intuitive description may be helpful. Bit "s1" may be modulated to cancel the signal component of B4, B5. This can be accomplished by monitoring the output of the LSB DAC circuit and modulating "s1" such that the sum of the LSB DAC circuit output is constant over a temporal average. The goal is that the LSB DAC circuit output is close to an average regardless of the values for B4, B5. Because there are 7 elements in the example cluster 2 (s 1=4 and B 4B 5=3), the average value is 3.5. Note that another value to which an error can be compared can be calculated using other techniques, and this disclosure is not limited to using a value equal to half the number of elements.It should also be noted that in the example shown in FIG. 6, "s 1" controls 4 elements in the LSB DAC circuit and "s 1 b" controls 1 element in the MSB DAC circuit because the elements of the MSB DAC circuit are weighted four times more than the elements in the LSB DAC circuit.Any difference between the average, e.g., 3.5, for example, and the actual LSB DAC output may be considered an immediate error for that particular sample and may be accumulated in a digital accumulator, e.g., an integrator. The accumulated value may be several bits, so it can be clipped by a quantizer and then added to B4, B5 as an input to the thermometer encoder. This magnitude can be considered the input signal. The modulation bit "s1" is then adjusted as much as possible to the signal to correct the errors. This limits the accumulated error over time and the average error (accumulated error divided by the number of samples) can be controlled to zero.The segmenting circuit 502 may include a digital noise shaper circuit 524. As seen in FIG. 6, the digital noise shaper circuit 524 may be coupled to the outputs of the thermometer encoder circuit 518 to receive a representation of the LSB subword B4, B5. In some examples, the digital noise shaper circuit 524 may include a delta-sigma modulator, as shown in FIG. 6, including an integrator circuit 526, e.g., a delaying integrator circuit, and a quantizer circuit 528. The digital noise shaper circuit 524 may output a modulated LSB subword "s1b", as seen in FIG. 6. As mentioned above, the LSB subword "s1b" is the LSBs plus shaped noise. When summed, the LSBs B4, B5 plus "s1" are equal to the shaped quantization noise. It should be noted that "s1" and "s1b" are always complementary.The MSB circuit 508 may receive the modulated LSB subword "s1b", and the LSB circuit 516 may receive a unified version of the modulated LSB subword "s1b" (e.g., via an inverter 530), namely "s1". The MSB DAC circuit 508 receives the MSBs and the LSBs, where the LSBs have shaped noise.In the example shown in FIG. 6, the digital noise shaper circuit 524 may be coupled to the outputs of the thermometer encoder circuit 518 of the cluster 506 or "cluster 2". In the particular non-limiting example shown in FIG. 6, cluster 2 has 7 DAC elements of equal size. Because cluster 2 has 7 DAC elements of equal size, it is desirable that the output sum of thermometer encoder circuit 518 of cluster 2 be 3.5.The actual output sum of thermometer encoder circuit 518 minus 3.5 is considered an immediate error or "error" as shown in Figure 6. The digital noise shaper circuit 524, e.g., the delta-sigma modulator, may accumulate and update the immediate error at each clock cycle using the integrator circuit 526. Quantizer circuit 528, e.g., a 1-bit quantizer, determines the quantized version of the accumulated error, e.g., "s1b" or "s1", in the next clock cycle. The delta-sigma modulator loop may cause the accumulated error to be limited to a finite value, thus the average error is 0, where the average error is equal to the accumulated error divided by the accumulated time. Quantizer circuit 528 may output modulated LSB subword "s1b", which may be provided to an input of MSB circuit 508, and LSB circuit 516 may receive a unified version of modulated LSB subword "s1b", namely "s1".Using the techniques of FIG. 6, the outputs of each of the thermometer encoder circuits 510, 518 may control the average element weight in its respective cluster because of the scrambler circuit in each cluster. Furthermore, the modulation of cluster 2 by signal "s1" to signal independent thermometer codes results in cluster 2. this can be achieved, for example, if half of the CADW-2 elements in cluster are "1" and half are "0" on average in time for any given LSB code, e.g., B4, B5 in the particular example shown in Figure 6.To achieve the signal independent thermometer codes in cluster 2, redundant bits "s1b" and "s1" may be fed into cluster 1 and cluster 2, respectively. Bit "s1b" may control one (1) DAC element in MSB DAC circuit 514 in cluster 504 or "cluster 1" and bit "s1" may control four (4) DAC elements in LSB DAC circuit 522 in cluster 2. In this particular example implementation, because the weight of a DAC element in MSB DAC circuit 514 is four times the weight of a DAC element in LSB DAC circuit 522, the total weight of the elements controlled by "s 1 band "s 1" is equal. Furthermore, bits "s1b" and "s1" are complementary, so changing "s1" only generates a mismatch error at the combined DAC output.The LSB circuit 516 may receive the LSB digital subword B 4, B 5 and the unified modulated LSB subword "s 1" and generate a first digital output (D 2=LSB-s 1). The MSB circuit may receive the MSB digital subword B1, B2, B3 and the modulated LSB subword "s1b" and generate a second digital output (D1=MSB+s1).The LSB DAC circuit 522 may receive and convert a representation of the first digital output and generate an analog output "Analog Output 2" using an LSB DAC circuit output. In some examples, the representation of the first digital output may include the result of the output of thermometer encoder circuit 518 added to -3.5 in FIG. 6. The MSB DAC circuit 514 may receive and convert a representation of the second digital output and generate an analog output "Analog Output 1" using an MSB DAC circuit output. The LSB DAC circuit 522 and the MSB DAC circuit 514 may generate their analog outputs proportional to the relative bit weights of the LSB and MSB digital subwords. As seen in FIG. 6, the LSB DAC circuit output is coupled to the MSB DAC circuit output to combine "Analog Output 1" and "Analog Output 2" to produce a combined analog output ("Analog Output") representing the stream of digital input words.FIG. 7 is a block diagram of another example of a DAC circuit for implementing various techniques of this disclosure. The DAC circuit 600 may implement the techniques described above with respect to FIG. 4. The DAC circuit 600 has some features similar to those described above with respect to FIG. 6, and for the sake of brevity, those features will not be described in detail again.In contrast to the example shown in FIG. 6, the DAC circuit 600 of FIG. 7 couples the digital noise shaper circuit 524, e.g., the delta-sigma modulator, to the input of the LSB circuit 516, e.g., the input of the thermometer encoder circuit 518 of the cluster 2. As before, the digital noise shaper circuit 524, e.g., the delta-sigma modulator, may accumulate and update the immediate error in each clock cycle using the integrator circuit 526, e.g., a delaying integrator circuit. Quantizer circuit 528, e.g., a 1-bit quantizer, determines the quantized version of the accumulated error, e.g., "s1b" or "s1", in the next clock cycle. Quantizer circuit 528 may output modulated LSB subword "s1b", which may be provided to an input of MSB circuit 508, and LSB circuit 516 may receive a unified version of modulated LSB subword "s1b", namely "s1".In the example shown in FIG. 7, it should be noted that the modulation bits (or modulated LSB subwords or "selection codes") "s1" and "s1b" are based on previous B4, B5values, not the current B4, B5values. In essence, the circuit of Figure 7 predicts the value of "s1b" for the next sample B4, B5. However, this prediction may be inaccurate, which may result in distortion at the output. The present inventors have overcome this problem using the techniques of Figs. 8 and 9. Note that there is some delay in FIG. 7 that results from the delaying integrator 526 in the delta-sigma modulator 524.FIG. 8 is a block diagram of another example of a DAC circuit for implementing various techniques of this disclosure. The DAC circuit 700 may implement the techniques described above with respect to FIG. 4. The DAC circuit 700 has some features similar to those described above with respect to FIGS. 6 and 7, and for the sake of brevity, those features will not be described in detail again.As mentioned above with respect to the DAC circuit 600 of FIG. 7, the modulation bits "s 1" and "s 1 b" are calculated using the previous B4, B5 values and not the current B4, B5 values. The DAC circuit 700 of FIG. 8 includes delay circuits 532 at the inputs of the MSB circuit 508 and the inputs of the LSB circuit 516, which may delay the samples by one clock cycle. Thus, the sample B4, B5 is synchronized to the "s1" signal and the sample B1, B2, B3 is synchronized to the "s1b" signal.However, these delay circuits 532 introduce latency. Desirably, the modulation bits "s1" and "s1b" are predetermined before the current values of B1-B5 are updated, and thus there is no latency in the design. However, in some examples, delta-sigma modulator 524 may generate undesired tones when an active B4, B5 signal is used. The inventors of the present invention have overcome the problem of the tones in Fig. 8 using the techniques of Fig. 9.FIG. 9 is a block diagram of another example of a DAC circuit for implementing various techniques of this disclosure. The DAC circuit 800 may implement the techniques described above with respect to FIG. 4. The DAC circuit 800 has some features similar to those described above with respect to FIGS. 6-8, and for the sake of brevity, those features will not be described in detail again. The circuit of FIG. 9 may eliminate the delays of FIGS. 7 and 8 and may eliminate unwanted tones.Delta-sigma modulator 802 of FIG. 9 has an error feedback configuration in which the input of modulator 802 is summed with an output of register 804. Delta-sigma modulator 802 is coupled to an input of LSB circuit 516 and modulated LSB subword "s1" received by LSB circuit 516 is a complement of modulated LSB subword "s1b" received from MSB circuit 508.Delta-sigma modulator 802 of FIG. 9 may calculate the modulation bits "s 1" and "s 1 b" based on the current B4, B5 information. Thus, the sample B4, B5 is synchronized to the "s1" signal and the sample B1, B2, B3 is synchronized to the "s1b" signal. In addition, delta-sigma modulator 802 may suppress unwanted tones.Delta-sigma modulator 802 may receive the current B4, B5 value and sum with a feedback signal 806 representing the previous error stored in register 804. The sum of the current B4, B5 value and the feedback signal 806 may be provided to the quantizer 808 to generate the modulation bits "s1" and "s1b". Also, as seen in FIG. 9, at adder 810, the sum of the current B4, B5 value and feedback signal 806 may be added to the "s1" value, minus 3.5 (the average of the 7 bits in the example shown in FIG. 9 to generate the immediate value at 812.FIG. 10A is a conceptual diagram illustrating a standard first order error feedback delta-sigma modulator. Delta-sigma modulator 802 of FIG. 9 is different from, but equivalent to, standard error feedback delta-sigma modulator 900 of FIG. 10A. Delta-sigma modulator 900 of FIG. 10A receives an input signal x(n) and subtracts a feedback error signal e(n-1) at subtractor 902 to generate a signal y(n). The signal y(n) is fed to a quantizer 904 to generate an output signal v(n). In addition, the signal y(n) is subtracted from the output signal v(n) at subtractor 906 to produce the current error signal e(n), which is supplied to a delay circuit 908. The output signal v(n)=x(n)+e(n)-e(n-1), where v(n) is the modulation bit "s1b".FIG. 10B shows the example of delta-sigma modulator 802 of FIG. 9 having the terminology presented in FIG. 10A. The terminology of the standard first order error feedback delta-sigma modulator 900 in Figure 10A is mapped to the modulator in Figure 10B to show its equivalence.As seen in FIG. 10B, the input to delta-sigma modulator 802 is the signal x(n)=B4(n ), B5(n). The modulation bit s1= -v(n)= -x(n)-[e(n)-e(n-1)]. The LSB DAC circuit 516 of FIG. 9 receives the LSBs B4(n), B5(n) and s1(n) such that DAC2data=x(n)+s1(n)=-[e(n)-e(n-1)].Referring to the Z range, Z(s1b)=X(Z)+(1-Z -1) E(Z). For the LSB cluster 506 of FIG. 9 or the "Cluster 2", Z(DAW2 data) = -(1-Z -1) E(Z). For the MSB cluster 504 of FIG. 9 or "Cluster1", Z(DAC1 data)=Z(signal)+(1-Z -1) E(Z), where (1-Z -1) E(Z) is the noise shaped component. Thus, the LSB cluster 506 of FIG. 9 receives noise and the MSB cluster 504 of FIG. 9 receives the signal plus a noise shaped component. When combined at the outputs of LSB DAC circuit 522 and MSB DAC circuit 514, both of FIG. 9, Z(DAC1 data)+Z(DAC2 data)=Z(signal)+(1-Z -1) E(Z)-(1-Z -1) E(Z)=Z(signal).FIGS. 11 and 12 are conceptual diagrams illustrating other examples of delta-sigma modulators that could be used to implement various techniques of this disclosure. Delta-sigma modulator 1000 of FIG. 11 is a first order delta-sigma modulator. Delta-sigma modulator 1000 receives an input signal x(n) and subtracts an output signal v(n) at subtractor 1002. The output of the subtractor 1002 is fed to a non-delay integrator 1004. The output of the integrator 1004 is fed to a quantizer 1006 to produce an output signal v(n). The output signal v(n)=x(n)+e(n)-e(n-1), where v(n) is the modulation bit "s1b". The non-delay integrator of FIG. 11 may result in identical signal and quantization noise transfer functions to those of the delta-sigma modulator 900 of FIG. 10A. However, in some example implementations, it may be impractical to implement a non-delay integrator.Delta-sigma modulator 1010 of FIG. 12 is another first order delta-sigma modulator and is similar to delta-sigma modulator 1000 of FIG. 11, and similar features will not be described again for purposes of brevity. In contrast to FIG. 11, delta-sigma modulator 1010 of FIG. 12 includes a delaying integrator 1012. The output signal v(n)=x(n-1)+e(n)-e(n-1), where v(n) is the modulation bit "s1b2".A delay integrator may be more practical. A delaying integrator will still provide shaped first order quantization noise, but now the input x(n) is delayed by one sample and appears at the output as x(n-1).FIG. 13 is a block diagram of another example of a DAC circuit for implementing various techniques of this disclosure. FIG. 13 is similar to the DAC circuit of FIG. 6, FIG. 13 but shows three (3) clusters (MSB clusters 504, LSB clusters 506, sub-LSB clusters 1102) instead of the two (2) clusters (MSB clusters 504, LSB clusters 506) of FIG. 6. It should be noted that the techniques of this disclosure are not limited to DAC circuits having two or three clusters, but may be extended to more than three clusters.Cluster 1102 may include sub-LSB circuit 1104 including thermometer encoder circuit 1106 and scrambler circuit 1108, and sub-LSB DAC circuit 1110, e.g., capacitor DAC, resistor DAC, current source DAC. The two sub-LSBs B6-B7 and the modulation bit "s2" may be converted by the thermometer encoder circuit 1106 into four balanced bits, which pass through the scrambler circuit 1108 and drive 4 DAC elements of the 8-level sub-LSB DAC circuit 1110. Each line shown between an encoder and a scrambler and a scrambler and a DAC represents multiple lines, where each one of the multiple lines may control a single DAC element, e.g., capacitor, resistor, current source, in sub-LSB DAC circuit 1110. Bits B6, B7 control 3 elements and modulation bit "s2" controls 4 elements. Any error contributed by the sub-LSB DAC circuit 522 depends on codes B 6, B 7 as mentioned above (when B 6, B 7 are active). The modulation bits "s 2" and "s 2 b" may also be referred to as "selection signals" or sub-LSB modulated subwords.As seen in FIG. 13, the MSB cluster 1 and the LSB cluster 2 are controlled using modulation bits "s1b" and "s1", respectively, as described above. To correct any gain errors that may occur between the LSB cluster 2 and the sub-LSB cluster 3, the modulation bits "s2b" and "s2" are included, where "s2b" is an input to the LSB cluster 2 and "s2" is an input to the sub-LSB cluster 3. It should be noted that "s2" and "s2b" are always complementary. The implementation of s1 / s2 control is shown and described in Figure 14.FIG. 14 shows an example of a delta-sigma modulator circuit 1200 for controlling the three clusters in FIG. 13. Delta-sigma modulator 802 shown in the lower portion of FIG. 14 is similar to delta-sigma modulator 802 of FIGS. 9 and 10B and will not be described in detail again. As seen in FIG. 14, the input to delta-sigma modulator 1202 in the upper portion is signal B6(n), B7(n), and the input to delta-sigma modulator 802 is signal B4(n), B5(n).The adder 1204 of the delta-sigma modulator 1202 receives the signal B4(n), B5(n) and sums the modulation bit "s2b(n)" from the delta-sigma modulator 802 and the previous error 1206 stored in the register 1208. The result 1210 is input to the quantizer 1212, e.g., a 1-bit quantizer, which outputs the modulation bit "s1b(n)". The modulation bit "s1b(n)" is inverted by the inverter 1214 to generate the modulation bit "s1(n)", and the modulation bits "s1b(n)" and "s1(n)" are input to the cluster 1 and the cluster 2, respectively, as seen in FIG. 13. Similarly, the modulation bit "s2b(n)" is inverted by the inverter 530 to generate the modulation bit "s2(n)", and the modulation bits "s2b(n)" and "s2(n)" are input to the cluster 2 and the cluster 3, respectively, as seen in FIG. 13.In delta-sigma modulator 1202, the output of adder 1204 is provided to adder 1216 and summed with modulation bit "s1(n)" and -4, where -4 represents the average of the 8 elements of cluster 2 (4 elements for "s1", 3 elements for B4, B5 and 1 element "s2"). The output of adder 1216 represents the immediate error stored in register 1208.FIG. 15 is a conceptual diagram illustrating an example of a DAC circuit for noise shaping an error resulting from a gain mismatch between the three DACs in FIG. 13. The circuit 1300 of FIG. 15 extends the concept diagram of FIG. 4 from two (2) to three (3) clusters. Similar features will not be described again.As seen in FIG. 15, delta-sigma modulator 1302 of cluster 3 may generate second modulation bit "s 2", which is subtracted from the LSB 2 input at sub-LSB DAC circuit 1104 to generate digital output "D 3". The digital output "D 3" drives the sub-LSB DAC circuit 1110.The modulation bit "s2" is added together with the LSB 1 to the delta sigma modulator 304 of cluster 2 to generate the modulation bit "s1".FIG. 16 illustrates the delta-sigma modulator configuration of FIG. 14 having a dual register technique, in accordance with this disclosure. As seen in Figure 16, each of the registers 804, 1208 of Figure 14 has been replaced by a respective dual register circuit 1502, 1504. The dual register circuit 1502 includes two registers 1506A, 1506B, wherein register 1506A can be selected by a clock signal and a control signal "sel2b" to close the switches 1508A, 1508B, and the switches 1508C and 1508D can be opened by a complementary control signal "sel2". The register 1506B may be selected by a clock signal and a control signal "sel 2" to close the switches 1508C, 1508D, and the switches 1508C and 1508D may be opened by a complementary control signal "sel2b". Dual register circuit 1504 includes two registers 1510A, 1510B and may be similarly selected using switches 1512A- 1512D.The dual register circuits 1502, 1504 shown in FIG. 16 may reduce or eliminate idle tones without the addition of dither. Dither may require additional head room, which may not be available in some implementations.The control signals may randomly select which register to use, which may reduce or eliminate idle tones. In some example implementations, it may be desirable to add dither to the delta-sigma modulator, as shown in FIG. 17.FIG. 17 illustrates delta sigma modulator circuit 802 of FIG. 10B with the addition of dither, in accordance with this disclosure. Dither may be added to delta-sigma modulator circuit 802 to aid in randomizing. As seen in FIG. 17, dither may be added at various locations in the circuit. In some examples, dither may be added to the input to quantizer 808. In other examples, dither may be added with the data input, e.g., B4(n), B5(n), by adder 810, and then input to register circuit 804.FIG. 18 shows an example of a code-selected register circuit for reducing tone generation according to this disclosure. The register circuit 1600 may be used instead of the register 804 in FIG. 10B and the registers 804, 1202 in FIG. 14, for example. To reduce tone generation, the data itself, e.g., B4, B5, may be the control signal for closing / opening the switches associated with the various registers to select a register.The example circuit in FIG. 18 includes 4 registers 1602A- 1602D and 8 switches 1604A- 1604H. Each register can be selected by controlling two associated switches to close and open the remaining six switches. For example, as seen in Figure 18, a combination of B4, B5 equal to "11" would close switches 1604G, 1604H to select register 1602D and open switches 1604A-1604F to deselect registers 1602A-1602C.The various techniques described above may be used to linearize a DAC circuit. These circuits may be used for any type of DAC circuit, including, but not limited to, capacitor DACs, resistor DACs, current DACs. Additionally, the DAC techniques of this disclosure may be used with any type of analog-to-digital converter, including, but not limited to, SAR ADCs, pipelined ADCs, and delta-sigma ADCs.FIG. 19 is a flow diagram illustrating an example of a method 1700 of operating a digital-to-analog converter circuit in an integrated circuit device to reduce gain mismatch errors. At block 1702, the method 1700 may include receiving a stream of input digital words, each input digital word including an MSB digital subword and an LSB digital subword.At block 1704, method 1700 may include noise shaping a representation of the LSB subword to generate a modulated LSB subword, wherein the modulated LSB subword has a smaller word length than the LSB subword.At block 1706, the method 1700 may include receiving the LSB digital subword and the modulated LSB subword using an LSB circuit and subtracting the modulated LSB subword from the corresponding LSB digital subword to generate and encode a first digital output.At block 1708, the method 1700 may include receiving the MSB digital subword and the modulated MSB subword using an MSB circuit and adding the modulated LSB subword to the corresponding MSB digital subword to generate and encode a second digital output.At block 1710, method 1700 may include receiving and converting a representation of the first digital output using an LSB DAC circuit and generating a first analog output using an LSB DAC circuit output.At block 1712, the method 1700 may include receiving and converting a representation of the second digital output using an MSB DAC circuit and generating a second analog output using an MSB DAC circuit output, wherein the LSB DAC circuit and the MSB DAC circuit have the first and second analog outputs proportional to the relative bit weights of the LSB and MSB subwords, respectively.At block 1714, the method 1700 may include combining each of the first analog output and the second analog output to generate an analog output representing the stream of digital input words.Various AnnotationsEach of the non-limiting aspects and examples described herein may be self-standing or may be combined with one or more of the other examples in various permutations and combinations.The above detailed description has references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples.". Such examples may include elements in addition to those shown or described. However, the inventors of the present invention also contemplate examples in which only those elements shown or described are provided. In addition, the inventors of the present invention also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof) either with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.In the case of non-uniform use between this document and any documents so incorporated by reference, the use in this document is predictive.In this document, the terms "a / an" are used, as is common in patent documents, to include one or more than one, regardless of any other instances or uses of "at least one" or "one or more.". In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" includes "A but not B", "B but not A", and "A and B", unless otherwise indicated. In this document, the terms "comprising" and "in which" are used as the equivalents of the respective terms "comprising" and "wherein" are used in a simple language. Moreover, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, apparatus, article, composition, formulation, or process having elements in addition to those recited in such term in a claim are still considered to fall within the scope of that claim. Moreover, in the following claims, the terms "first", "second", and "third", etc. are used merely as labels and are not intended to impose numerical requirements on their objects.Method examples described herein may be machine- or computer-implemented, at least in part. Some examples may include a computer readable medium or a machine readable medium encoded with instructions executable to form an electronic device to perform methods as described in the above examples. Implementation of such methods may include code such as microcode, assembly language code, higher level language code, or the like. Such code may include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in one example, the code may be stored substantially on one or more transitory, non-transitory, or non-transitory tangible computer readable media such as during execution or at other times. Examples of such tangible computer readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as by one of ordinary skill in the art upon consideration of the above description. The Abstract is presented to comply with 37 C.F.R. §1.72(b) for the reader to quickly ascertain the nature of the technical disclosure. It is submitted in the understanding that it will not be used to interpret or limit the scope or meaning of a claim. In addition, in the above detailed description, various features may be grouped together to simplify the disclosure. This should not be construed as intended to mean an unclaimed disclosed feature for any claim. Rather, the subject matter of the invention may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments may be combined with one another in various combinations or permutations. The scope of the present invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.In one aspect, a more accurate ADC circuit (e.g., where the number of bits of the ADC circuit is twelve or more) may require multiple calibration during its working life to avoid bit weight errors. Described are techniques for handling DAC element ratio errors between ADC element clusters in a DAC circuit to maintain the linear performance of analog-to-digital converter (ADC) circuits and digital-to-analog converter (DAC) circuits.The disclosure is subject matter of the following sections, which are not claims:Section (1): A digital-to-analog converter (DAC) circuit for reducing gain mismatch errors and having an input for receiving a stream of input digital words, each input digital word being divided into a most significant bit (MSB) subword and a least significant bit (LSB) subword, the circuit comprising: a digital noise shaper circuit for receiving a representation of the LSB subword, the digital noise shaper being configured to output a modulated LSB subword; an LSB DAC circuit for receiving and converting a combination of a representation of the LSB subword and the modulated LSB subword and generating a first analog output; an MSB DAC circuit for receiving and converting a combination of a representation of the digital MSB subword and the modulated LSB subword and generating a second analog output, wherein each of the first analog output and the second analog output are combined to generate an analog output representing the stream of digital input words.Section (2): The DAC circuit of section (1), the circuit comprising: a segmenting circuit having an input for receiving the stream of input digital words, the segmenting circuit comprising: the digital noise shaper circuit; an LSB circuit for receiving the LSB digital subword and the LSB modulated subword, the LSB circuit to subtract the LSB modulated subword from the corresponding LSB digital subword to generate a first digital output, the LSB circuit comprising an LSB encoder circuit; an MSB circuit for receiving the MSB digital subword and the LSB modulated subword, the MSB circuit to add the LSB modulated subword and the MSB digital subword to generate a second digital output, the MSB circuit comprising an MSB encoder circuit; wherein the LSB DAC circuit is configured to receive and convert a combination of a representation of the LSB subword and the LSB modulated subword and to generate a first analog output to receive and convert a representation of the first digital output of the LSB circuit and to generate the first analog output; and wherein the MSB DAC circuit is configured to receive and convert a combination of a representation of the MSB digital subword and the modulated LSB subword and to generate a second analog output to receive and convert a representation of the second digital output of the MSB circuit and to generate the second analog output, wherein the LSB DAC circuit and the MSB DAC circuit generate the first and second analog outputs, respectively, in proportion to the relative bit weights of the LSB and MSB digital subwords.Section (3): The DAC circuit according to a preceding section, in particular section (2), wherein the digital noise shaper circuit comprises a delta-sigma modulator circuit.Section (4): The DAC circuit of any preceding section, particularly section (3), wherein the delta-sigma modulator circuit comprises a delay integrator circuit and wherein the modulated LSB subword received by the LSB circuit is a complement of the modulated LSB subword received by the MSB circuit.Section (5): The DAC circuit of a previous section, in particular section (4), wherein the delta-sigma modulator circuit is coupled to an output of the LSB circuit.Section (6): The DAC circuit according to a preceding section, in particular section (4), wherein the delta-sigma modulator circuit is coupled to an input of the LSB circuit.Section (7): The DAC circuit of any preceding section, particularly section (6), further comprising: an MSB delay circuit coupled to an input of the MSB circuit for receiving and delaying the MSB digital subword; and an LSB delay circuit coupled to an input of the LSB circuit for receiving and delaying the LSB digital subword.Section (8): The DAC circuit of any preceding section, in particular section (2), wherein the digital noise shaper circuit comprises a delta-sigma modulator circuit having an error feedback configuration, wherein the delta-sigma modulator circuit is coupled to an input of the LSB circuit, and wherein the modulated LSB subword received by the LSB circuit is a complement of the modulated LSB subword received by the MSB circuit.Section (9): The DAC circuit of any preceding section, in particular section (2), wherein the stream of input digital words further comprises a sub-LSB digital sub-word, wherein the segmentation circuit further comprises: a sub-LSB digital noise shaper circuit having an input for receiving a representation of the sub-LSB sub-word, wherein the sub-LSB digital noise shaper is configured to output a sub-LSB modulated sub-word, wherein the sub-LSB modulated sub-word has a smaller word length than the sub-LSB sub-word; a sub-LSB circuit for receiving the sub-LSB digital subword and the sub-LSB modulated subword, the sub-LSB circuit to subtract the sub-LSB modulated subword from the corresponding sub-LSB digital subword to generate a third digital output, the sub-LSB circuit comprising a sub-LSB encoder circuit, the LSB circuit further receiving a representation of the sub-LSB modulated subword to generate the first digital output; a sub-LSB DAC circuit for receiving and converting a representation of the third digital output and generating a third analog output using a sub-LSB DAC circuit output, the sub-LSB DAC circuit output coupled to the MSB DAC circuit output and the LSB DAC circuit output for combining each of the first analog output, the second analog output and the third analog output to generate an analog output representing the stream of digital input words.Section (10): The DAC circuit of any preceding section, in particular section (1), wherein the first noise shaper circuit and the dual register circuit comprises a first register and a second register, wherein the first register and the second register are randomly selected.Section (11): The DAC circuit of any preceding section, particularly section (1), wherein the digital noise shaper circuit comprises a plurality of code selected registers.Section (12): The DAC circuit according to a preceding section, in particular section (1), further comprising: a dither generator circuit configured to supply different dither values to the digital noise shaper circuit.Section (13): A method of operating a digital-to-analog converter circuit to reduce gain mismatch errors, the method comprising: receiving a stream of input digital words, each input digital word being divided into a most significant bit (MSB) subword and a least significant bit (LSB) subword; noise shaping a representation of the LSB subword to generate a modulated LSB subword; receiving and converting a combination of a representation of the LSB subword and the modulated LSB subword and generating a first analog output; receiving and converting a combination of a representation of the MSB digital subword and the modulated LSB subword and generating a second analog output; and combining each of the first analog output and the second analog output to generate an analog output representing the stream of input digital words.Section (14): The method of section (13), the method further comprising: receiving the LSB digital subword and the LSB modulated subword using an LSB circuit and subtracting the LSB modulated subword from the corresponding LSB digital subword to generate and encode a first digital output; receiving the MSB digital subword and the LSB modulated subword using an MSB circuit and adding the LSB modulated subword and the MSB digital subword to generate and encode a second digital output; wherein receiving and converting a combination of a representation of the LSB subword and the modulated LSB subword and generating a first analog output comprises receiving and converting a representation of the first digital output using an LSB DAC circuit and generating the first analog output; and wherein receiving and converting a combination of a representation of the MSB digital subword and the modulated LSB subword and generating a second analog output comprises receiving and converting a representation of the second digital output using an MSB DAC circuit and generating the second analog output, wherein the LSB DAC circuit and the MSB DAC circuit generate the first and second analog outputs, respectively, in proportion to the relative bit weights of the LSB and MSB digital subwords.Section (15): The method of any preceding section, particularly section (14), wherein the noise shaping comprises a representation of the LSB subword to generate a modulated LSB subword using a delta-sigma modulator circuit to noise shape the representation of the LSB subword to generate the modulated LSB subword.Section (16): The method of any preceding section, particularly section (15), wherein using a delta-sigma modulator circuit to noise shape the representation of the LSB subword to generate the modulated LSB subword further comprises using a delaying integrator circuit.Section (17): The method of any preceding section, in particular section (15), further comprising: coupling the delta-sigma modulator circuit to an output of the LSB circuit.Section (18): The method of any preceding section, particularly section (15), further comprising: coupling the delta-sigma modulator circuit to an input of the LSB circuit.Section (19): The method of any preceding section, in particular section (18), further comprising: coupling an MSB delay circuit to an input of the MSB circuit for receiving and delaying the digital MSB subword; and coupling an LSB delay circuit to an input of the LSB circuit for receiving and delaying the digital LSB subword.Section (20): The method of any preceding section, particularly section (14), wherein noise shaping a representation of the LSB subword to generate a modulated LSB subword comprises using a delta-sigma modulator circuit having an error feedback configuration to noise shape the representation of the LSB subword to generate the modulated LSB subword, the method further comprising: coupling the delta-sigma modulator circuit to an input of the LSB circuit, and wherein the modulated LSB subword received by the LSB circuit is a complement of the modulated LSB subword received by the MSB circuit.

Claims

A digital-to-analog converter (DAC) circuit (300) for reducing gain mismatch errors and comprising an input for receiving a stream of input digital words, each input digital word being divided into a most significant bit (MSB) subword and a least significant bit (LSB) subword, the circuit comprising: a digital noise shaper circuit (304) for receiving a representation of the LSB subword, the digital noise shaper circuit (304) being configured to output a modulated LSB subword; an LSB DAC circuit (306) to receive and convert a combination of a representation of the LSB subword and the modulated LSB subword and to generate a first analog output; an MSB DAC circuit (302) to receive and convert a combination of a representation of the digital MSB subword and the modulated LSB subword and to generate a second analog output, wherein each of the first analog output and the second analog output are combined to generate an analog output representing the stream of digital input words.The DAC circuit (300) of claim 1, wherein the circuit comprises: a segmenting circuit (310) having an input for receiving the stream of input digital words, wherein the segmenting circuit (310) comprises: the digital noise shaper circuit (304); an LSB circuit (318) for receiving the LSB digital subword and the LSB modulated subword, wherein the LSB circuit is to combine the LSB modulated subword and the corresponding LSB digital subword to generate a first digital output; an MSB circuit (316) for receiving the MSB digital subword and the LSB modulated subword, the MSB circuit to combine the LSB modulated subword and the MSB digital subword to generate a second digital output.The DAC circuit (300; 800) of claim 1 or 2, wherein the digital noise shaper circuit (304) comprises a delta-sigma modulator circuit (802; 1000; 1010).The DAC circuit (300; 500) of any of claims 1 to 3, wherein the digital noise shaper circuit (304) comprises a delay integrator circuit (526), and wherein the modulated LSB subword received by the LSB circuit (318) is a complement of the modulated LSB subword received by the MSB circuit (316).The DAC circuit (300) of any of claims 2 to 4, wherein the digital noise shaper circuit (304) is coupled to an output of the LSB circuit (318).The DAC circuit (300) of any of claims 2 to 4, wherein the digital noise shaper circuit (304) is coupled to an input of the LSB circuit (318).The DAC circuit (300) of any of claims 2 to 6, further comprising: an MSB delay circuit coupled to an input of the MSB circuit for receiving and delaying the MSB digital subword; and an LSB delay circuit coupled to an input of the LSB circuit for receiving and delaying the LSB digital subword.The DAC circuit of any of claims 3 to 7, wherein the delta-sigma modulator circuit (1000; 1010) comprises an error feedback configuration, and wherein the delta-sigma modulator circuit (1000; 1010) is coupled to an input of the LSB circuit (318).The DAC circuit of any of claims 2 to 8, wherein the stream of input digital words further comprises a sub-LSB digital sub-word, wherein the segmenting circuit (310) further comprises: a sub-LSB digital noise shaper circuit having an input for receiving a representation of the sub-LSB sub-word, wherein the sub-LSB digital noise shaper circuit is configured to output a modulated sub-LSB sub-word; a sub-LSB circuit (1104) for receiving the sub-LSB digital sub-word and the sub-LSB modulated sub-word, the sub-LSB circuit to subtract the sub-LSB modulated sub-word from the corresponding sub-LSB digital sub-word to generate a third digital output; and a sub-LSB DAC circuit (1110) for receiving and converting a representation of the third digital output and to generate a third analog output.The DAC circuit of any of claims 1 to 9, wherein the digital noise shaper circuit (304) comprises a dual register circuit (1502) having a first register (1506A) and a second register (1506B), wherein the first register (1506A) and the second register (1506B) are randomly selected.The DAC circuit of any of claims 1 to 10, wherein the digital noise shaper circuit (304) comprises a plurality of code selected registers.The DAC circuit of any of claims 1 to 11, further comprising a dither generator circuit configured to provide different dither values to the digital noise shaper circuit (304).A method (1700) of operating a digital-to-analog converter circuit to reduce gain mismatch errors, the method comprising: receiving (1702) a stream of input digital words, each input digital word divided into a most significant bit (MSB) subword and a least significant bit (LSB) subword; noise shaping (1704) a representation of the LSB subword to generate a modulated LSB subword; receiving and converting a combination of a representation of the LSB subword and the modulated LSB subword and generating a first analog output; receiving and converting a combination of a representation of the MSB digital subword and the LSB modulated subword and generating a second analog output, and combining (1714) each of the first analog output and the second analog output to generate an analog output representing the stream of input digital words.The method (1700) of claim 13, the method further comprising: receiving (1706), using an LSB circuit (318), the LSB digital subword and the LSB modulated subword and combining the LSB modulated subword and the corresponding LSB digital subword to generate a first digital output; receiving (1708), using an MSB circuit (316), the MSB digital subword and the LSB modulated subword and combining the LSB modulated subword and the MSB digital subword to generate a second digital output.The method (1700) of claim 13 or 14, wherein the noise shaping comprises a representation of the LSB subword to generate a modulated LSB subword comprises using a delta sigma modulator circuit (802; 1000; 1010) to noise shape the representation of the LSB subword to generate the modulated LSB subword.The method (1700) of any of claims 13 to 15, wherein the noise shaping comprises using a delay integrator circuit.The method (1700) of any of claims 14 to 16, further comprising coupling a noise shaping circuit to an output of the LSB circuit (318).The method (1700) of any of claims 14 to 16, further comprising coupling a noise shaping circuit to an input of the LSB circuit (318).The method (1700) of any of claims 14 to 18, further comprising: coupling an MSB delay circuit to an input of the MSB circuit (316) to receive and delay the MSB digital subword; and coupling an LSB delay circuit to an input of the LSB circuit (318) to receive and delay the LSB digital subword.The method (1700) of any of claims 14 to 19, wherein noise shaping a representation of the LSB subword to generate a modulated LSB subword comprises using a delta-sigma modulator circuit (802; 1000; 1010) having an error feedback configuration to noise shape the representation of the LSB subword to generate the modulated LSB subword, the method (1700) further comprising: coupling the delta-sigma modulator circuit (802; 1000; 1010) to an input of the LSB circuit (318).An integrated circuit device, comprising: an analog-to-digital converter circuit comprising a digital-to-analog converter (DAC) circuit (300), the DAC circuit comprising: a segmentation circuit (310) comprising an input for receiving a stream of input digital words, each input digital word comprising an MSB digital subword and an LSB digital subword, the segmentation circuit (310) comprising: a digital noise shaper circuit (304) having an input for receiving a representation of the LSB subword, the digital noise shaper circuit (304) being configured to output a modulated LSB subword, the modulated LSB subword having a shorter word length than the LSB subword; an LSB circuit (318) for receiving the LSB digital subword and the LSB modulated subword, the LSB circuit (318) to subtract the LSB modulated subword from the corresponding LSB digital subword to generate a first digital output, the LSB circuit (318) comprising an LSB encoder circuit; an MSB circuit (316) for receiving the MSB digital subword and the LSB modulated subword, the MSB circuit (316) to add the LSB modulated subword and the MSB digital subword to generate a second digital output, the MSB circuit (316) comprising an MSB encoder circuit; an LSB DAC circuit (306) for receiving and converting a representation of the first digital output and generating a first analog output using an LSB DAC circuit output; an MSB DAC circuit (302) for receiving and converting a representation of the second digital output and generating a second analog output using an MSB DAC circuit output, wherein the LSB DAC circuit (306) and the MSB DAC circuit (302) generate the first or second analog output proportional to the relative bit weights of the LSB and MSB digital subwords, wherein the LSB DAC circuit output is coupled to the MSB DAC circuit output for combining each of the first analog output and the second analog output to generate an analog output representing the stream of input digital words.

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