Manufacturing method for a semiconductor device

Abstract

Method comprising: Forming a dielectric layer (106) over a substrate (104), Structuring the dielectric layer (106) to form a first recess (142), Structuring the dielectric layer (106) to form a second recess (144), Depositing a first layer (120) in the first recess (142), Depositing the first layer (120) in the second recess (144), Depositing a second layer (122) over the first layer (120), wherein the second layer (122) is different from the first layer (120), depositing the second layer (122) in the second recess (144), Performing a first chemical mechanical polishing (CMP) process on the second layer (122) using a first oxidizing agent, wherein the first CMP process ends upon detecting an endpoint, after performing the first CMP, performing a second CMP process on the second layer (122) and the first layer (120) using the first oxidizing agent, Forming a first conductive element over remaining portions of the first layer (120) after the second CMP polishing has been performed, and Forming a second conductive element over remaining portions of the first layer (120) and the second layer (122) in the second recess after the second CMP polishing has been performed, wherein after the first CMP process, a combined height of the first layer (120) and the second layer (122) above the dielectric layer (106) adjacent to the first recess (142) is greater than a combined height of the first layer (120) and the second layer (122) above the dielectric layer (106) adjacent to the second recess (144).

Description

STATE OF THE ART

[0001] In the current process of miniaturizing semiconductor devices, low-k dielectric materials are desirable as the intermetal and / or interlayer dielectric between conductive interconnects to reduce the RC delay due to capacitive effects during signal propagation. Therefore, the lower the dielectric layer constant of the dielectric, the lower the parasitic capacitance of adjacent conductive lines and the lower the RC delay of the integrated circuit (IC).

[0002] However, the materials currently considered or used as low-k dielectric materials are not ideal. In particular, when selecting a material based on its k value, and especially based on its low-k value, other characteristics, such as the material's hardness or strength, may not be ideal for use in a semiconductor manufacturing process. Therefore, improvements in processes using low-k dielectric materials are desirable.

[0003] JP 2017 - 157 591 A relates to a CMP polishing fluid for cobalt polishing, which comprises an aromatic carboxylic acid compound and water and has a pH value above 4.0. Further prior art can be found in US 2004 / 0 023 499 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 to 16 illustrate intermediate stages in forming a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0005] The invention is as defined in the independent claims. The dependent claims relate to corresponding developments. The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples. This repetition is done for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] In addition, terms relating to spatial relativity, such as "beneath," "under," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature(s) as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device being used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different manner (rotated 90 degrees or oriented differently), and the terms relating to spatial relativity used herein may be equally construed accordingly.

[0007] Fig. 1 to 16 illustrate cross-sectional and / or top views of intermediate stages in forming a semiconductor device 100 according to some embodiments. According to some embodiments, an interconnect structure may be formed over a substrate. The interconnect structure may include one or more conductive features, e.g., conductive lines, active devices, passive devices, and / or dummy devices. A method for forming a conductive feature may include overfilling a recess and then thinning the overfilled recess to a desired thickness, e.g., using a chemical mechanical polishing (CMP) process. In some embodiments, the conductive features may be formed using a metal that is comparatively expensive. For example, the conductive features may be formed using ruthenium.If a relatively expensive metal is used, overfilling and subsequent thinning can waste expensive metal and increase costs. Furthermore, the conductive features may be formed using a metal that is comparatively difficult to chemically polish. For example, to efficiently chemically polish ruthenium, it may be necessary to use a strong oxidizer, which can generate gases that are harmful when inhaled by humans. Using a weak oxidizer to chemically polish ruthenium may make the manufacturing process safer, but the CMP process time may be undesirably excessive.

[0008] According to some embodiments, a two-layer process may be used to form conductive features in a dielectric layer of an interconnect region. The first layer is formed in a recess of a dielectric layer in which a conductive feature will be formed, wherein the first layer comprises a material composition from which the conductive feature is desired to be fabricated. A second layer may be formed over the first layer, wherein the second layer comprises a material composition that may be less expensive than a material composition of the first layer and / or that may be more easily chemically mechanically polished than a material composition of the first layer. Multiple CMP processes may be performed to thin the second layer, the first layer, and the dielectric layer to a desired thickness.Because of the presence of the second layer, at least one of the CMP processes is substantially performed on the second layer rather than the first layer, which may result in wasting a cheaper metal and / or may be more efficient using only a relatively weak oxidizer, which may improve manufacturing reliability and / or save time.

[0009] With reference to Fig. 1, a semiconductor device 100 includes a semiconductor substrate 104. The semiconductor substrate 104 may be formed from a semiconductor material, such as doped or undoped silicon, or an active layer of an SOI (semiconductor on an insulator) substrate. The semiconductor substrate 104 may include other semiconductor materials, such as germanium, a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. Devices (not shown), such as transistors, diodes, capacitors, resistors, etc., may be formed in and / or on an active area of ​​the semiconductor substrate 104.

[0010] Fig. 1 through 16 show intermediate stages in forming an interconnect structure over the semiconductor substrate 104. A dielectric layer 106 is formed over the semiconductor substrate 104. In some embodiments, the dielectric layer 106 is an interlayer dielectric layer (ILD). The dielectric layer 106 may be formed from a polymer, which may be a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a combination thereof, or the like, which may be patterned using lithography. In other embodiments, the dielectric layer 106 is formed from a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), a combination thereof, or the like.The dielectric layer 106 may be formed using spin coating, lamination, chemical vapor deposition (CVD), or the like.

[0011] Fig. 2 to 15 show the formation of conductive features each in a region 110, a region 112 and a region 114 (which are shown, for example, in Fig. 2) may be formed in the semiconductor device 100. According to some embodiments, all of the regions 110, 112, and / or 114 may be arranged on a same semiconductor device 100, or each of the regions 110, 112, and 114 may be arranged on separate semiconductor devices 100. Although three regions 110, 112, and 114 are illustrated, in some embodiments, conductive features may be formed in additional regions or in fewer regions. When formed in a same semiconductor device 100, the regions 110, 112, and 114 may be arranged adjacent to each other or in separate portions of the semiconductor device 100. Conductive features formed in the regions 110, 112, and 114 may be a conductive line, an active device, a passive device, a seal ring, an alignment line (such as a scribe frame), a dummy device, a combination thereof, or the like. Fig. 1 to 16 show the formation of an SRAM device in region 110, a logic device in region 112, and a seal ring in region 114.

[0012] With reference to Fig. 2, a mask 108 is formed over the dielectric layer 106. In some embodiments, the mask 108 is a photoresist and may be formed using a spin-on technique. Although a single layer is shown, in some embodiments, the mask 108 may be a three-layer or a two-layer layer. In other embodiments, the mask 108 may be deposited using, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. The mask 108 may comprise silicon nitride, a metal hard mask layer, a combination thereof, or the like.

[0013] Next, the mask 108 is patterned, for example, using suitable photolithographic techniques. The resulting structure is shown in Fig. 3. As shown in Fig. 3, patterning of the mask 108 has formed recesses 142 in the mask 108. Portions of the dielectric layer 106 are exposed through the recesses 142.

[0014] With reference to Fig. 4, the pattern of mask 108 is transferred to dielectric layer 106. An etching process may be performed using mask 108 as an etch mask. The etching may be anisotropic in some embodiments. According to some embodiments, the etching process may be time-controlled such that, after a predetermined time elapses, the etching process ends and dielectric layer 106 has been etched by a desired amount. After the etching process is completed, recess 142 has been extended into dielectric layer 106. In some embodiments, recesses 142 may penetrate through only a portion of dielectric layer 106 and may not extend completely through dielectric layer 106. After etching, recesses 142 may have tapered sidewalls.

[0015] After the etching process is completed, the remaining portions of the mask 108 may be removed, for example, using an ashing process. The resulting structure is shown in Fig. 5 shown.

[0016] Next, with reference to Fig. 6, a mask 116 is formed over the dielectric layer 106. The mask layer 116 is formed in the recesses 142 in the dielectric layer 106. In some embodiments, the mask 116 is a photoresist and may be formed using a spin-on technique. Although a single layer is shown, in some embodiments, the mask 116 may be a three-layer or a two-layer layer. In other embodiments, the mask 116 may be deposited using, for example, ALD, CVD, PVD, or the like. The mask 116 may comprise silicon nitride, a metal hard mask layer, a combination thereof, or the like.

[0017] With reference to Fig. 7, the mask 116 is patterned, for example, using suitable photolithographic techniques. Patterning the mask 116 forms recesses 144. Portions of the dielectric layer 106 are exposed through the recesses 144.

[0018] Next, the pattern of the mask 116 is transferred to the dielectric layer 106. An etching process may be performed using the mask 116 as an etch mask. The etching may be anisotropic. According to some embodiments, the etching process may be time-controlled, such that after a predetermined time elapses, the etching process is terminated and the dielectric layer 106 has been etched by a desired amount. In other embodiments, the etching process may continue until the dielectric layer 106 is etched through and the semiconductor substrate 104 is detected. After the etching process is completed, the recess 144 is extended into the dielectric layer 106. In some embodiments, the recesses 144 may penetrate through the dielectric layer 106 and expose the semiconductor substrate 104. After etching, the recesses 144 may have tapered sidewalls. The resulting structure is shown in Fig. 8 shown.

[0019] When the etching process ends, the mask 116 may be removed, for example, using an ashing process. The resulting structure is shown in Fig. 9 shown.

[0020] Next, a seed layer 118 is formed over the dielectric layer 106 and in the recesses 142 and 144. In some embodiments, the seed layer 118 may comprise copper, although other suitable materials may be used. The seed layer 118 may be formed using a deposition process such as ALD, PVD, CVD, plasma-enhanced chemical vapor deposition (PECVD), or the like. The seed layer 118 may extend along top surfaces of the dielectric layer 106, along sidewalls of the recesses 142 and 144, and bottom surfaces of the recesses 142 and 144. The resulting structure is shown in Fig. 10 shown.

[0021] Fig. 11 and Fig. 12 illustrates the filling and overfilling of recesses 142 and 144 with a first layer 120 and a second layer 122. Some conductive features may be formed by overfilling recesses in a dielectric layer with a conductive material and then thinning the conductive material and dielectric layer to a desired size, for example, using a chemical mechanical polishing (CMP) process. However, during the CMP process, the excess portions of the conductive material, for example, portions that overfill the recesses, are removed. If the conductive material is relatively expensive, then the CMP process may waste a relatively expensive material. Furthermore, the conductive material used may affect the parameters and timing of the thinning process. For example, an oxidizer may be used in the CMP process.If a conductive material is used that is comparatively difficult to thin using a CMP process, then a CMP process that uses a relatively weak oxidizer can take a comparatively long time to complete. For example, if ruthenium is used as the conductive material and H2O2 is used as the oxidizer, the CMP process can be relatively long. If a strong oxidizer, such as IO4 or ClO4, is used in the CMP process, the process can be completed more quickly. However, the strong oxidizer can generate gases (e.g., RuO4) that are harmful to humans, making device fabrication more hazardous.

[0022] According to some embodiments, conductive features may be formed using a two-layer process. A first layer 120 may be formed using the conductive material that will be used in the formed conductive features. The first layer 120 may be deposited in recesses of the dielectric layer such that the recesses are filled or partially filled. Next, a second layer 122 (see Fig. 12) is formed over the first layer to a desired thickness. The second layer 122 may be relatively inexpensive compared to the first layer 120 and comparatively easy to thin using a CMP process. As such, during a subsequent CMP process, at least a portion of the material being thinned is the second layer 122 rather than the first layer 120. As such, the waste material generated is relatively inexpensive, and the CMP process can proceed comparatively faster using only a weak oxidizer, making the manufacturing process safer.

[0023] With reference to Fig. 11, a first layer 120 is formed over the seed layer 118 and in the recesses 142 and 144. In some embodiments, the first layer 120 may comprise a conductive material, for example, a metal. The first layer 120 may comprise a noble metal, such as ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, or a combination thereof. Noble metals may be advantageous due to the ability to resist oxidation and / or corrosion. The first layer 120 may be deposited using, for example, CVD. In other embodiments, the first layer 120 may be deposited using PVD, ALD, PECVD, or the like.

[0024] The deposition process of the first layer 120 may continue until the first layer 120 fills and / or overfills the recesses 142 and 144 of the regions 110 and 112. The deposition process may also end before the recesses are filled, as illustrated in the recess 144 of the region 114. After the deposition process, the first layer 120 may have a non-planar top surface including one or more peaks and one or more valleys, where valleys in the top surface correspond to the recesses 142 or 144 in the dielectric layer 106.

[0025] As in Fig. 11, the region 110, which may include relatively narrow recess openings compared to the regions 112 and 114, may be filled with the first layer 120 until the first layer 120 overfills the recesses 142 and 144 and extends a distance D1 above the top surface of the dielectric layer 106. In some embodiments, D1 may be about 1 nm to about 300 nm, such as about 30 nm Å. The region 112, which may include a recess opening that is relatively wider compared to the recess of the region 110 and relatively narrower compared to the recess of the region 114, may be filled with the first layer 120 until the first layer 120 overfills the recess 142 and extends a distance D2 above the top surface of the dielectric layer 106. D2 may be less than D1. In some embodiments, D2 may be about 1 nm to about 300 nm, such as about 25 nm.Region 114 may include a recess opening that is relatively wider compared to regions 110 and 112. Region 114 may include a recess that may be only partially filled with first layer 120. First layer 120 may also be deposited on a top surface of dielectric layer 106 in conductive feature 114 and may extend a distance D3 above the top surface of dielectric layer 106. D3 may be smaller than D1 and D2. In some embodiments, D3 may be about 1 nm to about 300 nm, such as about 20 nm.

[0026] With reference to Fig. 12, a second layer 122 is formed over the first layer 120. In some embodiments, the second layer 122 is deposited using, for example, PVD. In other embodiments, the second layer 122 may be deposited using CVD, ALD, PECVD, or the like. The second layer 122 may comprise a material that is relatively less expensive than a material used to form the first layer 120. The second layer 122 may comprise a material that is relatively easier to chemically mechanically polish using a weak oxidizer than a material used to form the first layer 120. In some embodiments, the second layer 122 may comprise a dielectric material, a metal nitride, a metal whose oxide is soluble in a suspension (e.g.,a suspension used in a CMP process), or a combination thereof. For example, according to some embodiments, the second layer 122 may comprise Co, Cu, Al, TiN, TaN, SiO2, SiN, the like, or a combination thereof. The second layer 122 may be selected depending at least in part on the material composition of the first layer 120. For example, the second layer 122 may be selected to avoid or minimize corrosion at an interface of the first layer 120 and the second layer 122.

[0027] In some embodiments, the second layer 122 may be formed to an equal height in each of the regions 110, 112, and 114. The second layer 122 may be formed to a thickness T1 in the region 110, where T1 is about 0 nm to about 1000 nm, such as about 150 nm. T1 may be measured from a top surface of the first layer 120 in the region 110. The second layer 122 may be formed to a thickness T2 in the region 112, where T2 is about 0 nm to about 1000 nm, such as about 150 nm. T2 may be measured from a top surface of the first layer 120 in the region 112. The second layer 122 may be formed to a thickness T3 in the region 110, where T3 is about 0 nm to about 1000 nm, such as about 100 nm. T3 can be measured from a top surface of the first layer 120 in the region 114.In some embodiments, T1 is less than both T2 and T3, T2 is greater than T1 but less than T3, and T3 is greater than each of T1 and T2. Although the second layer 122 does not extend into a recess in the dielectric layer 106 in region 110 or 112, in some embodiments, in region 114, the second layer 122 at least partially penetrates into and overfills the recess 144 (recesses 142 and 144 are shown in FIG. Fig. 11).

[0028] With reference to Fig. 13, one or more first CMP processes are performed on the semiconductor device 100. In some embodiments, each of the regions 110, 112, and / or 114 may be subjected to separate first CMP processes. In other embodiments, each of the regions 110, 112, and / or 114 may be subjected to a same first CMP process. Since the one or more first CMP processes are essentially a CMP of the second layer 120, a weak oxidant may be used to efficiently perform the CMP process(es). For example, an H2O2 oxidant may be used. The use of a strong oxidant, such as IO4 or ClO4, may be avoided, and manufacturing reliability may be improved.

[0029] The one or more first CMP processes may continue until the first layer 120 is detected. Due to the non-planar nature of the upper surface of the first layer 120, when the first layer 120 is detected in the one or more first CMP processes and the one or more first CMP processes end, portions of the second layer 122 may remain in the regions 100 and 112. The resulting structure is shown in Fig. 13. Due to the different heights of the first layer 120 between the regions 110, 112 and 114 (see above discussion with reference to Fig. 11), after the one or more first CMP processes, the combined thicknesses of the first layer 120 and the second layer 122 may vary between the regions 110, 112, and 114. According to some embodiments, the combined thickness of the first layer 120 and the second layer 122 in each of the regions 110, 112, and 114 after the one or more first CMP processes is substantially equal to or similar to the thickness of the first layer 120 after the first layer 120 has been deposited, wherein the thickness of the first layer 120 after it has been deposited is measured from a peak of the first layer 120 to an opposite surface of the first layer 120.

[0030] With reference to Fig. 14, one or more second CMP processes may optionally be performed in each of the regions 110, 112, and 114. In some embodiments, each of the regions 110, 112, and / or 114 may be subjected to separate second CMP processes. In other embodiments, each of the regions 110, 112, and / or 114 may be subjected to a same second CMP process. The one or more second CMP processes may remove the remaining portions of the seed layer 118, the first layer 120, and the second layer 122 that overfill the recesses 142 and 144 in the dielectric layer 106. The one or more second CMP processes may use a comparatively weak oxidizer, such as H2O2, resulting in a safer manufacturing process.Although portions of the first layer 120 may be removed in the one or more second CMP processes, because the amount of the first layer 120 removed is comparatively small, a weak oxidizer may be used without the one or more second CMP processes becoming prohibitively long.

[0031] In some embodiments, an end point of the one or more second CMP processes may be determined according to an elapsed time of the one or more second CMP processes. In embodiments in which an end point of the one or more second CMP processes is determined by time, after the one or more second CMP processes end, a thickness of the dielectric layer 106, a thickness of the first layer 120, and a combined thickness of the first layer 120 and the second layer 122 may vary in the region 110, the region 112, and / or the region 114. The thickness of the dielectric layer 106, the first layer 120, and / or a combined thickness of the first layer 120 and the second layer 122 may vary in the region 110, the region 112, and the region 114 according to the initial thickness deviation, for example, as described above in connection with Fig. 13. The resulting structure is shown in Fig. 14. In some embodiments, a thickness of the dielectric layer 106 and the first layer 120 in the region 110 is each a thickness T4, where T4 is about 5 nm to about 100 nm, such as 40 nm. In some embodiments, a thickness of the dielectric layer 106 in the region 112 is a thickness T5, where T5 is about 5 nm to about 100 nm, such as 35 nm. In some embodiments, a thickness of the dielectric layer 106 and / or a combined thickness of the first layer 120 and the second layer 122 in the region 114 is a thickness T6, where T6 is about 5 nm to about 100 nm, such as 30 nm. In some embodiments, T4 is greater than both T5 and T6, T5 is greater than T6 and less than T4, and T6 is less than each of T4 and T5.

[0032] In other embodiments, the one or more second CMP processes may end upon detection of an endpoint. For example, the one or more second CMP processes may end upon detection of the dielectric layer 106. In embodiments in which the one or more second CMP processes end upon detection of an endpoint, the combined thickness of the dielectric layer 106, the first layer 120, and the second layer 122 may be substantially the same in the region 110, the region 112, and the region 114 (in Fig. 14 not shown).

[0033] With reference to Fig. 15, one or more third CMP processes may be performed in each of regions 110, 112, and 114 to thin the first layer 120, the second layer 122, and the dielectric layer 106 to a target thickness. In some embodiments, each of regions 110, 112, and / or 114 may be subjected to separate third CMP processes. In other embodiments, each of regions 110, 112, and / or 114 may be subjected to a same third CMP process. In regions 110 and 112, the one or more third CMP processes may remove remaining portions of the seed layer 118, the first layer 120, and the dielectric layer 106. In region 114, the one or more third CMP processes may remove remaining portions of the seed layer 118, the first layer 120, the second layer 120, and the dielectric layer 106. The one or more third CMP processes may include a comparatively weak oxidizing agent, such asH2O2, resulting in a safer manufacturing process. Although portions of the first layer 120 may be removed in the one or more second CMP processes, since the amount of the first layer 120 removed is comparatively small, a weak oxidizer may be used without the one or more second CMP processes becoming prohibitively long.

[0034] The one or more third CMP processes may continue for a certain elapsed time, after which the dielectric layer 106 and the first layer 120 (and optionally the second layer 122) have a target thickness. In some embodiments, after the one or more third CMP processes have been completed, a thickness of the dielectric layer 106 and the first layer 120 (and optionally the second layer 122) has a substantially equal thickness T7. In some embodiments, T7 is about 5 nm to about 80 nm, such as about 20 nm. The resulting structure is shown in Fig. 15. A conductive feature 146 has been formed in region 110, a conductive feature 148 has been formed in region 112, and a conductive feature 150 has been formed in region 114. In some embodiments, conductive feature 146 is an SRAM device, conductive feature 148 is a logic device, and conductive feature 150 is a seal ring.

[0035] In subsequent processing, additional interconnect layers, such as interconnect layers 128, and / or additional sealing rings 150 may be formed over the dielectric layer 106, as shown in Fig. 16. As shown in Fig. 16, interconnect layers 128 may include conductive lines 132, vias 130, and a dielectric layer 138. The conductive lines 132 and / or the vias 130 may be configured to electrically and / or physically connect to the conductive feature 146, the conductive feature 148, and / or the conductive feature 150. In some embodiments, the conductive lines 132 and / or the vias 130 may connect one or more of the conductive feature 146, the conductive features 148, and / or the conductive feature 150 to each other or to external components. In some embodiments, the conductive lines 132 and / or the vias 130 may connect the conductive feature 146, the conductive features 148, and / or the conductive feature 150 to a power node or a ground node.

[0036] In one embodiment, the vias 130 and the conductive lines 132 may be formed, for example, using a dual damascene process, wherein an opening for both the vias 130 and the conductive lines 132 is formed in a given interconnect layer 128 within a respective dielectric layer, such as the dielectric layer 138. In one embodiment, the dielectric layer 138 is formed on the dielectric layer 106. In some embodiments, the dielectric layer 138 is formed from a polymer, which may be a photosensitive material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), a combination thereof, or the like, which may be patterned using lithography. In other embodiments, the dielectric layer 138 is formed from a nitride, such as silicon nitride, an oxide, such asSilicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. The dielectric layer 106 can be formed using spin coating, lamination, chemical vapor deposition (CVD), or the like.

[0037] Openings for the conductive lines 132 and the vias 130 may be formed by disposing and patterning a photoresist material over the dielectric layer 138. After the photoresist material has been disposed and patterned, a dry etching process, such as reactive ion etching, may be used to transfer the pattern from the patterned photoresist to the underlying dielectric layer 138. This process may be repeated to form both the via portion of the opening and the trench portion of the opening.

[0038] After the opening is formed, the opening may be filled with a conductive material to form the vias 130 and the conductive lines 132 within the dielectric layer 138. In one embodiment, the formation of the conductive material may be initiated by first forming a barrier layer (not separately described in Fig. 16). The barrier layer may be a barrier material, such as titanium nitride or tantalum nitride, which may be deposited using a deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like. However, any suitable material or deposition method may be used to form the barrier layer.

[0039] After the barrier layer is formed, a conductive material may be deposited to fill and overfill the openings within the dielectric layer 138. In one embodiment, the conductive material may be a material such as copper, tungsten, ruthenium, titanium dioxide, a combination thereof, or the like, formed, for example, using a seed layer (not shown) and a plating process such as electrochemical plating, although other forming processes such as sputtering, evaporation, or a PECVD process may alternatively be used depending on the desired materials. After the openings are filled with the conductive material, any excess conductive material outside the openings may be removed, and the conductive lines 132 and the dielectric layer 138 may be planarized, for example, using a chemical mechanical polishing process.The above processes can be repeated as needed to form a variety of interconnect lines suitable for a particular package design, such as in . Fig. 16 is required.

[0040] As in Fig. 16, in some embodiments, multiple conductive features 150 may be formed in multiple interconnect layers 128. The same or similar processes as those described above in connection with forming the conductive feature 150 in the dielectric layer 106 may be repeated to form additional conductive features 150 in the interconnect layers 128.

[0041] In some embodiments, die connectors 160 are formed over the interconnect layers 128. The die connectors 160 are each coupled to a corresponding topmost conductive line 132' that is furthest from the substrate 142. The die connectors 160 can provide external electrical connections to the semiconductor device 100. A passivation film 140 is located on the topmost dielectric layer 138' and on portions of the respective topmost conductive lines 132' to which the die connectors 160 are respectively coupled. Openings through the passivation film 140 are made to the respective topmost conductive lines 132' to which the die connectors 160 are respectively coupled. The die connectors 160, such as conductive pillars (e.g., comprising a metal such asCopper) are present in the openings through the passivation film 140 and are mechanically and electrically coupled to the respective uppermost conductive line 132, to which the corresponding die connectors 160 are respectively coupled. The die connectors 160 may be formed, for example, by plating or the like. The die connectors 160 may be electrically coupled to one or more of the respective conductive features of the regions 110, 112, and 114.

[0042] A dielectric material 162 is disposed on the passivation film 140 and the sidewalls of the die connectors 160. The dielectric material 162 laterally encapsulates the die connectors 160, and the dielectric material 162 is laterally adjacent to the substrate 104. The dielectric material 162 may be a polymer, such as PBO, polyimide, BCB, or the like; a nitride, such as silicon nitride or the like; an oxide, such as silicon oxide, PSG, BSG, BPSG, or the like; the like; or a combination thereof, and may be formed, for example, using spin coating, lamination, CVD, or the like.

[0043] In other embodiments, the die connectors 160 may not be formed. Instead, a solderable metallization (under bump metallization, UBM) (in Fig.16 not shown) may be formed and patterned over a topmost interconnect layer 128' according to some embodiments, thereby forming an electrical connection with a topmost conductive line 132. The UBM provides an electrical connection upon which an electrical connector, e.g., a solder ball / bump, a conductive pillar, or the like, may be disposed. In one embodiment, the UBM comprises a diffusion barrier layer, a seed layer, or a combination thereof. The diffusion barrier layer may comprise Ti, TiN, Ta, TaN, or combinations thereof. The seed layer may comprise copper or copper alloys. However, other metals, such as nickel, palladium, silver, gold, aluminum, combinations thereof, and multilayers thereof, may be included. In one embodiment, the UBM is formed using sputtering. In other embodiments, electroplating may be used.

[0044] Connectors (not shown) may be formed over the solderable metallization according to some embodiments. The connectors may be solder balls, metal pillars, C4 (Controlled Collapse Chip Connection) bumps, microbumps, bumps formed using an ENEPIG (nickel-electroless palladium-immersion gold) technique, combinations thereof (e.g., a metal pillar having a solder ball attached thereto), or the like. The connectors may comprise a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the connectors comprise a eutectic material and may, for example, comprise a solder bump or a solder ball. The solder material may, for example, be lead-based or lead-free solder, such asPb-Sn compositions for lead-based solder; lead-free solders include InSb; tin, silver, and copper (SAC) compositions; and other eutectic materials that share a common melting point and form conductive solder joints in electrical applications. For lead-free solder, SAC solders of various compositions can be used, such as SAC 105 (Sn 98.5%, Ag 1.0%, Cu 0.5%), SAC 305, and SAC 405. Lead-free interconnects, such as solder balls, can also be formed from SnCu interconnects without the use of silver (Ag). Alternatively, lead-free solder interconnects can comprise tin and silver, Sn-Ag, without the use of copper. The interconnects can form a grid, such as a ball grid array (BGA). In some embodiments, a reflow process may be performed, giving the connectors a partial sphere shape. Alternatively, the connectors may comprise other shapes.The connectors may, for example, also include non-spherical conductive connectors.

[0045] In some embodiments, the connectors comprise metal pillars (such as copper pillars) with or without a solder material thereon, formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be free of solder and may have substantially vertical sidewalls or tapered sidewalls.

[0046] As described herein, according to some embodiments, conductive features may be formed using a two-layer process. A first layer may be formed using a conductive material that will be used in conductive features formed in a dielectric layer. The first layer may be deposited in recesses of the dielectric layer such that the recesses are filled or partially filled. Next, a second layer is formed over the first layer to a desired thickness. The second layer may be relatively inexpensive compared to the first layer and relatively easy to thin using a CMP process. As such, during a subsequent CMP process, at least a portion of the material that is thinned is the second layer rather than the first layer.Therefore, the waste material produced is relatively inexpensive, and the CMP process can proceed at a relatively faster rate using only a weak oxidizer, making the manufacturing process safer.

[0047] A method is provided according to some embodiments. The method includes forming a dielectric layer over a substrate. The method further includes patterning the dielectric layer to form a first recess. The method further includes depositing a first layer in the first recess. The method further includes depositing a second layer over the first layer, wherein the second layer is different from the first layer. The method further includes performing a first chemical mechanical polishing (CMP) process on the second layer using a first oxidant, wherein the first CMP process ends upon detecting an endpoint. The method further includes, after performing the first CMP, performing a second CMP process on the second layer and the first layer using the first oxidant.The method further comprises forming a first conductive feature over remaining portions of the first layer after the second CMP polishing is performed. In one embodiment, the first layer comprises ruthenium. In one embodiment, the first oxidant comprises H2O2. In one embodiment, detecting the endpoint comprises detecting the first layer. In one embodiment, the first layer overfills the first recess and extends along a top surface of the dielectric layer after being deposited. In one embodiment, the method further comprises performing a third CMP process after the first CMP process and before the second CMP polishing, wherein the third CMP removes portions of the first layer that extend along the top surface of the dielectric layer.In one embodiment, the method comprises patterning the dielectric layer to form a second recess, depositing the first layer in the second recess, depositing the second layer in the second recess, and forming a second conductive element over remaining portions of the first layer and the second layer in the second recess after the second CMP polishing is performed. In one embodiment, after the one or more first CMP processes, a combined height of the first layer and the second layer above the dielectric layer adjacent to the first recess is greater than a combined height of the first layer and the second layer above the dielectric layer adjacent to the second recess.In one embodiment, the method comprises patterning the dielectric layer to form a third recess; and depositing the first layer in the third recess, wherein the first recess is adjacent to the second recess, and the second recess is adjacent to the third recess. In one embodiment, after the second CMP process, the second layer extends in the third recess, and the second layer does not extend in the first recess or the second recess. In one embodiment, an end point of the second CMP process is determined according to an elapsed time of the second CMP process.

[0048] A method is provided according to some embodiments. The method may include patterning a first dielectric layer to form a first recess and a second recess. The method may also include depositing a first layer in the first recess and the second recess, wherein the first layer extends along a top surface of the first dielectric layer between the first recess and the second recess, and wherein a top surface of the first layer includes a peak and a valley. The method further includes depositing a second layer over the first layer. The method may further include performing a first chemical mechanical polishing (CMP) process, wherein the first CMP process ends upon detection of the peak of the top surface of the first layer.The method may further comprise performing a second CMP process on the first layer, wherein the second CMP process ends after a first predetermined time. The method may further comprise performing a third CMP process on the first layer, wherein the third CMP process ends after a second predetermined time. In one embodiment, the first layer comprises a noble metal. In one embodiment, the first layer comprises ruthenium. In one embodiment, the first recess is adjacent to the second recess. In one embodiment, after the first CMP process, a combined thickness of the dielectric layer, the first layer, and the second layer is greater in a first region than in a second region, the first region being adjacent to the first recess and the second region being adjacent to the second recess.In one embodiment, after the second CMP process, the combined thickness of the dielectric layer, the first layer, and the second layer is greater in the first region than in the second region.

[0049] A device is provided according to some embodiments. The device comprises a substrate. The device structure further comprises a dielectric layer over the substrate. The device further comprises a first conductive feature in the dielectric layer, the first conductive feature comprising a first material. The device further comprises a second conductive feature in the dielectric layer adjacent to the first conductive feature, the second conductive feature comprising a second material over the first material. The device further comprises an electrical connector overlying at least one of the first conductive feature and the second conductive feature. In one embodiment, the first material is ruthenium.In one embodiment, an imaginary line passing through the second conductive feature in a direction parallel to a major surface of the substrate passes sequentially through the first material, the second material, and the first material.

Claims

[1] Method comprising: Forming a dielectric layer (106) over a substrate (104), Structuring the dielectric layer (106) to form a first recess (142), Structuring the dielectric layer (106) to form a second recess (144), Depositing a first layer (120) in the first recess (142), Depositing the first layer (120) in the second recess (144), Depositing a second layer (122) over the first layer (120), wherein the second layer (122) is different from the first layer (120), depositing the second layer (122) in the second recess (144), Performing a first chemical mechanical polishing (CMP) process on the second layer (122) using a first oxidizing agent, wherein the first CMP process ends upon detecting an endpoint, after performing the first CMP, performing a second CMP process on the second layer (122) and the first layer (120) using the first oxidizing agent, Forming a first conductive element over remaining portions of the first layer (120) after the second CMP polishing has been performed, and Forming a second conductive element over remaining portions of the first layer (120) and the second layer (122) in the second recess after the second CMP polishing has been performed, wherein after the first CMP process, a combined height of the first layer (120) and the second layer (122) above the dielectric layer (106) adjacent to the first recess (142) is greater than a combined height of the first layer (120) and the second layer (122) above the dielectric layer (106) adjacent to the second recess (144). [2] The method of claim 1, wherein the first layer (120) comprises ruthenium. [3] The method of claim 1 or 2, wherein the first oxidizing agent comprises H2O2. [4] Method according to one of the preceding claims, wherein detecting the endpoint comprises detecting the first layer (120). [5] The method of any preceding claim, wherein the first layer (120) overfills the first recess (142) and extends along a top surface of the dielectric layer (106) after being deposited. [6] The method of claim 5, further comprising performing a third CMP process after the first CMP process and before the second CMP polishing, wherein the third CMP removes portions of the first layer (120) that extend along the top surface of the dielectric layer (106). [7] Method according to one of the preceding claims, further comprising: Structuring the dielectric layer (106) to form a third recess, and Depositing the first layer (120) in the third recess, wherein the first recess (142) is adjacent to the second recess (144), and the second recess (144) is adjacent to the third recess. [8] The method of claim 7, wherein after the second CMP process, the second layer (122) extends in the third recess, and wherein the second layer (120) does not extend in the first recess or the second recess. [9] The method according to any one of the preceding claims, wherein an end point of the second CMP process is determined according to an elapsed time of the second CMP process. [10] A method comprising: Structuring a first dielectric layer (106) to form a first recess (142) and a second recess (144), wherein a depth of the second recess (144) is greater than a depth of the first recess (142). Depositing a first layer (120) in the first recess (142) and the second recess (144), wherein the first layer (120) extends along a top surface of the first dielectric layer (106) between the first recess (142) and the second recess (144), and wherein a top surface of the first layer (106) includes a peak and a valley, depositing a second layer (122) over the first layer (120), Performing a first chemical-mechanical polishing (CMP) process, wherein the first CMP process ends upon detection of the peak of the upper surface of the first layer (120), Performing a second CMP process on the first layer (120), wherein the second CMP process ends after a first predetermined time, and Performing a third CMP process on the first layer (120), wherein the third CMP process ends after a second predetermined time, wherein after the first CMP process, a combined thickness of the dielectric layer (106), the first layer (120), and the second layer (122) is greater in a first region (110) than in a second region (112), the first region (110) being adjacent to the first recess (142) and the second region (112) being adjacent to the second recess (144). [11] The method of claim 10, wherein the first layer (120) comprises a noble metal. [12] The method of claim 11, wherein the first layer (120) comprises ruthenium. [13] The method of any one of the preceding claims 10 to 12, wherein the first recess (142) is adjacent to the second recess (144). [14] The method of any one of the preceding claims 10 to 13, wherein after the second CMP process, the combined thickness of the dielectric layer (106), the first layer (120) and the second layer (122) is greater in the first region (110) than in the second region (112).

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