Glowing of film at different temperatures and the resulting structures

Abstract

A method comprising: forming a spacer layer (88) on a side wall of a gate stack using an atomic layer deposition process and annealing (314) the spacer layer (88) in a nitrogen environment, comprising: annealing (314) the spacer layer (88) during a first period while simultaneously increasing an annealing temperature from a first (T1) to a second temperature (T2); annealing (314) the spacer layer (88) during a second period while simultaneously increasing the annealing temperature at a second rate from the second (T2) to a third temperature (T3); annealing the spacer layer at the third temperature (T3) during a third period; annealing the spacer layer (88) during a fourth period while simultaneously decreasing the annealing temperature from the third temperature (T3) to a fourth temperature (T4) at a third rate;wherein the first temperature (T1) is between 400°C and 600°C and the second temperature (T2) is between 600°C and 1000°C and the combined duration of the first and second periods is at least 60 minutes and the duration of the third period is at least 60 minutes.

Description

GENERAL STATE OF THE ARTThe semiconductor industry has moved toward nanometer technology nodes in an effort to increase packaging densities, power, and cost, and three-dimensional designs such as a fin field effect transistor (FinFET) have been developed due to manufacturing and design issues. FinFET devices typically include high aspect ratio semiconductor fins in which channel and source / drain regions are formed. A gate is formed on and along the sides of the fin structure (e.g., by cladding), such that faster, more reliable, and more controllable semiconductor transistor devices may be fabricated due to the advantage of the increased surface area of the channel. However, the reduction in scaling involves new problems.US 8703624 B2 discloses a method for forming dielectric films with silicon which can withstand a high temperature annealing process. US 9418890 B2 discloses a method for depositing a material on a substrate within a processing chamber during a vapor deposition process, wherein the substrate is exposed to different treatment gases. US 2013 / 0309829 A1 discloses a method for manufacturing a semiconductor device having dislocations to improve carrier mobility. US 2016 / 0260811 A1 discloses a silicon-on-insulator device having elevated source / drain regions, a gate and two gate spacers, wherein a low-k layer is arranged over the elevated source / drain regions, the gate and the two gate spacers;BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure may be best understood when the following detailed description is studied together with the accompanying figures. It should be noted that various structural elements are not shown to scale in accordance with the practice customary in the industry. Rather, the dimensions for the various structural elements may be arbitrarily increased or decreased for purposes of illustration.FIGS. 1A-C, 2A-B, 3A-B, 4A-B, 5A-B, and 6A-B show different views of respective preliminary structures at intermediate stages in an exemplary process for forming a semiconductor device, in accordance with some embodiments.FIGS. 7A-B and 8A-B are cross-sectional views of respective preliminary structures at intermediate stages in another exemplary process of forming a semiconductor device, in accordance with some embodiments. FIG. 9 is a process flow for forming a gate spacer, in accordance with some embodiments. FIG. 10 is a process flow for forming and treating a material, in accordance with some embodiments.FIGS. 11A through 11H are schematic diagrams of reactions in forming and treating a material formed in FIG. 10, in accordance with some embodiments. FIG. 12 is a graphical representation of the temperature change in an annealing process, in accordance with some embodiments. FIG. 13 is a cross-sectional view of a portion of the preliminary structure of FIG. 8A illustrating further details of a gate spacer layer formed according to the process flow of FIG. 10, in accordance with some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the respective subject matter. Hereinafter, specific examples of components and arrangements will be described for convenience of the present disclosure. These are of course only examples which are not intended to be limiting. In the following description, forming a first feature on or on a second feature may include, for example, embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features are not in direct contact. In addition, in the present disclosure, reference numerals and / or reference numerals may be repeated in the various examples. This repetition is for convenience and convenience and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Spatially relative terms such as "below," "below," "lower / r," "above," "above," "upper / r," and the like may be further used herein to simplify the description to describe the relationship of an element or feature to one or more other elements or features as depicted in the figures. The terms spatially relative are intended to cover other orientations of the device during use or operation in addition to the orientation depicted in the figures. The device may be otherwise (rotated 90 degrees or oriented in another orientation) oriented, and the spatial-reference descriptors used herein may also be interpreted accordingly.Semiconductor component structures having structural elements with a lower k value (in the sense of a low-k dielectric) and methods for forming such structural elements are described here. Embodiments of the present disclosure include, in particular, forming a dielectric film and treating that film via an annealing process at different temperatures. The annealing process at different temperatures may increase the resistance of the dielectric film to damage in subsequent processing, such as etching prior to epitaxial growth, oxidation, and / or ion implantation.The dielectric film may be used for various dielectric features of a semiconductor device structure. By reducing a k value in the device, a capacitance (e.g., parasitic capacitance) of the device may be reduced, which may reduce the RC delay value (RC= Resist Capacitance) of the device. However, for example, if the k-value is reduced by adding carbon or introducing pores into a dielectric material, other properties such as plasma resistance may suffer therefrom. Embodiments described herein may provide a layer having lower k, high density, and plasma resistance and provide methods of forming the layer. The layer having the lower k value may have high plasma resistance and better capacity performance. Further, processes for forming dielectric features may be implemented with other processes described herein or in other processes and / or contexts.In some embodiments, the lower k-value layer is a dielectric material including silicon, oxygen, nitrogen, and carbon, such as SiOCN. In some embodiments, the layer has a k value of about 4.1. In some embodiments, the layer has a k-value in the range of about 3.0 to about 5.0. The density of the layer may be above 2.0 g / cm 3. In some embodiments, the density of the layer may range from about 2.0 g / cm 3 to about 3.0 g / cm 3. In some embodiments, the carbon concentration in the layer may be decreased to improve oxygen plasma resistance. In some embodiments, the layer has a carbon concentration with a molar fraction in the range of about 0% to about 5%.The layer may be formed using an atomic layer deposition (ALD) process by sequentially pulsing a silicon source precursor, a nitrogen carbon source precursor, and an oxygen source precursor in multiple cycles. After the ALD process, an annealing process may be performed to remove carbon and nitrogen. In some embodiments, the annealing process may be performed at different temperatures.Some aspects of embodiments described herein have been outlined broadly above. Some embodiments described herein are described in the context of fin field effect transistors (FinFET). Implementations of some aspects of the present disclosure may be used in other processes, other devices, and / or for other layers. Other example devices may include, for example, planar FET, HGAA-FET (HGAA), Vertical Gate All Around (VGAA), and other devices. Other modifications that can be made and are contemplated within the scope of other embodiments will readily occur to those skilled in the art. Although method embodiments are described in a particular order, various other method embodiments may be performed in any logical order and have fewer or more steps than those described herein.FIGS. 1A-C through 8A-B are views of respective preliminary structures at various stages in exemplary processes for forming semiconductor devices, in accordance with some embodiments. Aspects of FIGS. 1A-C through 5A-B relate to a gate-first process and a replacement gate process described herein. FIGS. 6A-B illustrate further aspects of a gate-first process described herein. FIGS. 7A-B and 8A-B illustrate further aspects of a replacement gate process described herein.FIGS. 1A, 1B, and 1C illustrate various views of a preliminary structure at a stage in an example process of forming a semiconductor device, in accordance with some embodiments. FIGS. 1A and 1B are various cross-sectional views of the preliminary structure, and FIG. 1C is a perspective view of the preliminary structure.The fins 74 are located on a semiconductor substrate 70, and isolation regions 78 are located on the semiconductor substrate 70 that are disposed between adjacent fins 74. The fins 74 each protrude beyond and between the adjacent isolation regions 78. Gate stacks (or more generally gate structures) each including a dielectric layer 80, a gate layer 82, and a mask 84 are formed along the sidewalls and on top surfaces of the fins 74. Source / drain regions 52 a- fare disposed in respective regions of the fins 74.FIG. 1C further illustrates reference cross-sections used in other figures. The cross-section A-A extends in a plane, e.g., along channels in the fin 74 between opposing source / drain regions 52 a- c. The cross-section B-B extends in a plane perpendicular to the cross-section A-A and through source / drain regions 52 aand 52 din adjacent fins 74. Figures ending with a designation "A" represent cross-sectional views at various processing operations corresponding to cross-section A-A, and figures ending with a designation "B" represent cross-sectional views at various processing operations corresponding to cross-section B-B.The semiconductor substrate 70 may be, or may include, a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, or the like, which may be doped or undoped (e.g., with a p-type or an n-type dopant). In some embodiments, the semiconductor material of the semiconductor substrate may include an elementary semiconductor such as silicon (Si) or germanium (Ge), a compound semiconductor, an alloy semiconductor, or a combination thereof.The fins 74 may be formed from the semiconductor substrate 70, for example, by etching trenches therebetween. The isolation regions 78 may be formed in trenches between the fins 74. The isolation regions 78 may include or be an insulating material such as an oxide (such as silicon oxide), a nitride, or the like, or a combination thereof. The fins 74 protrude between adjacent isolation regions 78, which thereby at least partially confine the fins 74 as active regions on the semiconductor substrate 70. The fins 74 and the isolation regions 78 may be formed via any suitable processes and include any suitable material. In some examples, the fins 74 may include heteroepitaxial (e.g., a lattice mismatched material to the semiconductor material of the semiconductor substrate 70) or other structures.The gate stacks are formed on the fins 74 and are laterally perpendicular thereto. Each gate stack includes a dielectric layer 80, a gate layer 82, and a mask 84. the gate stacks may be operable gate stacks in a gate first process or dummy gate stacks in a replacement gate process.In a gate-first process, the dielectric layer 80 may be a gate dielectric and the gate layer 82 may be a gate electrode. The gate dielectrics may include or be silicon oxide, silicon nitride, a high-k dielectric material, or the like, or multiple layers thereof. A high-k dielectric material may have a k value that is above about 7.0 and include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, multiple layers thereof, or a combination thereof. The gate electrodes may include or be made of silicon (e.g., polysilicon, which may be doped or undoped), a metal-containing material (such as titanium, tungsten, aluminum, ruthenium, or the like), or a combination thereof (such as silicide or multiple layers thereof). The masks 84 may include or be silicon nitride, silicon oxynitride, silicon carbon nitride, or the like, or a combination thereof. The layers for the masks 84, gate electrodes, and gate dielectrics may be deposited and patterned into the gate stacks for each gate stack using any suitable processes for forming the mask 84, the gate layer 82, and the dielectric layer 80.In a replacement gate process, the dielectric layer 80 may be an interfacial dielectric and the gate layer 82 may be a dummy gate. The interfacial dielectrics may include or be silicon oxide, silicon nitride, or the like, or a plurality of layers thereof. The dummy gates may include or be silicon (e.g., polysilicon) or another material. The masks 84 may include or be silicon nitride, silicon oxynitride, silicon carbon nitride, or the like, or a combination thereof. The layers for the masks 84, dummy gates, and interfacial dielectrics may be deposited and patterned into the gate stacks for each gate stack using any suitable processes for forming the mask 84, the gate layer 82, and the dielectric layer 80.FIGS. 2A and 2B illustrate the formation of a first gate spacer layer 86 along sidewalls and top surfaces of the gate stacks and fins 74. The first gate spacer layer 86 is conformally deposited along sidewalls and top surfaces of the fins 74 and gate stacks (e.g., along sidewalls of dielectric layers 80, gate layers 82, and masks 84, and on top surfaces of masks 84) and on top surfaces of the isolation regions 78. The first gate spacer layer 86 may be or may comprise silicon oxycarbonitride (SiOCN) or other material. The first gate spacer layer 86 may have a k-value in the range of about 5.0 to about 7.0. In some examples, the first gate spacer layer 86 may be deposited using an atomic layer deposition (ALD) process, however, other deposition techniques may be used. Further details of an example of the first gate spacer layer 86 will be described below with reference to FIG. 9. In some embodiments, the first gate spacer layer 86 may be omitted.FIGS. 3A and 3B illustrate the formation of a second gate spacer layer 88. The second gate spacer layer 88 is conformally deposited on the first gate spacer layer 86. The second gate spacer layer 88 is a dielectric layer containing silicon, oxygen, nitrogen, and carbon. In some embodiments, the second gate spacer layer 88 may be or include a silicon oxycarbonitride (SiOCN) or other material. In some embodiments, the second gate spacer layer 88 has a carbon concentration with a molar fraction in the range of about 0% to about 5%. In some embodiments, the second gate spacer layer 88 has a nitrogen concentration with a molar fraction in the range of about 0% to about 15%, such as about 5.3%. In some embodiments, the second gate spacer layer 88 has an oxygen concentration with a molar fraction in the range of about 40% to about 70%, such as about 65%. In some embodiments, the second gate spacer layer 88 has a silicon concentration with a molar fraction in the range of about 20% to about 40%, such as about 27%.The second gate spacer layer 88 may be a high density dielectric layer. The second gate spacer layer 88 may have a density greater than or equal to about 2.0 g / cm 3. The second gate spacer layer 88 may have a density in the range of about 2.0 g / cm 3 to about 3.0 g / cm 3 for example, such as about 2.3 g / cm 3. In some embodiments, the second gate spacer layer 88 has a lower k-value than the first gate spacer layer 86. In some embodiments, the second gate spacer layer 88 has a k-value of about 4.1. The second gate spacer layer 88 may have a k-value in the range of about 3.0 to about 5.0, for example.The second gate spacer layer 88 may be formed by sequentially pulsing a silicon source precursor, a nitrogen and carbon source precursor, and an oxygen source precursor in an ALD process, followed by an annealing process to reduce a carbon and / or nitrogen concentration. Further details of examples of the second gate spacer layer 88 and ALD and anneal processes for forming these examples of the second gate spacer layer 88 are described below with reference to FIGS. 10-13.FIGS. 4A and 4B illustrate the formation of gate spacers with respective portions of the first gate spacer layer 86 and the second gate spacer layer 88. Gate spacers (e.g., dual layer gate spacers as shown) are formed along sidewalls of the gate stacks (e.g., sidewalls of dielectric layer 80, gate layer 82, and mask 84) and on fins 74. Remaining gate spacers may also remain along sidewalls of the fins 74, for example, depending on the height of the fins 74 above the isolation regions 78. The gate spacers may be formed by anisotropically etching the second gate spacer layer 88 and the first gate spacer layer 86. The etching process may include an RIE, an NBE, or another etching process. The multi-layer gate spacers may include further and / or other layers and / or materials in other embodiments.FIGS. 5A and 5B illustrate the formation of source / drain regions 92. Recesses are formed in the fins 74 on opposite sides of the gate stacks and the source / drain regions 92 are formed in the recesses. The removal may be performed by an etching process. The etching process may be isotropic or anisotropic, or may be further selective with respect to one or more crystal planes of the semiconductor substrate 70. Thus, the recesses may have different cross-sectional profiles depending on the etching process being implemented. When forming the recess, the second gate spacer layer 88 may be exposed to the etch chemicals. The second gate spacer layer 88 may have a higher resistance to the etch chemicals as described herein while maintaining a lower k value for the target capacitance performance.In some embodiments, a cleaning process may be performed prior to epitaxially growing the source / drain regions 92 in the recesses to remove contaminants on the fins 74. For example, a plasma such as an oxygen plasma may be used to clean the surfaces. Due to the low carbon concentration, the second gate spacer layer 88 may withstand the cleaning plasma without substantial damage.After the cleaning process, epitaxial source / drain regions 92 may be formed in the recesses. The epitaxial source / drain regions 92 may include or be silicon germanium, silicon carbide, silicon phosphor, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The epitaxial source / drain regions 92 may be formed in the recesses by epitaxially growing a material in the recesses, for example, by metal organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or the like, or a combination thereof. The epitaxial source / drain regions 92 may extend (e.g., are raised) beyond sidewalls and top surfaces of the fins 74 and have facets that may correspond to crystal planes of the semiconductor substrate 70. In some examples, different material is used for epitaxial source / drain regions 92 for p-type and n-type devices. Appropriate masking during dicing or epitaxial growth may allow different materials to be used on different devices.Those of ordinary skill in the art will readily appreciate that the removal and epitaxial growth of the source / drain regions 92 may be omitted and source / drain regions may be formed using the gate stacks and gate spacers as masks by implanting dopants into the fins 74. In some examples, in which epitaxial source / drain regions 92 are implemented, these may also be doped, for example by in situ doping during epitaxial growth and / or implanting dopants into the epitaxial source / drain regions 92 after epitaxial growth. Thus, a source / drain region may be defined by doping (e.g. by implanting and / or in situ in epitaxial growth, if appropriate) and / or by epitaxial growth, if appropriate, further defining the active region in which the source / drain region is defined. Due to the high density of the second gate spacer layer 88, this may be able to withstand the doping process with lower damage due to bombardment with particles compared to some other gate spacer materials.FIGS. 6A and 6B illustrate, in continuation of a gate-first process, forming dielectric layers on the fins 74, the epitaxial source / drain regions 92, and gate stacks, and forming conductive features 104 extending through the dielectric layers to the epitaxial source / drain regions 92. After forming the source / drain regions 92, a contact etch stop layer (CESL) is conformally deposited on surfaces of the epitaxial source / drain regions 92, sidewalls and top surfaces of the multi-layer gate spacers, top surfaces of the mask 84, and top surfaces of the isolation regions 78, via any suitable process. An etch stop layer may typically provide a mechanism that stops an etch process when, e.g., contacts or vias are formed. An etch stop layer may be formed of a dielectric material having a different etch selectivity than adjacent layers or devices. The CESL 96 may include silicon nitride, silicon carbon nitride, or the like, or a combination thereof.A first interlayer dielectric (ILD) 100 may be formed on the CESL 96. The first ILD 100 may include or be silicon dioxide, a low-k dielectric material such as silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), organosilicate glass (OSG), SiO x C y, spin-on glass, spin-on polymers, silicon carbon material, a compound thereof, a composite thereof, or the like, or a combination thereof. The first ILD 100 may be deposited via any suitable process. In a gate-first process shown in FIGS. 6A and 6B, a top surface of the first ILD 100 may overlie the top portions of the CESL 96 and the gate stacks. Therefore, the top portions of the CESL 96 may remain on the gate stacks.Conductive features 104 are then formed in openings through the first ILD 100 and the CESL 96 for connection to the epitaxial source / drain regions 92. The conductive features 104 may include, for example, an adhesion and / or barrier layer and conductive material on the adhesion and / or barrier layer. In some examples, as illustrated, the conductive features 104 may include silicide regions 106 on the epitaxy source / drain regions 92. The adhesion and / or barrier layer may be conformally deposited in the openings and on the first ILD 100. The adhesion and / or barrier layer may be made of or comprise titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, tantalum oxide or the like or a combination thereof. Silicide regions 106 may be formed on upper portions of the epitaxy source / drain regions 92 by reacting upper portions of the epitaxy source / drain regions 92 with the adhesion and / or blocking layer. An annealing process may be performed to promote the reaction of the epitaxial source / drain regions 92 with the adhesion and / or barrier layer. The conductive material may be deposited on the adhesion and / or barrier layer and fill the openings. The conductive material may be or comprise tungsten, copper, aluminum, gold, silver, alloys thereof, or the like, or a combination thereof. The conductive features 104 may be, or may be referred to as, contacts, pins, etc.FIGS. 7A-B and 8A-B illustrate further aspects of a replacement gate process described herein. Processing is first performed as described above with reference to FIGS. 1A-C through 5A-B, and then proceeds to FIGS. 7A-B.FIGS. 7A and 7B illustrate replacing gate stacks with replacement gate structures after forming the epitaxial source / drain region in FIGS. 5A-5B. The CESL 96 and the first ILD 100 may be formed as described with respect to FIGS. 6A-B. The first ILD 100 and the CESL 96 are formed with top surfaces coplanar with top surfaces of the gate layers 82. A planarization process such as CMP may be performed to level the top surface of the first ILD 100 and the CESL 96 with the top surfaces of the gate layers 82. The CMP may also remove the mask 84 (as well as, in some cases, upper portions of the multi-layer gate spacers) on the gate layers 82. Accordingly, upper surfaces of the gate layers 82 are exposed via the first ILD 100 and the CESL 96.When the gate layers 82 have been exposed via the first ILD 100 and the CESL 96, the gate layers 82 and the dielectric layers 80 are removed, for example, by one or more etching processes. The gate layers 82 may be removed by an etch process selective to the gate layers 82, wherein the dielectric layers 80 serve as etch stop layers and thereafter may be removed by another etch process selective to the dielectric layers 80. The etching processes may be, for example, an RIE, an NBE, a wet etch, or another etching process. Recesses are formed between multi-layered gate spacers where the gate stacks have been removed, and channel regions of the fins 74 are exposed over the recesses.Upon removal of the gate layers 82 and dielectric layers 80, the top surface of the second gate spacer layer 88 is exposed to the etch chemicals. The second gate spacer layer 88 may have a higher density to withstand the etch chemicals, so that less spacer is lost during etching and capacitance performance in the device improves.Once the gate layers 82 and dielectric layers 80 have been removed, the replacement gate structures are formed in the recesses where the gate stacks have been removed. The replacement gate structures each include one or more conformal layers 120 and a gate electrode 122. The one or more conformal layers 120 include a gate dielectric layer and one or more work function tuning layers may include. The gate dielectric layer may be conformally deposited in the recesses where the gate stacks have been removed. The gate dielectric layer may be or include silicon oxide, silicon nitride, a high-k dielectric material, multiple layers thereof, or another dielectric material. Then, if implemented, a work function tuning layer may be conformally deposited on the gate dielectric layer. The work function tuning layer may include or be tantalum, tantalum nitride, titanium, titanium nitride, or the like, or a combination thereof. Any further work function tuning layers may be deposited sequentially, similar to the first work function tuning layer. The gate electrodes 122 are formed on the one or more conformal layers 120. The layer for the gate electrodes 122 may fill remaining recesses where the gate stacks have been removed. The gate electrodes 122 may be or include a metal-containing material such as Co, Ru, Al, W, Cu, multiple layers, or a combination thereof.FIGS. 8A and 8B illustrate the formation of a second ILD 130 on the replacement gate structures and the first ILD 100, and the formation of conductive features 134 extending through the second ILD 130, the first ILD 100, and the CESL 96 to the epitaxial source / drain regions 92. The second ILD 130 is formed on the first ILD 100, replacement gate structures, gate spacer layers, and the CESL 96. In some examples, an etch stop layer (ESL), not shown, may be deposited on the first ILD 100, etc., and the second ILD 130 may be deposited on the ESL. The ESL, when reacted, may include or be silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, or the like, or a combination thereof. The second ILD 130 may include or be silicon dioxide, a low-k dielectric material such as silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiO x C y, spin-on glass, spin-on polymers, silicon carbon material, a compound thereof, a composite thereof, or the like, or a combination thereof. The conductive features 134 may be formed through the second ILD 130, the first ILD 100, and the CESL 96 to the epitaxial source / drain regions 92 and with silicide regions 136, similar to that described above with respect to the conductive features 104 in FIGS. 6A-B.FIG. 9 is a process flow 200 for forming a gate spacer, in accordance with some embodiments. At operation 202, a first gate spacer layer is optionally formed on a device structure as generally shown in and described with respect to FIGS. 2A and 2B. The first gate spacer layer may be formed via an ALD process. The first gate spacer layer may be a SiOCN layer, a SiN layer, SiON, or the like. The first gate spacer layer may have a higher k value than a subsequent gate spacer layer. This working step 202 can be dispensed with.At operation 204, a second gate spacer layer is formed using an ALD process and an anneal process to achieve a desired film density and a desired k value. The second gate spacer layer, if it is optionally implemented, is formed on the first gate spacer layer or on the component structure. The formation of the second gate spacer layer is generally illustrated in FIGS. 3A and 3B and will be described with reference thereto. The second gate spacer layer may be a low carbon concentration SiOCN layer, such as a carbon concentration having a molar fraction in the range of over 0 to 5%. The second gate spacer layer has a lower k value than the first gate spacer layer. In some embodiments, operation 204 includes forming a dielectric layer using an ALD process and annealing (annealing) the dielectric layer after the ALD process. FIG. 10 describes a process that may be used at operation 204 in accordance with some embodiments of the present disclosure.At operation 206, the second and first gate spacer layers, if implemented, are anisotropically etched to form the gate spacer, such as is generally shown in and described with respect to FIGS. 4A and 4B.FIG. 10 is a process flow 300 for forming a dielectric layer such as the second gate spacer layer 88, in accordance with some embodiments. The process flow 300 may be used to form the second gate spacer layer at operation 204.The process flow 300 in this example includes an ALD process and an anneal process. The layer formed over the process flow 300 may be or may include silicon oxycarbonitride (SiOCN) or other material. The layer in the process flow 300 may be formed in multiple cycles via the ALD process, in which a silicon source precursor, a nitrogen and carbon source precursor, and an oxygen source precursor are successively passed through. The annealing process is performed after the ALD process to achieve a target k value and target material properties. The reactions between the precursors in combination with the annealing process may enable a dielectric film with lower k-value, high plasma and etch chemical resistance, and high density to physical bombardment in subsequent processes. When used in a gate spacer layer, the layer may provide a lower k-value film for capacitance power and a film resistant to damage in subsequent processes, thereby forming a higher power transistor.Operations 302- 310 represent one cycle of the ALD process. The cycle includes alternating pass (or pulsing) and flush operations, with each precursor being passed (or pulsed) at least once in the cycle and then flushed. In some embodiments, the ALD process may be performed in an ALD chamber at a temperature range of about 400° C. to about 800° C., such as at about 600° C. FIGS. 11A-11H schematically illustrate reactions in the course of the ALD process, in accordance with some embodiments.At operation 302, the silicon source precursor is passed through an ALD chamber. The silicon source precursor is directed through an ALD working chamber having a substrate to be processed, such as a substrate having a device structure shown in FIGS. 2A-B thereon. The silicon source precursor reacts with the end sites on the substrate surface to form a monolayer of intermediates. In some embodiments, the silicon source precursor may be hexachlorodisilane (HCD, Si 2 Cl 6) or others.FIG. 11A schematically illustrates bonds at the substrate surface of the device structure shown in FIGS. 2A-2B, which has a surface of a dielectric material, for example, the first gate spacer layer 86. FIG. 11B schematically illustrates surface reactions at operation 302 as HCD is passed through the ALD chamber. The HCD may react with the surface terminals at the temperature prevailing in the ALD chamber, for example, in such a way that silicon and chlorine atoms bond to the surface oxygen atoms and thereby form O-Si-Cl bonds on the substrate surface, while chlorine atoms (e.g. hydrogen chloride if hydroxide group terminals are present on the surface) are formed as a by-product. In some embodiments, an HCD precursor reacts with the substrate surface to form a first preliminary film of a monolayer of molecules on the substrate surface.At operation 303, the ALD chamber is flushed to remove byproducts and unused silicon source precursors from operation 302 from the ALD chamber.At operation 304, a nitrogen and carbon source precursor is introduced into the ALD chamber. In some embodiments, the nitrogen and carbon source precursor may comprise triethylamine (N(C 2 H 5)3, also known as RENA) or others. FIG. 11C schematically illustrates RENA molecules approaching the substrate surface with Si-Cl bonds. RENA may decompose in the ALD chamber and react with the preliminary film on the substrate surface. For example, a bond with N in the decomposed RENA may be released, so that the decomposed RENA may replace Cl in the Si-Cl bonds on the substrate surface, thus forming a second preliminary film. The chlorine atom releasing from the Si-Cl bond may react with hydrogen in the decomposed RENA to form hydrogen chloride as a by-product. In some embodiments, RENA may react with surface layers to form the second preliminary film of a monolayer of molecules on the substrate surface. In some embodiments, as shown in FIG. 11D, the second preliminary film may include RENA in multiple transition states.At operation 306, the ALD chamber is purged to remove byproducts and unused nitrogen and carbon source precursors from operation 304 from the ALD chamber.At operation 308, an oxygen source precursor is directed to the ALD chamber. In some embodiments, the oxygen source precursor may include oxygen gas (O 2). Decomposed RENA on the second preliminary film may further thermally decompose in the O 2- environment, thereby forming N-H bonds and releasing CO 2 and H 2 O. An exemplary reaction may be as follows: N-C 2 H 5+ 3 O 2 → N-H+2CO 2+ 2 H 2 OFIGS. 11E and 11F schematically illustrate the surface reaction at operation 308.At operation 310, the ALD chamber is purged to remove byproducts and unused oxygen source precursors from operation 308 from the ALD chamber.One cycle of the ALD process includes operations 302- 310. After operation 310, it is determined in operation 312 whether additional cycles are to be performed. If this is the case, a further cycle is carried out. Any number of cycles may be performed to deposit a gate spacer layer to the desired thickness. FIG. 11G schematically illustrates a reaction of HCD with the oxygen atom at the surface to start a new cycle.If additional cycles are not required, the ALD process may be completed. The deposited film may be a SiON:C material having Si-O, Si-N, and Si-N-CO 2- bonds. After deposition, the film may contain carbon at a molar fraction in the range of about 0% to about 5%, for example about 2.0%. After deposition, the film may contain nitrogen at a molar fraction in the range of about 0% to about 15%, for example about 6.3%. After deposition, the film may include silicon at a mole fraction in the range of about 20% to about 40%, for example about 27.4%. After deposition, the film may contain oxygen at a molar fraction in the range of about 40% to about 70%, for example about 64.3%.At operation 314, an anneal process is performed on the film formed by the ALD process to achieve a desired characteristic. The annealing process may be performed in an environment that includes N 2, O 2 or H 2.In some embodiments, the annealing process is performed at different temperatures. The annealing process is performed, for example, at different temperatures in an N 2- environment. In one embodiment, the annealing process may include: annealing the substrate for a first time period while simultaneously increasing the annealing temperature; annealing the substrate for a second time period while maintaining a constant annealing temperature; and annealing the substrate for a third time period while simultaneously decreasing the annealing temperature. The raising and lowering of the annealing temperature can be effected at a constant or different rate. For example, it can be rapidly increased at low temperatures and slowly increased at high temperatures. Likewise, it can be slowly reduced at high temperatures and rapidly reduced at low temperatures.FIG. 12 includes a temperature-time profile 402 for an annealing process in an N 2- environment. In one embodiment, the annealing process may be performed in an N 2- environment at a pressure of about 100 kPa. The annealing process can be carried out in an annealing chamber. The annealing chamber can be maintained at a temperature T 1 while the substrate to be processed is being conveyed into or out of the chamber. T1may be in a range from about 200° C. to about 500° C., for example about 400° C.In the example in FIG. 12, the annealing process is performed in five stages. At step I, the temperature is rapidly increased from T1 to T2. T2may be in a range from about 400° C. to about 600° C., for example about 580° C. At step I, the temperature may be increased at a rate of about 1° C. / min to about 20° C. / min, for example about 9° C. / min. Step I may be carried out for a period of time ranging from about 5 minutes to about 80 minutes, for example, for about 20 minutes.At step II, the temperature is slowly increased from T2 to T3. T3may be in a range from about 600° C. to about 1000° C., for example, about 700° C. At stage II, the temperature may be increased at a rate of about 1° C. / min to about 20° C. / min, for example, about 3° C. / min. Step II may be carried out for a period of time ranging from about 5 minutes to about 80 minutes, for example, for about 40 minutes. Steps I and II may increase or increase a temperature in total for a period ranging from about 5 minutes to about 180 minutes, for example about 60 minutes.In step III, the temperature is maintained at a temperature T3. Step III may be carried out for a period of time ranging from about 0 minutes to about 200 minutes, for example, for about 60 minutes.At step IV, the temperature is slowly decreased from T3 to T4. T4may be in a range from about 400° C. to about 600° C., for example, about 580° C. At stage IV, the temperature may be lowered at a rate of about 1° C. / min to about 20° C. / min, for example, at about 4° C. / min. Step IV may be carried out for a period of time ranging from about 5 minutes to about 80 minutes, for example, for about 30 minutes.At step V, the temperature is rapidly lowered from T4 to T5. T 5 may be in a range from about 200° C. to about 500° C., for example, about 400° C. At stage V, the temperature may be lowered at a rate of about 1° C. / min to about 20° C. / min, for example, about 7° C. / min. Step V may be carried out for a period of time ranging from about 5 minutes to about 80 minutes, for example, for about 28 minutes. T 5 may correspond to or may be different from T 1. Stages IV and V may decrease or decrease a temperature in total for a period ranging from about 5 minutes to about 180 minutes, for example about 60 minutes.The annealing process in operation 314 removes some carbon (in the form of carbon dioxide) and some nitrogen in the form of NH. Removal of carbon increases the resistance to plasma such as oxygen plasma. FIG. 11H schematically illustrates the removal of carbon and nitrogen in the annealing process. Removal of nitrogen reduces the k value. In some embodiments, the film may have a k value of less than 4.1. After annealing, the film may contain carbon at a molar fraction in the range of about 0% to about 5%, for example about 1.0% or less. After annealing, the film may contain nitrogen at a molar fraction in the range of about 0% to about 15%, for example about 5.3%. After annealing, the film may contain oxygen at a molar fraction in the range of about 40% to about 70%, for example about 65.3%. After annealing, the film may contain silicon at a molar fraction in the range of about 20% to about 40%, for example about 28.4%.The second gate spacer layer 88 may be a high density dielectric layer. The second gate spacer layer 88 may have a density of more than 2.0 g / cm 3. The second gate spacer layer 88 may have a density in the range of 2.0 g / cm 3 to 3.0 g / cm 3 for example, such as 2.3 g / cm 3. In some embodiments, the second gate spacer layer 88 has a lower k-value than the first gate spacer layer 86. In some embodiments, the second gate spacer layer 88 has a k-value of about 4.1. The second gate spacer layer 88 may have a k-value in the range of about 3.0 to about 5.0, for example.In another embodiment, operation 314 may be performed at a constant annealing temperature, for example, by an annealing process in a constant temperature hydrogen environment. In one example, the annealing process may be performed in a hydrogen environment at an annealing temperature in the range of about 200° C. to about 600° C., for example, about 450° C. The annealing process may be performed for a period of time in the range of about 0 seconds to about 2000 seconds, for example, about 600 seconds. During annealing, the annealing chamber may be at a lower pressure in the range of about 0 to about 1.33 kPa (0 torr to about 10 torr), for example, about 266 Pa (2 torr). In some embodiments, the hydrogen environment may comprise a hydrogen plasma.FIG. 13 illustrates a cross-sectional view of a portion of the preliminary structure of FIG. 8A, illustrating further details of a first gate spacer layer 86 and a second gate spacer layer 88, which are formed according to the process flow 300 in FIG. 10, in accordance with some embodiments. The first gate spacer layer 86 and the second gate spacer layer 88 have a carbon concentration profile 902, a nitrogen concentration profile 904, an oxygen concentration profile 906, a silicon concentration profile 908, and a k-value profile 910. In some examples, the carbon concentration 902 in the second gate spacer layer 88 is at a molar fraction in the range of 0% to 5%, such as below 3%, and more particularly below 1%. The second gate spacer layer 88 may undergo further carbon loss (e.g., at a molar fraction of about 1% to about 2%) during processing, e.g., after annealing in operation 314. Therefore, the carbon concentration 902 in the second gate spacer layer 88 may correspond to a molar fraction of at most about 5%, about 4%, about 3%, about 2%, about 1%, or about 0%. The second gate spacer layer 88 has a lower k value and a lower carbon concentration compared to the first gate spacer layer 86.Semiconductor device structures with dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed via an ALD process followed by an anneal process at different temperatures. The dielectric features may have a high density, a low carbon concentration, and a lower k value. The dielectric features formed according to the present disclosure may have higher resistance to etch chemicals, damage from plasma, and physical bombardment in subsequent processes while maintaining a low k value for the target capacitance performance.Some embodiments of the present disclosure provide a method including forming a layer using an atomic layer deposition (ALD) process and annealing the layer in a nitrogen environment. The annealing includes annealing the layer during a first period while simultaneously increasing an annealing temperature from a first temperature to a second temperature, annealing the layer at the second temperature during a second period, and annealing the layer during a third period while simultaneously decreasing the annealing temperature from the second temperature.Some embodiments of the disclosure provide a method comprising forming a layer using an atomic layer deposition (ALD) process, wherein the ALD process comprises, for a cycle of the ALD, passing a silicon source precursor, passing a carbon and nitride source precursor, and passing an oxygen source precursor. The method further includes annealing the layer to reduce an amount of carbon and nitrogen in the layer.Some embodiments of the present disclosure provide a structure having an active region on a substrate, the active region comprising a source / drain region, a gate structure on the active region, and a gate spacer along a sidewall of the gate structure, the gate spacer being laterally disposed between the gate structure and the source / drain region, the gate spacer comprising a first spacer layer and a second spacer layer formed on the first spacer layer, the second spacer layer having a carbon concentration with a molar fraction in the range of 0% to 5%, and the second spacer layer having a lower k value than the first spacer layer.

Claims

A method comprising: forming a spacer layer (88) on a sidewall of a gate stack using an atomic layer deposition process; and annealing (314) the spacer layer (88) in a nitrogen environment comprising: annealing (314) the spacer layer (88) during a first time period while simultaneously increasing an annealing temperature from a first (T1) to a second temperature (T2), annealing (314) the spacer layer (88) during a second time period while simultaneously increasing the annealing temperature at a second rate from the second (T2) to a third temperature (T3); annealing the spacer layer at the third temperature (T3) during a third time period; annealing the spacer layer (88) at a third rate for a fourth period while reducing the annealing temperature from the third temperature (T3) to a fourth temperature (T4); wherein the first temperature (T1) is between 400°C and 600°C and the second temperature (T2) is between 600°C and 1000°C, and the duration of the first and second periods together is at least 60 minutes and the duration of the third period is at least 60 minutes.The method of claim 1, wherein forming the spacer layer comprises: passing (302) a silicon source precursor, passing (304) a carbon and nitrogen source precursor, and passing (308) an oxygen source precursor.The method of claim 2, wherein the silicon source precursor comprises Si 2 Cl 6.The method of claim 2 or 3, wherein the carbon and nitrogen source precursor comprises N(C 2 H 5)3.The method of claim 2, 3 or 4, wherein the oxygen source precursor comprises O 2.The method of any preceding claim, further comprising: annealing the spacer layer (88) at a fourth rate for a fifth period of time while reducing the annealing temperature from the fourth temperature (T4) to the first temperature (T1); wherein the first rate is greater than the second rate and the fourth rate is greater than the third rate.The method of claim 6, wherein the second temperature (T2) is at least 580°C.The method of any preceding claim, wherein the first rate is about 9°C / min and the second rate is about 3°C / min.A method comprising: forming a first spacer layer (86) over a substrate using an atomic layer deposition process comprising: for one cycle of the atomic layer deposition process: passing (302) a silicon source precursor over the substrate, passing (304) a carbon and nitride source precursor over the substrate, and passing (308) an oxygen source precursor over the substrate, and annealing (314) the first spacer layer (86) to reduce an amount of carbon and nitrogen in the first spacer layer (86), wherein annealing (314) the first spacer layer (86) comprises: increasing an annealing temperature from a first (T1) to a second temperature (T2) at a first rate and increasing the annealing temperature from the second (T2) to a third temperature (T3) at a second rate, wherein the second rate is lower than the first; annealing the first spacer layer (86) during a third time period at the third temperature; decreasing the annealing temperature from the third temperature to a fourth temperature at a third rate; and wherein the first temperature (T1) is at least 400°C, the second temperature (T2) is at least 580°C, and the third temperature is at least 700°C; and wherein the first rate and the second rate are in the range of 1° C. / min and 20° C. / min.The method of claim 9, wherein annealing (314) the first spacer layer (86) comprises annealing the first spacer layer (86) in a nitrogen environment at about 100 kPa.The method of claim 9 or 10, further comprising: lowering the annealing temperature from a fourth temperature to a fifth temperature at a fourth rate, wherein the third rate is less than the fourth rate.The method of any of claims 9 to 11, wherein annealing (314) the first spacer layer (86) further comprises annealing the first spacer layer (86) at the third temperature in a hydrogen plasma.The method of any one of claims 9 to 12, wherein the silicon source precursor comprises Si 2 Cl 6, the carbon and nitrogen source precursor comprises N(C 2 H 5)3 and the oxygen source precursor comprises O 2.The method of any preceding claim, further comprising: forming a second spacer layer (88) on the first spacer layer (86), wherein the second spacer layer (88) has a carbon concentration with a molar fraction in the range of 0 percent % to 5% and the second spacer layer (88) has a lower k value than the first spacer layer (86).The method of claim 14, wherein the first spacer layer (86) and the second spacer layer (88) are formed along the entire sidewall of the gate structure (80, 82, 120, 122).The method of claim 14 or 15, wherein the second spacer layer (88) is formed with a density in the range of 2.0 g / cm 3 to 3.0 g / cm 3.The method of any of claims 14 to 16, wherein the first spacer layer (86) is formed with a k value in the range of 5.0 to 7.0.The method of any of claims 14 to 17, wherein the second spacer layer (88) is formed with a nitrogen concentration having a molar fraction in the range of 0% to 15%.The method of any one of claims 14 to 18, wherein the second spacer layer (88) is formed as a silicon oxycarbonitride film SiOCN having a k value of 4.1.

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