Method for producing a field-effect transistor using carbon nanotubes and a single-field-effect transistor

Abstract

A method of forming a gate-all-around field-effect transistor, GAA-FET, the method comprising: Forming a lower support layer (15) over a substrate (10), Arranging a first group of carbon nanotubes, CNTs, (100) over the lower support layer (15), Forming a first support layer (21) over the first group of CNTs (100) and the lower support layer (15) such that the first group of CNTs (100) is embedded in the first support layer (21), Arranging a second group of carbon nanotubes, CNTs, (100) over the first support layer (21), Forming a second support layer (22) over the second group of CNTs (100) and the first support layer (21), so that the second group of CNTs (100) is embedded in the second support layer (22), and Forming a fin structure (30) by structuring at least the first support layer (21) and the second support layer (22); wherein adjacent CNTs (100) in one of the groups of CNTs are in contact with each other, and wherein none of the CNTs (100) is in contact in the vertical direction with another CNT (100).

Description

PRIOR ARTAs the semiconductor industry reached the nanometer technology nodes to achieve higher device density, higher performance, and lower cost, challenges regarding both manufacturing and design issues have led to the development of three-dimensional designs, such as GAA structures. Low-dimensional materials that are not based on Si are promising candidates for providing superior electrostatics (e.g., for short channel effects) and higher performance (e.g., lower surface scattering). Carbon nanotubes (CNTs) are considered as such a promising candidate because of their high carrier mobility and a substantially one-dimensional structure.US 2012 / 0 032 149 A1 discloses a method for forming a single gate stack structure which contains CNTs.US 2016 / 0 293 668 A1 describes a method for forming CNT-FETs, in which CNTs are attached to side walls of a fin structure by electrostatic charging.SUMMARY OF THE INVENTIONThe present invention relates to a method of forming a gate-all-around field effect transistor (GAA-FET) according to claim 1, a method of forming a gate-all-around field effect transistor (GAA-FET) according to claim 10, and a semiconductor device according to claim 20 comprising a gate-all-around field effect transistor (GAA-FET). Preferred embodiments of the invention are set forth in the dependent claims.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, according to the standard industry method, various features are not drawn to scale. Rather, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. FIGS. 1A, 1B, 1C, 1D, 1E, and 1F illustrate various stages of a sequential manufacturing process of a GAA-FET according to an embodiment of the present disclosure. FIGS. 2A, 2B, 2C, 2D, and 2E illustrate various stages of a sequential manufacturing process of a GAA-FET, according to an embodiment of the present disclosure. FIGS. 3A, 3B, and 3C illustrate various stages of a sequential manufacturing process of a GAA-FET according to an embodiment of the present disclosure. FIGS. 4A, 4B, 4C, and 4D illustrate various stages of a sequential manufacturing process of a GAA-FET according to an embodiment of the present disclosure. FIGS. 5A and 5B illustrate various stages of a sequential manufacturing process of a GAA-FET according to an embodiment of the present disclosure. FIGS. 6A and 6B illustrate various stages of a sequential manufacturing process of a GAA-FET according to an embodiment of the present disclosure. FIGS. 7A and 7B illustrate various stages of a sequential manufacturing process of a GAA-FET according to an embodiment of the present disclosure. FIGS. 8A and 8B illustrate various stages of a sequential manufacturing process of a GAA-FET according to an embodiment of the present disclosure. FIGS. 9A, 9B, and 9C illustrate various stages of a sequential manufacturing process of a GAA-FET according to an embodiment of the present disclosure. FIGS. 10A, 10B, and 10C illustrate various stages of a sequential manufacturing process of a GAA-FET according to an embodiment of the present disclosure. FIGS. 11A and 11B illustrate various stages of a sequential manufacturing process of a GAA-FET according to an embodiment of the present disclosure. FIGS. 12A, 12B, and 12C illustrate various stages of a sequential manufacturing process of a GAA-FET according to an embodiment of the present disclosure. FIGS. 13A and 13B illustrate various stages of a sequential manufacturing process of a GAA-FET according to an embodiment of the present disclosure. FIGS. 14A, 14B, and 14C illustrate various stages of a sequential manufacturing process of a GAA-FET according to an embodiment of the present disclosure. FIG. 14D illustrates various stages of a sequential manufacturing process of a GAA-FET, according to an embodiment of the present disclosure.DETAILED DESCRIPTIONIt should be understood that the following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are of course merely examples and are not intended to be limiting. For example, dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired characteristics of the device. Furthermore, forming a first feature over or on a second feature in the description below may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Various features may be arbitrarily drawn at different scales for simplicity and clarity. In the accompanying drawings, some layers / features may be omitted for simplicity.Moreover, terms relating to spatial relativeity, such as "below," "below," "lower," "above," "upper," and the like, may be used herein for ease of discussion to describe the relationship of one element or feature to another element or feature (to other elements or features) as depicted in the figures. The terms relating to spatial relativeness are intended to encompass different orientations of the device being used or operated in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or otherwise oriented) and the spatially relative terms used herein may likewise be construed accordingly. Moreover, the term "made of" may mean either "comprising" or "consisting of.". In addition, in the subsequent manufacturing process, one of the plurality of additional operations may be present in / between the described operations, and the order of operations may be changed. In the present disclosure, an expression "one of A, B, and C" means "A, B, and / or C" (A, B, C, A, and B, A and C, B, and C, or A, B, and C), and does not mean an element of A, an element of B, and an element of C, unless otherwise specified.Carbon nanotubes (CNTs) having diameters on the order of nm (e.g., about 1 nm) are considered a material of choice for the fabrication of the ultimately scaled FET device due to their cylindrical geometry, excellent electrical and mechanical properties. A field effect transistor (FET) using a CNT having a gate length of about 10 nm or less exhibits excellent electrical characteristics. However, a manufacturing technology compatible with a CMOS manufacturing technology has not been established. In the present disclosure, a horizontal gate-all-around process flow compatible with CMOS technology is provided by stacking layers of aligned CNTs on a substrate and forming a fin structure from the stacked CNTs.In some embodiments, semiconductor devices include a novel structure of field effect transistors including stacked gate-all-around carbon nanotubes (GAA-CNTs). The semiconductor devices include an array of aligned CNTs with a gate dielectric layer enclosing them and a gate electrode layer. The GAA FETs with CNTs can be applied to logic circuits in an advanced technology node. However, fabricating CNT-based devices has led to problems such as difficulty in increasing a CNT density to achieve a higher current, prevention of inter-tube interactions that degrade CNT performance in a CNT bundle structure, and / or lack of a feasible fabrication process to integrate high density GAA-CNTs into a circuit. The following embodiments provide a GAA-FET using CNTs and its manufacturing process that can solve these problems.FIGS. 1A to 13B illustrate various stages of a sequential manufacturing process of a GAA-FET using carbon nanotubes, according to embodiments of the present disclosure. It should be appreciated that for additional embodiments of the method, additional operations may be provided before, during, and after the processes illustrated in FIGS. 1A-13B, and some of the operations described below may be replaced or eliminated. The order of the operations / processes may be interchangeable.As shown in FIG. 1A, a lower support layer 15 is formed over a substrate 10. In some embodiments, the substrate 10 is made of a suitable elemental semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as Group IV compound semiconductors (e.g., silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn), Group III-V compound semiconductors (e.g., gallium arsenide, indium gallium arsenide (InGaAs), indium arsenide, indium phosphide, indium antimonide, gallium arsenic phosphide, or gallium indium phosphide), or the like. An insulating material such as glass may be used as the substrate. The lower support layer 15 is made of an insulation material in some embodiments. In some embodiments, the bottom support layer includes one or more layers of silicon oxide, silicon nitride, SiON, SiOc, SiOCN, and SiCN, or other suitable insulating material. In other embodiments, the lower support layer comprises a polycrystalline or amorphous material of one of Si, Ge, and SeGe. The lower support layer 15 may be formed using suitable film formation methods such as thermal oxidation, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In certain embodiments, silicon oxide (e.g., SiO 2) is used as the lower support layer 15.Then, as illustrated in FIG. 1B, one or more carbon nanotubes (CNTs) 100 are disposed over the lower support layer 15. In some embodiments, the lower support layer is not used and the CNTs 100 are directly disposed on the substrate 10. The CNTs are disposed on the lower support layer 15 so as to be aligned substantially in the same direction (e.g., Y direction). The deviation from the Y direction of the orientation of the CNTs 100 is about ± 10 degrees in some embodiments, and is about ± 5 degrees in other embodiments. In certain embodiments, the deviation is about ±2 degrees. The CNTs 100 are arranged in a density in a range from about 50 tubes / μm to about 300 tubes / μm in some embodiments, and in other embodiments, the density is in a range from about 100 tubes / μm to about 200 tubes / μm. The length of the CNTs 100 (in the Y direction) is in a range from about 0.5 μm to about 5 μm in some embodiments, and is in a range from about 1 μm to about 2 μm in other embodiments. The average diameter of the CNTs 100 is in a range from about 1.0 nm to about 2.0 nm in some embodiments.Carbon nanotubes may be formed using various methods, such as arc discharge or laser ablation methods. The formed CNTs are dispersed in a solvent such as sodium dodecyl sulfate (SDS). The CNTs may be transferred to or disposed on a substrate using various methods, such as a floating self-aligned vapor deposition method, in some embodiments.After the CNTs 100 are transferred to the lower support layer 15, a first support layer 21 is formed over the CNTs (a first group of CNTs) disposed on the lower support layer 15 as illustrated in FIG. 1C. In some embodiments, the first support layer 21 comprises a polycrystalline or amorphous material of one of Si, Ge, and SeGe. In other embodiments, the first support layer 21 comprises one or more layers of silicon oxide, silicon nitride, SiON, SiOC, SiOCN, and SiCN, or other suitable insulating material. In some embodiments, the first support layer 21 comprises an organic material, such as organic polymers. In certain embodiments, the first support layer 21 is made of a different material than the lower support layer 15. In other embodiments, the first support layer 21 is made of the same material as the lower support layer 15. In one embodiment, ALD is used because of its high thickness uniformity and thickness controllability.In some embodiments, as shown in FIG. 1C, when the first support layer is conformally formed over the first group of CNTs 100, the top surface of the first support layer has a wavy shape that has peaks and valleys. The thickness of the first support layer 21 is in a range from about 2 nm to about 10 nm in some embodiments, and is in a range from about 3 nm to about 5 nm in other embodiments.Then, a second support layer 22 is formed over the first support layer 21. In some embodiments, the second support layer 22 is made of the same material as the first support layer in some embodiments. The thickness of the second support layer 22 is substantially equal to the thickness of the first support layer 21. The difference in thickness is within ± 5% of the average thickness in some embodiments.In addition, a second group of CNTs 100 is disposed on the second support layer 22. When the upper surface of the first support layer has the wavy shape, as illustrated in FIG. 1C, the second group of CNTs 100 tends to be disposed in the valleys of the wavy shape.In some embodiments, forming a group of CNTs and forming a support layer are repeated to form n support layers, each of which has embedded therein CNTs, where n is an integer equal to or greater than three. In some embodiments, n is up to 20, FIG. 1D shows an embodiment in which six support layers 21, 22, 23, 24, 25 and 26 are formed, and therefore six layers of CNTs disposed in one support layer 20 are formed. In the following explanation, the first to sixth support layers 21 to 26 are referred to as a support layer 20.In other embodiments, as illustrated in FIG. 1E, after the first support layer 21 is formed with the wavy top surface, one or more planarization operations are performed to level the top surface of the support layer 21. The planarization process includes an etch back process or a chemical mechanical polishing (CMP) process. In one embodiment, CMP is used.Then, as stated above, the second group of CNTs 100 and the second support layer 22 are formed on the planarized first support layer 21. The process is repeated to obtain the structure shown in FIG. 1F.In FIGS. 1D and 1F, the CNTs are arranged in a layer at a constant pitch, and the CNTs are aligned in the vertical direction. However, the arrangement of the CNTs in the support layer 20 is not limited to those of FIGS. 1D and 1F. In some embodiments, the CNTs in a layer have any pitch in the X direction. When the average diameter of the CNTs 100 is D CNT in some embodiments, the horizontal pitch P H of the CNTs is D CNT ≤ P H ≤ 10 × D CNT. In some embodiments, two adjacent CNTs are in contact with each other. In addition, in some embodiments, at least two CNTs 100 in different layers are not aligned with each other in the vertical direction. The vertical pitch P V of the CNTs 100 is determined by the thickness of the support layers. In some embodiments, a vertical pitch P V of the CNTs 100 in adjacent layers is 0.9×P A≤P V≤1.1×P A, where P A is an average pitch of the plurality of layers. In other embodiments, the vertical pitch is P V0,95 × P A ≤ P V ≤ 1.05 × P A.After the CNTs 100 are transferred via the substrate 10, a trimming process as illustrated in FIGS. 2A to 2E is performed in some embodiments. After the CNTs 100 are transferred onto the lower support layer 15 as illustrated in FIGS. 2A and 2B, a resist pattern 12 as a resist layer is formed over a central part of the CNTs 100 using a lithographic process. End portions of the CNTs 100 are exposed as illustrated in FIG. 2C. The width W 21 of the photoresist pattern 12 is in a range from about 50 nm to about 2000 nm in some embodiments, and is in a range from about 100 nm to about 1000 nm in other embodiments. Then, the exposed end portions of the CNTs 100 are removed by etching as shown in FIG. 2D. In addition, as illustrated in FIG. 2E, the resist pattern 12 is removed by dry etching and / or wet removal using an organic solvent.Referring to FIGS. 3A and 3B, a mask pattern 18 is formed over the support layer 20 using one or more lithography and etching operations, and the support layer 20 including the CNTs 100 is patterned into one or more fin patterns 30. The mask pattern 18 is a photoresist layer in some embodiments and may be a hard mask made of a dielectric material in other embodiments. In some embodiments, the fin structures 30 may be patterned using any suitable method. For example, the fin structures may be patterned using one or more photolithography processes including dual-patterning or multi-patterning processes. In general, double-patterning or multi-patterning processes combine photolithographic and self-aligning processes, thereby allowing patterns to be created that have, for example, smaller pitches than otherwise achievable using a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed and the remaining spacers, or mandrels, may then be used to pattern the fin structures.In some embodiments, the width of the fin structures 30 in the X direction is in a range from about 5 nm to about 20 nm, and in other embodiments is in a range from about 7 nm to about 12 nm. In FIG. 3B, the lower support layer 15 is made of a different material than the support layers 20, and therefore the lower support layer 15 is not patterned. In FIG. 3C, the lower support layer 15 is made of the same material or a similar material as the support layers 20, and therefore the lower support layer 15 is also patterned into a fin structure.The total number of CNTs 100 per fin structure is in a range from about 5 to about 100 in some embodiments, and is in a range from about 10 to about 50 in other embodiments.FIGS. 4A through 4D illustrate various configurations of CNTs in a fin structure 30. as shown in FIG. 4A, in some embodiments, the CNTs 100 are partially exposed at the side surface of the support layer 20. In such a case, a removal process is performed to remove the partially exposed CNTs, as illustrated in FIG. 4B. The removing process may be a plasma treatment using an oxygen-containing gas.In some embodiments, as shown in FIGS. 4C and 4D, the number of CNTs 100 in one layer is different from another layer. Additionally, in some embodiments, the pitch of the CNTs in one layer is different from the pitch of the CNTs 100 in another layer. The pitch of the CNTs 100 may vary within a layer in some embodiments. As shown in FIG. 4D, adjacent CNTs 100 in one layer are in contact with each other, and in certain embodiments, no CNTs in another layer are in contact with each other. In some embodiments, no CNT is in contact with another CNT in the vertical direction.Next, a sacrificial gate structure 40 is formed over the fin structure 30, as shown in FIGS. 5A and 5B. FIG. 5A is a cross-sectional view along the X direction, and FIG. 5B is cross-sectional views along the Y direction. The sacrificial gate structure 40 is formed by blanket depositing a sacrificial gate electrode layer over the fin structure 30 such that the fin structures 30 are fully embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer includes silicon, germanium, or silicon germanium, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in a range from about 100 nm to about 200 nm in some embodiments. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization process. The sacrificial gate electrode layer is deposited using a CVD including LPCVD and PECVD, PVD, ALD, or other suitable process. In some embodiments, a sacrificial gate dielectric layer is not formed between the fin structure 30 and the sacrificial gate electrode layer, and in other embodiments, a sacrificial gate dielectric layer is formed between the fin structure 30 and the sacrificial gate electrode layer.Next, a mask layer 42 is formed over the sacrificial gate electrode layer 40. The mask layer 42 includes one or more of a silicon nitride (SiN) layer and a silicon oxide layer. Next, a patterning process is performed on the mask layer, and the sacrificial gate electrode layer is patterned into the sacrificial gate structure 40, as illustrated in FIGS. 5A and 5B. By patterning the sacrificial gate structure, the fin structures 30 on opposite sides of the sacrificial gate structure 40 are partially exposed, thereby defining source / drain (S / D) regions, as shown in FIG. 5B. In this disclosure, a source and a drain are used interchangeably, and the structures thereof are substantially the same. In FIGS. 5A and 5B, two sacrificial gate structures 40 are formed over two fin structures 30, but the number of sacrificial gate structures is not limited to this configuration. In some embodiments, one or more than two sacrificial gate structures may be arranged in the Y direction. In certain embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structures to improve structure accuracy.After the sacrificial gate structure 40 is formed, a blanket layer of an insulating material for gate sidewall spacers 44 is conformally formed using CVD or other suitable methods, as shown in FIGS. 6A and 6B. The blanket layer is deposited in a conformal manner to be formed to have substantially equal thicknesses on vertical surfaces such as the sidewalls, horizontal surfaces, and the top of the sacrificial gate structures 40. In some embodiments, the blanket layer is deposited to a thickness in a range from about 2 nm to about 10 nm. In some embodiments, the insulating material of the blanket layer is a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN, and combinations thereof. In certain embodiments, the isolation material is one of SiOC, SiCON, and SiCN. As can be seen from FIGS. 5B and 6B, in some embodiments, the CNTs 100 are supported by the support layer 20, but are not supported (anchored) by the sidewall spacers 44. Before forming the blanket layer for the sidewall spacers 44, in some embodiments, the support layer 20 is slightly etched to expose the ends of the CNTs 100. In such a case, the ends of the CNTs 100 are supported (anchored) by the sidewall spacers 44.Additionally, as shown in FIGS. 6A and 6B, the sidewall spacers 44 are formed on opposing sidewalls of the sacrificial gate structures 40 using anisotropic etching. After the surface covering layer is formed, anisotropic etching is performed on the surface covering layer using, for example, reactive ion etching (RIE). During the anisotropic etching process, most of the isolation material is removed from horizontal surfaces, leaving the dielectric spacer layer on the vertical surfaces, such as the sidewalls of the sacrificial gate structures and the sidewalls of the exposed fin structures. The mask layer 42 may be exposed from the sidewall spacers. In some embodiments, an isotropic etch process may then be performed to remove the isolation material from the top portions of the S / D region of the exposed fin structures 30.A liner layer 46, such as an etch stop layer, is then formed to cover the gate structures 40 with the sidewall spacers 44 and the exposed fin structures 30. In some embodiments, the liner layer 46 includes a silicon nitride-based material, such as silicon nitride, SiON, SiOCN, or SiCN, and combinations thereof, formed using a CVD including LPCVD and PECVD, PVD, ALD, or other suitable process. In certain embodiments, the liner layer 46 is made of silicon nitride. In addition, as illustrated in FIGS. 6A and 6B, a first interlayer dielectric (ILD) 50 is formed. The materials for the first ILD layer 50 include compounds including Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials, such as polymers, may be used for the first ILD layer 50.After the first ILD layer 50 is formed, a planarization process such as CMP is performed to expose the sacrificial gate electrode layer 40, as shown in FIGS. 7A and 7B. Then, as illustrated in FIGS. 8A and 8B, the sacrificial gate electrode layer 40 is removed, thereby exposing a channel region of the fin structures in a gate space 55. The sacrificial gate structure 40 may be removed using a plasma dry etch and / or wet etch. When the sacrificial gate electrode layer 40 is polysilicon and the first ILD layer 50 is silicon oxide, a wet etchant such as a TMAH solution may be used to selectively remove the sacrificial gate electrode layer 40.In addition, as illustrated in FIGS. 9A to 9C, the support layer 20 in the gate space 55 is removed to free the CNTs 100. FIG. 9C is an isometric view. The support layer 20 may be selectively removed from the CNTs 100 using a plasma dry etch and / or wet etch. When the support layer 20 is polysilicon or amorphous silicon and the first ILD layer 50 is silicon oxide, a wet etchant such as a TMAH solution is used. When the sacrificial gate electrode layer 40 and the support layer 20 are made of the same material, the removal of the sacrificial gate electrode layer 40 and the removal of the support layer 20 are performed by the same etching process.After the channel regions of the CBTS 100 are freed, a gate dielectric layer 102 is formed around the CNTs 100, as shown in FIGS. 10A to 10C. FIG. 10C is an enlarged view of the gate structure. In some embodiments, the gate dielectric layer 102 includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, another suitable dielectric material, and / or combinations thereof. Examples of a high-k dielectric material include HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfNbO, zirconium oxide, aluminum oxide, titanium oxide, a hafnium dioxide-aluminum oxide alloy (HfO 2- Al 2 O 3), other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 102 is made of HfO 2 for an n-channel FET and is made of Al 2 O 3 for a p-channel FET. The gate dielectric layer 102 has a thickness in a range from about 0.5 nm to about 2.5 nm in some embodiments, and has a thickness in a range from about 1.0 nm to about 2.0 nm in other embodiments. The gate dielectric layer 102 may be formed using a CVD, an ALD, or any suitable method. In an embodiment, the gate dielectric layer 102 is formed using a high conformal deposition process, such as an ALD, to ensure that a gate dielectric layer having a uniform thickness around each channel region of the CNTs 100 is formed.In some embodiments, an interfacial layer (not shown) is formed around the CNTs before the gate dielectric layer 102 is formed. The interfacial layer is made of, for example, SiO 2 in some embodiments, and has a thickness in a range from about 0.5 nm to about 1.5 nm. In other embodiments, the thickness of the interfacial layer is in a range from about 0.6 nm to about 1.0 nm.In certain embodiments, one or more layers for adjusting the work function 104 are formed on the gate dielectric layer 102. The work function adjustment layers 104 are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multilayer of two or more of these materials. In certain embodiments, TiN is used as the work function adjustment layer 104. The work function adjustment layer 104 may be formed using ALD, PVD, CVD, electron beam evaporation, or other suitable process. In addition, the work function adjustment layer 104 may be formed separately for the n-channel FET and the p-channel FET that may use different metal layers.Then, as illustrated in FIGS. 10A and 10B, a gate electrode layer 106 is formed over the work function adjustment layer 104. The gate electrode layer 106 includes one or more layers of a conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 104 has a thickness in a range from about 0.5 nm to about 5.0 nm in some embodiments, and has a thickness in a range from about 0.8 nm to about 1.5 nm in other embodiments. The gate electrode layer 106 may be formed using a CVD, ALD, electroplating, or other suitable method. The gate electrode layer 106 is also deposited over the top surface of the first ILD layer 50, and the gate dielectric layer 102, the work function adjustment layer 104, and the gate electrode layer 106 formed over the first ILD layer 50 are then planarized using, for example, CMP until the first ILD layer 50 is exposed.In FIGS. 10A and 10B, the gate dielectric layer completely surrounds each of the CNTs 100, and the work function adjustment layer 104 also completely surrounds each of the CNTs 100. In some embodiments, spaces are formed between the work function adjustment layer 104 of adjacent CNTs 100, and the spaces are filled with the gate electrode layer 106.In other embodiments, as shown in FIGS. 11A and 11B, the work function adjustment layer 104 fills spaces between the gate dielectric layer 102 of adjacent CNTS 100, and the gate electrode layer 106 covers an outer surface of the work function adjustment layer 104.Then, as in Figs. 12A-12C, a second ILD layer 60 is formed over the first ILD layer 50, and source / drain contact openings 65 are formed using one or more lithographic and etching operations. FIG. 12C is an isometric view. By this operation, source / drain regions of the CNTS 100 are exposed in the source / drain contact holes 65. In some embodiments, as shown in FIG. 12B, a portion of the support layer 20 remains under the sidewall spacers 44. When the support layer 20 is made of a dielectric material, the remaining support layer 20 functions as inner spacers separating the gate electrode layer 106 and a subsequently formed source / drain contact 70 / 72.Next, as shown in FIGS. 13A and 13B, the source / drain contact openings 65 are filled with one or more layers of a conductive material. The conductive material includes one or more of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, and Zr, or any other suitable conductive materials. In some embodiments, a lower contact layer 70 surrounds the source / drain regions of the CNTs 100, and an upper contact layer 72 is formed on the lower contact layer 70. In some embodiments, the lower contact layer 70 is one or more of TiN, Ti, and TaN. The top contact layer is one or more of W, Cu, and Co. Additionally, in some embodiments, one or more gate contacts are formed at the same time as the source / drain contacts or using processes other than the source / drain contacts.The total number of CNTs 100 in one GAA-FET is in a range from about 5 to about 100 in some embodiments, and is in a range from about 10 to about 50 in other embodiments. In some embodiments, in a GAA FET, two CNTs of the CNTs contact each other in the horizontal direction, and no CNT contacts another CNT in the vertical direction.In some embodiments, the source / drain contacts are first formed and then the gate structure is formed.FIGS. 14A to 14D illustrate various stages of manufacturing processes of a GAA FET using carbon nanotubes, according to other embodiments of the present disclosure. It should be appreciated that for additional embodiments of the method, additional operations may be provided before, during, and after the processes illustrated in FIGS. 14A-14D, and some of the operations described below may be replaced or eliminated. The order of the operations / processes may be interchangeable. Materials, configurations, dimensions, processes, and / or operations the same as or similar to those described with reference to FIGS. 1A to 13B may be used in the embodiments below, and the detailed explanation may be omitted.When the source / drain contact openings 55 have been formed, the support layer 20 is further etched so that the support layer 20 is completely removed, as shown in FIG. 14A. Then, one or more layers of dielectric materials are formed in the source / drain contact opening 55, and inner spacers 90 are formed by anisotropic etching as in FIG. 14B. Then, similar to FIGS. 13A and 14B, the source / drain contacts 70 / 72 are formed as shown in FIG. 14C. The dielectric material for the inner spacers 90 includes one or more of SiN, SiON, SiOCN, SiOC, and SiCN, and combinations thereof.In other embodiments, once the source / drain contact openings 55 have been formed, the support layer 20 is further etched, but a thin layer of the support layer 20 remains, as shown in FIG. 14D. In some embodiments, the thin layer of the support structure 20 remains at end portions of the CNTs 100 opposite the gate structure. The inner spacers 90 are formed on the thin layer of the support structure.Subsequently, further CMOS processes are performed to form various features, such as additional interlayer dielectric layers, contacts / vias, interconnect metal layers and passivation layers, etc.It should be understood that not all advantages have necessarily been discussed herein, no particular advantage is required for all embodiments or examples, and other embodiments or examples may provide other advantages. For example, in the present disclosure, stacked structures of CNTs are formed as fin structures, it is possible to increase a CNT density within a GAA-FET.According to an aspect of the present disclosure, in a method of forming a gate-all-around field effect transistor (GAA-FET), a lower support layer is formed over a substrate, a first group of carbon nanotubes (CNTs) is disposed over the lower support layer. A first support layer is formed over the first group of CNTs and the lower support layer, such that the first group of CNTs is embedded in the first support layer. A second group of carbon nanotubes (CNTs) is disposed over the first support layer. A second support layer is formed over the second group of CNTs and the first support layer, such that the second group of CNTs is embedded in the second support layer. A fin structure is formed by patterning at least the first support layer and the second support layer. In one or more of the foregoing and following embodiments, the formation of a group of CNTs and the formation of a support layer are repeated to form n support layers in which CNTs are embedded, where n is an integer greater than or equal to three. In one or more of the foregoing or following embodiments, the lower support layer comprises an insulating material. In one or more of the foregoing or following embodiments, the substrate is a semiconductor material. In one or more of the foregoing and following embodiments, the first support layer and the second support layer are made of a same material. In one or more of the foregoing and following embodiments, the first support layer and the second support layer comprise a polycrystalline or amorphous material of one of Si, Ge, and SiGe. In one or more of the foregoing and following embodiments, the first support layer and the second support layer comprise a dielectric material. In one or more of the foregoing and following embodiments, the lower support layer is made of a different material than the first support layer and the second support layer. In one or more of the above and below embodiments, a planarization operation is performed after at least one of the first support layer and the second support layer is formed.According to another aspect of the present application, in a method of forming a gate-all-around field effect transistor (GAA-FET), a fin structure in which carbon nanotubes (CNTs) are embedded in a support material is formed over a substrate. A sacrificial gate structure is formed over the fin structure. A dielectric layer is formed over the sacrificial gate structure and the fin structure. The sacrificial gate structure is removed, exposing a portion of the fin structure. The support material is removed from the exposed portion of the fin structure, exposing channel regions of CNTs. A gate structure is formed around the exposed channel regions of CNTs. In one or more of the foregoing and following embodiments, the support material comprises a polycrystalline or amorphous material of one of Si, Ge, and SiGe. In one or more of the foregoing and following embodiments, the support material comprises a dielectric material different from the dielectric layer. In one or more of the foregoing and following embodiments, an opening is formed in the dielectric layer and the support material such that the source / drain regions of the CNTs are exposed, and one or more conductive layers are formed in the opening around the exposed source / drain regions of the CNTs. In one or more of the above and below embodiments, in the fin structure, two CNTs out of the CNTs contact each other in the horizontal direction, and no CNT contacts another CNT in the vertical direction. In one or more of the foregoing and following embodiments, the gate structure includes a gate dielectric layer enclosing each of the CNTs, a work function adjustment layer formed on the gate dielectric layer, and a body gate electrode layer formed on the work function adjustment layer. In one or more of the foregoing and following embodiments, the work function adjustment layer partially encloses the CNTs with the gate dielectric layer. In one or more of the foregoing and following embodiments, the work function adjustment layer fully encloses each of the CNTs with the gate dielectric layer. In one or more of the foregoing and following embodiments, the gate dielectric layer comprises one selected from the group consisting of HfO 2 and Al 2 O 3. In one or more of the foregoing or below embodiments, the work function adjustment layer includes TiN.According to another aspect of the present disclosure, in a method of forming a gate-all-around field effect transistor (GAA-FET), a first fin structure and a second fin structure in each of which the carbon nanotubes (CNTs) are embedded in a support material are formed over a substrate. A dummy gate structure is formed over the first and second fin structures. A dielectric layer is formed over the dummy gate structure and the first and second fin structures. The dummy gate structure is removed, exposing a portion of the first and second fin structures. The support material is removed from the exposed portion of the first and second fin structures, exposing channel regions of CNTs. A gate structure is formed around the exposed channel regions of CNTs. A total number of CNTs in the first fin structure is different than a total number of CNTs in the second fin structure.According to an aspect of the present disclosure, a semiconductor device having a gate-all-around field effect transistor includes carbon nanotubes (CNTs) disposed over a substrate, a gate structure formed around the CNTs in a channel region, and a source / drain contact formed around the CNTs in the source / drain region. Two CNTs out of the CNTs contact each other in the horizontal direction, and no CNT contacts another CNT in the vertical direction. In one or more of the foregoing and following embodiments, the gate structure includes a gate dielectric layer enclosing each of the CNTs, a work function adjustment layer formed on the gate dielectric layer, and a body gate electrode layer formed on the work function adjustment layer. In one or more of the foregoing and following embodiments, the work function adjustment layer partially encloses the CNTs with the gate dielectric layer. In one or more of the foregoing and following embodiments, the work function adjustment layer fully encloses each of the CNTs with the gate dielectric layer. In one or more of the foregoing and following embodiments, the gate dielectric layer comprises one selected from the group consisting of HfO 2 and Al 2 O 3. In one or more of the foregoing or below embodiments, wherein the work function adjustment layer comprises TiN. In one or more of the foregoing and following embodiments, the semiconductor device further comprises internal spacers formed between the gate structure and the source / drain contact.According to another aspect of the present application, a semiconductor device including a gate-all-around field effect transistor (GAA-FET) includes a first GAA-FET and a second GAA-FET. Each of the first GAA FET and the second GAA FET includes carbon nanotubes (CNTs) disposed over a substrate, a gate structure formed around the CNTs in a channel region, and a source / drain contact formed around the CNTs in a source / drain region. A total number of CNTs in the first GAA FET is different from a total number of CNTs in the second GAA FET. In one or more of the foregoing and following embodiments, the gate structure includes a gate dielectric layer enclosing each of the CNTs, a work function adjustment layer formed on the gate dielectric layer, and a body gate electrode layer formed on the work function adjustment layer. In one or more of the foregoing and following embodiments, the work function adjustment layer partially encloses the CNTs with the gate dielectric layer. In one or more of the foregoing and following embodiments, the work function adjustment layer fully encloses each of the CNTs with the gate dielectric layer. In one or more of the foregoing and following embodiments, the gate dielectric layer comprises one selected from the group consisting of HfO 2 and Al 2 O 3. In one or more of the foregoing or below embodiments, the work function adjustment layer includes TiN. In one or more of the foregoing and following embodiments, the semiconductor device further comprises internal spacers formed between the gate structure and the source / drain contact.According to another aspect of the present application, a semiconductor device having a gate-all-around field effect transistor includes carbon nanotubes (CNTs) disposed over a substrate, a gate structure formed around the CNTs in a channel region, and a source / drain contact formed around the CNTs in a source / drain region. The CNTs are arranged in a plurality of layers, and a pitch between adjacent layers is 0.9×P A≤P V≤1.1×P A, where P A is an average pitch of the plurality of layers. In one or more of the foregoing and following embodiments, the gate structure includes a gate dielectric layer enclosing each of the CNTs, a work function adjustment layer formed on the gate dielectric layer, and a body gate electrode layer formed on the work function adjustment layer. In one or more of the foregoing and following embodiments, the work function adjustment layer partially encloses the CNTs with the gate dielectric layer. In one or more of the foregoing and following embodiments, the work function adjustment layer fully encloses each of the CNTs with the gate dielectric layer. In one or more of the foregoing and following embodiments, the gate dielectric layer comprises one selected from the group consisting of HfO 2 and Al 2 O 3. In one or more of the foregoing and following embodiments, a total number of CNTs in at least one layer is different from a total number of CNTs in another layer.

Claims

A method of forming a gate-all-around field effect transistor, GAA-FET, the method comprising: forming a bottom support layer (15) over a substrate (10); disposing a first group of carbon nanotubes, CNTs, (100) over the bottom support layer (15); forming a first support layer (21) over the first group of CNTs (100) and the bottom support layer (15) such that the first group of CNTs (100) is embedded in the first support layer (21); disposing a second group of carbon nanotubes, CNTs, (100) over the first support layer (21); forming a second support layer (22) over the second group of CNTs (100) and the first support layer (21), such that the second group of CNTs (100) is embedded in the second support layer (22), and forming a fin pattern (30) by patterning at least the first support layer (21) and the second support layer (22); wherein adjacent CNTs (100) in one of the groups of CNTs are in contact with each other, and wherein none of the CNTs (100) is in contact with another CNT (100) in a vertical direction.The method of claim 1, wherein the forming of a group of CNTs (100) and the forming of a support layer are repeated to form n support layers (21-26) in which CNTs (100) are embedded, where n is an integer greater than or equal to three.The method of claim 1 or 2, wherein the lower support layer (15) comprises an insulation material.The method of any preceding claim, wherein the substrate (10) is a semiconductor material.Method according to any of the preceding claims, wherein the first support layer (21) and the second support layer (22) are made of a same material.The method of claim 5, wherein the first support layer (21) and the second support layer (22) comprise a polycrystalline or amorphous material of one of Si, Ge and SiGe.The method of claim 5 or 6, wherein the first support layer (21) and the second support layer (22) comprise a dielectric material.Method according to any of the preceding claims 5 to 7, wherein the lower support layer (15) is made of a different material than the first support layer (21) and the second support layer (22).The method according to any one of the preceding claims, further comprising performing a planarization process after at least one of the first support layer (21) and the second support layer (22) is formed.A method of forming a gate-all-around field effect transistor, GAA-FET, the method comprising: forming a fin structure (30) in the carbon nanotubes. CNTs (100) embedded in a support material (20) over a substrate (10), wherein forming the fin structure (30) comprises: forming a bottom support layer (15) over the substrate (10); disposing a first group of the CNTs (100) over the bottom support layer (15); forming a first support layer (21) of the support material (20) over the first group of CNTs (100) and the bottom support layer (15) such that the first group of CNTs (100) is embedded in the first support layer (21); disposing a second group of the CNTs (100) over the first support layer (21); and forming a second support layer (22) of the support material (20) over the second group of CNTs (100) and the first support layer (21), such that the second group of CNTs (100) is embedded in the second support layer (22); the method further comprising: forming a sacrificial gate structure (40) over the fin structure (30), forming a dielectric layer (50) over the sacrificial gate structure (40) and the fin structure (30), removing the sacrificial gate structure (40) such that a portion of the fin structure (30) is exposed, removing the support material (20) from the exposed portion of the fin structure (30) such that channel regions of CNTs (100) are exposed, and forming a gate structure around the exposed channel regions of CNTs.The method of claim 10, wherein the support material (20) comprises a polycrystalline or amorphous material of one of Si, Ge, and SiGe.The method of claim 10 or 11, wherein the support material (20) comprises a dielectric material different from the dielectric layer (50).The method of any of the preceding claims 10 to 12, further comprising: forming an opening (65) in the dielectric layer (50) and the support material (20) such that source / drain regions of the CNTs (100) are exposed; and forming one or more conductive layers in the opening around the exposed source / drain regions of the CNTs.The method according to any one of the preceding claims 10 to 13, wherein in the fin structure (30), two CNTs (100) out of the CNTs (100) contact each other in the horizontal direction, and no CNT contacts another CNT in the vertical direction.The method of any of the preceding claims 10 to 14, wherein the gate structure comprises a gate dielectric layer (102) enclosing each of the CNTs (100), a work function adjustment layer (104) formed on the gate dielectric layer (102), and a body gate electrode layer (106) formed on the work function adjustment layer (104).The method of claim 15, wherein the work function adjustment layer (104) partially encloses the CNTs (100) with the gate dielectric layer (102).The method of claim 15, wherein the work function adjustment layer (104) completely surrounds each of the CNTs (100) with the gate dielectric layer (102).The method of any of the preceding claims 15 to 17, wherein the gate dielectric layer (102) comprises one selected from the group consisting of HfO 2 and Al 2 O 3.The method of any of the preceding claims 15 to 18, wherein the work function adjustment layer (104) comprises TiN.A semiconductor device having a gate-all-around field effect transistor, GAA-FET, comprising: a first GAA-FET, and a second GAA-FET, wherein each of the first GAA-FET and the second GAA-FET comprises: multiple layers of carbon nanotubes, CNTs (100), disposed over a substrate (10), wherein adjacent CNTs (100) in one of the layers are in contact with each other, and wherein none of the CNTs (100) is in contact with another CNT (100) in a vertical direction; a gate structure formed around the CNTs (100) in a channel region and a source / drain contact (70, 72) formed around the CNTs (100) in a source / drain region, wherein: a total number of CNTs (100) in the first GAA-FET is different from a total number of CNTs (100) in the second GAA-FET.

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