Chip on film and display device having the same

Abstract

Chip-on-film (300), comprising: a circuit film (320) having an integrated driver circuit (310) disposed thereon; integrated circuit input contacts (336) and N gate-in-panel input contacts (332, 334) formed on a first contact region (322) of the circuit film (320), where N is a natural number equal to or greater than 2; integrated circuit output contacts, N gate-in-panel output contacts (362) of a first group and N gate-in-panel output contacts (364) of a second group formed on a second contact region (324) of the circuit film (320); N gate-in-panel input lines (342, 344) formed on the circuit film (320) and connecting the gate-in-panel input contacts (332, 334) to input terminals of a first edge region of the integrated driver circuit (310); and N gate-in-panel output lines (352) of a first group connecting the gate-in-panel output contacts (362) of the first group to output terminals of a second edge portion of the integrated driver circuit (310), and N gate-in-panel output lines (354) of a second group connecting the gate-in-panel output contacts (364) of the second group to output terminals of a third edge portion of the integrated driver circuit (310) formed on the circuit film (320); and wherein the N gate-in-panel input lines (342, 344) are connected via the integrated driver circuit (310) to the gate-in-panel output lines (352) of the first group and to the gate-in-panel output lines (354) of the second group.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of Korean Patent Application No. 10-20170163390, filed on November 30, 2017. BACKGROUNDTechnical field

[0002] The present disclosure relates to a chip-on-film (COF) and a display device having the same, wherein a number of input contacts is reduced using a branching structure. Description of the technology used

[0003] Nowadays, representative examples of display devices for displaying an image using digital data include a liquid crystal display (LCD) using liquid crystals, an organic light-emitting diode (OLED) display using OLEDs, and an electrophoretic display (EPD) using electrophoretic particles.

[0004] A gate-in-panel (GIP) gate driver, arranged in a panel, is used as a gate driver to drive the gate lines of a panel. The GIP gate driver receives required GIP drive signals from a printed circuit board (PCB) via GIP transmission lines of a chip-on-film (COF) with a data driver integrated circuit (IC) formed therein.

[0005] The COF, which includes the GIP transmission lines, has N GIP input contacts arranged on a left side of a circuit film and N GIP input contacts arranged on a right side of the circuit film. During COF bonding, only the N GIP input contacts arranged on one side are connected to a PCB, and the N GIP input contacts arranged on the other side are dummy contacts that are not used.

[0006] However, when the number of GIP drive signals is increased, as in an OLED display device, the number of GIP input contacts formed in each COF is also increased, and thereby there is a problem that a pitch (e.g., an offset) of the input contacts of the COF is decreased.

[0007] When the number of input contacts of a COF is increased, a matching error may occur during a process of connecting the COF to a PCB, and therefore, a horizontal width of the COF is increased, but then there is a problem that manufacturing cost is increased because the horizontal width of the COF is increased.

[0008] A method of additionally dividing two source circuit boards into two parts each has been proposed to avoid the matching error during the connection process, however, the additional source circuit boards need to be connected to each other via a connector and a flexible cable, and therefore there is a problem that the number of steps in a connection and manufacturing process is increased, thereby increasing a cycle time and manufacturing cost.

[0009] The following publications are cited as state of the art: US 2010 / 0 245 299 A1, US 2016 / 0 379 906 A1. SHORT DESCRIPTION

[0010] In various embodiments, the present disclosure provides a chip-on-film (COF) and a display device having the same, wherein a number of input contacts is reduced using a branching structure.

[0011] Additional advantages, objects, and features of the disclosure will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned from practice of the disclosure. The objects and other advantages of the disclosure may be realized and obtained by means of the structure particularly pointed out in the written description and claims hereof, as well as in the appended drawings.

[0012] To achieve these objects and other advantages, and in accordance with the purpose of the disclosure as embodied and broadly described herein, a chip-on-film (COF) according to claim 1 and a chip-on-film according to claim 6 are provided. Further embodiments are described in the appended claims. According to one aspect of the present disclosure, a chip-on-film comprises: a circuit film having a driver integrated circuit (IC) disposed thereon; N gate-in-panel (GIP) input contacts and IC input contacts formed in a first contact region of the circuit film (N is a natural number equal to or greater than 2); N GIP output contacts of a first group formed in a second contact region of the circuit film, and N GIP output contacts and IC output contacts of a second group;N GIP input lines formed on the circuit film and connecting the GIP input contacts to input terminals of a first edge portion of the driver IC; and N GIP output lines of the first group connecting the GIP output contacts of the first group to output terminals of a second edge portion of the driver IC; and N GIP output lines of a second group connecting the GIP output contacts of the second group to output terminals of a third edge portion of the driver IC formed on the circuit film, and wherein the N GIP input lines are connected to the GIP output lines of the first group and to the GIP output lines of the second group via the driver IC.

[0013] The driver IC may include N first interconnection lines separately connected to the GIP input lines, and N second interconnection lines separately connecting the GIP output lines of the first group and the GIP output lines of the second group, and the first interconnection lines may be separately connected via a contact hole to the second interconnection lines arranged in another layer thereof.

[0014] The second connecting lines can separately connect the output terminals of the second edge portion of the driver IC and the output terminals of the third edge portion facing the second edge portion.

[0015] The GIP output contacts of the first group may be arranged on one side of the second contact area, the GIP output contacts of the second group may be arranged on the other side, and the IC output contacts may be arranged at a central portion between one side and the other side.

[0016] The GIP input contacts may be arranged on one side and in a central portion or on opposite sides of the first contact area, and the GIP input lines connected to the GIP input contacts may be connected to the input terminals arranged on one side of the first edge area of ​​the driver IC, to input terminals arranged in the central portion of the first edge area, or to input terminals arranged separately on opposite sides of the first edge area.

[0017] According to another aspect of the present disclosure, a chip-on-film comprises: a circuit film having a driver integrated circuit (IC) formed thereon; N gate-in-panel (GIP) input contacts and IC input contacts arranged in a first edge region of the circuit film (N is a natural number equal to or greater than 2); N GIP output contacts of a first group arranged in a second contact region of the circuit film; and N GIP output contacts and IC output contacts of a second group; N GIP input lines formed on the circuit film and connected to the GIP input contacts; N GIP output lines of the first group connected to the GIP output contacts of the first group; and N GIP output lines of the second group connected to the GIP output contacts of the second group formed on the circuit film;and N first connecting lines formed on the circuit film and connected to the GIP input lines; N second connecting lines formed on the circuit film in a different layer than the first connecting lines and connecting the GIP output lines of the first group to the GIP output lines of the second group, wherein the first connecting lines are separately connected to the second connecting lines via a contact hole.

[0018] According to another aspect of the present disclosure, a display device is configured such that a first COF connected to a first gate driver formed on the panel and a second COF connected to a second gate driver formed on the panel transmit a plurality of GIP drive signals using the aforementioned COF. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are included to provide a further understanding of the disclosure and which are incorporated herein and constitute a part of this application, illustrate embodiments of the disclosure and, together with the description, serve to explain certain principles of the disclosure. Fig. 1 is a schematic block diagram illustrating a configuration of a display device according to an embodiment of the present disclosure; Fig. 2 is a diagram showing a COF structure with respect to a gate-in-panel (GIP) transmission path in accordance with a first embodiment of the present disclosure; Fig. Figure 3 is an enlarged view of a GIP transmission path used in the COF shown in Fig. 2 is illustrated; Fig. 4 is a diagram showing a COF structure with respect to a GIP transmission path according to a second embodiment of the present disclosure; Fig. 5 is a diagram showing a COF structure with respect to a GIP transmission path according to a third embodiment of the present disclosure; and Fig. 6 is a diagram showing a COF structure with respect to a GIP transmission path according to a fourth embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] Reference will now be made in detail to preferred embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.

[0021] Fig. 1 is a schematic block diagram showing a configuration of a display device according to an embodiment of the present disclosure.

[0022] Referring to Fig. 1, the display device may include a panel 100, a gate driver 200, 210 of the gate-in-panel (GIP) type, a data driver, source printed circuit boards (PCBs) 500, 510, etc.

[0023] The panel 100 can display an image using a pixel array PA in which subpixels are arranged in a matrix. A base pixel can have at least three subpixels capable of displaying white via a color mixture of white W, red R, green G, and blue B subpixels. For example, the base pixel can have subpixels of an R / G / B combination or subpixels of a W / R / G / B combination. The base pixel can have subpixels of an R / G / B combination, subpixels of a W / R / G combination, subpixels of a B / W / R combination, and / or subpixels of a G / B / W combination.

[0024] The panel 100 may include various display panels, such as a liquid crystal display (LCD) panel or an organic light-emitting diode (OLED) panel, and may include a touch panel having a touch sensing function and a display function.

[0025] The panel 100 may include first and second GIP-type gate drivers 200, 210 formed therein. The first and second gate drivers 200, 210 may be arranged in first and second non-active regions of the panel 100, respectively, to drive the gate lines comprising the pixel array PA. The first and second gate drivers 200, 210 may simultaneously supply gate signals to each of the gate lines at opposite ends to reduce gate signal delay.

[0026] The data driver may include a plurality of chips-on-film (COFs) 300 in which a plurality of data driver integrated circuits (ICs) 310 are separately formed on a plurality of circuit films 320.

[0027] The plurality of COFs 300 may connect the first and second source circuit boards 500, 510 to the panel 100. A first contact area of ​​each of the plurality of COFs 300 may include a plurality of input contacts attached to and connected to contact areas of the first and second source circuit boards 500, 510 via an anisotropic conductive film (ACF) using tape automatic bonding (TAB). A second contact area of ​​each of the plurality of COFs 300 may include a plurality of output contacts attached to and connected to contact areas of the panel 100 via an ACF using a TAB method.

[0028] The first and second PCBs 500, 510 may be connected to a control PCB 400 via first and second flat flexible cables (FFCs) 410, 420. A timing controller for generating a plurality of data control signals and outputting the data control signals with image data, a level shifter for generating and outputting a plurality of GIP drive signals under the control of the timing controller, and drive circuits, such as a power management circuit for generating and outputting a plurality of drive voltages required by a display device, may be formed on the control PCB 400.

[0029] The plurality of data driver ICs 310 may receive a plurality of data control signals and image data from the control PCB 400 via the FFCs 410, 420 and the source circuit boards 500, 510, convert the received image data into analog data signals, and supply the analog data signals to the data lines of the panel 100.

[0030] If the panel 100 is an organic light-emitting diode (OLED) panel, the plurality of data driver ICs 310 may include a sampling unit for detecting a pixel current that indicates electrical characteristics (a threshold voltage and mobility of a driver TFT and a threshold voltage of an OLED device) of each sub-pixel as a current or voltage, converting the pixel current into digital sampling data under the control of the timing controller, and passing the digital sampling data to the timing controller. The timing controller may update a compensation value of each sub-pixel using the sampling data of each sub-pixel received from the plurality of data driver ICs 310.The timing controller may compensate image data with a corresponding compensation value in accordance with each sub-pixel to compensate for brightness unevenness due to differences between the characteristics of the sub-pixels.

[0031] GIP drive signals generated by the level shifter of the control PCB 400 may be transmitted to a first COF 300 via the first FFC 410 and the first source PCB 500 and may be transmitted to at least one COF 300 via the second FFC 420 and the second source PCB 510.

[0032] For example, the GIP drive signals may include a plurality of scan clocks used as a start pulse, a reset pulse, alternating current (AC) drive voltages for an odd frame, an AC drive voltage for an even frame, and a scan signal for driving the gate lines. Further, the GIP drive signals may include a plurality of carrier clocks for controlling a shift operation of the gate drivers 200, 210. If the panel 100 is an OLED panel, the GIP drive signals may further include a plurality of scan clocks used as scan signals for driving the scan gate lines.

[0033] The first and last COFs 300 may further include a GIP transmission path. The first and last COFs 300 transmit a plurality of GIP driver signals supplied from the source circuit boards 500, 510 to the first and second gate drivers 200, 210 of the panel 100 via the GIP transmission path.

[0034] Specifically, according to an embodiment of the present disclosure, the first and last COFs 300 may each be connected to 2N GIP output contacts using a structure formed in a data driver IC or a circuit film by branching N GIP conductors connected to the N GIP input contacts into 2N parts. Accordingly, the number of GIP input contacts can be reduced from 2N as in the related art to N, that is, half of that in the related art.

[0035] Fig. 2 is a diagram showing a COF structure with respect to a GIP transmission path according to a first embodiment of the present disclosure. Fig. Figure 3 is an enlarged view of a GIP transmission path arranged in the COF shown in Fig. 2 is illustrated.

[0036] Referring to the Fig. 2 and Fig. 3, a COF 300 having a GIP transmission path according to an embodiment of the present disclosure may include N GIP input contacts 332, 334 disposed in a first contact region 322 of the circuit film 320 and 2N GIP output contacts 362, 364 formed in a second contact region 324 of the circuit film 320. The COF 300 may further include N GIP input lines 342, 344 formed on the circuit film 320 and connecting the N GIP input contacts 332, 334 to the data driver IC 310, and 2N GIP output lines 352, 354 formed on the circuit film 320 and connecting the data driver IC 310 and the 2N GIP output contacts 362, 364.

[0037] The data driver IC 310 may have first to fourth edge regions a, b, c, d. Terminals connected to the first contact region 322 may be arranged at a first edge portion a of the data driver IC 310, and terminals connected to the second contact region 324 may be arranged at the second to fourth edge regions b, c, d. The first and fourth edge regions a, d of the data driver IC 310 may face each other, and the second and third edge portions b, c may face each other.

[0038] The first contact area 322 of the circuit film 320 may be connected to the contact areas of the source circuit board 500 or 510. The first contact area 322 of the circuit film 320 may include the N GIP input contacts 332, 334 and the IC input contacts 336. The N GIP input contacts 332, 334 may include a first group 332 and a second group 334, each of which is divided into N / 2 parts, and the IC input contacts 336 may be arranged between the first and second groups 332, 334. The N / 2 GIP input contacts 332 of the first group may be arranged on one side of the first contact area 322, and the N / 2 input contacts 334 of the second group may be arranged on the other side. Furthermore, IC output contacts (not shown) connected to the source circuit board 500 or 510 may be formed on the first contact area 322.

[0039] The N GIP input lines 342, 344 formed in the circuit film 320 may also include the first group 342 and the second group 344, each of which is divided into N / 2 parts. The GIP input lines 342 of the first group may be separately connected to the GIP input contacts 332 of the first group and may be separately connected to the input terminals formed on one side of the first edge portion of the data driver IC 310. The GIP input lines 344 of the second group may be separately connected to the GIP input contacts 334 of the second group and may be separately connected to input terminals formed on the other end of the first edge portion of the data driver IC 310.

[0040] The second contact area 324 of the circuit film 320 may be connected to the contact area of ​​the panel 100. In this case, with respect to the 2N GIP output contacts 362, 364, the first group 362 or the second group 364 may be connected to the contact area of ​​the panel 100, and the other group may be a dummy contact that is not connected to the panel 100. The N GIP output contacts 362 of the first group may be formed on one side of the second contact area 324, the N GIP output contacts 364 of the second group may be formed on the other side of the second contact area 324, and IC output contacts 366 may be formed between the first group and the second group 362, 364. The IC output contacts 366 may be connected to output terminals of the fourth edge portion d of the data driver IC 310 via lines.

[0041] The 2N GIP output lines 352, 354 formed on the circuit film 320 may include a first group 352 and a second group 354, each of which is divided into N parts. The GIP output lines 352 of the first group may be separately connected to output terminals of the second edge portion b of the data driver IC 310 and may be separately connected to the N GIP output contacts 362 of the first group. The GIP output lines 354 of the second group may be separately connected to output terminals of the third edge portion c of the data driver IC 310 and may be separately connected to the N GIP output contacts 364 of the second group.

[0042] The N GIP input lines 342, 344 can be connected to the N GIP output lines 352 of the first group and also to the N GIP output lines 354 of the second group via the data driver IC 310. Accordingly, the N GIP input pins 332, 334 can be connected to the 2N GIP output pins 362, 364 via the data driver IC 310.

[0043] Referring to Fig. 3, the N GIP input lines 342, 344 may be separately connected to N first connection lines 312 formed in the data driver IC 310 via terminals of the first edge portion a of the data driver IC 310. The N first connection lines 312 may be separately connected to N second connection lines 314 in the data driver IC 310. The N second connection lines 314 and the N first connection lines 312 may cross each other with an insulating layer formed therebetween, and the N second connection lines 314 may be connected to the N first connection lines 312 via a through-hole formed in the insulating layer. The first connection lines 312 may extend in the Y-axis direction, and the second connection lines 314 may extend in the X-axis direction.

[0044] First ends of the N second connecting lines 314 can be separately connected to the N GIP output lines 352 of the first group via terminals of the second edge portion b of the data driver IC 310, and thereby they can be connected to the GIP output contacts 362 of the first group. The other ends of the N second connecting lines 314 can be separately connected to the N GIP output lines 354 of the second group via terminals of the third edge portion c of the data driver IC 310, and thereby they can be connected to the GIP output contacts 364 of the second group.

[0045] In other words, the N GIP output lines of the first group may be separately connected to the N GIP output lines 354 of the second group via the second connection lines 314 in the data driver IC 310 extending in the X-axis direction. The N GIP output lines 352 of the first group and the N GIP output lines 354 of the second group may be separately connected to the first connection lines 312 in the data driver IC 310 via the second connection lines 314 in the data driver IC 310.

[0046] The GIP output lines 352 of the first group may include Y-axis direction extension portions connected to the GIP output contacts 362 of the first group, and X-axis direction extension portions connecting the Y-axis direction extension portions to the output terminals of the second edge portion b of the data driver IC 310. The GIP output lines 354 of the second group may include Y-axis direction extension portions connected to the GIP output contacts 364 of the second group, and X-axis direction extension portions connecting the Y-axis direction extension portions to the output terminals of the third edge portion c of the data driver IC 310.

[0047] Thus, the COF 300 can use the second connection lines 314, which are connected to the first connection lines 312 in the data driver IC 310 via the branching structure, to connect the N GIP input pins to the 2N GIP output pins. Accordingly, the number of GIP input pins can be reduced from 2N according to the related art to N, that is, to half of that in the related art.

[0048] The Fig. 4 and Fig. 5 are diagrams showing a COF structure with respect to a GIP transmission path according to second and third embodiments of the present disclosure.

[0049] Referring to Fig. 4, in the first contact area 322 of the circuit film 320, N GIP input contacts 331 may be arranged on one side, and IC input contacts 336 may be arranged on the other side. N GIP input lines 341 connected to the N GIP input contacts 331 may be connected to input terminals arranged on one side of the first edge area a of the data driver IC 310. The other components are the same as described above with reference to Fig. 2 and Fig. 3 described.

[0050] Referring to Fig. 5, in the first contact area 322 of the circuit film 320, the N GIP input contacts 333 may be arranged in a central portion, and the IC input contacts 336 may be arranged on opposite sides of the first contact area 322 of the circuit film 320. The N GIP input lines 343 connected to the N GIP input contacts 333 may be connected to input terminals arranged in a central portion of the first edge area a of the data driver IC 310. The other components are the same as previously described with reference to Fig. 2 and Fig. 3 described.

[0051] Fig. 6 is a diagram showing a COF structure with respect to a GIP transmission path according to a fourth embodiment of the present disclosure.

[0052] Compared to the COF used in Fig. 3, the COF, which is shown in Fig. 6, may be formed such that all lines for a GIP are arranged on the circuit film 320 to independently transmit GIP drive signals without connection to the data driver IC 310, and first connection lines 380 and second connection lines 370 may be formed in different layers of a circuit film 320 and may be connected to each other via a through hole.

[0053] For example, the second interconnection lines 370 connecting the N-type output lines 352 for a GIP of the first group to the N-type output lines 354 for a GIP of the second group may be formed on the same layer as the GIP output lines 352, 354, and the GIP input lines 342, 344 may also be formed in the same layer. The first interconnection lines 380 connecting the GIP input lines 342, 344 may be formed in a different layer to cross the second interconnection lines 370 and may be connected to the GIP input lines 342, 344 and the second interconnection lines 370 via a through-hole.

[0054] The second connection lines 370 may overlap with an installation area for the data driver IC 310, and on the other hand, the first connection lines 380 may not overlap with the installation area for the data driver IC 310, may cross the second connection lines 370, and may be separately connected to the second connection lines 370 via a through hole.

[0055] The N GIP output lines 352 of the first group may include a Y-axis direction extension portion connected to the GIP output contacts 362 of the first group, and an X-axis direction extension portion connecting the Y-axis direction extension portion to one end of the second connecting lines 370. The GIP output lines 354 of the second group may include a Y-axis direction extension portion connected to the GIP output contacts of the second group, and an X-axis direction extension portion connecting the Y-axis direction extension portion to the other end of the second connecting lines 370.

[0056] The N GIP input lines 342, 344 may be connected to the N GIP output lines 352 of the first group and may also be connected to the N GIP output lines 354 of the second group formed on the circuit film 320 via a branching structure of the first connection lines 380 and the second connection lines 370. Accordingly, the N GIP input contacts 332, 334 may be connected to the 2N GIP output contacts 362, 364, and thereby the number of GIP input contacts can be reduced from 2N according to the related art to N, that is, to half of that in the related art.

[0057] The COF structure according to the previous embodiments described with reference to the Fig. 2 to 6 can be transferred in the same way to a PCB structure corresponding to the COF or to a COF of a display device using a gate driver IC.

[0058] A COF according to one embodiment can be connected to 2N GIP output contacts using a structure formed by branching N GIP lines connected to the N GIP input contacts into 2N parts in a driver IC or a circuit film. Accordingly, the number of GIP input contacts can be reduced from 2N according to the related art to N, that is, half of that in the related art.

[0059] Accordingly, even if a horizontal width of a COF is not increased, a pitch of an input contact can be kept unchanged, and thus a matching error during the connection process of a COF with a PCB can be minimized and manufacturing costs can be reduced.

[0060] In order to avoid the matching error of a COF and a circuit board, it is not necessary to divide each of the two source circuit boards into a plurality of parts and therefore connection processes and manufacturing processes can be easily performed, thereby reducing cycle time and manufacturing costs.

[0061] A COF according to an embodiment of the present disclosure can be used in any display device, such as an OLED display device or an LCD.

[0062] Various embodiments provide a chip-on-film comprising: a circuit film having a driver integrated circuit IC formed thereon; IC input contacts and N gate-in-panel (GIP) input contacts arranged in a first contact region of the circuit film, where N is a natural number equal to or greater than 2; IC output contacts, N GIP output contacts of a first group, and N GIP output contacts of a second group formed in a second contact region of the circuit film; N GIP input lines formed in the circuit film and connecting the GIP input contacts to the input terminals of a first edge region of the driver PC;and N GIP output lines of a second group connecting the GIP output contacts of the first group to the output terminals of a second edge region of the driver IC, and N GIP output lines of a second group connecting the GIP output contacts of the second group to the output terminals of a second edge region of the driver IC formed in the circuit film; and wherein the N GIP input lines are connected via the driver IC to the GIP output lines of the first group and to the GIP output lines of the second group.

[0063] In one or more embodiments, the driver IC comprises N first interconnection lines separately connected to the GIP input lines, and N second interconnection lines separately connecting the GIP output lines of the first group to the GIP output lines of the second group; and the first interconnection lines are separately connected to the second interconnection lines formed in another layer via a contact hole.

[0064] In one or more embodiments, the second connecting lines separately connect the output terminals of the second edge portion of the driver IC to the output terminals of the third edge portion facing the second edge portion.

[0065] In one or more embodiments, the GIP output contacts of the first group are formed on one side of the second contact area, the GIP output contacts of the second group are formed on the other side of the second contact area, and the IC output contacts are formed in a central portion between one and the other side.

[0066] In one or more embodiments, the GIP input contacts are formed on one side of the first contact area, in a central portion of the first contact area, or on two opposite sides of the first contact area; and the GIP input lines are connected to input terminals formed on one side of the first edge portion of the driver IC, to input terminals formed in the central portion of the first edge portion, or to input terminals formed separately on two opposite sides of the first edge portion.

[0067] Various embodiments provide a chip-on-film comprising: a circuit film with an integrated driver circuit IC formed thereon; IC input contacts and N gate-in-panel GIP input contacts formed on a first contact region of the circuit film, where N is a natural number equal to or greater than 2; IC output contacts, N GIP output contacts of a first group and N GIP output contacts of a second group formed in a second contact region of the circuit film; N GIP input lines formed on the circuit film and connected to the GIP input contacts; N GIP output lines of a first group connected to the GIP output contacts of the first group, and N GIP output lines of a second group connected to the GIP output contacts of the second group formed on the circuit film;and N first connecting lines formed on the circuit film and connected to the GIP input lines; and N second connecting lines formed in the circuit film in a different layer than the first connecting lines and connecting the GIP output lines of the first group to the GIP output lines of the second group, wherein the first connecting lines are separately connected to the second connecting lines via a through-hole.

[0068] In one or more embodiments, the first connecting lines do not overlap with an installation area for the driver IC; and the second connecting lines overlap with the installation area for the driver IC.

[0069] Various embodiments provide a display device comprising: a panel having a pixel array and first and second gate drivers arranged on opposite sides of the panel for driving gate lines of the pixel array; and a plurality of chips-on-film on which a plurality of data driver integrated circuits (ICs) for driving data lines of the pixel array are formed on a plurality of corresponding circuit films and which connect the panel to a circuit board, wherein the plurality of chips-on-film comprise chips-on-film according to one or more embodiments described herein as a first chip-on-film and as a second chip-on-film, wherein the first chip-on-film is connected to the first gate driver, the second chip-on-film is connected to the second gate driver, and the first and second chip-on-films transmit a plurality of GIP drive signals.

[0070] In one or more embodiments, the first and second chip-on-films are connected to the circuit board via the first contact area and to the panel via the second contact area; wherein for each of the first and second chip-on-films, only one group of the GIP output contacts of the first group and the GIP output contacts of the second group in the second contact area are connected to the panel and the remaining group is not connected to the panel.

[0071] It will be apparent to those skilled in the art that various modifications and variations of the present disclosure can be made without departing from the scope of the disclosure. Therefore, it is intended that the present disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims.

[0072] The various embodiments described above may be combined to provide further embodiments. These and other changes may be made to the embodiments in light of the foregoing detailed description. In general, the terms used in the following claims should not be construed to limit the claims to the specific embodiments disclosed in the description and claims. Accordingly, the claims are not limited by the disclosure.

Claims

[1] Chip-on-film (300), comprising: a circuit film (320) having an integrated driver circuit (310) disposed thereon; integrated circuit input contacts (336) and N gate-in-panel input contacts (332, 334) formed on a first contact region (322) of the circuit film (320), where N is a natural number equal to or greater than 2; integrated circuit output contacts, N gate-in-panel output contacts (362) of a first group and N gate-in-panel output contacts (364) of a second group formed on a second contact region (324) of the circuit film (320); N gate-in-panel input lines (342, 344) formed on the circuit film (320) and connecting the gate-in-panel input contacts (332, 334) to input terminals of a first edge region of the integrated driver circuit (310); and N gate-in-panel output lines (352) of a first group connecting the gate-in-panel output contacts (362) of the first group to output terminals of a second edge portion of the integrated driver circuit (310), and N gate-in-panel output lines (354) of a second group connecting the gate-in-panel output contacts (364) of the second group to output terminals of a third edge portion of the integrated driver circuit (310) formed on the circuit film (320); and wherein the N gate-in-panel input lines (342, 344) are connected via the integrated driver circuit (310) to the gate-in-panel output lines (352) of the first group and to the gate-in-panel output lines (354) of the second group. [2] The chip-on-film (300) of claim 1, wherein the driver integrated circuit (310) comprises N first interconnection lines (312) separately connected to the gate-in-panel input lines (342, 344), and N second interconnection lines (314) separately connecting the gate-in-panel output lines (352) of the first group to the gate-in-panel output lines (354) of the second group; and wherein the first interconnection lines (312) are separately connected to the second interconnection lines (314) formed in another layer thereof via a contact hole. [3] The chip-on-film (300) of claim 2, wherein the second connecting lines (314) connect output terminals of the second edge portion of the driver integrated circuit (310) to output terminals of the third edge portion facing the second edge portion. [4] The chip-on-film (300) of claim 3, wherein the gate-in-panel output contacts (362) of the first group are formed on one side of the second contact region (324), the gate-in-panel output contacts (364) of the second group are formed on the other side of the second contact region (324), and the integrated circuit output contacts are formed in a central portion between the one side and the other side. [5] The chip-on-film (300) of any one of claims 2 to 4, wherein the gate-in-panel input contacts (332, 334) are formed on one side of the first contact region (322), in a central portion of the first contact region (322), or on opposite sides of the first contact region (322); and wherein the gate-in-panel input lines (342, 344) are connected to input terminals arranged on one side of the first edge region of the driver integrated circuit (310), to input terminals arranged in the central portion of the first edge portion, or to input terminals formed separately on two opposite sides of the first edge portion. [6] Chip-on-film (300), comprising: a circuit film (320) having an integrated driver circuit (310) disposed thereon; integrated circuit input contacts (336) and N gate-in-panel input contacts (332, 334) arranged in a first contact region (322) of the circuit film (320), where N is a natural number equal to or greater than 2; integrated circuit output contacts, N gate-in-panel output contacts (362) of a first group and N gate-in-panel output contacts (364) of a second group formed in a second contact region (324) of the circuit film (320); N gate-in-panel input lines (342, 344) formed on the circuit film (320) and connected to the gate-in-panel input contacts (332, 334); N gate-in-panel output lines (352) of a first group connected to the gate-in-panel output contacts (362) of the first group, and N gate-in-panel output lines (354) of a second group connected to the gate-in-panel output contacts (364) of the second group formed on the circuit film (320); and N first connecting lines (380) formed on the circuit film (320) and connected to the gate-in-panel input lines (342, 344); and N second connecting lines (370) formed on the circuit film (320) in a different layer than the first connecting lines (380) and connecting the gate-in-panel output lines (352) of the first group to the gate-in-panel output lines (354) of the second group, wherein the first connecting lines (380) are separately connected to the second connecting lines (370) via a through hole. [7] The chip-on-film (300) of claim 6, wherein the first interconnection lines (380) do not overlap with an installation area for the driver integrated circuit (310); and wherein the second interconnection lines (370) overlap with the installation area for the driver integrated circuit (310). [8] Display device, comprising: a panel (100) having a pixel array (PA) and first and second gate drivers (200, 210) arranged on opposite sides of the panel (100) for driving gate lines of the pixel array (PA); and a plurality of chips-on-film (300) in which a plurality of integrated data driver circuits (310) for driving data lines of the pixel array (PA) are arranged on a plurality of corresponding circuit films (320) and which connect the panel (100) to a circuit board (500, 510), wherein the plurality of chips-on-film (300) comprises chips-on-film according to any one of claims 1 to 7 as the first chip-on-film and as the second chip-on-film, the first chip-on-film being connected to the first gate driver (200) and the second chip-on-film being connected to the second gate driver (210), the first and second chip-on-films transmitting a plurality of gate-in-panel drive signals. [9] The display device of claim 8, wherein the first and second chip-on-films (300) are each connected to the circuit board (500, 510) via the first contact area (322) and are each connected to the panel (100) via the second contact area (324); and wherein, for each of the first and second chip-on-films (300), only one group of the gate-in-panel output contacts (362) of the first group and the gate-in-panel output contacts (364) of the second group on the second contact area (324) is connected to the panel (100), and the remaining group is not connected to the panel (100).

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