FinFET ESD device with Schottky diode

Abstract

Electrostatic discharge device (100; 400) with Fin field-effect transistor, wherein the device (100; 400) comprises: a substrate (108; 408); a thyristor above the substrate (108; 408), the thyristor comprising: a p-well region (106; 406) above the substrate (108; 408), an n-well region (104; 404) laterally adjacent to the p-well region (106; 406) above the substrate (108; 408) and adjacent to a metal contact (128; 428), a first (P+)-doped region (112; 412) above the p-well region (106; 406), a first (N+)-doped region (114; 414) above the p-well region (106; 406), a second (N+)-doped region (116; 416) above the p-well region (106; 406), and a Schottky diode (102; 402) formed by the n-well region (104; 404) and the metal contact (128; 428), wherein the Schottky diode (102; 402) is free of (N+)-doped or (P+)-doped regions, and wherein the Schottky diode (102;402) controls an electrostatic discharge between the second (N+)-doped region (116; 416) and the n-tub region (104; 404).;

Description

BACKGROUNDThe invention described herein relates to integrated circuit devices. More particularly, the invention relates to circuits for managing electrostatic discharge (ESD) in fin-type field effect transistor (FinFET) structures.As integrated circuit technology has evolved, circuit devices have become smaller and smaller with the process technique used to fabricate this device. Accumulation of circuits in these advanced devices increases the influence of ESD or the discharge of static electricity from the surface of a body to a device. Considerations on ESD are relevant to manufacturing processes used in forming integrated circuit devices as well as in the end-user environment in which haptics increase the level of user-device interaction.US 2006 / 0 258 067 A1 discloses an apparatus for protecting against electrostatic discharge, the apparatus comprising a first and a second conductivity type region which are formed in a substrate and which contact one another, a first diffusion layer of dopants of the second conductivity type which are formed in the region of the first conductivity type and are electrically connected to an anode, a second diffusion layer of dopants of the first conductivity type which are formed in the region of the second conductivity type and are electrically connected to a cathode, and at least one of a third diffusion layer of dopants of the first conductivity type. The dopants in the first conductivity type region are formed between the first diffusion layer and the second conductivity type region and electrically connected to the anode via a first external resistor. Furthermore, the device comprises a fourth diffusion layer of dopants of the second conductivity type, which are formed in the region of the second conductivity type between the second diffusion layer and the region of the first conductivity type and are electrically connected to the cathode via a second external resistor.From the document US 2002 / 0 050 615 A1 a device for protecting against electrostatic discharge is known, comprising a first well of a first conductivity type, a second well of a second conductivity type opposite to the first conductivity type, which is in contact with the first well to form a junction, and a MOS of the first conductivity type. The first conductivity type MOS includes a control gate positioned on the second well, a first drain / source region of the first conductivity type formed on the junction, and a second drain / source region of the first conductivity type formed on the second well and coupled to a first pad. Further, the device includes a first doped region of the second conductivity type coupled to a second pad formed on the first well and associated with the first well, the second well, and the second drain / source region to construct a lateral semiconductor controlled rectifier (LSCR), a second doped region of the first conductivity type formed on the surface of the well and between the first doped region and the first drain / source region, and a dummy gate positioned between the first drain / source region and the second doped region and on the first well.SUMMARYIn a first aspect, an electrostatic discharge (ESD) device with a fin field effect transistor (FinFET) is defined according to independent claim 1. Advantageous embodiments thereof are defined in dependent claims 2 to 6.In a second aspect, according to independent claim 7, an electrostatic discharge (ESD) device is defined with a fin field effect transistor (FinFET). Advantageous embodiments thereof are defined in dependent claims 8 and 9.In a third aspect, an electrostatic discharge (ESD) device with a fin field effect transistor (FinFET) is defined according to independent claim 10. Advantageous embodiments thereof are defined in the dependent claims 11 to 14.BRIEF DESCRIPTION OF THE FIGURESThese and other features of this invention will be apparent from the following detailed description of the various aspects of the invention, taken in conjunction with the accompanying drawings which illustrate various embodiments of the invention. FIG. 1 shows a cross-sectional view of an IC structure including a FinFET device in accordance with embodiments of this invention. FIG. 2 is a diagram illustrating a current of a FinFET device versus voltage, in accordance with embodiments of this invention. FIG. 3 is a diagram illustrating a current of a FinFET device versus voltage, in accordance with embodiments of this invention. FIG. 4 shows a cross-sectional view of an IC structure including a FinFET device in accordance with embodiments of this invention.The figures of the invention are not necessarily to scale. The figures are intended to represent only typical aspects of the invention and thus are not intended to limit the spirit of the invention. In the figures, similar numbering represents similar elements between the figures.DETAILED DESCRIPTIONIn the following description, reference is made to the accompanying drawings, which form a part hereof, and in which is illustrated specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings. The different process steps discussed herein may be implemented in the same manner and / or performed with minor modifications for semiconductor elements performed in shapes different from a silicon layer. Further, semiconductor elements may represent a remaining portion of a single semiconductor on insulator (SOI) substrate formed from a layer of semiconductor material bonded to and disposed on a buried insulator layer, as described elsewhere.The conventional structures for reducing ESD voltage levels are not sufficient. Embodiments of the invention include a device having at least one Schottky diode to protect ESD nodes from voltages exceeding a device tolerance level. Schottky diodes (also known as "Schottky barrier diodes") are formed at a junction between a metal and a semiconductor material. The arrangement of the metal directly on the semiconductor material may allow a depletion region to form at the interface during operation of a device. The current-voltage characteristics of the Schottky diode depend on the polarity of the applied voltage. As used herein, "well terminals" are used to prevent latch-up and are disposed in the integrated circuit at appropriate distances from one another. Each well terminal represents an electrically conductive line coupling a well region of the integrated circuit to a power source, and each substrate terminal represents an electrically conductive line coupling a substrate region of the integrated circuit to ground. Couplings of the well and substrate regions respectively to power and ground reduce the substrate resistance, thus causing the positive feedback to be removed. In addition to use herein, an ohmic contact or "ohmic contact trench" is defined as one in which there is unimpeded transfer of main charge carriers from one material to another, in particular the contacts do not limit current. Contact can be achieved in this manner by sufficiently high doping of the semiconductor to enable tunnelling.Forming at least one device according to the present invention may include forming a p-well and an n-well on a semiconductor substrate directly adjacent to each other. As shown in FIG. 1, the p-well may be divided therein by three isolation trenches 118, 120, 122. The p-well region may include a (P+) doped region 112 between first and second trenches 118, 120, a first (N+) doped region at a side adjacent to the second trench 120, and a second (N+) doped region 116 at an opposite side of the gate 121 at a third trench 122. These structures may thereby define a Schottky diode 102 within the FinFET structure, such that the Schottky diode 102 is formed without using additional process masks, as required in conventional structures, for example. Optionally, a supply terminal 150 (shown in phantom) may be used in conjunction with embodiments of this invention. A supply terminal 150 is an electronic circuit which sets either the positive or negative peaks of a signal by offsetting its DC value to a predetermined value. The entire structure of a general clamping circuit is composed of three parts: the clamping device, the delay element and the detecting element. The P - N - P - N switch of the thyristor may include a substrate 112 (p type), an n well region 104, a p well region 106, and a negatively charged gate 121.FIG. 1 specifically shows a cross-sectional view of an electrostatic discharge (ESD) device with FinFET (hereafter simply "device") 100, according to an embodiment of the present invention. The device 100 includes a semiconductor substrate 108 that may be formed of a bulk substrate silicon or a doped silicon below a p-well region 106 at an n-well region 104. The semiconductor substrate 108 may include, but is not limited to, germanium, silicon germanium, silicon carbon, and those III-V compound semiconductors having a composition substantially defined by the formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 where X1, X2, X3, Y1, Y2, Y3, and Y4represent relative proportionalitys that are each greater than or equal to 0 and X1+X2+X3+Y1+Y2+Y3+Y4=1 (where 1 represents the total relative mole size).With continued reference to FIG. 1, the p-well region 106 may be positively doped, for example with ions of boron and / or BF 2( boron fluoride). Other suitable substrates include II-VI compound semiconductors having a composition of Zn A1 Cd A2 Si B1 Te S2, where A1, A2, B1, B2represent relative proportionalitys that are each greater than or equal to 0 and A1+A2+B1+B2= 1 (where 1 is a total mole size). Further, a portion or the entire semiconductor substrate 108 may be strained. At the center of the FinFET ESD device 100, a Fin 124 is shown.The device 100 comprises a Schottky diode 102. The Schottky diode 102 is formed to be laterally adjacent to the n-well region 104, and is formed by the connection between a metal surface and the semiconductor substrate 108. In this embodiment, a metal contact 125 forms the metal surface and may be electrically connected to the n-well region 104. The Schottky diode 102 is electrically coupled at a source side 126 of the FinFET ESD device to a thyristor (SCR) having an extra terminal at a contact 125 as an anode for applying a latch voltage for turn-on. The metal contact 125 may include a metal, such as, but not limited to: molybdenum, platinum, chromium, or tungsten, and may include certain silicides (e.g., palladium silicide and platinum silicide). The n-well region 104 may be negatively doped, e.g., with ions of arsenic and / or phosphorus, to serve as an anode region of the Schottky diode 102. This n-well region 104 represents a source side 126 of the device 110, in particular an NMOS FinFET.The SCR of the device 100 may also include a (P+) doped region 112 including a well terminal for applying a reverse bias to the n-well region 104 and the p-well region 106 to avoid latch-up. The device 100 may also include a first (N+) doped fin region 114 acting as a drain region and a second (N+) doped region 116 acting as a source region at a gate 124 (Fin) formed over a p-well region 106 between the first (N+) doped region 114 and a second (N+) doped region 116. The device 100 may include a shallow isolation trench 118 laterally adjacent to the (P+) doped region 112, which is also laterally adjacent to the isolation trench 120. The isolation trench 122 is disposed at the second (N+) doped region 116 and the n-well region 104. Optionally, the supply terminal 150 may be electrically coupled to the (P+) doped region 112 to set either positive or negative peaks of a signal to a predetermined value by offsetting a DC value.Referring to FIG. 2, a comparison plot 200 is shown depicting a general transmission line pulse (TLP) current of a PNPN switch according to embodiments of the present invention versus voltage. A test TLP of 100 nanoseconds (ns) was used to test responses of the device 100 as a simulation of ESD events. Comparison plot 200 illustrates a comparison of a TLP current voltage (IV) between a conventional NMOS device and an NMOS device using a Schottky diode as the functional ISCR according to embodiments of the invention. The ISCR may be considered to indicate less drift and loss of current in its optional characteristics, which denotes less damage to the device and a higher damage threshold of about 1.7 amps (A) compared to 0.7 A in conventional devices.Referring to FIG. 3, a plot 300 depicting a general ISCR current versus voltage is provided in accordance with alternative embodiments of the present invention. Plot 300 shows the direct current (DC) characteristics of an NMOS device with a Schottky diode according to embodiments of the invention during a TLP current-voltage test as referenced in FIG. 2. The illustration 300 shows a high holding voltage (in particular greater than 5.5 volts (V)) at an operating temperature of approximately 125° C. The ISCR is shown to have no latch-up risk for the chip operating at the voltage below 5 volts.Referring to FIG. 4, a FinFET ESDS device 400 is shown that also includes a Schottky diode 402 according to an alternative embodiment of the invention. In this embodiment, the Schottky diode 402 includes a metal contact 425 that laterally adjoins an n-well region 404 and is formed by the transition between metal and semiconductor substrate. The n-well region 404 is coupled to a drain side 426 of the FinFET device 410 to function as a thyristor having an extra terminal on the metal contact 424 as an anode for applying a latch voltage for turn-on. The metal contact 424 may include a metal, such as molybdenum, platinum, chromium, or tungsten, and / or certain silicides (e.g., palladium silicide and platinum silicide). The n-well region 404 may be doped, e.g., with arsenic and / or phosphorus, to function as an anode region of the Schotty diode 402. The n-well region 404 is at a drain side 426 of the FinFET device 410.The device 400 may also include a (P+) doped region 412 forming a well terminal to apply a reverse bias to the n-well region 404 and the p-well region 406 to avoid latch-up. The device 400 may also include a first (N+) doped region 416 functioning as a drain and a second (N+) doped region 414 functioning as a source region adjacent to a gate 424 (Fin) formed over the well region 406. Gate 424 is disposed between a first (N+) doped region 414 and a second (N+) doped region 416. The device 400 may also include a shallow isolation trench 418 laterally adjacent to the (P+) doped region 412, which in turn may laterally adjacent to an isolation trench 420. The isolation trench 420 is disposed between a second (N+) doped region 414 and a (P+) doped region 412. Isolation trench 422 is disposed between (N+) doped region 416 and n-well region 404.As used herein, the singular forms "a," "an," and "the" may include the plural forms unless the context indicates otherwise. Range boundaries may be combined and / or interchanged. For example, areas may include all subareas included therein, unless the context or language otherwise indicates it. As used to a particular value of a range, "about" refers to both boundaries of a range and, unless otherwise dependent on the accuracy of the instrument that measures the value, it may indicate a tolerance of + / - 10% of the value.Spatial terms such as "inner," "outer," "under," "below," "lower," "over," "upper," and the like may be used herein for ease of description to describe an element or relationship of a feature with at least one other element or feature as depicted in the figures. Spatial indications are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "below" other elements or features would then be oriented "on" or "over" the other elements or features. Accordingly, the example term "below" may include an orientation of above and below. The device may be otherwise oriented "rotated through 90° or other orientation" and the spatial relative descriptive words used herein may be interpreted accordingly.

Claims

A fin field effect transistor electrostatic discharge device (100; 400), the device (100; 400) comprising: a substrate (108; 408); a thyristor over the substrate (108; 408), the thyristor comprising: a p-well region (106; 406) over the substrate (108; 408); an n-well region (104; 404) laterally adjacent to the p-well region (106; 406) over the substrate (108; 408) and adjacent to a metal contact (128; 428); a first (P+) doped region (112; 412) over the p-well region (106; 406); a first (N+) doped region (114; 414) over the p-well region (106; 406); and a second (N+) doped region (116; 406); 416) over the p-well region (106; 406) and a Schottky diode (102; 402) formed by the n-well region (104; 404) and the metal contact (128; 428), wherein the Schottky diode (102; 402) is free of (N+) doped or (P+) doped regions, and wherein the Schottky diode (102; 402) controls electrostatic discharge between the second (N+) doped region (116; 416) and the n-well region (104; 404).The device (100; 400) of claim 1, wherein the substrate (108; 408) is p-type doped.The device (100; 400) of claim 1, wherein the substrate (108; 408) is a bulk silicon substrate.The apparatus (100; 400) of claim 1, wherein the thyristor comprises a PNPN switch.The device (100; 400) of claim 4, wherein the PNPN switch with the (P+) doped region (112; 412) is maintained at a positive potential with respect to the second (N+) doped region (116; 416).The device (100; 400) of claim 1, wherein the Schottky diode (402) is laterally adjacent to a drain of the thyristor.An electrostatic discharge device (100; 400) having a fin field effect transistor, comprising: a substrate (108; 408) having a p-well region (106; 406) and an n-well region (104; 404), wherein the p-well region (106; 406) is located at the n-well region (104; 404), and wherein the n-well region (104; 404) abuts a metal contact (128; 428) and is free of (N+) doped or (P+) doped regions; a Schottky diode (102; 402) formed by the n-well region (104; 404) and the metal contact (128; 428) to form a thyristor comprising: a (P+) doped region (112; 412) that defines a well terminal within the p-well region (106; 406), a first (N+) doped region (114; 416) forming a drain within the p-well region (112; 412), a second (N+) doped region (116; 414) forming a source, and wherein the Schottky diode (102; 402) controls electrostatic discharge between the second (N+) doped region (116; 414) and the n-well region (104; 404).The device (100; 400) of claim 7, wherein the thyristor with the (P+) doped region (112; 412) is maintained at a positive potential with respect to the second (N+) doped region (116; 414).The device (100) of claim 7, further comprising a supply terminal (150) electrically coupled to the source.An electrostatic discharge device (100; 400) for a fin field effect transistor, comprising: a substrate (108; 408) having a p-well region (106; 406) and an n-well region (104; 404), wherein the p-well region (106; 406) is located at the n-well region (104; 404), and wherein the n-well region (104; 404) is free of (N+) doped or (P+) doped regions; a Schottky diode (102; 402) formed by the n-well region (104; 404) and a metal contact (128; 428) adjacent to the n-well region (104; 404) to form a thyristor, comprising: a (P+) doped region (112; 412) that includes a well terminal within the p-well region (106; 406), a first (N+) doped region (116; 414) forming a source within the p-well region (106; 406), a second (N+) doped region (114; 416) forming a drain, and wherein the Schottky diode (102; 402) controls electrostatic discharge between the second (N+) doped region (114; 416) and the n-well region (104; 404).The device (100; 400) of claim 7 or 10, further comprising insulating regions (118, 120, 122; 418, 420, 422) on a device isolation trench and / or an ohmic contact trench, each trench laterally adjoining the (P+) doped region (112; 412) and the first (N+) doped region (114; 416).The device (100; 400) of claim 11, further comprising the device isolation trench and an ohmic contact trench of different sizes.The apparatus (100; 400) of claim 10, wherein the thyristor comprises a PNPN switch.The device (100; 400) of claim 10, wherein the (P+) doped region (112; 412) is maintained at a positive potential with respect to the second (N+) doped region (114; 416).

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