Bond structure of dies with hanging bonds and method for their manufacture

Abstract

Procedure, comprehensive: Polishing a semiconductor substrate (134) of a first die (70) to expose first silicon vias (142) extending into the semiconductor substrate (134); Formation of a dielectric layer (76) on the semiconductor substrate (134); Forming a plurality of bond pads (152A / 152B / 152C / 152D) in the dielectric layer (76), wherein the plurality of bond pads (152A / 152B / 152C / 152D) comprise first active bond pads (152A), first dummy bond pads (152B) and second dummy bond pads (152C), wherein the first active bond pads (152A) are electrically connected to the first silicon vias (142); Bonding of the first die (70) to a second die (60-1), wherein both the first active bond pads (152A) and the first dummy bond pads (152B) are bonded to respective bond pads in the second die (60-1); and Arranging a filler dielectric (78-1) such that it laterally surrounds the second die (60-1), wherein the filler dielectric (78-1) lies over and touches the upper surfaces of the second dummy bond pads (152C), the second dummy bond pads (152C) being located between the first die (70) and the second die (60-1).

Description

BACKGROUND

[0001] IC packages are becoming increasingly complex, with more device dies being housed in the same package to accommodate more functions. For example, a package structure has been developed to include a plurality of device dies, such as processors and memory dies, in the same package. The package structure may include device dies formed using different technologies and having different functions, bonded to the same device die to form a system. This can save manufacturing costs and optimize device performance. For example, memory dies may be bonded to logic dies. Further, the memory dies may form memory die stacks, with upper memory dies bonded to the respective lower memory dies.

[0002] US 2016 / 0 276 307 A1 discloses a PoP semiconductor device comprising an upper semiconductor package arranged over a lower semiconductor package. The upper semiconductor package comprises a substrate and a first semiconductor chip arranged over the substrate. First and second encapsulants are applied over the first semiconductor chip and the substrate. After the second encapsulant is applied, a first build-up interconnect structure is formed over the substrate. The upper package is arranged over the lower package. The lower package comprises a second semiconductor chip and modular interconnect units arranged around the second semiconductor chip. A second build-up interconnect structure is formed over the second semiconductor chip and the modular interconnect unit.The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I / O pattern of the stackup interconnect structure on the upper semiconductor package is designed to match the I / O pattern of the modular interconnect units.

[0003] US 2012 / 0 298 410 A1 discloses a structure for testing interconnect regions and methods for testing interconnect regions.

[0004] DE 10 2017 127 227 A1 discloses an interconnection structure over a substrate.

[0005] US 2018 / 0 204 868 A1 discloses a structure for a semiconductor device.

[0006] DE 10 2017 122 831 A1 discloses housing structures and training methods.

[0007] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS The Fig. 1 to 4 show cross-sectional views of intermediate stages in forming dummy dies according to some embodiments. The Fig. 5 to 10 show cross-sectional views of intermediate stages in forming device dies according to some embodiments. The Fig. 11 to 23 show cross-sectional views of intermediate stages in forming stacked die packages according to some embodiments. The Fig. 24 to 32 show the cross-sectional views and top views of some packages with stacked dies according to some embodiments. Fig. 33 shows a process flow for forming a package according to some embodiments. DETAILED DESCRIPTION

[0008] The invention is defined by claim 1, which defines a method, by claim 10, which defines a method, and by claim 16, which defines an IC package. According to various embodiments, a package comprising stacked dies and the method of forming the same are provided. The intermediate stages in forming the package according to some embodiments are shown. Some variations of some embodiments are described. Like reference numerals are used to refer to like elements throughout the various views and example embodiments. According to some embodiments of the present disclosure, the package includes an upper die bonded to a lower die, the upper die including an active pad and a hanging pad. The lower die has a silicon via penetrating the associated semiconductor substrate.A dielectric layer is formed over the silicon via, and an active bond pad and a dummy pad are formed within the dielectric layer. The dummy pad is bonded to the suspended pad, improving bond strength and reducing bond structure issues.

[0009] The Fig. 1 to 23 show cross-sectional views of intermediate stages in forming a package according to some embodiments of the present disclosure. The corresponding processes are also schematically shown in the Fig. The process flow shown in Figure 33 is reproduced.

[0010] The Fig. 1 to 4 illustrate the formation of dummy dies according to some embodiments, wherein these dummy dies are arranged in die stacks. The corresponding process is described as process 201 in the Fig. 33 shown process flow 200. With reference to Fig. 1, a wafer 20 is provided. The wafer 20 includes a substrate 22 and a buffer layer 24 over the substrate 22. According to some embodiments of the present disclosure, the substrate 22 is a silicon substrate. According to further embodiments, the substrate 22 may be formed from a material having a coefficient of thermal expansion (CTE) close to that of silicon and a thermal conductivity close to that of silicon or higher. The buffer layer 24 may be formed from a material having a lower elastic modulus than the subsequently formed bond layer 26 ( Fig. 2) (and is therefore softer) so that it can act as a stress-absorbing layer that absorbs the stress from the bonding layer 26. For example, the buffer layer 24 can be formed from a tetraethyl orthosilicate oxide (TEOS oxide), undoped silicate glass (USG), or the like. Forming the buffer layer 24 can involve plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), chemical vapor deposition (CVD), or the like.

[0011] With reference to Fig. 2, a bonding layer 26 is formed. According to some embodiments of the present disclosure, the bonding layer 26 is formed from an oxide, which may be an oxygen-containing oxide such as silicon oxide, silicon oxynitride, or the like. The bonding layer 26 may be formed using PECVD, LPCVD, CVD, or the like.

[0012] According to some embodiments, dummy metal pads 27 are formed in the bonding layer 26. According to some embodiments, no dummy metal pads are formed in the bonding layer 26. The dummy metal pads 27 may be made of copper, for example, and diffusion barrier layers may, but need not, be formed to separate the copper in the dummy metal pads 27 from the bonding layer 26 and the buffer layer 24. According to some embodiments, the dummy metal pads 27 may be formed using a single damascene process.

[0013] Fig. Figure 3 shows the formation of trenches 28 in wafer 20. Viewed from the top surface of wafer 20, trenches 28 form a grid. Trenches 28 extend from the top surface of bonding layer 26 to a mid-plane of substrate 22, with the mid-plane lying between the top surface and the bottom surface of substrate 22. Trenches 28 can be formed using a blade, a laser beam, or the like.

[0014] Fig. 4 shows the singulation of wafer 20 through a grinding process. According to some embodiments of the present disclosure, wafer 20 is turned upside down and attached to a tape 30. A grinding process is then performed from the backside of wafer 20 to thin substrate 22 until the portions of wafer 20 over trenches 28 are removed. Thus, wafer 20 is separated into separate dummy dies 32. The resulting dummy dies 32 are devoid of active devices and passive devices and may be free of metals therein. According to some embodiments, dummy dies 32 include substrate 22 and planar dielectric layers and are free of other metal features, except that dummy bond pads 27 may be formed.

[0015] The Fig. Figures 5 to 10 show the formation of upper dies, so named because they are used as upper-level dies in the formation of packages. The corresponding process is described as process 202 in the Fig. 33. According to some embodiments of the present disclosure, the upper dies are memory dies, while the upper dies may also be logic dies, input / output (IO) dies, or the like. The memory dies may be SRAM (static random access memory) dies, DRAM (dynamic random access memory) dies, NAND memory dies, RRAM (resistive random access memory) dies, MRAM (magnetoresistive random access memory) dies, or the like. As shown in Fig. 5, a wafer 31 is shown. The wafer 31 includes a semiconductor substrate 34, which according to some embodiments may be a silicon substrate, a germanium substrate, or the like. Integrated circuit devices 36 are formed, for example, on top of the semiconductor substrate 34. The integrated circuit devices 36 may include transistors, resistors, capacitors, inductors, and / or the like. The integrated circuit devices 36 may perform the memory function, logic function, IO function, or the like. An interconnect structure 38 is formed over the semiconductor substrate 34 and includes dielectric layers 37 and metal lines and vias 40 in the dielectric layers 37. The metal lines and vias 40 are electrically connected to the integrated circuit devices 36.

[0016] With reference to Fig. 6, silicon through-vias 42 are formed to extend into the semiconductor substrate 34. According to some embodiments, the silicon through-vias 42 extend from a top surface of the interconnect structure 38 into the semiconductor substrate 34. According to alternative embodiments, the silicon through-vias 42 are preformed in the semiconductor substrate 34 prior to forming all or a top portion of the interconnect structure 38. The silicon through-vias 42 may be formed from a conductive material such as tungsten, copper, or the like. An insulating layer (not shown) may be formed to enclose each of the silicon through-vias 42 to electrically isolate the respective silicon through-via 42 from the semiconductor substrate 34.Forming the silicon vias 42 may include etching the dielectric layers 37 and the semiconductor substrate 34 to form openings and filling the openings with the insulating layer and the conductive material. A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, may be performed to level the upper surfaces of the silicon vias 42 with the upper surface of the upper dielectric layer 37.

[0017] Fig. 7 shows the further formation of the wafer 31. According to some embodiments, the formation includes forming dielectric layers 39 and metal lines and vias 40 to extend the interconnect structure 38, forming upper metal pads 44 in an upper layer of the dielectric layers 39, forming a passivation layer 46, and forming metal pads 48. According to some embodiments of the present disclosure, some of the dielectric layers 37 and 39 are made of low-k dielectrics. The passivation layer 46 may be made of a non-low-k dielectric having a dielectric constant greater than or equal to the dielectric constant of silicon oxide (3.9). The metal pads 48 may be formed of aluminum or aluminum-copper.

[0018] Fig. 8 shows the formation of a dielectric layer 50, vias 51, a dielectric layer 54, and bond pads 52A and 52B in the dielectric layer 54. According to some embodiments, as shown in Fig. 8, dielectric layers 50 and 54 are separate dielectric layers formed in different formation processes. According to alternative embodiments, dielectric layers 50 and 54 are parts of the same dielectric layer formed in the same formation process. Dielectric layer 54 may be formed from an oxygen-containing dielectric such as silicon oxide, silicon oxynitride, or the like. Dielectric layer 50 may be formed from the same material as dielectric layer 54 or may be formed from a different material than dielectric layer 54. For example, dielectric layer 50 may be formed from silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, or the like.Bond pads 52A and 52B and vias 51 may be made of copper and may be formed using single or dual damascene processes. The top surfaces of dielectric layer 54 and bond pads 52A and 52B are coplanar.

[0019] Fig. Figure 9 shows the formation of trenches 56 in wafer 31. Viewed from the top surface of wafer 31, trenches 56 form a grid, with one trench 56 shown as an example. Trenches 56 extend from the top surface of dielectric layer 54 to a middle plane of semiconductor substrate 34, the middle plane being located between the top surface and the bottom surface of semiconductor substrate 34. Trenches 56 can be formed using a blade, a laser beam, or the like.

[0020] Fig. Figure 10 illustrates the singulation of wafer 31 by a grinding process. According to some embodiments of the present disclosure, wafer 31 is turned upside down and attached to a belt 58. A grinding process is then performed from the backside of wafer 31 to thin semiconductor substrate 34 until the portions of semiconductor substrate 34 above trenches 56 are removed. Thus, wafer 31 is separated into separate dies 60 that are identical to each other.

[0021] The Fig. 11 to 23 show the cross-sectional views when packing the dummy dies 32 ( Fig. 4) and the Dies 60 ( Fig. 10) to form a package. With reference to Fig. 11, a carrier 62 is provided. According to some embodiments, the carrier 62 is made of silicon, glass, or the like and is provided in the form of a wafer large enough to accommodate a plurality of device dies that are bonded thereto. A dielectric layer 64 is formed on the carrier 62. The corresponding process is described as process 203 in the Fig. 33. According to some embodiments of the present disclosure, the dielectric layer 64 is made of a relatively soft material that is softer than the subsequently formed bonding layer 68 and is therefore used as a buffer layer for absorbing stress. The dielectric layer 64 may be formed of a TEOS oxide, USG, or the like. Forming the dielectric layer 64 may include PECVD, LPCVD, CVD, or the like. According to some embodiments, metal features 66 are formed in the dielectric layer 64. The metal features 66 may be used as alignment marks for aligning subsequent device die placement and bonding. The metal features 66 may be formed, for example, by damascene processes.

[0022] With reference to Fig. 12, a bonding layer 68 is formed. The corresponding process is described as process 204 in the Fig. 33. According to some embodiments of the present disclosure, the bonding layer 68 is formed from an oxide, which may be an oxygen-containing oxide such as silicon oxide, silicon oxynitride, or the like. The bonding layer 68 may be formed using PECVD, LPCVD, CVD, or the like. Forming the bonding layer 68 may include a deposition process followed by a planarization process.

[0023] Fig. 13 shows the placement and bonding of a level 1 die (of level 1 dies) 70 on the bond layer 68. The corresponding process is described as process 206 in the Fig. 33. Although one Level 1 die 70 is shown, a plurality of Level 1 dies 70 are arranged and bonded to the bond layer 68. The plurality of Level 1 dies 70 may be arranged as an array. The alignment marks 66 are used to align the Level 1 die(s) to intended positions. According to some embodiments, the level 1 dies 70 are logic dies, which may be application processor dies (AP dies), graphics processor dies (GPU dies), field programmable gate array dies (FPGA dies), application-specific integrated circuit dies (ASIC dies), input / output dies (IO dies), network processor dies (NPU dies), tensor processor dies (TPU dies), artificial intelligence dies (AI dies), or the like. The features in the logic dies 70 are labeled according to the labels of the dies 60 ( Fig. 10), except that the reference numbers of the features in the level 1 dies 70 are incremented by 100 compared to the reference numbers of the corresponding features in the dies 60. For example, the logic dies 70 may include a semiconductor substrate 134, integrated circuit devices 136, an interconnect structure 138, metal lines and vias 140, silicon vias 142, metal pads 144 and 148, and a bond layer 154. Forming the dies 70 may include process steps similar to those described in the Fig. 5 to 7, subsequently forming the bonding layer 154 ( Fig. 13), and then the Fig. 9 and Fig. 10. Some materials of the labeled features of the Level 1 dies may also be similar to the materials of the corresponding features in the dies 60. The Level 1 dies 70 may have structures that differ from the structures of the dies 60 ( Fig. 10). As in Fig. As shown in Figure 13, the metal pads 148 are embedded in a dielectric layer, such as the bond layer 154. According to some embodiments, the level 1 dies 70 have a thickness T1 in the range between about 50 µm and about 150 µm.

[0024] The bonding of the dies 70 to the bonding layer 68 can be done by fusion bonding (dielectric-dielectric bonding), whereby Si-O-Si bonds can be formed that bond the bonding layers 154 and 68 together.

[0025] Fig. 14 shows a gap-filling process for forming dielectric regions 72 that fill the gaps between and enclose the level-1 dies 70. The corresponding process is described as process 208 in the Fig. 33. According to some embodiments, the gap filling process includes dispensing or coating a flowable dielectric and then curing the flowable dielectric. The respective dielectric region 72 may be comprised of a molding compound, a mold fill, a resin, an epoxy, or the like. According to alternative embodiments, forming the dielectric regions 72 may include depositing one or more dielectric layers. For example, the dielectric regions 72 may include a dielectric liner formed of silicon nitride and another dielectric (such as silicon oxide) over the dielectric liner. A planarization process, such as a CMP process or a mechanical grinding process, may be performed to remove excess dielectric and level the top surface of the semiconductor substrate 134 with the dielectric regions 72.According to some embodiments, the level 1 dies after the gap filling process have a thickness T2 in the range between about 10 µm and about 15 µm.

[0026] Fig. 15 shows a backside grinding process for thinning the level 1 dies 70 and exposing the silicon vias 142. The corresponding process is described as process 210 in the Fig. 33 shown process flow 200. The back grinding process may be a continuing part of the Fig. 14 or it may be a separate process separate from the planarization process shown in Fig. 14 is performed. After the back-side grinding process, the semiconductor substrate 134 is also exposed, with its upper surface being coplanar with the upper surfaces of the silicon vias 142 and the dielectric regions 72. Next, the semiconductor substrate 134 is etched using an etchant that attacks the semiconductor substrate 134 and does not attack the silicon vias 142 and the dielectric region 72. As a result, a recess is formed, with the upper portions of the silicon vias 142 being arranged in the recess and protruding from the upper surface of the remaining portion of the semiconductor substrate 134. In a subsequent process, an insulating layer 74 is formed. The corresponding process is also known as process 210 in the FIG. Fig. 33. The insulating layer 74 is formed from a dielectric, which may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or the like. A planarization process is then performed to level the top surfaces of the silicon vias 142, the insulating layer 74, and the dielectric regions 72. According to some embodiments, after the formation of the insulating layer 74, the Level 1 dies have a thickness T3 in the range between about 3 μm and about 10 μm.

[0027] Fig. 16 shows the formation of a bonding layer 76 and bonding pads 152A and 152B in the bonding layer 76. The corresponding process is described as process 212 in the Fig. 33. The bond layer 76 may be formed from an oxygen-containing dielectric such as silicon oxide, silicon oxynitride, or the like. The formation method may include CVD, ALD, PECVD, or the like. The bond pads 152A and 152B may include copper and may be formed using a single damascene process. The top surfaces of the bond layer 76 and the bond pads 152A and 152B are coplanar. According to some embodiments, the bond pads 152A are active bond pads that are electrically and / or signal-wise connected to the integrated circuit devices 136. The bond pads 152B, on the other hand, are dummy bond pads that are electrically floating at this time. The bond pads 152B may have bottom surfaces that contact the top surface of the insulating layer 74.

[0028] According to some embodiments of the present disclosure, when the bond pads 152A and 152B are formed, bond pads 152C and 152D are also formed simultaneously. The function and positions of the bond pads 152C and 152D are described in subsequent sections with reference to the Fig. 27 to 32. According to alternative embodiments of the present disclosure, one or both of the bond pads 152C and 152D are not formed.

[0029] With reference to Fig. 17, the device die(s) 60 are bonded to the device die 70. The device dies 60 are also referred to as level 2 dies 60-1. The corresponding process is described as process 214 in the Fig. 33. Throughout the description, the reference symbol of a feature may be followed by a hyphen and an integer to indicate its level. For example, the dies 60 may be designated according to their levels as 60-1, 60-2, ..., 60-n ( Fig. 20). According to some embodiments of the present disclosure, the bonding may include fusion bonding, which includes direct metal bonding between the bond pads 152A / 152B and the bond pads 52A / 52B, and dielectric-to-dielectric bonding between the dielectric layer 54 and the dielectric layer 76. After bonding, the bond pads 152A and 52A, which are bonded together, are used for electrical and / or signal connection between the level 2 die 60-1 (which may be a memory die) and the level 1 die 70. For example, the integrated circuit devices 36 (which may include memory cells) in the level 2 dies 60-1 are electrically and / or signal-wise connected to the integrated circuit devices 136 in the level 1 dies 70 via the bond pads 152A and 52A.

[0030] The bond pad 52B is a hanging bond, which is schematically shown in Fig. 25 to show some details. The bond pad 52B is electrically connected to the integrated circuit devices 36 ( Fig. 17) (even if the corresponding device die 60 is still a separate die). If the resulting package 96 ( Fig. 23) is turned on, the hanging bond pad 52B may have a voltage received from the integrated circuit devices 36. If the Level 2 die 60-1 is used in other circuits or other parts of the resulting package, for example, as a Tier 3 die as described in the following sections, the bond pad 52B may be a functional (active) pad that conducts voltages and / or currents. Because the Level 2 die 60-1 is connected to the Level 1 die 70 according to some embodiments of the present disclosure, the bond pad 52B has no electrical and signal function and is therefore hanging. Accordingly, voltages may be applied to the bond pads 52B and 152B, but no current flows through the bond pads 52B and 152B because the bond pad 152B is an end node of the current / voltage path.

[0031] Fig. 18 shows the bonding of dummy dies 32-1 to the dielectric layer 76. The corresponding process is described as process 216 in the Fig. 33. The bonding may be performed by melt bonding, wherein the dielectric layers 26 in the dummy dies 32-1 are bonded to the dielectric layer 76. Since there are a plurality of level 2 dies 60-1 (one shown), the dummy dies 32-1 are arranged between the plurality of level 2 dies 60-1 to occupy the spaces otherwise occupied by a gap fill material 78-1 ( Fig. 19). Since the dummy dies 32-1 have EOTs close to those of the level 1 dies 70 and the level 2 dies 60, adding the dummy dies 32-1 reduces stress and warpage in the resulting package.

[0032] Fig. 19 shows a gap-filling process for forming dielectric regions 78-1 surrounding the level-2 dies 60-1. The corresponding process is described as process 218 in the Fig. 33. According to some embodiments, the gap filling process includes dispensing or coating a flowable dielectric and then curing the flowable dielectric. The respective dielectric region 78-1 may be formed from a molding compound, a mold fill, a resin, an epoxy, or the like. According to alternative embodiments, forming the dielectric regions 78-1 may include depositing one or more dielectric layers. For example, the dielectric regions 78-1 may include a dielectric liner formed from silicon nitride and another dielectric (such as silicon oxide) over the dielectric liner. A planarization process, such as a CMP process or a mechanical grinding process, may be performed to remove excess dielectrics and level the top surface of the semiconductor substrate 34 with the dielectric regions 78-1.

[0033] In subsequent processes, a backside grinding process is performed to thin the level 2 dies 60-1 and the dummy dies 32-1 and to expose the silicon vias 42. The corresponding process is described as process 220 in the Fig. 33. After the back grinding process, the semiconductor substrate 34 is also exposed, with its upper surface being coplanar with the upper surfaces of the silicon vias 42 and the dielectric regions 78-1. Next, the semiconductor substrate 34 is etched to form a recess, with the upper portions of the silicon vias 42 disposed in the recess and protruding from the upper surface of the remaining portion of the semiconductor substrate 34. In a subsequent process, an insulating layer 80-1 is formed in the recess. The corresponding process is also shown as process 220 in the Fig. 33. The insulating layer 80-1 is formed from a dielectric, which may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or the like. A planarization process is then performed to level the top surfaces of the silicon vias 42, the insulating layer 80-1, and the dielectric regions 78-1.

[0034] Fig. 19 further shows the formation of a bonding layer 82-1 and bonding pads 252A and 252B in the bonding layer 82-1. The corresponding process is described as process 222 in the Fig. 33. The bond layer 82-1 may be formed from an oxygen-containing dielectric such as silicon oxide, silicon oxynitride, or the like. The formation method may include CVD, ALD, PECVD, or the like. The bond pads 252A and 252B may be formed from copper and may be formed using a single damascene process. The top surfaces of the bond layer 82-1 and the bond pads 252A and 252B are coplanar. According to some embodiments, the bond pads 252A are active bond pads that are electrically connected to the integrated circuits, such as 36. For example, if the die 60-1 and the subsequently bonded die 60-2 are identical, the bond pads 252B may be active bond pads just like the bond pads 252A. Fig. 19 schematically illustrates a dashed line 83 depicting the conductive features electrically connecting the bond pads 252B to the integrated circuit devices 36, wherein the conductive features may include a silicon via and metal pads, metal lines, vias, or the like. The bond pads 252B may also be dummy bond pads according to alternative embodiments. According to some embodiments, there is a one-to-one correspondence between the bond pads 252A / 252B and the underlying bond pads 52A / 52B (and 152A / 152B), wherein each of the bond pads 252A / 252B is vertically aligned with and overlaps a corresponding bond pad 52A / 52B and a corresponding bond pad 152A / 152B.

[0035] According to some embodiments of the present disclosure, when the bond pads 252A and 252B are formed, bond pads 252C and 252D are also formed simultaneously. The function and positions of the bond pads 252C and 252D are described in subsequent sections with reference to the Fig. 27 to 32 are described in detail.

[0036] Fig. 20 shows the repetition of the Fig. 17 to 19 to stack more levels of dies 60. For example, assume that there are n levels of dies 60, where the top-level dies are referred to as level-n dies 60-n. The integer n can be any number greater than or equal to 2. The upper-level dies 60-2 to 60-n can be identical to or different from the level-2 die 60-1. After the top-level dies 60-n and the dummy dies 32-n are bonded, gap-fill regions 78-n are formed and planarized, followed by the formation of a dielectric layer 82-n, which can also be a bonding layer.

[0037] Fig. Figure 21 shows a carrier exchange process. The corresponding process is described as process 224 in the Fig. 33. A carrier 85 is bonded to the bonding layer 82-n by a bonding layer 84, wherein the bonding method is fusion bonding. According to some embodiments, the carrier 85 is made of silicon and is a blank carrier that does not include any active devices, passive devices, conductive traces, or the like. The bonding layer 84 may be formed from an oxygen-containing material such as silicon oxide, silicon oxynitride, or the like.

[0038] Next, the carrier 62, the buffer layer 64, and the bonding layer 68 are removed, for example, in a CMP process or a mechanical grinding process. In subsequent processes, a passivation layer 86 is formed, which may comprise silicon oxide, silicon nitride, or composite layers thereof. An opening 88 is formed in the passivation layer 86. The corresponding process is described as process 226 in the Fig. 33 shown process flow 200. The resulting structure is shown in Fig. 22. A test process can then be performed, for example, by bringing the test pins of a probe card (not shown) into contact with the metal pads 148 to determine whether the resulting package is defective or not. Known good packages are recorded. The corresponding process is described as process 228 in the Fig. 33 shown process flow 200 is shown.

[0039] Fig. Figure 23 shows the formation of a polymer layer 90, which may be made of polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like. Electrical connectors 92, which may include metal pillars 93 and solder regions 94, are then formed on the metal pads 148. The corresponding process is described as process 230 in the Fig. 33. The resulting structure is referred to as a reconstructed wafer (package) 97. In a subsequent process, a dicing process is performed on the reconstructed wafer 97, and a plurality of identical packages 96 are formed. The corresponding process is described as process 232 in the Fig. 33 shown process flow 200 is shown.

[0040] The Fig. 24 to 32 schematically illustrate cross-sectional and top views of packages 96 according to some embodiments of the present disclosure. Some details are not shown, and these details may be understood by reference to the Fig. 11 to 23. In these figures, two levels of device dies 60 are shown to illustrate the likely multiple levels of Fig. 23. The functional (active) bond pads 52A and 152A, hanging bond pads 52B, and dummy bond pads 152B are shown. Some of the bond pads are shown as 52A / 52B to indicate that these bond pads may be functional bond pads 52A or hanging bond pads 52B. Similarly, some of the bond pads are shown as 152A / 152B to indicate that these bond pads may be functional bond pads 152A or dummy bond pads 152B. It should be understood that although the dielectric fill regions 72 ( Fig. 23) in the Fig. 24 to 32 are not shown, the dielectric regions 72 in the Fig. 24 to 32 shown packages 96 may (but do not have to) be present.

[0041] According to some embodiments of the present disclosure, as in Fig. 24, the bond pads formed on the level 1 die 70 (e.g., 152A and 152B) are all overlapped by the level 2 die 60-1, and no bond pads are formed directly below and in contact with the dielectric regions 78-1 and the dummy dies 32-1. Fig. Figure 25 shows an enlarged view of the bond pads 52A, 52B, 152A and 152B.

[0042] Fig. Figure 26 shows a top view of bond pads 52A, 52B, 152A, and 152B, Level 1 die 70, Level 2 die 60-1, and dummy dies 32-1. According to some embodiments of the present disclosure, bond pads 52A, 52B, 152A, and 152B form an array and are confined within the area occupied by Level 2 die 60, with no bond pads outside the area occupied by Level 2 die 60-1.

[0043] The Fig. 27 and Fig. 28 show a top view and a cross-sectional view of the package 96 according to some embodiments. These embodiments are similar to the embodiments in FIGS. Fig. 24 and Fig. 26, except that further dummy bond pads 152C are formed in a region overlapped by the dielectric regions 78-1. Accordingly, in the package 96, the dummy pads 152C are electrically floating, with the upper surface of the bond pads 152C in contact with the lower surface of the dielectric regions 78-1. Moreover, the bond pads 152C are completely enclosed in the dielectric regions. During the formation of the bond pads, the edge portions of a dense pad region, such as the pad array, may be uneven, for example, when the edge portions of the pad array are polished more or less than the center portions of the pad array. By forming the dummy pads 152C, the unevenness is concentrated in the dummy pads 152C, which are edge portions of the pad array, while the bond pads 152A and 152B are more uniform.

[0044] The Fig. 29 and Fig. 30 show a top view and a cross-sectional view of the package 96 according to some embodiments. These embodiments are similar to the embodiments in FIGS. Fig. 24 and Fig. 26, except that dummy bond pads 152C and 152D are further formed in a region overlapped by dielectric regions 78-1 and dummy dies 32-1. In package 96, dummy pads 152C and 152D are electrically floating, with the upper surfaces of bond pads 152C in contact with the lower surface of dielectric regions 78-1 and the upper surfaces of bond pads 152D in contact with the lower surface of dummy dies 32. According to some embodiments, dummy pads 152C and 152D are completely enclosed within the dielectric regions. According to alternative embodiments, bond pads 152D are bonded to bond pads 27 in dummy dies 32-1. Forming the dummy pads 152C and 152D improves the uniformity of the planarization process for forming the pads 152A and 152B.

[0045] The Fig. 31 and Fig. 32 show a top view and a cross-sectional view of the package 96 according to some embodiments. These embodiments are similar to the embodiments in FIGS. Fig. 24 and Fig. 26, except that no dummy dies 32 are used. The dummy bond pads 152C are further formed in an area overlapped by the dielectric regions 78-1. Accordingly, in the package 96, the dummy pads 152C are electrically floating, with the upper surfaces of the bond pads 152C in contact with the lower surface of the dielectric regions 72. Furthermore, the dummy pads 152C are completely enclosed within the dielectric regions. Forming the dummy pads 152C improves uniformity in the planarization process for forming the bond pads 152A and 152B.

[0046] In the embodiments shown above, some processes and features are described in accordance with some embodiments of the present disclosure. Other features and processes may also be provided. For example, test structures may be provided to assist in verification testing of the 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate that enable testing of the 3D packages or the 3DIC, the use of probes and / or probe plates, and the like. Verification testing may be performed on both intermediate structures and the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with test methods that include intermediate verification of known good dies to increase yield and reduce costs.

[0047] The embodiments of the present disclosure have several advantageous features. By forming an additional dielectric layer and dummy pads in the additional dielectric layer in a lower-level die, the dangling pads in an upper-level die are bonded to the dummy pads instead of being in contact with a dielectric. Bond strength is thus improved.

Claims

[1] Method comprising: Polishing a semiconductor substrate (134) of a first die (70) to expose first silicon vias (142) extending into the semiconductor substrate (134); Forming a dielectric layer (76) on the semiconductor substrate (134); Forming a plurality of bond pads (152A / 152B / 152C / 152D) in the dielectric layer (76), the plurality of bond pads (152A / 152B / 152C / 152D) comprising first active bond pads (152A), first dummy bond pads (152B), and second dummy bond pads (152C), the first active bond pads (152A) being electrically connected to the first silicon vias (142); Bonding the first die (70) to a second die (60-1), wherein both the first active bond pads (152A) and the first dummy bond pads (152B) are bonded to respective bond pads in the second die (60-1); and Arranging a fill dielectric (78-1) to laterally enclose the second die (60-1), the fill dielectric (78-1) overlying and contacting upper surfaces of the second dummy bond pads (152C), the second dummy bond pads (152C) being located between the first die (70) and the second die (60-1). [2] The method of claim 1, wherein the first active bond pads (152A) are bonded to a second plurality of active bond pads (52A) in the second die (60-1), and wherein the first dummy bond pads (152B) are bonded to hanging bond pads (52B) in the second die (60-1), and wherein both the second plurality of active bond pads (52A) and the hanging bond pads (52B) are electrically connected to integrated circuit devices in the second die (60-1). [3] The method according to claim 1 or 2, wherein the first die (70) and the second die (60-1) are bonded by hybrid bonding. [4] The method of any preceding claim, further comprising bonding a dummy die (32-1) to the first die (70). [5] The method of claim 4, wherein the plurality of bond pads further comprises third dummy bond pads (152D), and wherein the dummy die (32-1) further comprises fourth dummy bond pads (27) bonded to the third dummy bond pads (152D). [6] Method according to one of the preceding claims, further comprising: Planarizing the second die (60-1) and the fill dielectric (78-1) until second silicon vias (42) are exposed in the second die (60-1); and forming third active bond pads (252A) electrically connected to the second silicon vias (42). [7] A method according to any one of the preceding claims, wherein the first die (70) is a logic die and the second die is a memory die. [8] The method of any preceding claim, further comprising stacking a third die (60-2) identical to the second die (60-1) over the second die (60-1), wherein no bond pads in the second die (60-1) that are also bonded to the third die (60-3) are used as hanging bond pads. [9] Method comprising: Forming a first die (70), comprising: a first semiconductor substrate (134), and a first silicon via (142) penetrating the first semiconductor substrate (134); Forming a second die (60-1), comprising: a second semiconductor substrate (34), a second silicon via (42) penetrating the second semiconductor substrate, a second active bond pad (52A), and a first hanging bond pad (52B); bonding the second die (60) via the first die (70), wherein the second active bond pad (52A) is electrically connected to the first die (70) via a first active bond pad (152A) between the first die (70) and the second die (60), and wherein the first hanging bond pad (52B) is bonded to a first dummy pad (152B) between the first die (70) and the second die (60); and performing a gap filling process for embedding the second die (60-1) in a gap filling material (78-1), the gap filling material (78-1) laterally enclosing the second die (60-1), the gap filling material (78-1) overlying and contacting a top surface of a second dummy pad (152C), the second dummy pad (152C) being located between the first die (70) and the second die (60-1). [10] The method of claim 9, further comprising: Arranging the first die (70) over a carrier (62); Encapsulating the first die (70) in a fill dielectric (72); Forming a dielectric layer (76) overlapping the first die (70) and the fill dielectric (72); and Forming the first active bond pad (152A) and the first dummy pad (152B) in the dielectric layer (76). [11] The method of claim 9 or 10, further comprising: Bonding a dummy die (32-1) to the first die (70), wherein the dummy die (32-1) touches a third dummy pad (152D) between the first die and the second die, and wherein the third dummy pad (152D) is at a same level as the first active bond pad (152A) and the first dummy pad (152B). [12] The method of claim 11, wherein the dummy die (32-1) further comprises a fourth dummy pad (27) bonded to the third dummy pad (152D) in the first die. [13] The method of any one of claims 9 to 12, wherein the first dummy pad (152B) is electrically floating before the second die (60-1) is bonded to the first die (70). [14] A method according to any one of claims 9 to 12, further comprising: Polishing the first semiconductor substrate (134) to expose the first silicon via; Forming an additional dielectric layer (74) over and touching the first semiconductor substrate (134); and Forming the first active bond pad (152A) and the first dummy pad (152B) in the dielectric layer (76), wherein an entire lower surface of the first dummy pad (152B) is in contact with an upper surface of the additional dielectric layer (74) in the first die (70). [15] IC package comprising: a first die (70), comprising: a first semiconductor substrate (134), a first silicon via (142) penetrating the first semiconductor substrate (134), a dielectric layer (76) over the first die (70), an additional dielectric layer (74) over and touching the first semiconductor substrate (134), a first active bond pad (152A) in the dielectric layer (76), the first active bond pad overlying and contacting the first silicon via, a first dummy bond pad (152B) in the dielectric layer (76), an entire lower surface of the first dummy bond pad (152B) being located above and contacting the additional dielectric layer (74); a second die (60-1), comprising: a second active bond pad (52A) over the first active bond pad and bonded thereto; and a hanging bond pad (52B) over the first dummy bond pad and bonded thereto; a second dummy bonding pad (152C) in the dielectric layer (76); and a fill dielectric (78-1) laterally enclosing the second die (60-1), the fill dielectric (78-1) contacting a top surface of the second dummy bond pad (152C). [16] The package of claim 15, wherein the first die (70) is a logic die and the second die is a memory die. [17] Package according to claim 15 or 16, further comprising: a third dummy bonding pad (152D) in the dielectric layer (76); and a dummy die (27) over the third dummy bond pad (152D) and touching it.

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